From e070ae0f02b10bfd482146a748095ca782f73039 Mon Sep 17 00:00:00 2001
From: Frazer Carsley <frazer.carsley@arm.com>
Date: Mon, 19 Jan 2026 15:16:52 +0000
Subject: [PATCH] corstone1000: enable OF_UPSTREAM device tree support

Enable OF_UPSTREAM option set for corstone1000 platform. Remove
legacy u-boot corstone1000 device trees.
Add device tree files for FVP and MPS3 platforms to add device
tree nodes that are missing from the upstream. These are done in a
modular way.

Signed-off-by: Clement Faure <clement.faure@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Upstream-Status: Pending [Not submitted to upstream yet]
---
 arch/arm/dts/Makefile                        |   3 -
 arch/arm/dts/corstone1000-extsys-u-boot.dtsi |  14 ++
 arch/arm/dts/corstone1000-fvp-u-boot.dtsi    |   9 +
 arch/arm/dts/corstone1000-fvp.dts            |  82 --------
 arch/arm/dts/corstone1000-mps3-u-boot.dtsi   |   9 +
 arch/arm/dts/corstone1000-mps3.dts           |  32 ---
 arch/arm/dts/corstone1000-u-boot.dtsi        |  30 +++
 arch/arm/dts/corstone1000-virtio-u-boot.dtsi |  13 ++
 arch/arm/dts/corstone1000.dtsi               | 194 -------------------
 board/armltd/corstone1000/corstone1000.c     |   4 +-
 configs/corstone1000_defconfig               |   5 +-
 11 files changed, 81 insertions(+), 314 deletions(-)
 create mode 100644 arch/arm/dts/corstone1000-extsys-u-boot.dtsi
 create mode 100644 arch/arm/dts/corstone1000-fvp-u-boot.dtsi
 delete mode 100644 arch/arm/dts/corstone1000-fvp.dts
 create mode 100644 arch/arm/dts/corstone1000-mps3-u-boot.dtsi
 delete mode 100644 arch/arm/dts/corstone1000-mps3.dts
 create mode 100644 arch/arm/dts/corstone1000-u-boot.dtsi
 create mode 100644 arch/arm/dts/corstone1000-virtio-u-boot.dtsi
 delete mode 100644 arch/arm/dts/corstone1000.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7c8cf3a5a1d..89b3728379b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1206,9 +1206,6 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
 
 dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
 
-dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
-				corstone1000-fvp.dtb
-
 dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
 
 include $(srctree)/scripts/Makefile.dts
diff --git a/arch/arm/dts/corstone1000-extsys-u-boot.dtsi b/arch/arm/dts/corstone1000-extsys-u-boot.dtsi
new file mode 100644
index 00000000000..074f45f0e69
--- /dev/null
+++ b/arch/arm/dts/corstone1000-extsys-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ */
+
+&{/soc} {
+	extsys0: remoteproc@1a010310 {
+		compatible = "arm,corstone1000-extsys";
+		reg = <0x1a010310 0x4>, <0x1a010314 0x4>;
+		reg-names = "reset-control", "reset-status";
+		firmware-name = "es_flashfw.elf";
+	};
+};
diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
new file mode 100644
index 00000000000..5cb7762fc1c
--- /dev/null
+++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ */
+
+#include "corstone1000-u-boot.dtsi"
+#include "corstone1000-extsys-u-boot.dtsi"
+#include "corstone1000-virtio-u-boot.dtsi"
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
deleted file mode 100644
index cd8a132271e..00000000000
--- a/arch/arm/dts/corstone1000-fvp.dts
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 or MIT
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- * Copyright (c) 2022, Linaro Limited. All rights reserved.
- *
- */
-
-/dts-v1/;
-
-#include "corstone1000.dtsi"
-
-/ {
-	model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
-	compatible = "arm,corstone1000-fvp";
-
-	smsc: ethernet@4010000 {
-		compatible = "smsc,lan91c111";
-		reg = <0x40100000 0x10000>;
-		phy-mode = "mii";
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-		reg-io-width = <2>;
-	};
-
-	virtio: virtio-net@40400000 {
-		compatible = "virtio,mmio";
-		reg = <0x40400000 0x10000>;
-		interrupts = <145>;
-	};
-
-	vmmc_v3_3d: fixed_v3_3d {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmc_supply";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	sdmmc0: mmc@40300000 {
-		compatible = "arm,pl18x", "arm,primecell";
-		reg = <0x40300000 0x1000>;
-		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-		max-frequency = <12000000>;
-		vmmc-supply = <&vmmc_v3_3d>;
-		clocks = <&smbclk>, <&refclk100mhz>;
-		clock-names = "smclk", "apb_pclk";
-	};
-
-	sdmmc1: mmc@50000000 {
-		compatible = "arm,pl18x", "arm,primecell";
-		reg = <0x50000000 0x10000>;
-		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-		max-frequency = <12000000>;
-		vmmc-supply = <&vmmc_v3_3d>;
-		clocks = <&smbclk>, <&refclk100mhz>;
-		clock-names = "smclk", "apb_pclk";
-	};
-};
-
-&cpus {
-	cpu1: cpu@1 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a35";
-		reg = <0x1>;
-		enable-method = "psci";
-		next-level-cache = <&L2_0>;
-	};
-	cpu2: cpu@2 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a35";
-		reg = <0x2>;
-		enable-method = "psci";
-		next-level-cache = <&L2_0>;
-	};
-	cpu3: cpu@3 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a35";
-		reg = <0x3>;
-		enable-method = "psci";
-		next-level-cache = <&L2_0>;
-	};
-};
-
diff --git a/arch/arm/dts/corstone1000-mps3-u-boot.dtsi b/arch/arm/dts/corstone1000-mps3-u-boot.dtsi
new file mode 100644
index 00000000000..0d9d6c5e6e1
--- /dev/null
+++ b/arch/arm/dts/corstone1000-mps3-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ */
+
+#include "corstone1000-u-boot.dtsi"
+#include "corstone1000-extsys-u-boot.dtsi"
+
diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts
deleted file mode 100644
index e3146747c2d..00000000000
--- a/arch/arm/dts/corstone1000-mps3.dts
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 or MIT
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- * Copyright (c) 2022, Linaro Limited. All rights reserved.
- *
- */
-
-/dts-v1/;
-
-#include "corstone1000.dtsi"
-
-/ {
-	model = "ARM Corstone1000 FPGA MPS3 board";
-	compatible = "arm,corstone1000-mps3";
-
-	smsc: ethernet@4010000 {
-		compatible = "smsc,lan9220", "smsc,lan9115";
-		reg = <0x40100000 0x10000>;
-		phy-mode = "mii";
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-		reg-io-width = <2>;
-		smsc,irq-push-pull;
-	};
-
-	usb_host: usb@40200000 {
-		compatible = "nxp,usb-isp1763";
-		reg = <0x40200000 0x100000>;
-		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-		bus-width = <16>;
-		dr_mode = "host";
-	};
-};
diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi
new file mode 100644
index 00000000000..a75bc7016aa
--- /dev/null
+++ b/arch/arm/dts/corstone1000-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright 2025-2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ */
+
+/ {
+	nvmxip: nvmxip-qspi@08000000 {
+		compatible = "nvmxip,qspi";
+		reg = <0x08000000 0x2000000>;
+		lba_shift = <9>;
+		lba = <65536>;
+	};
+
+	fwu-mdata {
+		compatible = "u-boot,fwu-mdata-gpt";
+		fwu-mdata-store = <&nvmxip>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		smem_mem: smem_region@88000000 {
+			reg = <0x0 0x88000000 0x0 0x100000>;
+			no-map;
+		};
+	};
+};
diff --git a/arch/arm/dts/corstone1000-virtio-u-boot.dtsi b/arch/arm/dts/corstone1000-virtio-u-boot.dtsi
new file mode 100644
index 00000000000..89ff06a51f8
--- /dev/null
+++ b/arch/arm/dts/corstone1000-virtio-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/*
+ * Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ */
+
+/ {
+	virtio: virtio-net@40400000 {
+		compatible = "virtio,mmio";
+		reg = <0x40400000 0x10000>;
+		interrupts = <145>;
+	};
+};
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
deleted file mode 100644
index 74e95dcbc6b..00000000000
--- a/arch/arm/dts/corstone1000.dtsi
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 or MIT
-/*
- * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
- * Copyright (c) 2022, Linaro Limited. All rights reserved.
- *
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	interrupt-parent = <&gic>;
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	cpus: cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0>;
-			next-level-cache = <&L2_0>;
-		};
-	};
-
-	memory@88200000 {
-		device_type = "memory";
-		reg = <0x88200000 0x77e00000>;
-	};
-
-	nvmxip: nvmxip-qspi@08000000 {
-		compatible = "nvmxip,qspi";
-		reg = <0x08000000 0x2000000>;
-		lba_shift = <9>;
-		lba = <65536>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		smem_mem: smem_region@88000000 {
-			reg = <0x0 0x88000000 0x0 0x100000>;
-			no-map;
-		};
-	};
-
-	gic: interrupt-controller@1c000000 {
-		compatible = "arm,gic-400";
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-		interrupt-controller;
-		reg =	<0x1c010000 0x1000>,
-			<0x1c02f000 0x2000>,
-			<0x1c04f000 0x1000>,
-			<0x1c06f000 0x2000>;
-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
-			      IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	L2_0: l2-cache0 {
-		compatible = "cache";
-		cache-level = <2>;
-		cache-size = <0x80000>;
-		cache-line-size = <64>;
-		cache-sets = <1024>;
-	};
-
-	refclk100mhz: refclk100mhz {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-		clock-output-names = "apb_pclk";
-	};
-
-	smbclk: refclk24mhzx2 {
-		/* Reference 24MHz clock x 2 */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <48000000>;
-		clock-output-names = "smclk";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts =	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
-				 IRQ_TYPE_LEVEL_LOW)>,
-				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
-				 IRQ_TYPE_LEVEL_LOW)>,
-				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
-				 IRQ_TYPE_LEVEL_LOW)>,
-				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
-				 IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	uartclk: uartclk {
-		/* UART clock - 50MHz */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <50000000>;
-		clock-output-names = "uartclk";
-	};
-
-	psci {
-		compatible = "arm,psci-1.0", "arm,psci-0.2";
-		method = "smc";
-	};
-
-	fwu-mdata {
-		compatible = "u-boot,fwu-mdata-gpt";
-		fwu-mdata-store = <&nvmxip>;
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		interrupt-parent = <&gic>;
-		ranges;
-
-		extsys0: remoteproc@1a010310 {
-			compatible = "arm,corstone1000-extsys";
-			reg = <0x1a010310 0x4>, <0x1a010314 0x4>;
-			reg-names = "reset-control", "reset-status";
-			firmware-name = "es_flashfw.elf";
-		};
-
-		timer@1a220000 {
-			compatible = "arm,armv7-timer-mem";
-			reg = <0x1a220000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			clock-frequency = <50000000>;
-			ranges;
-
-			frame@1a230000 {
-				frame-number = <0>;
-				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-				reg = <0x1a230000 0x1000>;
-			};
-		};
-
-		uart0: serial@1a510000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x1a510000 0x1000>;
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uartclk>, <&refclk100mhz>;
-			clock-names = "uartclk", "apb_pclk";
-		};
-
-		uart1: serial@1a520000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0x1a520000 0x1000>;
-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&uartclk>, <&refclk100mhz>;
-			clock-names = "uartclk", "apb_pclk";
-		};
-
-		mhu_hse1: mailbox@1b820000 {
-			compatible = "arm,mhuv2-tx", "arm,primecell";
-			reg = <0x1b820000 0x1000>;
-			clocks = <&refclk100mhz>;
-			clock-names = "apb_pclk";
-			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-			#mbox-cells = <2>;
-			arm,mhuv2-protocols = <0 0>;
-			secure-status = "okay";     /* secure-world-only */
-			status = "disabled";
-		};
-
-		mhu_seh1: mailbox@1b830000 {
-			compatible = "arm,mhuv2-rx", "arm,primecell";
-			reg = <0x1b830000 0x1000>;
-			clocks = <&refclk100mhz>;
-			clock-names = "apb_pclk";
-			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			#mbox-cells = <2>;
-			arm,mhuv2-protocols = <0 0>;
-			secure-status = "okay";     /* secure-world-only */
-			status = "disabled";
-		};
-	};
-};
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
index 1b9c3a9ed16..db8919298e1 100644
--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -264,7 +264,7 @@ struct mm_region *mem_map = corstone1000_mem_map;
 int board_init(void)
 {
 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
-	if (!strcmp(DEVICE_TREE, "corstone1000-fvp"))
+	if (!strcmp(DEVICE_TREE, "arm/corstone1000-fvp"))
 		update_info.images = fw_fvp_images;
 	else
 		update_info.images = fw_mps3_images;
@@ -396,7 +396,7 @@ int board_late_init(void)
 	const char *cmp_dtb = DEVICE_TREE;
 	int ret;
 
-	if (!strcmp(cmp_dtb, "corstone1000-fvp")) {
+	if (!strcmp(cmp_dtb, "arm/corstone1000-fvp")) {
 		ret = uclass_first_device_err(UCLASS_VIRTIO, &virtio_bus);
 		if (!virtio_bus) {
 			log_err("Cannot find virtio device, err (%d)\n", ret);
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 450d69762ab..350607892fa 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3"
+CONFIG_DEFAULT_DEVICE_TREE="arm/corstone1000-mps3"
 CONFIG_SYS_BOOTM_LEN=0x800000
 CONFIG_SYS_LOAD_ADDR=0x82100000
 CONFIG_IDENT_STRING=" corstone1000 aarch64 "
@@ -55,6 +55,9 @@ CONFIG_CMD_RTC=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_GETTIME=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
+CONFIG_OF_UPSTREAM_VENDOR="arm"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y

