From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001
From: sahil <sahil@arm.com>
Date: Mon, 2 May 2022 17:43:17 +0530
Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region

Enable SCP QSPI flash region access by adding it in the PlatformLibMem

Upstream-Status: Pending
Signed-off-by: Xueliang Zhong <xueliang.zhong@arm.com>
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005
---
 Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h         | 4 ++++
 .../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c    | 8 +++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
index 4966011e..c7219136 100644
--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
@@ -41,6 +41,10 @@
 #define NEOVERSEN1SOC_EXP_PERIPH_BASE0               0x1C000000
 #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ            0x1300000
 
+// SCP QSPI flash device
+#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE              0x18000000
+#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ                0x2000000
+
 /*
  * Platform information structure stored in Non-secure SRAM. Platform
  * information are passed from the trusted firmware with the below structure
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 5cacd437..8bb94074 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -15,7 +15,7 @@
 #include <NeoverseN1Soc.h>
 
 // The total number of descriptors, including the final "end-of-table" descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20
 
 /** A helper function to locate the NtFwConfig PPI and get the base address of
   NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
@@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length          = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ;
   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
+  // SCP QSPI flash device
+  VirtualMemoryTable[++Index].PhysicalBase  = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
+  VirtualMemoryTable[Index].VirtualBase     = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE;
+  VirtualMemoryTable[Index].Length          = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ;
+  VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
   if (PlatInfo->MultichipMode == 1) {
     //Remote DDR (2GB)
     VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdExtMemorySpace) +
