From 33d8f45c8f14e9e0d7add7d2804ed76c7d7fd0c2 Mon Sep 17 00:00:00 2001
From: Emekcan Aras <emekcan.aras@arm.com>
Date: Sat, 25 Feb 2023 09:04:38 +0000
Subject: [PATCH 1/7] Platform: corstone1000: Add watchdog_reset_timer

From: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>

Implement watchdog_reset_timer

Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/20552]
Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
Change-Id: I2684ca54f9a456b22efcbcd364abef3537d4c91f
---
 .../arm/corstone1000/Native_Driver/watchdog.c   | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
index 4e024a3b1..f6e182194 100644
--- a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
@@ -80,6 +80,23 @@ int corstone1000_watchdog_init()
     return ARM_DRIVER_OK;
 }
 
+/**
+ *  \brief Reset the Secure Enclave & SoC Watchdog's.
+ *
+ *  \returns ARM Driver return code.
+ */
+int corstone1000_watchdog_reset_timer() {
+    /* Unlock, clear and lock the watchdog timer */
+    arm_watchdog_unlock(&SE_WD_DEV);
+    arm_watchdog_clear_interrupt_and_refresh_counter(&SE_WD_DEV);
+    arm_watchdog_lock(&SE_WD_DEV);
+    /* Unlock, clear and lock the watchdog timer */
+    arm_watchdog_unlock(&SOC_WD_DEV);
+    arm_watchdog_clear_interrupt_and_refresh_counter(&SOC_WD_DEV);
+    arm_watchdog_lock(&SOC_WD_DEV);
+    return ARM_DRIVER_OK;
+}
+
 /*
  * Secure Host Watchdog WS1 Handler
  * efi_reset_system from the host triggers "Secure
-- 
2.17.1

