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https://git.yoctoproject.org/meta-arm
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arm-bsp/u-boot: corstone1000: enable OF_UPSTREAM device tree support
Enable OF_UPSTREAM support for the corstone1000 platforms in U-Boot. This patchset enables OF_UPSTREAM device tree support in U-Boot for the corstone1000 platforms. This allows U-Boot to build using upstream Linux kernel device tree sources instead of downstream copies. The following changes are introduced: - Enable OF_UPSTREAM to support upstream device tree. - Update DEVICE_TREE naming with "arm/" prefix. - Add device tree overlay to retain U-Boot specific device tree nodes. - Remove legacy device trees for corstone1000. Signed-off-by: Clement Faure <clement.faure@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Clement Faure
Jon Mason
@@ -1,8 +1,8 @@
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# Corstone1000 specific U-boot support
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DEPENDS:append = " openssl-native efitools-native"
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CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "corstone1000-mps3"
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CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "corstone1000-fvp"
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CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "arm/corstone1000-mps3"
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CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "arm/corstone1000-fvp"
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EXTRA_OEMAKE:append = ' DEVICE_TREE=${CORSTONE1000_DEVICE_TREE}'
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UBOOT_CONFIG ??= "EFI"
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@@ -64,6 +64,11 @@ SRC_URI:append = " \
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'', 'file://0037-corstone1000-purge-remoteproc-DTS-node.patch' , d)} \
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"
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# Add OF_UPSTREAM support
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SRC_URI:append = " \
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file://0038-corstone1000-enable-OF_UPSTREAM-device-tree-support.patch \
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"
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do_configure:append() {
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openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ -keyout ${B}/CRT.key -out ${B}/corstone1000_defconfig/CRT.crt -nodes -days 365
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}
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@@ -0,0 +1,525 @@
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From 59fb1656586228bb2e2fdaf1de65b1f7aabc508e Mon Sep 17 00:00:00 2001
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From: Clement Faure <clement.faure@arm.com>
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Date: Wed, 11 Jun 2025 08:38:21 +0000
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Subject: [PATCH] corstone1000: enable OF_UPSTREAM device tree support
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Enable OF_UPSTREAM option set for corstone1000 platform. Remove
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legacy u-boot corstone1000 device trees.
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Add device tree files for FVP and MPS3 platforms to add device
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tree nodes that are missing from the upstream.
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Upstream-Status: Pending [Not submitted to upstream yet]
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Signed-off-by: Clement Faure <clement.faure@arm.com>
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---
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arch/arm/dts/Makefile | 3 -
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arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 42 +++++
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arch/arm/dts/corstone1000-fvp.dts | 82 ---------
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arch/arm/dts/corstone1000-mps3-u-boot.dtsi | 8 +
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arch/arm/dts/corstone1000-mps3.dts | 32 ----
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arch/arm/dts/corstone1000-u-boot.dtsi | 39 +++++
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arch/arm/dts/corstone1000.dtsi | 194 ---------------------
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board/armltd/corstone1000/corstone1000.c | 4 +-
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configs/corstone1000_defconfig | 5 +-
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9 files changed, 95 insertions(+), 314 deletions(-)
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create mode 100644 arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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delete mode 100644 arch/arm/dts/corstone1000-fvp.dts
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create mode 100644 arch/arm/dts/corstone1000-mps3-u-boot.dtsi
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delete mode 100644 arch/arm/dts/corstone1000-mps3.dts
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create mode 100644 arch/arm/dts/corstone1000-u-boot.dtsi
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delete mode 100644 arch/arm/dts/corstone1000.dtsi
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diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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index 267b0179a5f..a595983f1d0 100644
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -1221,9 +1221,6 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
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dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
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-dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
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- corstone1000-fvp.dtb
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-
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dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
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include $(srctree)/scripts/Makefile.dts
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diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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new file mode 100644
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index 00000000000..6b89d653417
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--- /dev/null
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+++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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@@ -0,0 +1,42 @@
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+// SPDX-License-Identifier: GPL-2.0 or MIT
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+/*
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+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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+ *
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+ */
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+
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+#include "corstone1000-u-boot.dtsi"
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+
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+/ {
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+ virtio: virtio-net@40400000 {
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+ compatible = "virtio,mmio";
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+ reg = <0x40400000 0x10000>;
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+ interrupts = <145>;
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+ };
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+};
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+
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+&{/cpus} {
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35";
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+ reg = <0x1>;
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+ enable-method = "psci";
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+ next-level-cache = <&L2_0>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35";
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+ reg = <0x2>;
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+ enable-method = "psci";
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+ next-level-cache = <&L2_0>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35";
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+ reg = <0x3>;
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+ enable-method = "psci";
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+ next-level-cache = <&L2_0>;
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+ };
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+};
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+
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diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
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deleted file mode 100644
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index cd8a132271e..00000000000
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--- a/arch/arm/dts/corstone1000-fvp.dts
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+++ /dev/null
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@@ -1,82 +0,0 @@
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-// SPDX-License-Identifier: GPL-2.0 or MIT
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-/*
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- * Copyright (c) 2022, Arm Limited. All rights reserved.
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- * Copyright (c) 2022, Linaro Limited. All rights reserved.
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- *
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- */
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-
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-/dts-v1/;
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-
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-#include "corstone1000.dtsi"
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-
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-/ {
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- model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
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- compatible = "arm,corstone1000-fvp";
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-
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- smsc: ethernet@4010000 {
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- compatible = "smsc,lan91c111";
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- reg = <0x40100000 0x10000>;
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- phy-mode = "mii";
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- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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- reg-io-width = <2>;
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- };
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-
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- virtio: virtio-net@40400000 {
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- compatible = "virtio,mmio";
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- reg = <0x40400000 0x10000>;
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- interrupts = <145>;
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- };
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-
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- vmmc_v3_3d: fixed_v3_3d {
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- compatible = "regulator-fixed";
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- regulator-name = "vmmc_supply";
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- regulator-min-microvolt = <3300000>;
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- regulator-max-microvolt = <3300000>;
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- regulator-always-on;
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- };
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-
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- sdmmc0: mmc@40300000 {
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- compatible = "arm,pl18x", "arm,primecell";
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- reg = <0x40300000 0x1000>;
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- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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- max-frequency = <12000000>;
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- vmmc-supply = <&vmmc_v3_3d>;
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- clocks = <&smbclk>, <&refclk100mhz>;
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- clock-names = "smclk", "apb_pclk";
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- };
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-
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- sdmmc1: mmc@50000000 {
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- compatible = "arm,pl18x", "arm,primecell";
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- reg = <0x50000000 0x10000>;
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- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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- max-frequency = <12000000>;
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- vmmc-supply = <&vmmc_v3_3d>;
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- clocks = <&smbclk>, <&refclk100mhz>;
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- clock-names = "smclk", "apb_pclk";
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- };
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-};
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-
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-&cpus {
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- cpu1: cpu@1 {
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- device_type = "cpu";
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- compatible = "arm,cortex-a35";
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- reg = <0x1>;
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- enable-method = "psci";
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- next-level-cache = <&L2_0>;
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- };
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- cpu2: cpu@2 {
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- device_type = "cpu";
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- compatible = "arm,cortex-a35";
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- reg = <0x2>;
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- enable-method = "psci";
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- next-level-cache = <&L2_0>;
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- };
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- cpu3: cpu@3 {
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- device_type = "cpu";
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- compatible = "arm,cortex-a35";
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- reg = <0x3>;
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- enable-method = "psci";
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- next-level-cache = <&L2_0>;
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- };
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-};
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-
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diff --git a/arch/arm/dts/corstone1000-mps3-u-boot.dtsi b/arch/arm/dts/corstone1000-mps3-u-boot.dtsi
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new file mode 100644
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index 00000000000..9ab744d8d20
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--- /dev/null
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+++ b/arch/arm/dts/corstone1000-mps3-u-boot.dtsi
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@@ -0,0 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0 or MIT
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+/*
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+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
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+ *
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+ */
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+
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+#include "corstone1000-u-boot.dtsi"
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+
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diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts
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deleted file mode 100644
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index e3146747c2d..00000000000
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--- a/arch/arm/dts/corstone1000-mps3.dts
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+++ /dev/null
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@@ -1,32 +0,0 @@
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-// SPDX-License-Identifier: GPL-2.0 or MIT
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-/*
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- * Copyright (c) 2022, Arm Limited. All rights reserved.
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- * Copyright (c) 2022, Linaro Limited. All rights reserved.
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- *
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- */
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-
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-/dts-v1/;
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-
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-#include "corstone1000.dtsi"
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-
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-/ {
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- model = "ARM Corstone1000 FPGA MPS3 board";
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- compatible = "arm,corstone1000-mps3";
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-
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- smsc: ethernet@4010000 {
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- compatible = "smsc,lan9220", "smsc,lan9115";
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- reg = <0x40100000 0x10000>;
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- phy-mode = "mii";
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- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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- reg-io-width = <2>;
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- smsc,irq-push-pull;
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- };
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-
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- usb_host: usb@40200000 {
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- compatible = "nxp,usb-isp1763";
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- reg = <0x40200000 0x100000>;
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- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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- bus-width = <16>;
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- dr_mode = "host";
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- };
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-};
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diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi
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new file mode 100644
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index 00000000000..95dd277d4cc
|
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--- /dev/null
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+++ b/arch/arm/dts/corstone1000-u-boot.dtsi
|
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@@ -0,0 +1,39 @@
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+// SPDX-License-Identifier: GPL-2.0 or MIT
|
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+/*
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+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
+ *
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||||
+ */
|
||||
+
|
||||
+/ {
|
||||
+ nvmxip: nvmxip-qspi@08000000 {
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+ compatible = "nvmxip,qspi";
|
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+ reg = <0x08000000 0x2000000>;
|
||||
+ lba_shift = <9>;
|
||||
+ lba = <65536>;
|
||||
+ };
|
||||
+
|
||||
+ fwu-mdata {
|
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+ compatible = "u-boot,fwu-mdata-gpt";
|
||||
+ fwu-mdata-store = <&nvmxip>;
|
||||
+ };
|
||||
+
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+
|
||||
+ smem_mem: smem_region@88000000 {
|
||||
+ reg = <0x0 0x88000000 0x0 0x100000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&{/soc} {
|
||||
+ extsys0: remoteproc@1a010310 {
|
||||
+ compatible = "arm,corstone1000-extsys";
|
||||
+ reg = <0x1a010310 0x4>, <0x1a010314 0x4>;
|
||||
+ reg-names = "reset-control", "reset-status";
|
||||
+ firmware-name = "es_flashfw.elf";
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
|
||||
deleted file mode 100644
|
||||
index 74e95dcbc6b..00000000000
|
||||
--- a/arch/arm/dts/corstone1000.dtsi
|
||||
+++ /dev/null
|
||||
@@ -1,194 +0,0 @@
|
||||
-// SPDX-License-Identifier: GPL-2.0 or MIT
|
||||
-/*
|
||||
- * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||
- * Copyright (c) 2022, Linaro Limited. All rights reserved.
|
||||
- *
|
||||
- */
|
||||
-
|
||||
-#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
-
|
||||
-/ {
|
||||
- interrupt-parent = <&gic>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
-
|
||||
- aliases {
|
||||
- serial0 = &uart0;
|
||||
- serial1 = &uart1;
|
||||
- };
|
||||
-
|
||||
- chosen {
|
||||
- stdout-path = "serial0:115200n8";
|
||||
- };
|
||||
-
|
||||
- cpus: cpus {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
-
|
||||
- cpu: cpu@0 {
|
||||
- device_type = "cpu";
|
||||
- compatible = "arm,cortex-a35";
|
||||
- reg = <0>;
|
||||
- next-level-cache = <&L2_0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- memory@88200000 {
|
||||
- device_type = "memory";
|
||||
- reg = <0x88200000 0x77e00000>;
|
||||
- };
|
||||
-
|
||||
- nvmxip: nvmxip-qspi@08000000 {
|
||||
- compatible = "nvmxip,qspi";
|
||||
- reg = <0x08000000 0x2000000>;
|
||||
- lba_shift = <9>;
|
||||
- lba = <65536>;
|
||||
- };
|
||||
-
|
||||
- reserved-memory {
|
||||
- #address-cells = <2>;
|
||||
- #size-cells = <2>;
|
||||
- ranges;
|
||||
-
|
||||
- smem_mem: smem_region@88000000 {
|
||||
- reg = <0x0 0x88000000 0x0 0x100000>;
|
||||
- no-map;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- gic: interrupt-controller@1c000000 {
|
||||
- compatible = "arm,gic-400";
|
||||
- #interrupt-cells = <3>;
|
||||
- #address-cells = <0>;
|
||||
- interrupt-controller;
|
||||
- reg = <0x1c010000 0x1000>,
|
||||
- <0x1c02f000 0x2000>,
|
||||
- <0x1c04f000 0x1000>,
|
||||
- <0x1c06f000 0x2000>;
|
||||
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
- IRQ_TYPE_LEVEL_LOW)>;
|
||||
- };
|
||||
-
|
||||
- L2_0: l2-cache0 {
|
||||
- compatible = "cache";
|
||||
- cache-level = <2>;
|
||||
- cache-size = <0x80000>;
|
||||
- cache-line-size = <64>;
|
||||
- cache-sets = <1024>;
|
||||
- };
|
||||
-
|
||||
- refclk100mhz: refclk100mhz {
|
||||
- compatible = "fixed-clock";
|
||||
- #clock-cells = <0>;
|
||||
- clock-frequency = <100000000>;
|
||||
- clock-output-names = "apb_pclk";
|
||||
- };
|
||||
-
|
||||
- smbclk: refclk24mhzx2 {
|
||||
- /* Reference 24MHz clock x 2 */
|
||||
- compatible = "fixed-clock";
|
||||
- #clock-cells = <0>;
|
||||
- clock-frequency = <48000000>;
|
||||
- clock-output-names = "smclk";
|
||||
- };
|
||||
-
|
||||
- timer {
|
||||
- compatible = "arm,armv8-timer";
|
||||
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
- IRQ_TYPE_LEVEL_LOW)>,
|
||||
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
- IRQ_TYPE_LEVEL_LOW)>,
|
||||
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
- IRQ_TYPE_LEVEL_LOW)>,
|
||||
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
- IRQ_TYPE_LEVEL_LOW)>;
|
||||
- };
|
||||
-
|
||||
- uartclk: uartclk {
|
||||
- /* UART clock - 50MHz */
|
||||
- compatible = "fixed-clock";
|
||||
- #clock-cells = <0>;
|
||||
- clock-frequency = <50000000>;
|
||||
- clock-output-names = "uartclk";
|
||||
- };
|
||||
-
|
||||
- psci {
|
||||
- compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
- method = "smc";
|
||||
- };
|
||||
-
|
||||
- fwu-mdata {
|
||||
- compatible = "u-boot,fwu-mdata-gpt";
|
||||
- fwu-mdata-store = <&nvmxip>;
|
||||
- };
|
||||
-
|
||||
- soc {
|
||||
- compatible = "simple-bus";
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- interrupt-parent = <&gic>;
|
||||
- ranges;
|
||||
-
|
||||
- extsys0: remoteproc@1a010310 {
|
||||
- compatible = "arm,corstone1000-extsys";
|
||||
- reg = <0x1a010310 0x4>, <0x1a010314 0x4>;
|
||||
- reg-names = "reset-control", "reset-status";
|
||||
- firmware-name = "es_flashfw.elf";
|
||||
- };
|
||||
-
|
||||
- timer@1a220000 {
|
||||
- compatible = "arm,armv7-timer-mem";
|
||||
- reg = <0x1a220000 0x1000>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- clock-frequency = <50000000>;
|
||||
- ranges;
|
||||
-
|
||||
- frame@1a230000 {
|
||||
- frame-number = <0>;
|
||||
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- reg = <0x1a230000 0x1000>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- uart0: serial@1a510000 {
|
||||
- compatible = "arm,pl011", "arm,primecell";
|
||||
- reg = <0x1a510000 0x1000>;
|
||||
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&uartclk>, <&refclk100mhz>;
|
||||
- clock-names = "uartclk", "apb_pclk";
|
||||
- };
|
||||
-
|
||||
- uart1: serial@1a520000 {
|
||||
- compatible = "arm,pl011", "arm,primecell";
|
||||
- reg = <0x1a520000 0x1000>;
|
||||
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&uartclk>, <&refclk100mhz>;
|
||||
- clock-names = "uartclk", "apb_pclk";
|
||||
- };
|
||||
-
|
||||
- mhu_hse1: mailbox@1b820000 {
|
||||
- compatible = "arm,mhuv2-tx", "arm,primecell";
|
||||
- reg = <0x1b820000 0x1000>;
|
||||
- clocks = <&refclk100mhz>;
|
||||
- clock-names = "apb_pclk";
|
||||
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- #mbox-cells = <2>;
|
||||
- arm,mhuv2-protocols = <0 0>;
|
||||
- secure-status = "okay"; /* secure-world-only */
|
||||
- status = "disabled";
|
||||
- };
|
||||
-
|
||||
- mhu_seh1: mailbox@1b830000 {
|
||||
- compatible = "arm,mhuv2-rx", "arm,primecell";
|
||||
- reg = <0x1b830000 0x1000>;
|
||||
- clocks = <&refclk100mhz>;
|
||||
- clock-names = "apb_pclk";
|
||||
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- #mbox-cells = <2>;
|
||||
- arm,mhuv2-protocols = <0 0>;
|
||||
- secure-status = "okay"; /* secure-world-only */
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-};
|
||||
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
|
||||
index 1b9c3a9ed16..db8919298e1 100644
|
||||
--- a/board/armltd/corstone1000/corstone1000.c
|
||||
+++ b/board/armltd/corstone1000/corstone1000.c
|
||||
@@ -264,7 +264,7 @@ struct mm_region *mem_map = corstone1000_mem_map;
|
||||
int board_init(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
|
||||
- if (!strcmp(DEVICE_TREE, "corstone1000-fvp"))
|
||||
+ if (!strcmp(DEVICE_TREE, "arm/corstone1000-fvp"))
|
||||
update_info.images = fw_fvp_images;
|
||||
else
|
||||
update_info.images = fw_mps3_images;
|
||||
@@ -396,7 +396,7 @@ int board_late_init(void)
|
||||
const char *cmp_dtb = DEVICE_TREE;
|
||||
int ret;
|
||||
|
||||
- if (!strcmp(cmp_dtb, "corstone1000-fvp")) {
|
||||
+ if (!strcmp(cmp_dtb, "arm/corstone1000-fvp")) {
|
||||
ret = uclass_first_device_err(UCLASS_VIRTIO, &virtio_bus);
|
||||
if (!virtio_bus) {
|
||||
log_err("Cannot find virtio device, err (%d)\n", ret);
|
||||
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
|
||||
index d1401550660..34c0c7cb172 100644
|
||||
--- a/configs/corstone1000_defconfig
|
||||
+++ b/configs/corstone1000_defconfig
|
||||
@@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
|
||||
CONFIG_DM_GPIO=y
|
||||
-CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3"
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="arm/corstone1000-mps3"
|
||||
CONFIG_SYS_BOOTM_LEN=0x800000
|
||||
CONFIG_SYS_LOAD_ADDR=0x82100000
|
||||
CONFIG_IDENT_STRING=" corstone1000 aarch64 "
|
||||
@@ -55,6 +55,9 @@ CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_GETTIME=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
+CONFIG_OF_UPSTREAM=y
|
||||
+CONFIG_OF_UPSTREAM_BUILD_VENDOR=y
|
||||
+CONFIG_OF_UPSTREAM_VENDOR="arm"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
--
|
||||
2.43.0
|
||||
|
||||
Reference in New Issue
Block a user