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arm/hafnium: update to v2.9
Updating to the latest version of hafnium. Also, dropping tc patches, as they are either experimental or a similar feature has been added. Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Jon Mason
-249
@@ -1,249 +0,0 @@
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From 3bc797e097ef2b29acf36560e4d2bfeec31f8d81 Mon Sep 17 00:00:00 2001
|
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From: Ben Horgan <ben.horgan@arm.com>
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Date: Fri, 4 Mar 2022 16:48:14 +0000
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Subject: [PATCH] feat: emulate cntp timer register accesses using cnthps
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Upstream-Status: Inappropriate [Experimental feature]
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Signed-off-by: Ben Horgan <ben.horgan@arm.com>
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Change-Id: I67508203273baf3bd8e6be2d99717028db945715
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---
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Makefile | 3 +-
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src/arch/aarch64/hypervisor/BUILD.gn | 1 +
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src/arch/aarch64/hypervisor/cpu.c | 11 ++-
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src/arch/aarch64/hypervisor/handler.c | 6 ++
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src/arch/aarch64/hypervisor/timer_el1.c | 104 ++++++++++++++++++++++++
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src/arch/aarch64/hypervisor/timer_el1.h | 20 +++++
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src/arch/aarch64/msr.h | 8 ++
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7 files changed, 150 insertions(+), 3 deletions(-)
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create mode 100644 src/arch/aarch64/hypervisor/timer_el1.c
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create mode 100644 src/arch/aarch64/hypervisor/timer_el1.h
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diff --git a/Makefile b/Makefile
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index 95cab9a56bfd..21cca938531d 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -60,7 +60,8 @@ CHECKPATCH := $(CURDIR)/third_party/linux/scripts/checkpatch.pl \
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# debug_el1.c : uses XMACROS, which checkpatch doesn't understand.
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# perfmon.c : uses XMACROS, which checkpatch doesn't understand.
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# feature_id.c : uses XMACROS, which checkpatch doesn't understand.
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-CHECKPATCH_IGNORE := "src/arch/aarch64/hypervisor/debug_el1.c\|src/arch/aarch64/hypervisor/perfmon.c\|src/arch/aarch64/hypervisor/feature_id.c"
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+# timer_el1.c : uses XMACROS, which checkpatch doesn't understand.
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+CHECKPATCH_IGNORE := "src/arch/aarch64/hypervisor/debug_el1.c\|src/arch/aarch64/hypervisor/perfmon.c\|src/arch/aarch64/hypervisor/feature_id.c\|src/arch/aarch64/hypervisor/timer_el1.c"
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OUT ?= out/$(PROJECT)
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OUT_DIR = out/$(PROJECT)
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diff --git a/src/arch/aarch64/hypervisor/BUILD.gn b/src/arch/aarch64/hypervisor/BUILD.gn
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index 6068d1e8f075..de1a414dac68 100644
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--- a/src/arch/aarch64/hypervisor/BUILD.gn
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+++ b/src/arch/aarch64/hypervisor/BUILD.gn
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@@ -45,6 +45,7 @@ source_set("hypervisor") {
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"handler.c",
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"perfmon.c",
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"psci_handler.c",
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+ "timer_el1.c",
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"vm.c",
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]
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diff --git a/src/arch/aarch64/hypervisor/cpu.c b/src/arch/aarch64/hypervisor/cpu.c
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index 5e025b596674..edd5df134cfc 100644
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--- a/src/arch/aarch64/hypervisor/cpu.c
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+++ b/src/arch/aarch64/hypervisor/cpu.c
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@@ -98,13 +98,20 @@ void arch_regs_reset(struct vcpu *vcpu)
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if (is_primary) {
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/*
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* cnthctl_el2 is redefined when VHE is enabled.
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- * EL1PCTEN, don't trap phys cnt access.
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- * EL1PCEN, don't trap phys timer access.
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+ * EL1PCTEN, don't trap phys cnt access. Except when in
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+ * secure world without vhe.
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+ * EL1PCEN, don't trap phys timer access. Except when in
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+ * secure world without vhe.
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*/
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if (has_vhe_support()) {
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cnthctl |= (1U << 10) | (1U << 11);
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} else {
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+#if SECURE_WORLD == 1
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+ cnthctl &= ~(1U << 0);
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+ cnthctl &= ~(1U << 1);
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+#else
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cnthctl |= (1U << 0) | (1U << 1);
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+#endif
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}
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}
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diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c
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index 3422ff7b8265..c495df40f3f5 100644
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--- a/src/arch/aarch64/hypervisor/handler.c
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+++ b/src/arch/aarch64/hypervisor/handler.c
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@@ -34,6 +34,7 @@
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#include "psci_handler.h"
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#include "smc.h"
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#include "sysregs.h"
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+#include "timer_el1.h"
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/**
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* Hypervisor Fault Address Register Non-Secure.
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@@ -1295,6 +1296,11 @@ void handle_system_register_access(uintreg_t esr_el2)
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inject_el1_sysreg_trap_exception(vcpu, esr_el2);
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return;
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}
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+ } else if (timer_el1_is_register_access(esr_el2)) {
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+ if (!timer_el1_process_access(vcpu, vm_id, esr_el2)) {
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+ inject_el1_unknown_exception(vcpu, esr_el2);
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+ return;
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+ }
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} else {
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inject_el1_sysreg_trap_exception(vcpu, esr_el2);
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return;
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diff --git a/src/arch/aarch64/hypervisor/timer_el1.c b/src/arch/aarch64/hypervisor/timer_el1.c
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new file mode 100644
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index 000000000000..c30e5543f436
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--- /dev/null
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+++ b/src/arch/aarch64/hypervisor/timer_el1.c
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@@ -0,0 +1,104 @@
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+/*
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+ * Copyright 2022 The Hafnium Authors.
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+ *
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+ * Use of this source code is governed by a BSD-style
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+ * license that can be found in the LICENSE file or at
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+ * https://opensource.org/licenses/BSD-3-Clause.
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+ */
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+
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+#include "timer_el1.h"
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+
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+#include "hf/dlog.h"
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+
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+#include "msr.h"
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+#include "sysregs.h"
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+
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+/*
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+ * Physical timer (CNTP) register encodings as defined in
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+ * table D13-8 of the ARMv8 ARM (DDI0487F).
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+ * TYPE, op0, op1, crn, crm, op2
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+ * The register names are the concatenation of
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+ * "CNTP_", TYPE and "_EL2".
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+ */
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+#define CNTP_REGISTERS \
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+ X(CTL, 3, 3, 14, 2, 1) \
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+ X(CVAL, 3, 3, 14, 2, 2) \
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+ X(TVAL, 3, 3, 14, 2, 0) \
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+
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+bool timer_el1_is_register_access(uintreg_t esr)
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+{
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+ uintreg_t sys_register = GET_ISS_SYSREG(esr);
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+ bool is_timer_access;
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+ switch (sys_register) {
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+#define X(type, op0, op1, crn, crm, op2) \
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+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
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+ is_timer_access = true; \
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+ break;
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+ CNTP_REGISTERS
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+#undef X
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+ case (GET_ISS_ENCODING(3, 3, 14, 0, 1)):
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+ is_timer_access = true;
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+ break;
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+ default:
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+ is_timer_access = false;
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+ }
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+
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+ return is_timer_access;
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+}
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+
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+/* Accesses to CNTP timer emulated with CNTHPS */
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+bool timer_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
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+ uintreg_t esr)
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+{
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+ uintreg_t sys_register = GET_ISS_SYSREG(esr);
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+ uintreg_t rt_register = GET_ISS_RT(esr);
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+ uintreg_t value;
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+
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+ if (ISS_IS_READ(esr)) {
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+ switch (sys_register) {
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+#define X(type, op0, op1, crn, crm, op2) \
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+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
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+ value = read_msr(MSR_CNTHPS_##type##_EL2); \
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+ vcpu->regs.r[rt_register] = value; \
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+ break;
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+ CNTP_REGISTERS
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+#undef X
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+ case (GET_ISS_ENCODING(3, 3, 14, 0, 1)):
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+ value = read_msr(cntpct_el0);
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+ vcpu->regs.r[rt_register] = value;
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+ break;
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+ default:
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+ dlog_notice(
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+ "Unsupported timer register "
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+ "read: "
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+ "op0=%d, op1=%d, crn=%d, crm=%d, op2=%d, "
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+ "rt=%d.\n",
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+ GET_ISS_OP0(esr), GET_ISS_OP1(esr),
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+ GET_ISS_CRN(esr), GET_ISS_CRM(esr),
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+ GET_ISS_OP2(esr), GET_ISS_RT(esr));
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+ break;
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+ }
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+ } else {
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+ value = vcpu->regs.r[rt_register];
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+ switch (sys_register) {
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+#define X(type, op0, op1, crn, crm, op2) \
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+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
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+ write_msr(MSR_CNTHPS_##type##_EL2, value); \
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+ break;
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+ CNTP_REGISTERS
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+#undef X
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+ default:
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+ dlog_notice(
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+ "Unsupported timer register "
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+ "write: "
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+ "op0=%d, op1=%d, crn=%d, crm=%d, op2=%d, "
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+ "rt=%d, value=%d.\n",
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+ GET_ISS_OP0(esr), GET_ISS_OP1(esr),
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+ GET_ISS_CRN(esr), GET_ISS_CRM(esr),
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+ GET_ISS_OP2(esr), GET_ISS_RT(esr), value);
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+ break;
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+ }
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+ }
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+
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+ return true;
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+}
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diff --git a/src/arch/aarch64/hypervisor/timer_el1.h b/src/arch/aarch64/hypervisor/timer_el1.h
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new file mode 100644
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index 000000000000..04a43b6ca335
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--- /dev/null
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+++ b/src/arch/aarch64/hypervisor/timer_el1.h
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@@ -0,0 +1,20 @@
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+/*
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+ * Copyright 2022 The Hafnium Authors.
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+ *
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+ * Use of this source code is governed by a BSD-style
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+ * license that can be found in the LICENSE file or at
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+ * https://opensource.org/licenses/BSD-3-Clause.
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+ */
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+
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+#pragma once
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+
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+#include "hf/arch/types.h"
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+
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+#include "hf/cpu.h"
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+
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+#include "vmapi/hf/ffa.h"
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+
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+bool timer_el1_is_register_access(uintreg_t esr);
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+
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+bool timer_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
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+ uintreg_t esr);
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diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
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index 6edc39f2af48..bf1a66d1d4c5 100644
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--- a/src/arch/aarch64/msr.h
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+++ b/src/arch/aarch64/msr.h
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@@ -131,3 +131,11 @@
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#define MSR_ELR_EL12 S3_5_C4_C0_1
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|
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#endif
|
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+
|
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+/*
|
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+ * Secure EL2 Physical timer (CNTHPS) register encodings as defined in
|
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+ * table D13-8 of the ARMv8 ARM (DDI0487F).
|
||||
+ */
|
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+#define MSR_CNTHPS_CTL_EL2 S3_4_C14_C5_1
|
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+#define MSR_CNTHPS_CVAL_EL2 S3_4_C14_C5_2
|
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+#define MSR_CNTHPS_TVAL_EL2 S3_4_C14_C5_0
|
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-32
@@ -1,32 +0,0 @@
|
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From 1fef5bd2504ce3a203c56a3b66dba773cd4893c6 Mon Sep 17 00:00:00 2001
|
||||
From: Davidson K <davidson.kumaresan@arm.com>
|
||||
Date: Thu, 8 Sep 2022 10:47:10 +0530
|
||||
Subject: [PATCH] feat(vhe): enable vhe and disable branch protection for TC
|
||||
|
||||
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
|
||||
Change-Id: I60cd607d9f2bf0114b482980e7ca68e24aaf4d1f
|
||||
Upstream-Status: Pending [Not submitted to upstream yet]
|
||||
---
|
||||
BUILD.gn | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/BUILD.gn b/BUILD.gn
|
||||
index cc6a78f4fdb8..acd1f9d1634b 100644
|
||||
--- a/BUILD.gn
|
||||
+++ b/BUILD.gn
|
||||
@@ -245,7 +245,6 @@ aarch64_toolchains("secure_tc") {
|
||||
heap_pages = 180
|
||||
max_cpus = 8
|
||||
max_vms = 16
|
||||
- branch_protection = "standard"
|
||||
toolchain_args = {
|
||||
plat_ffa = "//src/arch/aarch64/plat/ffa:spmc"
|
||||
plat_psci = "//src/arch/aarch64/plat/psci:spmc"
|
||||
@@ -254,6 +253,7 @@ aarch64_toolchains("secure_tc") {
|
||||
secure_world = "1"
|
||||
pl011_base_address = "0x7ff80000"
|
||||
enable_mte = "1"
|
||||
+ enable_vhe = "1"
|
||||
plat_log_level = "LOG_LEVEL_INFO"
|
||||
}
|
||||
}
|
||||
-156
@@ -1,156 +0,0 @@
|
||||
From 9f5b07e30c82713b9598ea60d9f802bd419b560f Mon Sep 17 00:00:00 2001
|
||||
From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
|
||||
Date: Tue, 26 Apr 2022 14:43:58 +0100
|
||||
Subject: [PATCH] feat: emulate interrupt controller register access
|
||||
|
||||
This emulates ICC_SGI1R_EL1 and ICC_IGRPEN1_EL1 register
|
||||
|
||||
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
|
||||
Change-Id: I0c11f034f3676067597461a183a341c809adcaa4
|
||||
Upstream-Status: Inappropriate [Experimental feature]
|
||||
---
|
||||
src/arch/aarch64/hypervisor/handler.c | 5 ++
|
||||
src/arch/aarch64/hypervisor/perfmon.c | 84 +++++++++++++++++++++++++++
|
||||
src/arch/aarch64/hypervisor/perfmon.h | 5 ++
|
||||
src/arch/aarch64/msr.h | 3 +
|
||||
4 files changed, 97 insertions(+)
|
||||
|
||||
diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c
|
||||
index c495df40f3f5..13578fc99670 100644
|
||||
--- a/src/arch/aarch64/hypervisor/handler.c
|
||||
+++ b/src/arch/aarch64/hypervisor/handler.c
|
||||
@@ -1301,6 +1301,11 @@ void handle_system_register_access(uintreg_t esr_el2)
|
||||
inject_el1_unknown_exception(vcpu, esr_el2);
|
||||
return;
|
||||
}
|
||||
+ } else if (intr_ctrl_is_register_access(esr_el2)) {
|
||||
+ if (!intr_ctrl_el1_process_access(vcpu, vm_id, esr_el2)) {
|
||||
+ inject_el1_unknown_exception(vcpu, esr_el2);
|
||||
+ return;
|
||||
+ }
|
||||
} else {
|
||||
inject_el1_sysreg_trap_exception(vcpu, esr_el2);
|
||||
return;
|
||||
diff --git a/src/arch/aarch64/hypervisor/perfmon.c b/src/arch/aarch64/hypervisor/perfmon.c
|
||||
index f13b035480d8..05e216c84c2e 100644
|
||||
--- a/src/arch/aarch64/hypervisor/perfmon.c
|
||||
+++ b/src/arch/aarch64/hypervisor/perfmon.c
|
||||
@@ -116,6 +116,10 @@
|
||||
X(PMEVTYPER30_EL0 , 3, 3, 14, 15, 6) \
|
||||
X(PMCCFILTR_EL0 , 3, 3, 14, 15, 7)
|
||||
|
||||
+#define INTR_CTRL_REGISTERS \
|
||||
+ X(ICC_IGRPEN1_EL1 , 3, 0, 12, 12, 7) \
|
||||
+ X(ICC_SGI1R_EL1 , 3, 0, 12, 11, 5) \
|
||||
+
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
@@ -232,3 +236,83 @@ uintreg_t perfmon_get_pmccfiltr_el0_init_value(ffa_vm_id_t vm_id)
|
||||
|
||||
return 0;
|
||||
}
|
||||
+
|
||||
+bool intr_ctrl_is_register_access(uintreg_t esr)
|
||||
+{
|
||||
+ uintreg_t op0 = GET_ISS_OP0(esr);
|
||||
+ uintreg_t op1 = GET_ISS_OP1(esr);
|
||||
+ uintreg_t crn = GET_ISS_CRN(esr);
|
||||
+ uintreg_t crm = GET_ISS_CRM(esr);
|
||||
+
|
||||
+ if (op0 == 3 && op1 == 0 && crn == 12 && crm == 12) {
|
||||
+ return true;
|
||||
+ }
|
||||
+
|
||||
+ if (op0 == 3 && op1 == 0 && crn == 12 && crm == 11) {
|
||||
+ return true;
|
||||
+ }
|
||||
+
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
+bool intr_ctrl_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
|
||||
+ uintreg_t esr)
|
||||
+{
|
||||
+ uintreg_t sys_register = GET_ISS_SYSREG(esr);
|
||||
+ uintreg_t rt_register = GET_ISS_RT(esr);
|
||||
+ uintreg_t value;
|
||||
+
|
||||
+ /* +1 because Rt can access register XZR */
|
||||
+ CHECK(rt_register < NUM_GP_REGS + 1);
|
||||
+
|
||||
+ if (ISS_IS_READ(esr)) {
|
||||
+ switch (sys_register) {
|
||||
+#define X(reg_name, op0, op1, crn, crm, op2) \
|
||||
+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
|
||||
+ value = read_msr(reg_name); \
|
||||
+ break;
|
||||
+ INTR_CTRL_REGISTERS
|
||||
+#undef X
|
||||
+ default:
|
||||
+ value = vcpu->regs.r[rt_register];
|
||||
+ dlog_notice(
|
||||
+ "Unsupported interrupt control register "
|
||||
+ "read: "
|
||||
+ "op0=%d, op1=%d, crn=%d, crm=%d, op2=%d, "
|
||||
+ "rt=%d.\n",
|
||||
+ GET_ISS_OP0(esr), GET_ISS_OP1(esr),
|
||||
+ GET_ISS_CRN(esr), GET_ISS_CRM(esr),
|
||||
+ GET_ISS_OP2(esr), GET_ISS_RT(esr));
|
||||
+ break;
|
||||
+ }
|
||||
+ if (rt_register != RT_REG_XZR) {
|
||||
+ vcpu->regs.r[rt_register] = value;
|
||||
+ }
|
||||
+ } else {
|
||||
+ if (rt_register != RT_REG_XZR) {
|
||||
+ value = vcpu->regs.r[rt_register];
|
||||
+ } else {
|
||||
+ value = 0;
|
||||
+ }
|
||||
+ switch (sys_register) {
|
||||
+#define X(reg_name, op0, op1, crn, crm, op2) \
|
||||
+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
|
||||
+ write_msr(reg_name, value); \
|
||||
+ break;
|
||||
+ INTR_CTRL_REGISTERS
|
||||
+#undef X
|
||||
+ default:
|
||||
+ dlog_notice(
|
||||
+ "Unsupported interrupt control register "
|
||||
+ "write: "
|
||||
+ "op0=%d, op1=%d, crn=%d, crm=%d, op2=%d, "
|
||||
+ "rt=%d.\n",
|
||||
+ GET_ISS_OP0(esr), GET_ISS_OP1(esr),
|
||||
+ GET_ISS_CRN(esr), GET_ISS_CRM(esr),
|
||||
+ GET_ISS_OP2(esr), GET_ISS_RT(esr));
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
diff --git a/src/arch/aarch64/hypervisor/perfmon.h b/src/arch/aarch64/hypervisor/perfmon.h
|
||||
index 81669ba1c401..c90d45bfc239 100644
|
||||
--- a/src/arch/aarch64/hypervisor/perfmon.h
|
||||
+++ b/src/arch/aarch64/hypervisor/perfmon.h
|
||||
@@ -70,3 +70,8 @@ bool perfmon_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
|
||||
uintreg_t esr_el2);
|
||||
|
||||
uintreg_t perfmon_get_pmccfiltr_el0_init_value(ffa_vm_id_t vm_id);
|
||||
+
|
||||
+bool intr_ctrl_is_register_access(uintreg_t esr);
|
||||
+
|
||||
+bool intr_ctrl_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
|
||||
+ uintreg_t esr);
|
||||
diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
|
||||
index bf1a66d1d4c5..b88a14b52f68 100644
|
||||
--- a/src/arch/aarch64/msr.h
|
||||
+++ b/src/arch/aarch64/msr.h
|
||||
@@ -139,3 +139,6 @@
|
||||
#define MSR_CNTHPS_CTL_EL2 S3_4_C14_C5_1
|
||||
#define MSR_CNTHPS_CVAL_EL2 S3_4_C14_C5_2
|
||||
#define MSR_CNTHPS_TVAL_EL2 S3_4_C14_C5_0
|
||||
+
|
||||
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
|
||||
+#define ICC_SGI1R_EL1 S3_0_C12_C11_5
|
||||
-41
@@ -1,41 +0,0 @@
|
||||
From 41f3ff2f011da69ff81234769353955e51c7e588 Mon Sep 17 00:00:00 2001
|
||||
From: Davidson K <davidson.kumaresan@arm.com>
|
||||
Date: Thu, 7 Oct 2021 12:20:08 +0530
|
||||
Subject: [PATCH] feat(vhe): set STAGE1_NS while mapping memory from NWd to SWd
|
||||
|
||||
If the memory is shared by a VM executing in non secure world, attribute
|
||||
MM_MODE_NS had to be set while mapping that in a S-EL0 SP executing in
|
||||
secure world. It will not be needed for a S-EL1 SP since the NS bit is
|
||||
available only for the stage 1 translations and the stage 1 translations
|
||||
for a S-EL1 SP will be handled by a trusted OS running in S-EL1.
|
||||
|
||||
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
|
||||
Change-Id: I074e2d5a50a659bd3c097d797c4901f08d210b1b
|
||||
Upstream-Status: Pending [Not submitted to upstream yet]
|
||||
---
|
||||
src/ffa_memory.c | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
diff --git a/src/ffa_memory.c b/src/ffa_memory.c
|
||||
index 5826cb2fdd4b..bae677633dea 100644
|
||||
--- a/src/ffa_memory.c
|
||||
+++ b/src/ffa_memory.c
|
||||
@@ -2618,6 +2618,18 @@ struct ffa_value ffa_memory_retrieve(struct vm_locked to_locked,
|
||||
|
||||
memory_to_attributes = ffa_memory_permissions_to_mode(
|
||||
permissions, share_state->sender_orig_mode);
|
||||
+
|
||||
+ if (to_locked.vm->el0_partition) {
|
||||
+ /*
|
||||
+ * Get extra mapping attributes for the given VM ID.
|
||||
+ * If the memory is shared by a VM executing in non secure
|
||||
+ * world, attribute MM_MODE_NS had to be set while mapping
|
||||
+ * that in a SP executing in secure world.
|
||||
+ */
|
||||
+ memory_to_attributes |= arch_mm_extra_attributes_from_vm(
|
||||
+ retrieve_request->sender);
|
||||
+ }
|
||||
+
|
||||
ret = ffa_retrieve_check_update(
|
||||
to_locked, memory_region->sender, share_state->fragments,
|
||||
share_state->fragment_constituent_counts,
|
||||
@@ -3,15 +3,6 @@
|
||||
COMPATIBLE_MACHINE = "(tc?)"
|
||||
HAFNIUM_PLATFORM = "secure_tc"
|
||||
|
||||
FILESEXTRAPATHS:prepend:tc := "${THISDIR}/files/tc:"
|
||||
|
||||
SRC_URI:append = " \
|
||||
file://0001-feat-emulate-cntp-timer-register-accesses-using-cnth.patch \
|
||||
file://0002-feat-emulate-interrupt-controller-register-access.patch \
|
||||
file://0003-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch \
|
||||
file://0001-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch;patchdir=project/reference \
|
||||
"
|
||||
|
||||
do_compile() {
|
||||
PATH="${S}/prebuilts/linux-x64/clang/bin:$PATH" oe_runmake -C ${S}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user