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arm-bsp/u-boot:cs1k: Split Cortex-a320 device tree
The U-Boot maintainers rejected the previous patch [1] for two primary reasons: 1. The Cortex-A320 changes should be considered a separate platform 2. The NPU node bindings do not match those in the Linux kernel The former is handled by this commit. The latter point has not been resolved, hence marking the newly added patch as Inappropriate. This is simply the first step in resolving the comments. [1] https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com Signed-off-by: Frazer Carsley <frazer.carsley@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Frazer Carsley
committed by
Jon Mason
Jon Mason
parent
73cde0a9ec
commit
4414e4d2a0
@@ -3,10 +3,13 @@
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DEPENDS:append = " openssl-native efitools-native"
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DEPENDS:append = " openssl-native efitools-native"
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CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "arm/corstone1000-mps3"
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CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "arm/corstone1000-mps3"
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CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "arm/corstone1000-fvp"
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CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "arm/corstone1000-fvp"
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CORSTONE1000_DEVICE_TREE:cortexa320 = "corstone1000-a320-fvp"
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EXTRA_OEMAKE:append = ' DEVICE_TREE=${CORSTONE1000_DEVICE_TREE}'
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EXTRA_OEMAKE:append = ' DEVICE_TREE=${CORSTONE1000_DEVICE_TREE}'
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CORSTONE1000_DEFCONFIG = "corstone1000_defconfig"
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CORSTONE1000_DEFCONFIG:cortexa320 = "corstone1000-a320_defconfig"
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UBOOT_CONFIG ??= "EFI"
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UBOOT_CONFIG ??= "EFI"
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UBOOT_CONFIG[EFI] = "corstone1000_defconfig"
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UBOOT_CONFIG[EFI] = "${CORSTONE1000_DEFCONFIG}"
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UBOOT_ENTRYPOINT = "0x80000000"
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UBOOT_ENTRYPOINT = "0x80000000"
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UBOOT_LOADADDRESS = "0x80000000"
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UBOOT_LOADADDRESS = "0x80000000"
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UBOOT_BOOTARGS = "${LINUX_KERNEL_ARGS} loglevel=9"
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UBOOT_BOOTARGS = "${LINUX_KERNEL_ARGS} loglevel=9"
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@@ -75,12 +78,7 @@ SRC_URI:append = " \
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# Add Cortex-a320 support
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# Add Cortex-a320 support
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SRC_URI:append = " \
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SRC_URI:append = " \
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file://0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch \
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file://0039-corstone1000-a320-Add-Corstone1000-board-variant.patch \
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"
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# Add Cortex-a320 specific configurations
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SRC_URI:append:cortexa320 = " \
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file://corstone1000-a320.cfg \
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"
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"
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uboot_configure_config:append() {
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uboot_configure_config:append() {
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-219
@@ -1,219 +0,0 @@
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From ef9306fde5247ccd8fecec5f886f52426c01af61 Mon Sep 17 00:00:00 2001
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From: Frazer Carsley <frazer.carsley@arm.com>
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Date: Wed, 25 Feb 2026 14:08:07 +0000
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Subject: [PATCH] corstone1000: Add Cortex-A320 support on FVP
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Enable Cortex-A320 support on the Corstone-1000 platform
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(including FVP) and update the device tree to support the integrated
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Ethos-U85 NPU and GIC-700 interrupt controller. These updates make
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the platform fully compatible with Cortex-A320 while retaining
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backward compatibility with Cortex-A35 and GIC-400.
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**Cortex-A320 enablement**
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* Extend Corstone-1000 compatibility list to include `cortex-a320`.
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* Ensure build and device-tree logic support both Cortex-A35 and
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Cortex-A320 configurations.
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**Ethos-U85 integration**
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* Add `/ethosu@1a050000` node describing the NPU register block at
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`0x1A050000`.
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* Introduce associated reserved memory regions:
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* `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`).
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* `ethosu_reserved@A0000000`: 32 MiB DDR carve-out
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(`shared-dma-pool`).
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* Connect memory regions through `memory-region` and `sram` phandles.
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* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and
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`ethosu-mem-config` for full driver support.
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* Enable the NPU node conditionally via `CONFIG_ETHOS_U85`.
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**GIC-700 support**
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* Introduce `CONFIG_GIC_700` to toggle between GIC-400 and
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GIC-700.
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* Add full GICv3 node guarded by `#ifdef CONFIG_GIC_700`.
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* Adjust `cpu@1..3` `reg` values to `0x100/0x200/0x300` under
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GIC-700 (keep `0x1/0x2/0x3` for GIC-400).
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* Update Ethos-U85 interrupt assignment to **SPI 16** to align with
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the new interrupt map.
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These updates align the Corstone-1000 platform with Arm’s latest
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Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt
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and memory mapping for both secure and non-secure domains.
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Upstream-Status: Submitted (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/)
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Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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---
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arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 38 +++++++++++
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arch/arm/dts/corstone1000-u-boot.dtsi | 79 +++++++++++++++++++++++
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arch/arm/include/asm/armv8/cpu.h | 1 +
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board/armltd/corstone1000/Kconfig | 8 +++
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4 files changed, 126 insertions(+)
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diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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index 5cb7762fc1c..7ad4ca9e070 100644
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--- a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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+++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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@@ -7,3 +7,41 @@
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#include "corstone1000-u-boot.dtsi"
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#include "corstone1000-extsys-u-boot.dtsi"
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#include "corstone1000-virtio-u-boot.dtsi"
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+
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+&{/cpus} {
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+#ifdef CONFIG_GIC_700
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+ reg = <0x100>;
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+#else
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+ reg = <0x1>;
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+#endif
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+ enable-method = "psci";
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+ next-level-cache = <&L2_0>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+#ifdef CONFIG_GIC_700
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+ reg = <0x200>;
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+#else
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+ reg = <0x2>;
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+#endif
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+ enable-method = "psci";
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+ next-level-cache = <&L2_0>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+#ifdef CONFIG_GIC_700
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+ reg = <0x300>;
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+#else
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+ reg = <0x3>;
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+#endif
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+ enable-method = "psci";
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+ next-level-cache = <&L2_0>;
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+ };
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+};
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diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi
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index 4ea6f1d9724..fef56d1ec66 100644
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--- a/arch/arm/dts/corstone1000-u-boot.dtsi
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+++ b/arch/arm/dts/corstone1000-u-boot.dtsi
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@@ -28,3 +28,82 @@
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};
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};
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};
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+
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+&{/cpus} {
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+ cpu: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+ reg = <0>;
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+ next-level-cache = <&L2_0>;
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+ };
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+};
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+
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+#ifdef CONFIG_ETHOS_U85
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+&{/reserved-memory} {
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+ ethosu_sram: ethosu_sram@02400000 {
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+ reg = <0x02400000 0x200000>;
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+ no-map;
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+ };
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+
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+ ethosu_reserved: ethosu_reserved@A0000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0xA0000000 0x02000000>;
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+ no-map;
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+
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+ };
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+};
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+
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+/ {
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+ ethosu: ethosu@1A050000 {
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+ compatible = "arm,ethosu-direct";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ // Base address and size of NPU registers
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+ reg = <0x1A050000 0x4000>;
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+
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+ memory-region = <ðosu_reserved>;
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+ sram = <ðosu_sram>;
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+
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+ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses
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+ dma-ranges = <0x02400000 0x02400000 0x200000>,
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+ <0xA0000000 0xA0000000 0x02000000>;
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+
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+ interrupts = <0 16 4>;
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+ interrupt-names = "irq";
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+
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+ // Memory region configuration
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+ region-cfgs = <3 3 0 3 3 3 3 3>;
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+
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+ // Memory regions used for the command stream
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+ cs-region = <2>;
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+
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+ // Memory interface configuration for Ethos-U85
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+ ethosu_mem_config {
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+ compatible = "arm,ethosu-mem-config";
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+ // <beats outstanding_read outstanding_write>
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+ sram = <0 64 32>;
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+ ext = <1 64 32>;
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+ // <mem_domain mem_type axi_port>
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+ configs = <0 0 0>,
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+ <0 0 0>,
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+ <0 0 1>,
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+ <0 0 1>;
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+ };
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+ };
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+};
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+#endif
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+
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+#ifdef CONFIG_GIC_700
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+gic: &{/interrupt-controller@1c000000} {
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+ compatible = "arm,gic-v3";
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+ #interrupt-cells = <3>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ interrupt-controller;
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+ reg = <0x1c000000 0x00010000>,
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+ <0x1c040000 0x00100000>;
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+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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+ };
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+#endif
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diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
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index e906fdf1bf1..4ef2ff07f7a 100644
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--- a/arch/arm/include/asm/armv8/cpu.h
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+++ b/arch/arm/include/asm/armv8/cpu.h
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@@ -11,6 +11,7 @@
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#define MIDR_PARTNUM_CORTEX_A73 0xD09
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#define MIDR_PARTNUM_CORTEX_A75 0xD0A
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#define MIDR_PARTNUM_CORTEX_A76 0xD0B
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+#define MIDR_PARTNUM_CORTEX_A320 0xD8F
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#define MIDR_PARTNUM_SHIFT 0x4
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#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
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|
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diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig
|
|
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index 709674d4cf7..eea5c9b8972 100644
|
|
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--- a/board/armltd/corstone1000/Kconfig
|
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+++ b/board/armltd/corstone1000/Kconfig
|
|
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@@ -9,4 +9,12 @@ config SYS_VENDOR
|
|
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config SYS_CONFIG_NAME
|
|
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default "corstone1000"
|
|
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|
|
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+config ETHOS_U85
|
|
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+ bool "Enable Arm Ethos-U85 NPU support"
|
|
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+ default n
|
|
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+
|
|
||||||
+config GIC_700
|
|
||||||
+ bool "Enable GIC-700 support"
|
|
||||||
+ default n
|
|
||||||
+
|
|
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endif
|
|
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+594
@@ -0,0 +1,594 @@
|
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|
From 9f95097d9b2d9b1360b5c105161509ea9a5b198d Mon Sep 17 00:00:00 2001
|
||||||
|
From: Frazer Carsley <frazer.carsley@arm.com>
|
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|
Date: Wed, 25 Feb 2026 14:28:08 +0000
|
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|
Subject: [PATCH] corstone1000-a320: Add Corstone1000 board variant
|
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|
MIME-Version: 1.0
|
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|
Content-Type: text/plain; charset=UTF-8
|
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|
Content-Transfer-Encoding: 8bit
|
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|
|
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|
Enable Cortex-A320 support on the Corstone-1000 platform
|
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|
(including FVP) and support for the integrated Ethos-U85 NPU and GIC-700
|
||||||
|
interrupt controller by way of a new device-tree. These updates make the
|
||||||
|
platform fully compatible with Cortex-A320 while retaining backward
|
||||||
|
compatibility with Cortex-A35 and GIC-400.
|
||||||
|
|
||||||
|
**Cortex-A320 enablement**
|
||||||
|
|
||||||
|
* Extend Corstone-1000 compatibility list to include `cortex-a320`.
|
||||||
|
* Add new device-tree to support Cortex-A320 configurations, retaining
|
||||||
|
existing board support code.
|
||||||
|
|
||||||
|
**Ethos-U85 integration**
|
||||||
|
|
||||||
|
* Add `/ethosu@1a050000` node describing the NPU register block at
|
||||||
|
`0x1A050000`.
|
||||||
|
* Introduce associated reserved memory regions:
|
||||||
|
* `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`).
|
||||||
|
* `ethosu_reserved@A0000000`: 32 MiB DDR carve-out
|
||||||
|
(`shared-dma-pool`).
|
||||||
|
* Connect memory regions through `memory-region` and `sram` phandles.
|
||||||
|
* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and
|
||||||
|
`ethosu-mem-config` for full driver support.
|
||||||
|
**GIC-700 support**
|
||||||
|
|
||||||
|
* Add full GICv3 node.
|
||||||
|
* Map `cpu@1..3` `reg` values to `0x100/0x200/0x300` under
|
||||||
|
GIC-700
|
||||||
|
* Update Ethos-U85 interrupt assignment to **SPI 16** to align with
|
||||||
|
the new interrupt map.
|
||||||
|
|
||||||
|
These updates align the Corstone-1000 platform with Arm’s latest
|
||||||
|
Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt
|
||||||
|
and memory mapping for both secure and non-secure domains.
|
||||||
|
|
||||||
|
Upstream-Status: Inappropriate [Unsupported ethosu device-tree nodes, denied by maintainers (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/)]
|
||||||
|
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
|
||||||
|
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||||
|
---
|
||||||
|
arch/arm/Kconfig | 1 +
|
||||||
|
arch/arm/dts/corstone1000-a320-fvp.dts | 51 ++++
|
||||||
|
arch/arm/dts/corstone1000-a320.dtsi | 237 ++++++++++++++++++
|
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|
arch/arm/include/asm/armv8/cpu.h | 3 +
|
||||||
|
board/armltd/corstone1000-a320/Kconfig | 12 +
|
||||||
|
board/armltd/corstone1000-a320/MAINTAINERS | 7 +
|
||||||
|
board/armltd/corstone1000/corstone1000.c | 6 +-
|
||||||
|
configs/corstone1000-a320_defconfig | 89 +++++++
|
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|
.../arm/arm,corstone1000-a320.yml | 31 +++
|
||||||
|
9 files changed, 434 insertions(+), 3 deletions(-)
|
||||||
|
create mode 100644 arch/arm/dts/corstone1000-a320-fvp.dts
|
||||||
|
create mode 100644 arch/arm/dts/corstone1000-a320.dtsi
|
||||||
|
create mode 100644 board/armltd/corstone1000-a320/Kconfig
|
||||||
|
create mode 100644 board/armltd/corstone1000-a320/MAINTAINERS
|
||||||
|
create mode 100644 configs/corstone1000-a320_defconfig
|
||||||
|
create mode 100644 doc/device-tree-bindings/arm/arm,corstone1000-a320.yml
|
||||||
|
|
||||||
|
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
|
||||||
|
index 625d2e995d2..aacc39fa60c 100644
|
||||||
|
--- a/arch/arm/Kconfig
|
||||||
|
+++ b/arch/arm/Kconfig
|
||||||
|
@@ -2405,6 +2405,7 @@ source "arch/arm/mach-npcm/Kconfig"
|
||||||
|
|
||||||
|
source "board/armltd/total_compute/Kconfig"
|
||||||
|
source "board/armltd/corstone1000/Kconfig"
|
||||||
|
+source "board/armltd/corstone1000-a320/Kconfig"
|
||||||
|
source "board/bosch/shc/Kconfig"
|
||||||
|
source "board/bosch/guardian/Kconfig"
|
||||||
|
source "board/Marvell/octeontx/Kconfig"
|
||||||
|
diff --git a/arch/arm/dts/corstone1000-a320-fvp.dts b/arch/arm/dts/corstone1000-a320-fvp.dts
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000000..c01c629e0ca
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm/dts/corstone1000-a320-fvp.dts
|
||||||
|
@@ -0,0 +1,51 @@
|
||||||
|
+// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||||
|
+/*
|
||||||
|
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
|
||||||
|
+ *
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+/dts-v1/;
|
||||||
|
+
|
||||||
|
+#include "corstone1000-a320.dtsi"
|
||||||
|
+#include "corstone1000-virtio-u-boot.dtsi"
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)";
|
||||||
|
+ compatible = "arm,corstone1000-a320-fvp";
|
||||||
|
+
|
||||||
|
+ smsc: ethernet@4010000 {
|
||||||
|
+ compatible = "smsc,lan91c111";
|
||||||
|
+ reg = <0x40100000 0x10000>;
|
||||||
|
+ phy-mode = "mii";
|
||||||
|
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ reg-io-width = <2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ vmmc_v3_3d: regulator-vmmc {
|
||||||
|
+ compatible = "regulator-fixed";
|
||||||
|
+ regulator-name = "vmmc_supply";
|
||||||
|
+ regulator-min-microvolt = <3300000>;
|
||||||
|
+ regulator-max-microvolt = <3300000>;
|
||||||
|
+ regulator-always-on;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdmmc0: mmc@40300000 {
|
||||||
|
+ compatible = "arm,pl18x", "arm,primecell";
|
||||||
|
+ reg = <0x40300000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ max-frequency = <12000000>;
|
||||||
|
+ vmmc-supply = <&vmmc_v3_3d>;
|
||||||
|
+ clocks = <&smbclk>, <&refclk100mhz>;
|
||||||
|
+ clock-names = "smclk", "apb_pclk";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ sdmmc1: mmc@50000000 {
|
||||||
|
+ compatible = "arm,pl18x", "arm,primecell";
|
||||||
|
+ reg = <0x50000000 0x10000>;
|
||||||
|
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ max-frequency = <12000000>;
|
||||||
|
+ vmmc-supply = <&vmmc_v3_3d>;
|
||||||
|
+ clocks = <&smbclk>, <&refclk100mhz>;
|
||||||
|
+ clock-names = "smclk", "apb_pclk";
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
diff --git a/arch/arm/dts/corstone1000-a320.dtsi b/arch/arm/dts/corstone1000-a320.dtsi
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000000..28424db77bb
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/arch/arm/dts/corstone1000-a320.dtsi
|
||||||
|
@@ -0,0 +1,237 @@
|
||||||
|
+// SPDX-License-Identifier: GPL-2.0 or MIT
|
||||||
|
+/*
|
||||||
|
+ * Copyright 2026, Arm Limited and/or its affiliates <open-source-office@arm.com>
|
||||||
|
+ *
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
+
|
||||||
|
+#include "corstone1000-u-boot.dtsi"
|
||||||
|
+
|
||||||
|
+/ {
|
||||||
|
+ interrupt-parent = <&gic>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+
|
||||||
|
+ aliases {
|
||||||
|
+ serial0 = &uart0;
|
||||||
|
+ serial1 = &uart1;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ chosen {
|
||||||
|
+ stdout-path = "serial0:115200n8";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpus: cpus {
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+
|
||||||
|
+ L2: l2-cache {
|
||||||
|
+ compatible = "cache";
|
||||||
|
+ cache-unified;
|
||||||
|
+ cache-level = <2>;
|
||||||
|
+ cache-size = <0x80000>;
|
||||||
|
+ cache-line-size = <64>;
|
||||||
|
+ cache-sets = <1024>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu: cpu@0 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a320";
|
||||||
|
+ reg = <0>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ next-level-cache = <&L2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu1: cpu@100 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a320";
|
||||||
|
+ reg = <0x100>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ next-level-cache = <&L2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu2: cpu@200 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a320";
|
||||||
|
+ reg = <0x200>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ next-level-cache = <&L2>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ cpu3: cpu@300 {
|
||||||
|
+ device_type = "cpu";
|
||||||
|
+ compatible = "arm,cortex-a320";
|
||||||
|
+ reg = <0x300>;
|
||||||
|
+ enable-method = "psci";
|
||||||
|
+ next-level-cache = <&L2>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ gic: interrupt-controller@1c000000 {
|
||||||
|
+ compatible = "arm,gic-v3";
|
||||||
|
+ #interrupt-cells = <3>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ ranges;
|
||||||
|
+ interrupt-controller;
|
||||||
|
+ reg = <0x1c000000 0x00010000>,
|
||||||
|
+ <0x1c040000 0x00100000>;
|
||||||
|
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ memory@88200000 {
|
||||||
|
+ device_type = "memory";
|
||||||
|
+ reg = <0x88200000 0x77e00000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ refclk100mhz: clock-100000000 {
|
||||||
|
+ compatible = "fixed-clock";
|
||||||
|
+ #clock-cells = <0>;
|
||||||
|
+ clock-frequency = <100000000>;
|
||||||
|
+ clock-output-names = "apb_pclk";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ smbclk: clock-48000000 {
|
||||||
|
+ /* Reference 24MHz clock x 2 */
|
||||||
|
+ compatible = "fixed-clock";
|
||||||
|
+ #clock-cells = <0>;
|
||||||
|
+ clock-frequency = <48000000>;
|
||||||
|
+ clock-output-names = "smclk";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ timer {
|
||||||
|
+ compatible = "arm,armv8-timer";
|
||||||
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uartclk: clock-50000000 {
|
||||||
|
+ /* UART clock - 50MHz */
|
||||||
|
+ compatible = "fixed-clock";
|
||||||
|
+ #clock-cells = <0>;
|
||||||
|
+ clock-frequency = <50000000>;
|
||||||
|
+ clock-output-names = "uartclk";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ psci {
|
||||||
|
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||||
|
+ method = "smc";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ethosu: ethosu@1A050000 {
|
||||||
|
+ compatible = "arm,ethosu-direct";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+
|
||||||
|
+ // Base address and size of NPU registers
|
||||||
|
+ reg = <0x1A050000 0x4000>;
|
||||||
|
+
|
||||||
|
+ memory-region = <ðosu_reserved>;
|
||||||
|
+ sram = <ðosu_sram>;
|
||||||
|
+
|
||||||
|
+ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses
|
||||||
|
+ dma-ranges = <0x02400000 0x02400000 0x200000>,
|
||||||
|
+ <0xA0000000 0xA0000000 0x02000000>;
|
||||||
|
+
|
||||||
|
+ interrupts = <0 16 4>;
|
||||||
|
+ interrupt-names = "irq";
|
||||||
|
+
|
||||||
|
+ // Memory region configuration
|
||||||
|
+ region-cfgs = <3 3 0 3 3 3 3 3>;
|
||||||
|
+
|
||||||
|
+ // Memory regions used for the command stream
|
||||||
|
+ cs-region = <2>;
|
||||||
|
+
|
||||||
|
+ // Memory interface configuration for Ethos-U85
|
||||||
|
+ ethosu_mem_config {
|
||||||
|
+ compatible = "arm,ethosu-mem-config";
|
||||||
|
+ // <beats outstanding_read outstanding_write>
|
||||||
|
+ sram = <0 64 32>;
|
||||||
|
+ ext = <1 64 32>;
|
||||||
|
+ // <mem_domain mem_type axi_port>
|
||||||
|
+ configs = <0 0 0>,
|
||||||
|
+ <0 0 0>,
|
||||||
|
+ <0 0 1>,
|
||||||
|
+ <0 0 1>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ soc {
|
||||||
|
+ compatible = "simple-bus";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ interrupt-parent = <&gic>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ timer@1a220000 {
|
||||||
|
+ compatible = "arm,armv7-timer-mem";
|
||||||
|
+ reg = <0x1a220000 0x1000>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+ ranges;
|
||||||
|
+
|
||||||
|
+ frame@1a230000 {
|
||||||
|
+ frame-number = <0>;
|
||||||
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ reg = <0x1a230000 0x1000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uart0: serial@1a510000 {
|
||||||
|
+ compatible = "arm,pl011", "arm,primecell";
|
||||||
|
+ reg = <0x1a510000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&uartclk>, <&refclk100mhz>;
|
||||||
|
+ clock-names = "uartclk", "apb_pclk";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ uart1: serial@1a520000 {
|
||||||
|
+ compatible = "arm,pl011", "arm,primecell";
|
||||||
|
+ reg = <0x1a520000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&uartclk>, <&refclk100mhz>;
|
||||||
|
+ clock-names = "uartclk", "apb_pclk";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ mhu_hse1: mailbox@1b820000 {
|
||||||
|
+ compatible = "arm,mhuv2-tx", "arm,primecell";
|
||||||
|
+ reg = <0x1b820000 0x1000>;
|
||||||
|
+ clocks = <&refclk100mhz>;
|
||||||
|
+ clock-names = "apb_pclk";
|
||||||
|
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ #mbox-cells = <2>;
|
||||||
|
+ arm,mhuv2-protocols = <0 0>;
|
||||||
|
+ secure-status = "okay"; /* secure-world-only */
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ mhu_seh1: mailbox@1b830000 {
|
||||||
|
+ compatible = "arm,mhuv2-rx", "arm,primecell";
|
||||||
|
+ reg = <0x1b830000 0x1000>;
|
||||||
|
+ clocks = <&refclk100mhz>;
|
||||||
|
+ clock-names = "apb_pclk";
|
||||||
|
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ #mbox-cells = <2>;
|
||||||
|
+ arm,mhuv2-protocols = <0 0>;
|
||||||
|
+ secure-status = "okay"; /* secure-world-only */
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&{/reserved-memory} {
|
||||||
|
+ ethosu_sram: ethosu_sram@02400000 {
|
||||||
|
+ reg = <0x02400000 0x200000>;
|
||||||
|
+ no-map;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ethosu_reserved: ethosu_reserved@A0000000 {
|
||||||
|
+ compatible = "shared-dma-pool";
|
||||||
|
+ reg = <0xA0000000 0x02000000>;
|
||||||
|
+ no-map;
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
|
||||||
|
index e906fdf1bf1..1ae679f7119 100644
|
||||||
|
--- a/arch/arm/include/asm/armv8/cpu.h
|
||||||
|
+++ b/arch/arm/include/asm/armv8/cpu.h
|
||||||
|
@@ -1,6 +1,7 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2018 NXP
|
||||||
|
+ * (C) Copyright 2026 Arm Limited
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define MIDR_PARTNUM_CORTEX_A35 0xD04
|
||||||
|
@@ -11,6 +12,7 @@
|
||||||
|
#define MIDR_PARTNUM_CORTEX_A73 0xD09
|
||||||
|
#define MIDR_PARTNUM_CORTEX_A75 0xD0A
|
||||||
|
#define MIDR_PARTNUM_CORTEX_A76 0xD0B
|
||||||
|
+#define MIDR_PARTNUM_CORTEX_A320 0xD8F
|
||||||
|
#define MIDR_PARTNUM_SHIFT 0x4
|
||||||
|
#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
|
||||||
|
|
||||||
|
@@ -40,3 +42,4 @@ is_cortex_a(72)
|
||||||
|
is_cortex_a(73)
|
||||||
|
is_cortex_a(75)
|
||||||
|
is_cortex_a(76)
|
||||||
|
+is_cortex_a(320)
|
||||||
|
diff --git a/board/armltd/corstone1000-a320/Kconfig b/board/armltd/corstone1000-a320/Kconfig
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000000..607e5f6689b
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/board/armltd/corstone1000-a320/Kconfig
|
||||||
|
@@ -0,0 +1,12 @@
|
||||||
|
+if TARGET_CORSTONE1000-A320
|
||||||
|
+
|
||||||
|
+config SYS_BOARD
|
||||||
|
+ default "corstone1000-a320"
|
||||||
|
+
|
||||||
|
+config SYS_VENDOR
|
||||||
|
+ default "armltd"
|
||||||
|
+
|
||||||
|
+config SYS_CONFIG_NAME
|
||||||
|
+ default "corstone1000-a320"
|
||||||
|
+
|
||||||
|
+endif
|
||||||
|
diff --git a/board/armltd/corstone1000-a320/MAINTAINERS b/board/armltd/corstone1000-a320/MAINTAINERS
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000000..e62978b487e
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/board/armltd/corstone1000-a320/MAINTAINERS
|
||||||
|
@@ -0,0 +1,7 @@
|
||||||
|
+CORSTONE1000-A320 BOARD
|
||||||
|
+M: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||||
|
+M: Frazer Carsley <frazer.carsley@arm.com>
|
||||||
|
+M: Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
|
||||||
|
+S: Maintained
|
||||||
|
+F: board/armltd/corstone1000-a320/
|
||||||
|
+F: configs/corstone1000-a320_defconfig
|
||||||
|
diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
|
||||||
|
index db8919298e1..0557865f59b 100644
|
||||||
|
--- a/board/armltd/corstone1000/corstone1000.c
|
||||||
|
+++ b/board/armltd/corstone1000/corstone1000.c
|
||||||
|
@@ -1,6 +1,6 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
- * (C) Copyright 2022, 2025 Arm Limited
|
||||||
|
+ * (C) Copyright 2022, 2025-2026 Arm Limited
|
||||||
|
* (C) Copyright 2022 Linaro
|
||||||
|
* Rui Miguel Silva <rui.silva@linaro.org>
|
||||||
|
*/
|
||||||
|
@@ -264,7 +264,7 @@ struct mm_region *mem_map = corstone1000_mem_map;
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
|
||||||
|
- if (!strcmp(DEVICE_TREE, "arm/corstone1000-fvp"))
|
||||||
|
+ if (!strstr(DEVICE_TREE, "fvp"))
|
||||||
|
update_info.images = fw_fvp_images;
|
||||||
|
else
|
||||||
|
update_info.images = fw_mps3_images;
|
||||||
|
@@ -396,7 +396,7 @@ int board_late_init(void)
|
||||||
|
const char *cmp_dtb = DEVICE_TREE;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
- if (!strcmp(cmp_dtb, "arm/corstone1000-fvp")) {
|
||||||
|
+ if (!strstr(cmp_dtb, "fvp")) {
|
||||||
|
ret = uclass_first_device_err(UCLASS_VIRTIO, &virtio_bus);
|
||||||
|
if (!virtio_bus) {
|
||||||
|
log_err("Cannot find virtio device, err (%d)\n", ret);
|
||||||
|
diff --git a/configs/corstone1000-a320_defconfig b/configs/corstone1000-a320_defconfig
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000000..d0ae1e745db
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/configs/corstone1000-a320_defconfig
|
||||||
|
@@ -0,0 +1,89 @@
|
||||||
|
+CONFIG_ARM=y
|
||||||
|
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||||
|
+CONFIG_TARGET_CORSTONE1000=y
|
||||||
|
+CONFIG_TEXT_BASE=0x80000000
|
||||||
|
+CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||||
|
+CONFIG_NR_DRAM_BANKS=1
|
||||||
|
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||||
|
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
|
||||||
|
+CONFIG_DM_GPIO=y
|
||||||
|
+CONFIG_DEFAULT_DEVICE_TREE="corstone1000-a320-fvp"
|
||||||
|
+CONFIG_SYS_BOOTM_LEN=0x800000
|
||||||
|
+CONFIG_SYS_LOAD_ADDR=0x82100000
|
||||||
|
+CONFIG_IDENT_STRING=" corstone1000-a320 aarch64 "
|
||||||
|
+CONFIG_FWU_NUM_IMAGES_PER_BANK=4
|
||||||
|
+CONFIG_EFI_SECURE_BOOT=y
|
||||||
|
+CONFIG_EFI_SET_TIME=y
|
||||||
|
+CONFIG_EFI_MM_COMM_TEE=y
|
||||||
|
+CONFIG_FFA_SHARED_MM_BUF_SIZE=4096
|
||||||
|
+CONFIG_FFA_SHARED_MM_BUF_OFFSET=0
|
||||||
|
+CONFIG_FFA_SHARED_MM_BUF_ADDR=0x81FFF000
|
||||||
|
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
|
||||||
|
+CONFIG_EFI_CAPSULE_ON_DISK=y
|
||||||
|
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
|
||||||
|
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
|
||||||
|
+CONFIG_EFI_CAPSULE_CRT_FILE="CRT.crt"
|
||||||
|
+CONFIG_FIT=y
|
||||||
|
+CONFIG_FIT_SIGNATURE=y
|
||||||
|
+CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||||
|
+CONFIG_DISTRO_DEFAULTS=y
|
||||||
|
+CONFIG_BOOTDELAY=3
|
||||||
|
+CONFIG_USE_BOOTARGS=y
|
||||||
|
+CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
|
||||||
|
+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run prepare_ondisk_fwu ; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
|
||||||
|
+CONFIG_CONSOLE_RECORD=y
|
||||||
|
+CONFIG_SYS_CBSIZE=512
|
||||||
|
+CONFIG_LOGLEVEL=7
|
||||||
|
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||||
|
+# CONFIG_DISPLAY_BOARDINFO is not set
|
||||||
|
+CONFIG_BOARD_INIT=y
|
||||||
|
+CONFIG_SYS_PROMPT="corstone1000# "
|
||||||
|
+# CONFIG_CMD_CONSOLE is not set
|
||||||
|
+CONFIG_CMD_FWU_METADATA=y
|
||||||
|
+CONFIG_CMD_BOOTZ=y
|
||||||
|
+# CONFIG_CMD_XIMG is not set
|
||||||
|
+CONFIG_CMD_NVEDIT_EFI=y
|
||||||
|
+CONFIG_CMD_GPT=y
|
||||||
|
+CONFIG_CMD_LOADM=y
|
||||||
|
+# CONFIG_CMD_LOADS is not set
|
||||||
|
+CONFIG_CMD_MMC=y
|
||||||
|
+CONFIG_CMD_USB=y
|
||||||
|
+# CONFIG_CMD_SETEXPR is not set
|
||||||
|
+CONFIG_CMD_CACHE=y
|
||||||
|
+CONFIG_CMD_EFIDEBUG=y
|
||||||
|
+CONFIG_CMD_RTC=y
|
||||||
|
+CONFIG_CMD_TIME=y
|
||||||
|
+CONFIG_CMD_GETTIME=y
|
||||||
|
+CONFIG_OF_CONTROL=y
|
||||||
|
+CONFIG_VERSION_VARIABLE=y
|
||||||
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
+CONFIG_REGMAP=y
|
||||||
|
+CONFIG_CLK=y
|
||||||
|
+CONFIG_ARM_FFA_TRANSPORT=y
|
||||||
|
+CONFIG_MISC=y
|
||||||
|
+CONFIG_ARM_PL180_MMCI=y
|
||||||
|
+CONFIG_MTD=y
|
||||||
|
+CONFIG_NVMXIP_QSPI=y
|
||||||
|
+CONFIG_PHYLIB=y
|
||||||
|
+CONFIG_PHY_SMSC=y
|
||||||
|
+CONFIG_SMC911X=y
|
||||||
|
+CONFIG_PHY=y
|
||||||
|
+CONFIG_RAM=y
|
||||||
|
+CONFIG_DM_RTC=y
|
||||||
|
+CONFIG_RTC_EMULATION=y
|
||||||
|
+CONFIG_DM_SERIAL=y
|
||||||
|
+CONFIG_SYSRESET=y
|
||||||
|
+CONFIG_SYSRESET_PSCI=y
|
||||||
|
+CONFIG_TEE=y
|
||||||
|
+CONFIG_OPTEE=y
|
||||||
|
+CONFIG_USB=y
|
||||||
|
+CONFIG_USB_ISP1760=y
|
||||||
|
+CONFIG_VIRTIO_MMIO=y
|
||||||
|
+CONFIG_VIRTIO_NET=y
|
||||||
|
+# CONFIG_RANDOM_UUID is not set
|
||||||
|
+CONFIG_ERRNO_STR=y
|
||||||
|
+# CONFIG_HEXDUMP is not set
|
||||||
|
+CONFIG_FWU_MULTI_BANK_UPDATE=y
|
||||||
|
+CONFIG_FWU_MDATA_V2=y
|
||||||
|
+CONFIG_FWU_ARM_PSA=y
|
||||||
|
+# CONFIG_TOOLS_MKEFICAPSULE is not set
|
||||||
|
diff --git a/doc/device-tree-bindings/arm/arm,corstone1000-a320.yml b/doc/device-tree-bindings/arm/arm,corstone1000-a320.yml
|
||||||
|
new file mode 100644
|
||||||
|
index 00000000000..9c8671d1775
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/doc/device-tree-bindings/arm/arm,corstone1000-a320.yml
|
||||||
|
@@ -0,0 +1,31 @@
|
||||||
|
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
+%YAML 1.2
|
||||||
|
+---
|
||||||
|
+$id: http://devicetree.org/schemas/arm/arm,corstone1000-a320.yaml#
|
||||||
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
+
|
||||||
|
+title: ARM Corstone1000-A320
|
||||||
|
+
|
||||||
|
+maintainers:
|
||||||
|
+ - Frazer Carsley <frazer.carsley@arm.com>
|
||||||
|
+ - Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||||
|
+ - Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
|
||||||
|
+
|
||||||
|
+description: |+
|
||||||
|
+ ARM's Corstone1000-A320 platform is a Corstone1000 variant that supports
|
||||||
|
+ Cortex-A320 processors, enables the use of an integrated Ethos-U85 NPU and
|
||||||
|
+ an upgraded GIC-700 interrupt controller.
|
||||||
|
+
|
||||||
|
+properties:
|
||||||
|
+ $nodename:
|
||||||
|
+ const: '/'
|
||||||
|
+ compatible:
|
||||||
|
+ oneOf:
|
||||||
|
+ - description: Corstone1000-A320 FVP is the Fixed Virtual Platform
|
||||||
|
+ implementation of this system. See ARM ecosystems FVP's.
|
||||||
|
+ items:
|
||||||
|
+ - const: arm,corstone1000-a320-fvp
|
||||||
|
+
|
||||||
|
+additionalProperties: true
|
||||||
|
+
|
||||||
|
+...
|
||||||
@@ -1,2 +0,0 @@
|
|||||||
CONFIG_ETHOS_U85=y
|
|
||||||
CONFIG_GIC_700=y
|
|
||||||
Reference in New Issue
Block a user