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arm-autonomy/xen: Backport improvements to xen 4.14
These patches improve the overall stability of Xen. Change-Id: I40c93f1c28fe9bd9548883c1cc0c38e1be7f56c3 Issue-Id: SCM-1520 Signed-off-by: Diego Sueiro <diego.sueiro@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Diego Sueiro
Jon Mason
+40
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From 3b418b33265402aab0cb1bf2b745a25724bae2d8 Mon Sep 17 00:00:00 2001
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Message-Id: <3b418b33265402aab0cb1bf2b745a25724bae2d8.1602684880.git.diego.sueiro@arm.com>
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From: Bertrand Marquis <bertrand.marquis@arm.com>
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Date: Tue, 18 Aug 2020 14:47:38 +0100
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Subject: [PATCH] arm: Add Neoverse N1 processor identification
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Add MIDR and CPU part numbers for Neoverse N1
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Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
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Acked-by: Julien Grall <jgrall@amazon.com>
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Upstream-Status: Backport
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Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
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---
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xen/include/asm-arm/processor.h | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
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index aa642e3..3ca67f8 100644
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--- a/xen/include/asm-arm/processor.h
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+++ b/xen/include/asm-arm/processor.h
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@@ -58,6 +58,7 @@
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#define ARM_CPU_PART_CORTEX_A73 0xD09
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#define ARM_CPU_PART_CORTEX_A75 0xD0A
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#define ARM_CPU_PART_CORTEX_A76 0xD0B
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+#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
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#define MIDR_CORTEX_A12 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A12)
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#define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17)
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@@ -68,6 +69,7 @@
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#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
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#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
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#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
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+#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
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/* MPIDR Multiprocessor Affinity Register */
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#define _MPIDR_UP (30)
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--
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2.7.4
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+42
@@ -0,0 +1,42 @@
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From 858c0be8c2fa4125a0fa0acaa03ae730e5c7cb3c Mon Sep 17 00:00:00 2001
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Message-Id: <858c0be8c2fa4125a0fa0acaa03ae730e5c7cb3c.1602684183.git.diego.sueiro@arm.com>
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From: Bertrand Marquis <bertrand.marquis@arm.com>
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Date: Tue, 18 Aug 2020 14:47:39 +0100
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Subject: [PATCH] xen/arm: Enable CPU Erratum 1165522 for Neoverse
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Enable CPU erratum of Speculative AT on the Neoverse N1 processor
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versions r0p0 to r2p0.
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Also Fix Cortex A76 Erratum string which had a wrong errata number.
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Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
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Acked-by: Julien Grall <jgrall@amazon.com>
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Upstream-Status: Backport
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Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
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---
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xen/arch/arm/cpuerrata.c | 8 +++++++-
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1 file changed, 7 insertions(+), 1 deletion(-)
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diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
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index 0248893..6c09017 100644
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--- a/xen/arch/arm/cpuerrata.c
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+++ b/xen/arch/arm/cpuerrata.c
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@@ -477,8 +477,14 @@ static const struct arm_cpu_capabilities arm_errata[] = {
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},
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#endif
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{
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+ /* Neoverse r0p0 - r2p0 */
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+ .desc = "ARM erratum 1165522",
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+ .capability = ARM64_WORKAROUND_AT_SPECULATE,
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+ MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 2 << MIDR_VARIANT_SHIFT),
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+ },
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+ {
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/* Cortex-A76 r0p0 - r2p0 */
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- .desc = "ARM erratum 116522",
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+ .desc = "ARM erratum 1165522",
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.capability = ARM64_WORKAROUND_AT_SPECULATE,
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MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT),
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},
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--
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2.7.4
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+35
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From 1814a626fb5811184eda64fe22f0055df4600211 Mon Sep 17 00:00:00 2001
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Message-Id: <1814a626fb5811184eda64fe22f0055df4600211.1602684203.git.diego.sueiro@arm.com>
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From: Julien Grall <jgrall@amazon.com>
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Date: Tue, 25 Aug 2020 18:38:10 +0100
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Subject: [PATCH] xen/arm: Update silicon-errata.txt with the Neovers AT
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erratum
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Commit 858c0be8c2fa "xen/arm: Enable CPU Erratum 1165522 for Neoverse"
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added a new erratum but forgot to update silicon-errata.txt.
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Update the file accordingly to keep track of errata workaround in Xen.
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Signed-off-by: Julien Grall <jgrall@amazon.com>
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Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
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Acked-by: Stefano Stabellini <sstabellini@kernel.org>
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Upstream-Status: Backport
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Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
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---
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docs/misc/arm/silicon-errata.txt | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
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index 11e5a9d..e15d092 100644
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--- a/docs/misc/arm/silicon-errata.txt
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+++ b/docs/misc/arm/silicon-errata.txt
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@@ -51,4 +51,5 @@ stable hypervisors.
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| ARM | Cortex-A57 | #1319537 | N/A |
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| ARM | Cortex-A72 | #1319367 | N/A |
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| ARM | Cortex-A76 | #1165522 | N/A |
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+| ARM | Neoverse-N1 | #1165522 | N/A
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| ARM | MMU-500 | #842869 | N/A |
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--
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2.7.4
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+51
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From 968bb86d04913f52d7678a842474f2a674a8b23e Mon Sep 17 00:00:00 2001
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Message-Id: <968bb86d04913f52d7678a842474f2a674a8b23e.1602683678.git.diego.sueiro@arm.com>
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From: Wei Chen <wei.chen@arm.com>
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Date: Fri, 28 Aug 2020 02:34:03 +0000
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Subject: [PATCH] xen/arm: Missing N1/A76/A75 FP registers in vCPU context
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switch
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Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports
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FP/SIMD or not. But currently, these two MACROs only consider value 0
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of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs
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that support FP/SIMD and half-precision floating-point arithmetic, the
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ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64).
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For these CPUs, xen will treat them as no FP/SIMD support, the
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vfp_save/restore_state will not take effect.
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From the TRM documents of Cortex-A75/A76/N1, we know these CPUs support
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basic Advanced SIMD/FP and half-precision floating-point arithmetic. In
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this case, on N1/A76/A75 platforms, Xen will always miss the floating
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pointer registers save/restore. If different vCPUs are running on the
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same pCPU, the floating pointer registers will be corrupted randomly.
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This patch fixes Xen on these new cores.
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Signed-off-by: Wei Chen <wei.chen@arm.com>
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Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
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Reviewed-by: Julien Grall <jgrall@amazon.com>
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Upstream-Status: Backport
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Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
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---
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xen/include/asm-arm/cpufeature.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h
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index 674beb0..10878ea 100644
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--- a/xen/include/asm-arm/cpufeature.h
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+++ b/xen/include/asm-arm/cpufeature.h
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@@ -13,8 +13,8 @@
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#define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1)
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#define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2)
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#define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1)
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-#define cpu_has_fp (boot_cpu_feature64(fp) == 0)
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-#define cpu_has_simd (boot_cpu_feature64(simd) == 0)
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+#define cpu_has_fp (boot_cpu_feature64(fp) < 8)
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+#define cpu_has_simd (boot_cpu_feature64(simd) < 8)
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#define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1)
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#endif
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--
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2.7.4
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+51
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From f4c1a541fa351e4f613471bbf397931f9e1ddd27 Mon Sep 17 00:00:00 2001
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Message-Id: <f4c1a541fa351e4f613471bbf397931f9e1ddd27.1602683707.git.diego.sueiro@arm.com>
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From: Wei Chen <wei.chen@arm.com>
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Date: Fri, 28 Aug 2020 02:34:04 +0000
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Subject: [PATCH] xen/arm: Throw messages for unknown FP/SIMD implement ID
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Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
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FP/SIMD implementations. Currently, we exactly know the meaning of
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0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
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features presented. If there is a value 0x2 bumped in the future,
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Xen behaviors for value <= 0x1 can also take effect. But what Xen
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done for value <= 0x1 may not always cover new value 0x2 required.
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We throw these messages to break the silence when Xen detected
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unknown FP/SIMD IDs to notice user to check.
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Signed-off-by: Wei Chen <wei.chen@arm.com>
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Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
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Acked-by: Julien Grall <jgrall@amazon.com>
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Upstream-Status: Backport
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Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
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---
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xen/arch/arm/setup.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
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index 7968cee..f16b33f 100644
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--- a/xen/arch/arm/setup.c
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+++ b/xen/arch/arm/setup.c
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@@ -133,6 +133,18 @@ static void __init processor_id(void)
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cpu_has_simd ? " AdvancedSIMD" : "",
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cpu_has_gicv3 ? " GICv3-SysReg" : "");
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+ /* Warn user if we find unknown floating-point features */
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+ if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) )
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+ printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, "
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+ "this may result in corruption on the platform\n",
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+ boot_cpu_feature64(fp));
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+
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+ /* Warn user if we find unknown AdvancedSIMD features */
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+ if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) )
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+ printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, "
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+ "this may result in corruption on the platform\n",
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+ boot_cpu_feature64(simd));
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+
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printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
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boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
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printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",
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--
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2.7.4
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FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}-4.14:"
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SRC_URI += " \
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file://0001-arm-Add-Neoverse-N1-processor-identification.patch \
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file://0002-xen-arm-Enable-CPU-Erratum-1165522-for-Neoverse.patch \
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file://0003-xen-arm-Update-silicon-errata.txt-with-the-Neovers-A.patch \
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file://0004-xen-arm-Missing-N1-A76-A75-FP-registers-in-vCPU-cont.patch \
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file://0005-xen-arm-Throw-messages-for-unknown-FP-SIMD-implement.patch \
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"
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