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arm-bsp/u-boot:corstone1000: Add Cortex-A320 suppport
Update Corstone-1000 U-Boot device tree for the Cortex-A320 variant and enable GICv3/GIC-600, while keeping compatibility with the existing GIC-400 setup. A single DT image now supports either configuration via Kconfig guards. **Device-tree updates (Cortex-A320)** * Map Ethos-U85 NPU registers at `0x1A050000` (16 KiB) and its SRAM at `0x02400000` (2 MiB, no-map), plus a 32 MiB DDR carve-out for DMA. * Add `/ethosu@1a050000` with interrupts, `dma-ranges`, `cs-region`, and `ethosu-mem-config` for driver probe. * Guard the NPU node behind `CONFIG_ETHOS_U85`. * Add a Cortex-A320 compatible string to the Corstone-1000 DTS downstream. **GICv3/GIC-600 selection** * Introduce `CONFIG_GIC_V3` to select the new interrupt controller. * Add a full GICv3/GIC-600 node guarded by `#ifdef CONFIG_GIC_V3`. * When GICv3 is enabled, set `cpu@1..3` `reg` to `0x100/0x200/0x300` (retain `0x1/0x2/0x3` for GIC-400). * Update the Ethos-U85 interrupt to **SPI 16** to match the interrupt map. Signed-off-by: Frazer Carsley <frazer.carsley@arm.com> Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Frazer Carsley
committed by
Jon Mason
Jon Mason
parent
4f82af2fa7
commit
7680400f78
@@ -74,6 +74,16 @@ SRC_URI:append = " \
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file://0040-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch \
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file://0040-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch \
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"
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"
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# Add Cortex-a320 support
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SRC_URI:append = " \
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file://0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch \
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"
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# Add Cortex-a320 specific configurations
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SRC_URI:append:cortexa320 = " \
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file://corstone1000-a320.cfg \
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"
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uboot_configure_config:append() {
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uboot_configure_config:append() {
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openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ -keyout ${B}/CRT.key -out $builddir/CRT.crt -nodes -days 365
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openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ -keyout ${B}/CRT.key -out $builddir/CRT.crt -nodes -days 365
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}
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}
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@@ -0,0 +1,223 @@
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From 6a1e76a1c0e52c11e9abdcb5990002468650bd81 Mon Sep 17 00:00:00 2001
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From: Frazer Carsley <frazer.carsley@arm.com>
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Date: Fri, 15 Aug 2025 09:22:26 +0100
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Subject: [PATCH] corstone1000: Add Cortex-A320 support on FVP
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Enable Cortex-A320 support on the Corstone-1000 platform
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(including FVP) and update the device tree to support the integrated
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Ethos-U85 NPU and GIC-600 interrupt controller. These updates make
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the platform fully compatible with Cortex-A320 while retaining
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backward compatibility with Cortex-A35 and GIC-400.
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**Cortex-A320 enablement**
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* Extend Corstone-1000 compatibility list to include `cortex-a320`.
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* Ensure build and device-tree logic support both Cortex-A35 and
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Cortex-A320 configurations.
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**Ethos-U85 integration**
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* Add `/ethosu@1a050000` node describing the NPU register block at
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`0x1A050000`.
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* Introduce associated reserved memory regions:
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* `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`).
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* `ethosu_reserved@A0000000`: 32 MiB DDR carve-out
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(`shared-dma-pool`).
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* Connect memory regions through `memory-region` and `sram` phandles.
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* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and
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`ethosu-mem-config` for full driver support.
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* Enable the NPU node conditionally via `CONFIG_ETHOS_U85`.
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**GICv3/GIC-600 support**
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* Introduce `CONFIG_GIC_V3` to toggle between GIC-400 (v2) and
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GIC-600 (v3).
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* Add full GICv3 node guarded by `#ifdef CONFIG_GIC_V3`.
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* Adjust `cpu@1..3` `reg` values to `0x100/0x200/0x300` under
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GICv3 (keep `0x1/0x2/0x3` for GIC-400).
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* Update Ethos-U85 interrupt assignment to **SPI 16** to align with
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the new interrupt map.
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These updates align the Corstone-1000 platform with Arm’s latest
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Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt
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and memory mapping for both secure and non-secure domains.
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Upstream-Status: Submitted (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/)
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Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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---
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arch/arm/dts/corstone1000-fvp-u-boot.dtsi | 18 +++++-
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arch/arm/dts/corstone1000-u-boot.dtsi | 76 +++++++++++++++++++++++
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arch/arm/include/asm/armv8/cpu.h | 1 +
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board/armltd/corstone1000/Kconfig | 7 +++
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4 files changed, 99 insertions(+), 3 deletions(-)
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diff --git a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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index 6b89d653417..0539e6c092a 100644
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--- a/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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+++ b/arch/arm/dts/corstone1000-fvp-u-boot.dtsi
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@@ -17,24 +17,36 @@
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&{/cpus} {
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cpu1: cpu@1 {
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device_type = "cpu";
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- compatible = "arm,cortex-a35";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+#ifdef CONFIG_GIC_V3
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+ reg = <0x100>;
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+#else
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reg = <0x1>;
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+#endif
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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- compatible = "arm,cortex-a35";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+#ifdef CONFIG_GIC_V3
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+ reg = <0x200>;
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+#else
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reg = <0x2>;
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+#endif
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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- compatible = "arm,cortex-a35";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+#ifdef CONFIG_GIC_V3
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+ reg = <0x300>;
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+#else
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reg = <0x3>;
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+#endif
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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diff --git a/arch/arm/dts/corstone1000-u-boot.dtsi b/arch/arm/dts/corstone1000-u-boot.dtsi
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index b29ac74217e..206403ea9a5 100644
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--- a/arch/arm/dts/corstone1000-u-boot.dtsi
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+++ b/arch/arm/dts/corstone1000-u-boot.dtsi
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@@ -29,6 +29,15 @@
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};
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};
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+&{/cpus} {
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+ cpu: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a35","arm,cortex-a320";
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+ reg = <0>;
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+ next-level-cache = <&L2_0>;
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+ };
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+};
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+
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&{/soc} {
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extsys0: remoteproc@1a010310 {
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compatible = "arm,corstone1000-extsys";
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@@ -37,3 +46,70 @@
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firmware-name = "es_flashfw.elf";
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};
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};
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+
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+#ifdef CONFIG_ETHOS_U85
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+&{/reserved-memory} {
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+ ethosu_sram: ethosu_sram@02400000 {
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+ reg = <0x02400000 0x200000>;
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+ no-map;
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+ };
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+
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+ ethosu_reserved: ethosu_reserved@A0000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0xA0000000 0x02000000>;
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+ no-map;
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+ };
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+};
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+
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+/ {
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+ ethosu: ethosu@1A050000 {
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+ compatible = "arm,ethosu-direct";
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+
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+ // Base address and size of NPU registers
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+ reg = <0x1A050000 0x4000>;
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+
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+ memory-region = <ðosu_reserved>;
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+ sram = <ðosu_sram>;
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+
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+ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses
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+ dma-ranges = <0x02400000 0x02400000 0x200000>,
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+ <0xA0000000 0xA0000000 0x02000000>;
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+
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+ interrupts = <0 16 4>;
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+ interrupt-names = "irq";
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+
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+ // Memory region configuration
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+ region-cfgs = <3 3 0 3 3 3 3 3>;
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+
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+ // Memory regions used for the command stream
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+ cs-region = <2>;
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+
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+ // Memory interface configuration for Ethos-U85
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+ ethosu_mem_config {
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+ compatible = "arm,ethosu-mem-config";
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+ // <beats outstanding_read outstanding_write>
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+ sram = <0 64 32>;
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+ ext = <1 64 32>;
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+ // <mem_domain mem_type axi_port>
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+ configs = <0 0 0>,
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+ <0 0 0>,
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+ <0 0 1>,
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+ <0 0 1>;
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+ };
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+ };
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+};
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+#endif
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+#ifdef CONFIG_GIC_V3
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+gic: &{/interrupt-controller@1c000000} {
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+ compatible = "arm,gic-v3";
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+ #interrupt-cells = <3>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ interrupt-controller;
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+ reg = <0x1c000000 0x00010000>,
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+ <0x1c040000 0x00080000>;
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+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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+ };
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+#endif
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+
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diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
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index 4dbb589aab8..ffd8f8f358f 100644
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--- a/arch/arm/include/asm/armv8/cpu.h
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+++ b/arch/arm/include/asm/armv8/cpu.h
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@@ -8,6 +8,7 @@
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#define MIDR_PARTNUM_CORTEX_A57 0xD07
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#define MIDR_PARTNUM_CORTEX_A72 0xD08
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#define MIDR_PARTNUM_CORTEX_A76 0xD0B
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+#define MIDR_PARTNUM_CORTEX_A320 0xD8F
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#define MIDR_PARTNUM_SHIFT 0x4
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#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
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diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig
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index 709674d4cf7..9476d64d0b0 100644
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--- a/board/armltd/corstone1000/Kconfig
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+++ b/board/armltd/corstone1000/Kconfig
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@@ -9,4 +9,11 @@ config SYS_VENDOR
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config SYS_CONFIG_NAME
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default "corstone1000"
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+config ETHOS_U85
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+ bool "Enable Arm Ethos-U85 NPU support"
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+ default n
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+
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+config GIC_V3
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+ bool "Enable GIC v3 support"
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+ default n
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endif
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--
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2.50.1
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@@ -0,0 +1,2 @@
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CONFIG_ETHOS_U85=y
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CONFIG_GIC_V3=y
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