From 853f3e05652bf431fd4efc9ce0d5f276e22c1dc9 Mon Sep 17 00:00:00 2001 From: Arunachalam Ganapathy Date: Thu, 15 Apr 2021 10:24:57 +0100 Subject: [PATCH] arm-bsp/tc0: Update TF-A revision, add trusted-services support - Update TF-A revision - Add patch for trusted services support - Add patch for GICR changes to support latest tc0 model Change-Id: I3ba1fd9c1f89721fc6349db4e0270c8b42e9fcf0 Signed-off-by: Arunachalam Ganapathy --- ...support-for-Trusted-Services-Secure-.patch | 199 ++++++++++++++++++ .../0002-tc0-update-GICR-base-address.patch | 59 ++++++ .../trusted-firmware-a-tc0.inc | 9 +- 3 files changed, 266 insertions(+), 1 deletion(-) create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch create mode 100644 meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0002-tc0-update-GICR-base-address.patch diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch new file mode 100644 index 00000000..99e3cf28 --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch @@ -0,0 +1,199 @@ +From bda42d4e1c56022692b60447279d5321f872aa2b Mon Sep 17 00:00:00 2001 +From: Davidson K +Date: Wed, 10 Mar 2021 12:07:15 +0530 +Subject: [PATCH 1/2] product/tc0: Add support for Trusted Services Secure + Partitions + +This patch adds support for the crypto and secure storage secure +partitions for the Total Compute platform. These secure partitions +have to be managed by Hafnium executing at S-EL2 + +Signed-off-by: Davidson K +Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e +Upstream-Status: Pending [Not submitted to upstream yet] +--- + Makefile | 4 + + docs/plat/arm/arm-build-options.rst | 4 + + .../fdts/tc0_spmc_ts_optee_sp_manifest.dts | 118 ++++++++++++++++++ + plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts | 10 ++ + 4 files changed, 136 insertions(+) + create mode 100644 plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts + +diff --git a/Makefile b/Makefile +index b6c8b210c..d85c52bb4 100644 +--- a/Makefile ++++ b/Makefile +@@ -514,6 +514,10 @@ ifneq (${SPD},none) + ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp) + DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG + endif ++ ++ ifeq ($(findstring ts_optee_sp,$(ARM_SPMC_MANIFEST_DTS)),ts_optee_sp) ++ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG ++ endif + else + # All other SPDs in spd directory + SPD_DIR := spd +diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst +index a1d231357..32cf19291 100644 +--- a/docs/plat/arm/arm-build-options.rst ++++ b/docs/plat/arm/arm-build-options.rst +@@ -98,6 +98,10 @@ Arm Platform Build Options + device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest + file name contains pattern optee_sp. + ++ - ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and ++ secure-storage) as SP in tb_fw_config device tree. This flag is defined only ++ when ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern ts_optee_sp. ++ + For a better understanding of these options, the Arm development platform memory + map is explained in the :ref:`Firmware Design`. + +diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts +new file mode 100644 +index 000000000..ac91db238 +--- /dev/null ++++ b/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts +@@ -0,0 +1,118 @@ ++/* ++ * Copyright (c) 2020, Arm Limited. All rights reserved. ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++/dts-v1/; ++ ++/ { ++ compatible = "arm,ffa-core-manifest-1.0"; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ++ attribute { ++ spmc_id = <0x8000>; ++ maj_ver = <0x1>; ++ min_ver = <0x0>; ++ exec_state = <0x0>; ++ load_address = <0x0 0xfd000000>; ++ entrypoint = <0x0 0xfd000000>; ++ binary_size = <0x80000>; ++ }; ++ ++ hypervisor { ++ compatible = "hafnium,hafnium"; ++ vm1 { ++ is_ffa_partition; ++ debug_name = "op-tee"; ++ load_address = <0xfd280000>; ++ vcpu_count = <8>; ++ mem_size = <0x1980000>; /* 25MB TZC DRAM */ ++ }; ++ vm2 { ++ is_ffa_partition; ++ debug_name = "secure-storage"; ++ load_address = <0xfee00000>; ++ vcpu_count = <1>; ++ mem_size = <0x200000>; /* 2MB TZC DRAM */ ++ }; ++ vm3 { ++ is_ffa_partition; ++ debug_name = "crypto"; ++ load_address = <0xfec00000>; ++ vcpu_count = <1>; ++ mem_size = <0x200000>; /* 2MB TZC DRAM */ ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <0x2>; ++ #size-cells = <0x0>; ++ ++ CPU0:cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x0>; ++ enable-method = "psci"; ++ }; ++ ++ /* ++ * SPMC (Hafnium) requires secondary cpu nodes are declared in ++ * descending order ++ */ ++ CPU7:cpu@700 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x700>; ++ enable-method = "psci"; ++ }; ++ ++ CPU6:cpu@600 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x600>; ++ enable-method = "psci"; ++ }; ++ ++ CPU5:cpu@500 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x500>; ++ enable-method = "psci"; ++ }; ++ ++ CPU4:cpu@400 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x400>; ++ enable-method = "psci"; ++ }; ++ ++ CPU3:cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x300>; ++ enable-method = "psci"; ++ }; ++ ++ CPU2:cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x200>; ++ enable-method = "psci"; ++ }; ++ ++ CPU1:cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,armv8"; ++ reg = <0x0 0x100>; ++ enable-method = "psci"; ++ }; ++ }; ++ ++ /* 32MB of TC0_TZC_DRAM1_BASE */ ++ memory@fd000000 { ++ device_type = "memory"; ++ reg = <0x0 0xfd000000 0x2000000>; ++ }; ++}; +diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts +index de5f95d5e..82c6ccb27 100644 +--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts ++++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts +@@ -27,6 +27,16 @@ + + secure-partitions { + compatible = "arm,sp"; ++#if TS_SP_FW_CONFIG ++ secure-storage { ++ uuid = <0xdc1eef48 0x4ccfb17a 0xcfdf8bac 0x141b71f7>; ++ load-address = <0xfee00000>; ++ }; ++ crypto { ++ uuid = <0xd9df52d5 0x4bb216a2 0x6dd2a49a 0xc0e8843b>; ++ load-address = <0xfec00000>; ++ }; ++#endif + #if OPTEE_SP_FW_CONFIG + op-tee { + uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>; +-- +2.29.2 + diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0002-tc0-update-GICR-base-address.patch b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0002-tc0-update-GICR-base-address.patch new file mode 100644 index 00000000..038847bd --- /dev/null +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tc0/0002-tc0-update-GICR-base-address.patch @@ -0,0 +1,59 @@ +From bc31cd2454854ab44aa9861b98f13848c2b474aa Mon Sep 17 00:00:00 2001 +From: Usama Arif +Date: Tue, 30 Mar 2021 16:39:19 +0100 +Subject: [PATCH 2/2] tc0: update GICR base address + +The number of ITS have changed from 4 to 1, resulting +in GICR base address change. + +Signed-off-by: Usama Arif +Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7 +Upstream-Status: Pending [Not submitted to upstream yet] +--- + fdts/tc0.dts | 4 ++-- + plat/arm/board/tc0/include/platform_def.h | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/fdts/tc0.dts b/fdts/tc0.dts +index 2d7611cf2..382860d9d 100644 +--- a/fdts/tc0.dts ++++ b/fdts/tc0.dts +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2020, Arm Limited. All rights reserved. ++ * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -236,7 +236,7 @@ + ranges; + interrupt-controller; + reg = <0x0 0x30000000 0 0x10000>, /* GICD */ +- <0x0 0x30140000 0 0x200000>; /* GICR */ ++ <0x0 0x30080000 0 0x200000>; /* GICR */ + interrupts = <0x1 0x9 0x4>; + }; + +diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h +index 30b5ab716..b169d7720 100644 +--- a/plat/arm/board/tc0/include/platform_def.h ++++ b/plat/arm/board/tc0/include/platform_def.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2020, Arm Limited. All rights reserved. ++ * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -220,7 +220,7 @@ + /* GIC related constants */ + #define PLAT_ARM_GICD_BASE UL(0x30000000) + #define PLAT_ARM_GICC_BASE UL(0x2C000000) +-#define PLAT_ARM_GICR_BASE UL(0x30140000) ++#define PLAT_ARM_GICR_BASE UL(0x30080000) + + /* + * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current +-- +2.29.2 + diff --git a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc index 20b52e9d..bd35296e 100644 --- a/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc +++ b/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc @@ -3,9 +3,16 @@ # Intermediate SHA with 2.4 baseline version, required for Theodul DSU # --- This SRC_URI will be removed once below SRCREV_tfa gets merged to TF-A master SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;branch=integration;name=tfa" -SRCREV_tfa = "9bc3007d3bb9363dbd5f6655d2b17d599e22bac4" +SRCREV_tfa = "8078b5c5a0c2a47710df96412d88df53486e2b29" PV = "2.4+git${SRCPV}" +FILESEXTRAPATHS_prepend_tc0 := "${THISDIR}/files/tc0:" + +SRC_URI_append = " \ + file://0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch \ + file://0002-tc0-update-GICR-base-address.patch \ + " + DEPENDS += "scp-firmware" COMPATIBLE_MACHINE = "tc0"