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arm-bsp/trusted firmware-a: corstone1000: implement EFI reset system
This commit implements efi_reset_system for corstone1000 platform. In order to reset the system, the host uses secure host watchdog to assert an interrupt (WS1) on the secure-enclave side, then secure-enclave resets the system. Change-Id: I772181cd43e789f1d6508aaa433eb109d8f85b5d Signed-off-by: Emekcan Aras <emekcan.aras@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
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+60
@@ -0,0 +1,60 @@
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Upstream-Status: Pending [Not submitted to upstream yet]
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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From 1b99c6dd614002a79e4dda96d630089775a1d233 Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Wed, 17 Nov 2021 18:45:32 +0000
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Subject: [PATCH] corstone1000: implement platform specific psci reset
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This implements platform specific psci reset for the corstone1000.
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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---
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.../corstone1000/common/corstone1000_pm.c | 23 +++++++++++++++++--
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1 file changed, 21 insertions(+), 2 deletions(-)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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index 12b322e27..e95ab30b7 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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@@ -6,17 +6,36 @@
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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-
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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+
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+#define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000
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+#define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008
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+#define SECURE_WATCHDOG_MASK_ENABLE 0x01
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+#define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000
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+
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+static void __dead2 corstone1000_system_reset(void)
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+{
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+
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+ uint32_t volatile * const watchdog_ctrl_reg = (int *) SECURE_WATCHDOG_ADDR_CTRL_REG;
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+ uint32_t volatile * const watchdog_val_reg = (int *) SECURE_WATCHDOG_ADDR_VAL_REG;
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+
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+ *(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
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+ *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
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+ while (1){
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+ wfi();
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+ }
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+}
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+
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plat_psci_ops_t plat_arm_psci_pm_ops = {
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- /* dummy struct */
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+ .system_reset = corstone1000_system_reset,
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.validate_ns_entrypoint = NULL
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};
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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+ ops = &plat_arm_psci_pm_ops;
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return ops;
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}
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--
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2.25.1
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@@ -14,6 +14,7 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
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SRC_URI:append = " \
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SRC_URI:append = " \
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file://0001-Rename-Diphda-to-corstone1000.patch \
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file://0001-Rename-Diphda-to-corstone1000.patch \
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file://0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch \
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file://0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch \
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file://0003-corstone1000-implement-platform-specific-psci-reset.patch \
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"
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"
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TFA_DEBUG = "1"
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TFA_DEBUG = "1"
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