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Oscar Belshaw
3a97808a24
Select the TF-A and TF-A Tests 2.15 release series for Corstone1000 and update the FPGA and Cortex-A320 FVP documentation to reference the 2.15.0 recipe. Remove the TF-A Cortex-A320 and multicore patches and the TF-A Tests Cortex-A320 patch, as these changes are included upstream. Drop the obsolete TFA_MBEDTLS workaround. Add a patch to align the BL configuration mapping with the enclosing shared RAM page. ARM_FW_CONFIG_BASE follows the meminfo_t structure and is not page aligned, causing mmap_add_region_check() to reject the mapping with -EINVAL. Base the mapping at ARM_SHARED_RAM_BASE while preserving the firmware configuration load address and reserved space. Add a Corstone1000 BL2 hook that waits 25 ms after arm_io_setup() and before common GPT initialization when RESET_TO_BL2 and ARM_GPT_SUPPORT are enabled. Enable the system counter and initialize the delay timer before waiting, since their common initialization occurs later. Apply the hook to FPGA, Cortex-A35 FVP and Cortex-A320 FVP builds. The delay works around invalid MBR signatures observed during early flash access on MPS3 with TF-A 2.15. It retains the common GPT-before-MMU ordering and existing reset handling. This is a temporary timing workaround: the underlying cause remains under investigation, and 25 ms is a tested delay rather than a documented hardware requirement. Change-Id: Ic57f6474c6019edd58caeca8e2751d05d17678c7 Signed-off-by: Oscar Belshaw <Oscar.Belshaw@arm.com> Signed-off-by: Ross Burton <ross.burton@arm.com>