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These changes are to add support to build optee-os for N1SDP target. Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
47 lines
1.3 KiB
Diff
47 lines
1.3 KiB
Diff
Upstream-Status: Pending [Not submitted to upstream yet]
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Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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From 0c3ce4c09cd7d2ff4cd2e62acab899dd88dc9514 Mon Sep 17 00:00:00 2001
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From: Vishnu Banavath <vishnu.banavath@arm.com>
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Date: Wed, 20 Jul 2022 16:45:59 +0100
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Subject: [PATCH] HACK: disable instruction cache and data cache.
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For some reason, n1sdp fails to boot with instruction cache and
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data cache enabled. This is a temporary change to disable I cache
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and D cache until a proper fix is found.
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Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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%% original patch: 0003-HACK-disable-instruction-cache-and-data-cache.patch
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diff --git a/core/arch/arm/kernel/entry_a64.S b/core/arch/arm/kernel/entry_a64.S
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index 875b6e69..594d6928 100644
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--- a/core/arch/arm/kernel/entry_a64.S
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+++ b/core/arch/arm/kernel/entry_a64.S
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@@ -52,7 +52,7 @@
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.macro set_sctlr_el1
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mrs x0, sctlr_el1
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- orr x0, x0, #SCTLR_I
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+ bic x0, x0, #SCTLR_I
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orr x0, x0, #SCTLR_SA
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orr x0, x0, #SCTLR_SPAN
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#if defined(CFG_CORE_RWDATA_NOEXEC)
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@@ -490,11 +490,11 @@ LOCAL_FUNC enable_mmu , : , .identity_map
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isb
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/* Enable I and D cache */
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- mrs x1, sctlr_el1
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+ /* mrs x1, sctlr_el1
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orr x1, x1, #SCTLR_I
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orr x1, x1, #SCTLR_C
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msr sctlr_el1, x1
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- isb
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+ isb */
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/* Adjust stack pointers and return address */
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msr spsel, #1
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--
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2.17.1
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