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7680400f78
Update Corstone-1000 U-Boot device tree for the Cortex-A320 variant and enable GICv3/GIC-600, while keeping compatibility with the existing GIC-400 setup. A single DT image now supports either configuration via Kconfig guards. **Device-tree updates (Cortex-A320)** * Map Ethos-U85 NPU registers at `0x1A050000` (16 KiB) and its SRAM at `0x02400000` (2 MiB, no-map), plus a 32 MiB DDR carve-out for DMA. * Add `/ethosu@1a050000` with interrupts, `dma-ranges`, `cs-region`, and `ethosu-mem-config` for driver probe. * Guard the NPU node behind `CONFIG_ETHOS_U85`. * Add a Cortex-A320 compatible string to the Corstone-1000 DTS downstream. **GICv3/GIC-600 selection** * Introduce `CONFIG_GIC_V3` to select the new interrupt controller. * Add a full GICv3/GIC-600 node guarded by `#ifdef CONFIG_GIC_V3`. * When GICv3 is enabled, set `cpu@1..3` `reg` to `0x100/0x200/0x300` (retain `0x1/0x2/0x3` for GIC-400). * Update the Ethos-U85 interrupt to **SPI 16** to match the interrupt map. Signed-off-by: Frazer Carsley <frazer.carsley@arm.com> Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
See ../README.md