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9bcc166bd5
This change enables N1SDP cache to improve performance by removing this patch: HACK-disable-instruction-cache-and-data-cache.patch Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
53 lines
1.9 KiB
Diff
53 lines
1.9 KiB
Diff
Upstream-Status: Pending [Not submitted to upstream yet]
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Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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From 2eb1da30564428551ca687d456d848129105abac Mon Sep 17 00:00:00 2001
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From: Vishnu Banavath <vishnu.banavath@arm.com>
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Date: Tue, 25 Oct 2022 19:08:49 +0100
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Subject: [PATCH] plat-n1sdp: register DRAM1 to optee-os
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N1SDP supports two DRAM's. This change is to add 2nd DRAM
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starting at 0x8080000000 address.
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Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk
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index 06b4975a..5374e406 100644
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--- a/core/arch/arm/plat-n1sdp/conf.mk
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+++ b/core/arch/arm/plat-n1sdp/conf.mk
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@@ -38,4 +38,4 @@ CFG_SHMEM_START ?= 0x83000000
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CFG_SHMEM_SIZE ?= 0x00210000
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# DRAM1 is defined above 4G
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$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
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-$(call force,CFG_CORE_ARM64_PA_BITS,36)
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+$(call force,CFG_CORE_ARM64_PA_BITS,42)
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diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
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index cfb7f19b..bb951ce6 100644
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--- a/core/arch/arm/plat-n1sdp/main.c
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+++ b/core/arch/arm/plat-n1sdp/main.c
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@@ -33,6 +33,7 @@ static struct pl011_data console_data __nex_bss;
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
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register_ddr(DRAM0_BASE, DRAM0_SIZE);
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+register_ddr(DRAM1_BASE, DRAM1_SIZE);
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE);
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diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
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index 81b99409..bf0a3c83 100644
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--- a/core/arch/arm/plat-n1sdp/platform_config.h
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+++ b/core/arch/arm/plat-n1sdp/platform_config.h
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@@ -35,6 +35,9 @@
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#define DRAM0_BASE 0x80000000
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#define DRAM0_SIZE 0x80000000
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+#define DRAM1_BASE 0x8080000000ULL
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+#define DRAM1_SIZE 0x80000000ULL
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+
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#define GICD_BASE 0x30000000
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#define GICC_BASE 0x2C000000
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#define GICR_BASE 0x300C0000
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--
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2.17.1
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