mozjs-115: fix the build on ARMv5

The JIT uses the ISB instruction, but being a multi-core barrier
instruction this doesn't exist on the single-core ARMv5 ISA. Check the
ISA level before using ISB.

Also set [cleandirs] for ${B} to ensure clean builds are done when
reconfiguring.

[ YOCTO #14572 ]

Signed-off-by: Ross Burton <ross.burton@arm.com>
Signed-off-by: Khem Raj <raj.khem@gmail.com>

meta-oe/recipes-extended/mozjs/mozjs-115/armv5.patch

@@ -0,0 +1,19 @@
+The ISB instruction isn't available in ARMv5 or v6, so
+guard it's use to fix the build on qemuarmv5.
+
+Upstream-Status: Pending
+Signed-off-by: Ross Burton <ross.burton@arm.com>
+
+diff --git a/js/src/jit/arm/Architecture-arm.cpp b/js/src/jit/arm/Architecture-arm.cpp
+--- a/js/src/jit/arm/Architecture-arm.cpp	2024-01-18 17:31:32.078718197 +0000
++++ b/js/src/jit/arm/Architecture-arm.cpp	2024-01-18 18:00:16.738921445 +0000
+@@ -529,7 +529,9 @@
+ void FlushExecutionContext() {
+ #ifndef JS_SIMULATOR_ARM
++#if __ARM_ARCH >= 7
+   // Ensure that any instructions already in the pipeline are discarded and
+   // reloaded from the icache.
+   asm volatile("isb\n" : : : "memory");
++#endif
+ #else
+   // We assume the icache flushing routines on other platforms take care of this

meta-oe/recipes-extended/mozjs/mozjs-115_115.6.0.bb

@@ -16,6 +16,7 @@ SRC_URI = "https://archive.mozilla.org/pub/firefox/releases/${PV}esr/source/fire
            file://musl-disable-stackwalk.patch \
            file://0001-add-arm-to-list-of-mozinline.patch \
            file://py3.12.patch \
+           file://armv5.patch \
            "
 SRC_URI[sha256sum] = "66d7e6e5129ac8e6fe83e24227dc7bb8dc42650bc53b21838e614de80d22bc66"
 
@@ -75,6 +76,7 @@ do_configure() {
         ${JIT} \
         ${ICU}
 }
+do_configure[cleandirs] += "${B}"
 
 do_install() {
     oe_runmake 'DESTDIR=${D}' install