mirror of
https://github.com/openembedded/meta-openembedded.git
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Robert Joslyn
6704d6d3d7
This is a security and bugfix release. With this update, the backported patches for CVE-2021-2314 and CVE-2021-23222 are no longer needed. Full release notes are available at: https://www.postgresql.org/docs/release/13.5/ Signed-off-by: Robert Joslyn <robert.joslyn@redrectangle.org> Signed-off-by: Armin Kuster <akuster808@gmail.com>
39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
From 0b60fe3c39b2f62f9867d955da82d9d20c42d028 Mon Sep 17 00:00:00 2001
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From: "Richard W.M. Jones" <rjones@redhat.com>
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Date: Sun, 20 Nov 2016 15:04:52 +0000
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Subject: [PATCH] Add support for RISC-V.
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The architecture is sufficiently similar to aarch64 that simply
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extending the existing aarch64 macro works.
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---
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src/include/storage/s_lock.h | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
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index 6b368a5..f7d3387 100644
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--- a/src/include/storage/s_lock.h
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+++ b/src/include/storage/s_lock.h
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@@ -317,11 +317,12 @@ tas(volatile slock_t *lock)
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/*
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* On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
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+ * On RISC-V, the same.
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*
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* We use the int-width variant of the builtin because it works on more chips
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* than other widths.
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*/
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-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64)
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+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv)
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#ifdef HAVE_GCC__SYNC_INT32_TAS
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#define HAS_TEST_AND_SET
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@@ -338,7 +339,7 @@ tas(volatile slock_t *lock)
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#define S_UNLOCK(lock) __sync_lock_release(lock)
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#endif /* HAVE_GCC__SYNC_INT32_TAS */
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-#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */
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+#endif /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */
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/*
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