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Koen Kooi
ff0f815593
Acked-by: Martin Jansa <Martin.Jansa@gmail.com> Acked-by: Eric Bénard <eric@eukrea.com> Acked-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
104 lines
4.0 KiB
Diff
104 lines
4.0 KiB
Diff
Date: Mon, 22 Nov 2010 13:28:54 +0000
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From: Julian Brown <julian at codesourcery dot com>
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To: gcc-patches at gcc dot gnu dot org
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Cc: DJ Delorie <dj at redhat dot com>
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Subject: [PATCH] Volatile bitfields vs. inline asm memory constraints
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Message-ID: <20101122132854.0aca431a@rex.config>
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Mime-Version: 1.0
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Content-Type: multipart/mixed; boundary="MP_/ONpW806RnQ1ziaYj7_Y5E27"
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Mailing-List: contact gcc-patches-help at gcc dot gnu dot org; run by ezmlm
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Precedence: bulk
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List-Id: <gcc-patches.gcc.gnu.org>
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List-Archive: <http://gcc.gnu.org/ml/gcc-patches/>
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List-Post: <mailto:gcc-patches at gcc dot gnu dot org>
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List-Help: <mailto:gcc-patches-help at gcc dot gnu dot org>
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Sender: gcc-patches-owner at gcc dot gnu dot org
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Delivered-To: mailing list gcc-patches at gcc dot gnu dot org
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Hi,
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This patch fixes the issue in the (Launchpad, not GCC) bug tracker:
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https://bugs.launchpad.net/gcc-linaro/+bug/675347
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The problem was introduced by the patch from DJ to honour volatile
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bitfield types:
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http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01167.html
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but not exposed (on ARM) until the option was made the default (on the
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Linaro branch) -- it's not yet the default on mainline.
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The issue is as follows: after DJ's patch and with
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-fstrict-volatile-bitfields, in expr.c:expand_expr_real_1, the if
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condition with the comment "In cases where an aligned union has an
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unaligned object as a field, we might be extracting a BLKmode value
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from an integer-mode (e.g., SImode) object [...]" triggers for a normal
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(non-bitfield) volatile field of a struct/class.
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But, this appears to be over-eager: in the particular case mentioned
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above, when expanding a "volatile int" struct field used as a memory
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constraint for an inline asm, we end up with something which is no
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longer addressable (I think because of the actions of
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extract_bit_field). So, compilation aborts.
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My proposed fix is to restrict the conditional by only making it execute
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for -fstrict-volatile-bitfields only for non-naturally-aligned accesses:
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this appears to work (fixes test in question, and no regressions for
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cross to ARM Linux, gcc/g++/libstdc++, with -fstrict-volatile-bitfields
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turned on), but I don't know if there will be unintended consequences.
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DJ, does it look sane to you?
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Incidentally the constraints in the inline asm in the Launchpad
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testcase might be slightly dubious (attempting to force (mem (reg)) by
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using both "+m" (var) and "r" (&var) constraints), but replacing
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them with e.g.:
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asm volatile("0:\n"
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"ldrex %[newValue], %[_q_value]\n"
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"sub %[newValue], %[newValue], #1\n"
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"strex %[result], %[newValue], %[_q_value]\n"
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"teq %[result], #0\n"
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"bne 0b\n"
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: [newValue] "=&r" (newValue),
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[result] "=&r" (result)
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: [_q_value] "Q" (_q_value)
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: "cc", "memory");
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still leads to a warning (not an error) with trunk and
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-fstrict-volatile-bitfields:
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atomic-changed.cc:24:35: warning: use of memory input without lvalue in
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asm operand 2 is deprecated [enabled by default]
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The warning goes away with the attached patch. So, I don't think the
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problem is purely that the original inline asm is invalid.
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OK to apply, or any comments?
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Julian
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ChangeLog
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gcc/
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* expr.c (expand_expr_real_1): Only use BLKmode for volatile
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accesses which are not naturally aligned.
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Index: gcc-4_5-branch/gcc/expr.c
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===================================================================
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--- gcc-4_5-branch.orig/gcc/expr.c 2010-12-23 00:42:11.690101002 -0800
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+++ gcc-4_5-branch/gcc/expr.c 2010-12-24 15:07:39.400101000 -0800
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@@ -9029,7 +9029,8 @@
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&& modifier != EXPAND_INITIALIZER)
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/* If the field is volatile, we always want an aligned
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access. */
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- || (volatilep && flag_strict_volatile_bitfields > 0)
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+ || (volatilep && flag_strict_volatile_bitfields > 0
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+ && (bitpos % GET_MODE_ALIGNMENT (mode) != 0))
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/* If the field isn't aligned enough to fetch as a memref,
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fetch it as a bit field. */
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|| (mode1 != BLKmode
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