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f88e5b146e
License-Update: Update lincense year to 2024 In version 16.2, ICU support is enabled by default, add PACKAGECONFIG icu to align with upstream, enable icu by default. And fix buildpaths QA warning. Signed-off-by: Changqing Li <changqing.li@windriver.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
From ba079b8d6a50796db41bb0ddf4c22bfe022ef898 Mon Sep 17 00:00:00 2001
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From: "Richard W.M. Jones" <rjones@redhat.com>
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Date: Sun, 20 Nov 2016 15:04:52 +0000
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Subject: [PATCH 1/5] Add support for RISC-V.
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The architecture is sufficiently similar to aarch64 that simply
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extending the existing aarch64 macro works.
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---
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src/include/storage/s_lock.h | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
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index c9fa84c..9b491e8 100644
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--- a/src/include/storage/s_lock.h
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+++ b/src/include/storage/s_lock.h
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@@ -252,11 +252,12 @@ spin_delay(void)
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/*
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* On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
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+ * On RISC-V, the same.
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*
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* We use the int-width variant of the builtin because it works on more chips
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* than other widths.
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*/
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-#if defined(__arm__) || defined(__arm) || defined(__aarch64__)
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+#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__riscv)
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#ifdef HAVE_GCC__SYNC_INT32_TAS
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#define HAS_TEST_AND_SET
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@@ -290,7 +291,7 @@ spin_delay(void)
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#endif /* __aarch64__ */
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#endif /* HAVE_GCC__SYNC_INT32_TAS */
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-#endif /* __arm__ || __arm || __aarch64__ */
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+#endif /* __arm__ || __arm || __aarch64__ || __riscv */
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/* S/390 and S/390x Linux (32- and 64-bit zSeries) */
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--
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2.25.1
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