From bf01840f5bf1fc8e5542251bc4eb26f823f50ae5 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Wed, 26 Dec 2018 14:41:00 -0800 Subject: [PATCH] rust-cross: Add riscv64 data layout information clang --target=riscv64 -emit-llvm -S -x c /dev/null -o aaa | cat aaa | grep "target datalayout" Signed-off-by: Khem Raj --- recipes-devtools/rust/rust.inc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/recipes-devtools/rust/rust.inc b/recipes-devtools/rust/rust.inc index d360d70..f526476 100644 --- a/recipes-devtools/rust/rust.inc +++ b/recipes-devtools/rust/rust.inc @@ -218,6 +218,14 @@ TARGET_POINTER_WIDTH[powerpc] = "32" TARGET_C_INT_WIDTH[powerpc] = "32" MAX_ATOMIC_WIDTH[powerpc] = "32" +## riscv64-unknown-linux-{gnu, musl} +DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" +LLVM_TARGET[riscv64] = "${RUST_TARGET_SYS}" +TARGET_ENDIAN[riscv64] = "little" +TARGET_POINTER_WIDTH[riscv64] = "64" +TARGET_C_INT_WIDTH[riscv64] = "64" +MAX_ATOMIC_WIDTH[riscv64] = "64" + def arch_for(d, thing): return d.getVar('{}_ARCH'.format(thing))