* get rid of annoying
'+v8' is not a recognized feature for this target (ignoring feature)
messages in aarch64 builds, they are shown in the log very often:
$ grep -c 'is not a recognized feature for this target (ignoring feature)' cargo/1.49.0-r0/temp/log.do_compile.76960
3824
and sometimes the formatting looks strange as well e.g.:
| ''+v8' is not a recognized feature for this target (ignoring feature)
| +v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| ''+v8+v8' is not a recognized feature for this target' is not a recognized feature for this target (ignoring feature)
| (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| ''''''+v8+v8+v8+v8+v8' is not a recognized feature for this target' is not a recognized feature for this target' is not a recognized feature for this target' is not a recognized feature for this target' is not a recognized feature for this target+v8 (ignoring feature)
| (ignoring feature)
| (ignoring feature)
| (ignoring feature)
| (ignoring feature)
| ' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| '+v8' is not a recognized feature for this target (ignoring feature)
| ''+v8+v8' is not a recognized feature for this target' is not a recognized feature for this target (ignoring feature)
| (ignoring feature)
* not sure when it was changed (if 'v8' ever was valid feature for aarch64)
but with 1.49.0 rustc (from gentoo) I see following cpu and feature options
for arm and aarch64 (and v8 is listed only for arm, for aarch64 only v8.[123456]a)
# rustc --target=arm-unknown-linux-gnueabihf --print target-cpus
Available CPUs for this target:
arm1020e
arm1020t
arm1022e
arm10e
arm10tdmi
arm1136j-s
arm1136jf-s
arm1156t2-s
arm1156t2f-s
arm1176j-s
arm1176jz-s
arm1176jzf-s
arm710t
arm720t
arm7tdmi
arm7tdmi-s
arm8
arm810
arm9
arm920
arm920t
arm922t
arm926ej-s
arm940t
arm946e-s
arm966e-s
arm968e-s
arm9e
arm9tdmi
cortex-a12
cortex-a15
cortex-a17
cortex-a32
cortex-a35
cortex-a5
cortex-a53
cortex-a55
cortex-a57
cortex-a7
cortex-a72
cortex-a73
cortex-a75
cortex-a76
cortex-a76ae
cortex-a77
cortex-a78
cortex-a8
cortex-a9
cortex-m0
cortex-m0plus
cortex-m1
cortex-m23
cortex-m3
cortex-m33
cortex-m35p
cortex-m4
cortex-m55
cortex-m7
cortex-r4
cortex-r4f
cortex-r5
cortex-r52
cortex-r7
cortex-r8
cortex-x1
cyclone
ep9312
exynos-m3
exynos-m4
exynos-m5
generic
iwmmxt
krait
kryo
mpcore
mpcorenovfp
neoverse-n1
sc000
sc300
strongarm
strongarm110
strongarm1100
strongarm1110
swift
xscale
# rustc --target=aarch64-unknown-linux-gnu --print target-cpus
Available CPUs for this target:
a64fx
apple-a10
apple-a11
apple-a12
apple-a13
apple-a7
apple-a8
apple-a9
apple-latest
apple-s4
apple-s5
carmel
cortex-a34
cortex-a35
cortex-a53
cortex-a55
cortex-a57
cortex-a65
cortex-a65ae
cortex-a72
cortex-a73
cortex-a75
cortex-a76
cortex-a76ae
cortex-a77
cortex-a78
cortex-x1
cyclone
exynos-m3
exynos-m4
exynos-m5
falkor
generic
kryo
neoverse-e1
neoverse-n1
saphira
thunderx
thunderx2t99
thunderx3t110
thunderxt81
thunderxt83
thunderxt88
tsv110
# rustc --target=arm-unknown-linux-gnueabihf --print target-features
Available features for this target:
32bit - Prefer 32-bit Thumb instrs.
8msecext - Enable support for ARMv8-M Security Extensions.
a12 - Cortex-A12 ARM processors.
a15 - Cortex-A15 ARM processors.
a17 - Cortex-A17 ARM processors.
a32 - Cortex-A32 ARM processors.
a35 - Cortex-A35 ARM processors.
a5 - Cortex-A5 ARM processors.
a53 - Cortex-A53 ARM processors.
a55 - Cortex-A55 ARM processors.
a57 - Cortex-A57 ARM processors.
a7 - Cortex-A7 ARM processors.
a72 - Cortex-A72 ARM processors.
a73 - Cortex-A73 ARM processors.
a75 - Cortex-A75 ARM processors.
a76 - Cortex-A76 ARM processors.
a77 - Cortex-A77 ARM processors.
a8 - Cortex-A8 ARM processors.
a9 - Cortex-A9 ARM processors.
aclass - Is application profile ('A' series).
acquire-release - Has v8 acquire/release (lda/ldaex etc) instructions.
aes - Enable AES support.
armv2 - ARMv2 architecture.
armv2a - ARMv2a architecture.
armv3 - ARMv3 architecture.
armv3m - ARMv3m architecture.
armv4 - ARMv4 architecture.
armv4t - ARMv4t architecture.
armv5t - ARMv5t architecture.
armv5te - ARMv5te architecture.
armv5tej - ARMv5tej architecture.
armv6 - ARMv6 architecture.
armv6-m - ARMv6m architecture.
armv6j - ARMv7a architecture.
armv6k - ARMv6k architecture.
armv6kz - ARMv6kz architecture.
armv6s-m - ARMv6sm architecture.
armv6t2 - ARMv6t2 architecture.
armv7-a - ARMv7a architecture.
armv7-m - ARMv7m architecture.
armv7-r - ARMv7r architecture.
armv7e-m - ARMv7em architecture.
armv7k - ARMv7a architecture.
armv7s - ARMv7a architecture.
armv7ve - ARMv7ve architecture.
armv8-a - ARMv8a architecture.
armv8-m.base - ARMv8mBaseline architecture.
armv8-m.main - ARMv8mMainline architecture.
armv8-r - ARMv8r architecture.
armv8.1-a - ARMv81a architecture.
armv8.1-m.main - ARMv81mMainline architecture.
armv8.2-a - ARMv82a architecture.
armv8.3-a - ARMv83a architecture.
armv8.4-a - ARMv84a architecture.
armv8.5-a - ARMv85a architecture.
armv8.6-a - ARMv86a architecture.
avoid-movs-shop - Avoid movs instructions with shifter operand.
avoid-partial-cpsr - Avoid CPSR partial update for OOO execution.
bf16 - Enable support for BFloat16 instructions.
cde - Support CDE instructions.
cdecp0 - Coprocessor 0 ISA is CDEv1.
cdecp1 - Coprocessor 1 ISA is CDEv1.
cdecp2 - Coprocessor 2 ISA is CDEv1.
cdecp3 - Coprocessor 3 ISA is CDEv1.
cdecp4 - Coprocessor 4 ISA is CDEv1.
cdecp5 - Coprocessor 5 ISA is CDEv1.
cdecp6 - Coprocessor 6 ISA is CDEv1.
cdecp7 - Coprocessor 7 ISA is CDEv1.
cheap-predicable-cpsr - Disable +1 predication cost for instructions updating CPSR.
cortex-a78 - Cortex-A78 ARM processors.
cortex-x1 - Cortex-X1 ARM processors.
crc - Enable support for CRC instructions.
crypto - Enable support for Cryptography extensions.
d32 - Extend FP to 32 double registers.
db - Has data barrier (dmb/dsb) instructions.
dfb - Has full data barrier (dfb) instruction.
disable-postra-scheduler - Don't schedule again after register allocation.
dont-widen-vmovs - Don't widen VMOVS to VMOVD.
dotprod - Enable support for dot product instructions.
dsp - Supports DSP instructions in ARM and/or Thumb2.
execute-only - Enable the generation of execute only code..
expand-fp-mlx - Expand VFP/NEON MLA/MLS instructions.
exynos - Samsung Exynos processors.
fp-armv8 - Enable ARMv8 FP.
fp-armv8d16 - Enable ARMv8 FP with only 16 d-registers.
fp-armv8d16sp - Enable ARMv8 FP with only 16 d-registers and no double precision.
fp-armv8sp - Enable ARMv8 FP with no double precision.
fp16 - Enable half-precision floating point.
fp16fml - Enable full half-precision floating point fml instructions.
fp64 - Floating point unit supports double precision.
fpao - Enable fast computation of positive address offsets.
fpregs - Enable FP registers.
fpregs16 - Enable 16-bit FP registers.
fpregs64 - Enable 64-bit FP registers.
fullfp16 - Enable full half-precision floating point.
fuse-aes - CPU fuses AES crypto operations.
fuse-literals - CPU fuses literal generation operations.
hwdiv - Enable divide instructions in Thumb.
hwdiv-arm - Enable divide instructions in ARM mode.
i8mm - Enable Matrix Multiply Int8 Extension.
iwmmxt - ARMv5te architecture.
iwmmxt2 - ARMv5te architecture.
krait - Qualcomm Krait processors.
kryo - Qualcomm Kryo processors.
lob - Enable Low Overhead Branch extensions.
long-calls - Generate calls via indirect call instructions.
loop-align - Prefer 32-bit alignment for loops.
m3 - Cortex-M3 ARM processors.
mclass - Is microcontroller profile ('M' series).
mp - Supports Multiprocessing extension.
muxed-units - Has muxed AGU and NEON/FPU.
mve - Support M-Class Vector Extension with integer ops.
mve.fp - Support M-Class Vector Extension with integer and floating ops.
mve1beat - Model MVE instructions as a 1 beat per tick architecture.
mve2beat - Model MVE instructions as a 2 beats per tick architecture.
mve4beat - Model MVE instructions as a 4 beats per tick architecture.
nacl-trap - NaCl trap.
neon - Enable NEON instructions.
neon-fpmovs - Convert VMOVSR, VMOVRS, VMOVS to NEON.
neonfp - Use NEON for single precision FP.
no-branch-predictor - Has no branch predictor.
no-movt - Don't use movt/movw pairs for 32-bit imms.
no-neg-immediates - Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding..
noarm - Does not support ARM mode execution.
nonpipelined-vfp - VFP instructions are not pipelined.
perfmon - Enable support for Performance Monitor extensions.
prefer-ishst - Prefer ISHST barriers.
prefer-vmovsr - Prefer VMOVSR.
prof-unpr - Is profitable to unpredicate.
r4 - Cortex-R4 ARM processors.
r5 - Cortex-R5 ARM processors.
r52 - Cortex-R52 ARM processors.
r7 - Cortex-R7 ARM processors.
ras - Enable Reliability, Availability and Serviceability extensions.
rclass - Is realtime profile ('R' series).
read-tp-hard - Reading thread pointer from register.
reserve-r9 - Reserve R9, making it unavailable as GPR.
ret-addr-stack - Has return address stack.
sb - Enable v8.5a Speculation Barrier.
sha2 - Enable SHA1 and SHA256 support.
slow-fp-brcc - FP compare + branch is slow.
slow-load-D-subreg - Loading into D subregs is slow.
slow-odd-reg - VLDM/VSTM starting with an odd register is slow.
slow-vdup32 - Has slow VDUP32 - prefer VMOV.
slow-vgetlni32 - Has slow VGETLNi32 - prefer VMOV.
slowfpvfmx - Disable VFP / NEON FMA instructions.
slowfpvmlx - Disable VFP / NEON MAC instructions.
soft-float - Use software floating point features..
splat-vfp-neon - Splat register from VFP to NEON.
strict-align - Disallow all unaligned memory access.
swift - Swift ARM processors.
thumb-mode - Thumb mode.
thumb2 - Enable Thumb2 instructions.
trustzone - Enable support for TrustZone security extensions.
use-misched - Use the MachineScheduler.
v4t - Support ARM v4T instructions.
v5t - Support ARM v5T instructions.
v5te - Support ARM v5TE, v5TEj, and v5TExp instructions.
v6 - Support ARM v6 instructions.
v6k - Support ARM v6k instructions.
v6m - Support ARM v6M instructions.
v6t2 - Support ARM v6t2 instructions.
v7 - Support ARM v7 instructions.
v7clrex - Has v7 clrex instruction.
v8 - Support ARM v8 instructions.
v8.1a - Support ARM v8.1a instructions.
v8.1m.main - Support ARM v8-1M Mainline instructions.
v8.2a - Support ARM v8.2a instructions.
v8.3a - Support ARM v8.3a instructions.
v8.4a - Support ARM v8.4a instructions.
v8.5a - Support ARM v8.5a instructions.
v8.6a - Support ARM v8.6a instructions.
v8m - Support ARM v8M Baseline instructions.
v8m.main - Support ARM v8M Mainline instructions.
vfp2 - Enable VFP2 instructions.
vfp2sp - Enable VFP2 instructions with no double precision.
vfp3 - Enable VFP3 instructions.
vfp3d16 - Enable VFP3 instructions with only 16 d-registers.
vfp3d16sp - Enable VFP3 instructions with only 16 d-registers and no double precision.
vfp3sp - Enable VFP3 instructions with no double precision.
vfp4 - Enable VFP4 instructions.
vfp4d16 - Enable VFP4 instructions with only 16 d-registers.
vfp4d16sp - Enable VFP4 instructions with only 16 d-registers and no double precision.
vfp4sp - Enable VFP4 instructions with no double precision.
virtualization - Supports Virtualization extension.
vldn-align - Check for VLDn unaligned access.
vmlx-forwarding - Has multiplier accumulator forwarding.
vmlx-hazards - Has VMLx hazards.
wide-stride-vfp - Use a wide stride when allocating VFP registers.
xscale - ARMv5te architecture.
zcz - Has zero-cycle zeroing instructions.
Rust-specific features:
crt-static - Enables libraries with C Run-time Libraries(CRT) to be statically linked.
Use +feature to enable a feature, or -feature to disable it.
For example, rustc -C -target-cpu=mycpu -C target-feature=+feature1,-feature2
# rustc --target=aarch64-unknown-linux-gnu --print target-features
Available features for this target:
a35 - Cortex-A35 ARM processors.
a53 - Cortex-A53 ARM processors.
a55 - Cortex-A55 ARM processors.
a57 - Cortex-A57 ARM processors.
a64fx - Fujitsu A64FX processors.
a65 - Cortex-A65 ARM processors.
a72 - Cortex-A72 ARM processors.
a73 - Cortex-A73 ARM processors.
a75 - Cortex-A75 ARM processors.
a76 - Cortex-A76 ARM processors.
a77 - Cortex-A77 ARM processors.
aes - Enable AES support.
aggressive-fma - Enable Aggressive FMA for floating-point..
alternate-sextload-cvt-f32-pattern - Use alternative pattern for sextload convert to f32.
altnzcv - Enable alternative NZCV format for floating point comparisons.
am - Enable v8.4-A Activity Monitors extension.
amvs - Enable v8.6-A Activity Monitors Virtualization support.
apple-a10 - Apple A10.
apple-a11 - Apple A11.
apple-a12 - Apple A12.
apple-a13 - Apple A13.
apple-a7 - Apple A7 (the CPU formerly known as Cyclone).
arith-bcc-fusion - CPU fuses arithmetic+bcc operations.
arith-cbz-fusion - CPU fuses arithmetic + cbz/cbnz operations.
balance-fp-ops - balance mix of odd and even D-registers for fp multiply(-accumulate) ops.
bf16 - Enable BFloat16 Extension.
bti - Enable Branch Target Identification.
call-saved-x10 - Make X10 callee saved..
call-saved-x11 - Make X11 callee saved..
call-saved-x12 - Make X12 callee saved..
call-saved-x13 - Make X13 callee saved..
call-saved-x14 - Make X14 callee saved..
call-saved-x15 - Make X15 callee saved..
call-saved-x18 - Make X18 callee saved..
call-saved-x8 - Make X8 callee saved..
call-saved-x9 - Make X9 callee saved..
carmel - Nvidia Carmel processors.
ccdp - Enable v8.5 Cache Clean to Point of Deep Persistence.
ccidx - Enable v8.3-A Extend of the CCSIDR number of sets.
ccpp - Enable v8.2 data Cache Clean to Point of Persistence.
complxnum - Enable v8.3-A Floating-point complex number support.
cortex-a78 - Cortex-A78 ARM processors.
cortex-x1 - Cortex-X1 ARM processors.
crc - Enable ARMv8 CRC-32 checksum instructions.
crypto - Enable cryptographic instructions.
custom-cheap-as-move - Use custom handling of cheap instructions.
disable-latency-sched-heuristic - Disable latency scheduling heuristic.
dit - Enable v8.4-A Data Independent Timing instructions.
dotprod - Enable dot product support.
ecv - Enable enhanced counter virtualization extension.
ete - Enable Embedded Trace Extension.
exynos-cheap-as-move - Use Exynos specific handling of cheap instructions.
exynosm3 - Samsung Exynos-M3 processors.
exynosm4 - Samsung Exynos-M4 processors.
f32mm - Enable Matrix Multiply FP32 Extension.
f64mm - Enable Matrix Multiply FP64 Extension.
falkor - Qualcomm Falkor processors.
fgt - Enable fine grained virtualization traps extension.
fmi - Enable v8.4-A Flag Manipulation Instructions.
force-32bit-jump-tables - Force jump table entries to be 32-bits wide except at MinSize.
fp-armv8 - Enable ARMv8 FP.
fp16fml - Enable FP16 FML instructions.
fptoint - Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int.
fullfp16 - Full FP16.
fuse-address - CPU fuses address generation and memory operations.
fuse-aes - CPU fuses AES crypto operations.
fuse-arith-logic - CPU fuses arithmetic and logic operations.
fuse-crypto-eor - CPU fuses AES/PMULL and EOR operations.
fuse-csel - CPU fuses conditional select operations.
fuse-literals - CPU fuses literal generation operations.
harden-sls-blr - Harden against straight line speculation across BLR instructions.
harden-sls-retbr - Harden against straight line speculation across RET and BR instructions.
i8mm - Enable Matrix Multiply Int8 Extension.
jsconv - Enable v8.3-A JavaScript FP conversion instructions.
kryo - Qualcomm Kryo processors.
lor - Enables ARM v8.1 Limited Ordering Regions extension.
lse - Enable ARMv8.1 Large System Extension (LSE) atomic instructions.
lsl-fast - CPU has a fastpath logical shift of up to 3 places.
mpam - Enable v8.4-A Memory system Partitioning and Monitoring extension.
mte - Enable Memory Tagging Extension.
neon - Enable Advanced SIMD instructions.
neoversee1 - Neoverse E1 ARM processors.
neoversen1 - Neoverse N1 ARM processors.
no-neg-immediates - Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding..
nv - Enable v8.4-A Nested Virtualization Enchancement.
pa - Enable v8.3-A Pointer Authentication extension.
pan - Enables ARM v8.1 Privileged Access-Never extension.
pan-rwv - Enable v8.2 PAN s1e1R and s1e1W Variants.
perfmon - Enable ARMv8 PMUv3 Performance Monitors extension.
pmu - Enable v8.4-A PMU extension.
predictable-select-expensive - Prefer likely predicted branches over selects.
predres - Enable v8.5a execution and data prediction invalidation instructions.
rand - Enable Random Number generation instructions.
ras - Enable ARMv8 Reliability, Availability and Serviceability Extensions.
rasv8_4 - Enable v8.4-A Reliability, Availability and Serviceability extension.
rcpc - Enable support for RCPC extension.
rcpc-immo - Enable v8.4-A RCPC instructions with Immediate Offsets.
rdm - Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions.
reserve-x1 - Reserve X1, making it unavailable as a GPR.
reserve-x10 - Reserve X10, making it unavailable as a GPR.
reserve-x11 - Reserve X11, making it unavailable as a GPR.
reserve-x12 - Reserve X12, making it unavailable as a GPR.
reserve-x13 - Reserve X13, making it unavailable as a GPR.
reserve-x14 - Reserve X14, making it unavailable as a GPR.
reserve-x15 - Reserve X15, making it unavailable as a GPR.
reserve-x18 - Reserve X18, making it unavailable as a GPR.
reserve-x2 - Reserve X2, making it unavailable as a GPR.
reserve-x20 - Reserve X20, making it unavailable as a GPR.
reserve-x21 - Reserve X21, making it unavailable as a GPR.
reserve-x22 - Reserve X22, making it unavailable as a GPR.
reserve-x23 - Reserve X23, making it unavailable as a GPR.
reserve-x24 - Reserve X24, making it unavailable as a GPR.
reserve-x25 - Reserve X25, making it unavailable as a GPR.
reserve-x26 - Reserve X26, making it unavailable as a GPR.
reserve-x27 - Reserve X27, making it unavailable as a GPR.
reserve-x28 - Reserve X28, making it unavailable as a GPR.
reserve-x3 - Reserve X3, making it unavailable as a GPR.
reserve-x30 - Reserve X30, making it unavailable as a GPR.
reserve-x4 - Reserve X4, making it unavailable as a GPR.
reserve-x5 - Reserve X5, making it unavailable as a GPR.
reserve-x6 - Reserve X6, making it unavailable as a GPR.
reserve-x7 - Reserve X7, making it unavailable as a GPR.
reserve-x9 - Reserve X9, making it unavailable as a GPR.
saphira - Qualcomm Saphira processors.
sb - Enable v8.5 Speculation Barrier.
sel2 - Enable v8.4-A Secure Exception Level 2 extension.
sha2 - Enable SHA1 and SHA256 support.
sha3 - Enable SHA512 and SHA3 support.
slow-misaligned-128store - Misaligned 128 bit stores are slow.
slow-paired-128 - Paired 128 bit loads and stores are slow.
slow-strqro-store - STR of Q register with register offset is slow.
sm4 - Enable SM3 and SM4 support.
spe - Enable Statistical Profiling extension.
specrestrict - Enable architectural speculation restriction.
ssbs - Enable Speculative Store Bypass Safe bit.
strict-align - Disallow all unaligned memory access.
sve - Enable Scalable Vector Extension (SVE) instructions.
sve2 - Enable Scalable Vector Extension 2 (SVE2) instructions.
sve2-aes - Enable AES SVE2 instructions.
sve2-bitperm - Enable bit permutation SVE2 instructions.
sve2-sha3 - Enable SHA3 SVE2 instructions.
sve2-sm4 - Enable SM4 SVE2 instructions.
tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.
thunderx - Cavium ThunderX processors.
thunderx2t99 - Cavium ThunderX2 processors.
thunderx3t110 - Marvell ThunderX3 processors.
thunderxt81 - Cavium ThunderX processors.
thunderxt83 - Cavium ThunderX processors.
thunderxt88 - Cavium ThunderX processors.
tlb-rmi - Enable v8.4-A TLB Range and Maintenance Instructions.
tme - Enable Transactional Memory Extension.
tpidr-el1 - Permit use of TPIDR_EL1 for the TLS base.
tpidr-el2 - Permit use of TPIDR_EL2 for the TLS base.
tpidr-el3 - Permit use of TPIDR_EL3 for the TLS base.
tracev8.4 - Enable v8.4-A Trace extension.
trbe - Enable Trace Buffer Extension.
tsv110 - HiSilicon TS-V110 processors.
uaops - Enable v8.2 UAO PState.
use-aa - Use alias analysis during codegen.
use-experimental-zeroing-pseudos - Hint to the compiler that the MOVPRFX instruction is merged with destructive operations.
use-postra-scheduler - Schedule again after register allocation.
use-reciprocal-square-root - Use the reciprocal square root approximation.
v8.1a - Support ARM v8.1a instructions.
v8.2a - Support ARM v8.2a instructions.
v8.3a - Support ARM v8.3a instructions.
v8.4a - Support ARM v8.4a instructions.
v8.5a - Support ARM v8.5a instructions.
v8.6a - Support ARM v8.6a instructions.
vh - Enables ARM v8.1 Virtual Host extension.
zcm - Has zero-cycle register moves.
zcz - Has zero-cycle zeroing instructions.
zcz-fp - Has zero-cycle zeroing instructions for FP registers.
zcz-fp-workaround - The zero-cycle floating-point zeroing instruction has a bug.
zcz-gp - Has zero-cycle zeroing instructions for generic registers.
Rust-specific features:
crt-static - Enables libraries with C Run-time Libraries(CRT) to be statically linked.
Use +feature to enable a feature, or -feature to disable it.
For example, rustc -C -target-cpu=mycpu -C target-feature=+feature1,-feature2
Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
534 lines
17 KiB
PHP
534 lines
17 KiB
PHP
SUMMARY = "Rust compiler and runtime libaries"
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HOMEPAGE = "http://www.rust-lang.org"
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SECTION = "devel"
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LICENSE = "MIT | Apache-2.0"
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LIC_FILES_CHKSUM = "file://COPYRIGHT;md5=93a95682d51b4cb0a633a97046940ef0"
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inherit rust
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inherit cargo_common
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DEPENDS += "file-native python3-native"
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DEPENDS_append_class-native = " rust-llvm-native"
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S = "${RUSTSRC}"
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# We generate local targets, and need to be able to locate them
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export RUST_TARGET_PATH="${WORKDIR}/targets/"
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export FORCE_CRATE_HASH="${BB_TASKHASH}"
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export YOCTO_ALTERNATE_EXE_PATH = "${STAGING_LIBDIR}/llvm-rust/bin/llvm-config"
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export YOCTO_ALTERNATE_MULTILIB_NAME = "/${BASELIB}"
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# We don't want to use bitbakes vendoring because the rust sources do their
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# own vendoring.
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CARGO_DISABLE_BITBAKE_VENDORING = "1"
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# We can't use RUST_BUILD_SYS here because that may be "musl" if
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# TCLIBC="musl". Snapshots are always -unknown-linux-gnu
|
|
SNAPSHOT_BUILD_SYS = "${BUILD_ARCH}-unknown-linux-gnu"
|
|
setup_cargo_environment () {
|
|
# The first step is to build bootstrap and some early stage tools,
|
|
# these are build for the same target as the snapshot, e.g.
|
|
# x86_64-unknown-linux-gnu.
|
|
# Later stages are build for the native target (i.e. target.x86_64-linux)
|
|
cargo_common_do_configure
|
|
|
|
printf '[target.%s]\n' "${SNAPSHOT_BUILD_SYS}" >> ${CARGO_HOME}/config
|
|
printf "linker = '%s'\n" "${RUST_BUILD_CCLD}" >> ${CARGO_HOME}/config
|
|
}
|
|
|
|
# Right now this is focused on arm-specific tune features.
|
|
# We get away with this for now as one can only use x86-64 as the build host
|
|
# (not arm).
|
|
# Note that TUNE_FEATURES is _always_ refering to the target, so we really
|
|
# don't want to use this for the host/build.
|
|
def llvm_features_from_tune(d):
|
|
f = []
|
|
feat = d.getVar('TUNE_FEATURES')
|
|
if not feat:
|
|
return []
|
|
feat = frozenset(feat.split())
|
|
|
|
mach_overrides = d.getVar('MACHINEOVERRIDES')
|
|
mach_overrides = frozenset(mach_overrides.split(':'))
|
|
|
|
if 'vfpv4' in feat:
|
|
f.append("+vfp4")
|
|
if 'vfpv3' in feat:
|
|
f.append("+vfp3")
|
|
if 'vfpv3d16' in feat:
|
|
f.append("+d16")
|
|
|
|
if 'vfpv2' in feat or 'vfp' in feat:
|
|
f.append("+vfp2")
|
|
|
|
if 'neon' in feat:
|
|
f.append("+neon")
|
|
|
|
if 'aarch64' in feat:
|
|
f.append("+v8.1a")
|
|
|
|
if 'mips32' in feat:
|
|
f.append("+mips32")
|
|
|
|
if 'mips32r2' in feat:
|
|
f.append("+mips32r2")
|
|
|
|
if target_is_armv7(d):
|
|
f.append('+v7')
|
|
|
|
if ('armv6' in mach_overrides) or ('armv6' in feat):
|
|
f.append("+v6")
|
|
|
|
if 'dsp' in feat:
|
|
f.append("+dsp")
|
|
|
|
if 'thumb' in feat:
|
|
if d.getVar('ARM_THUMB_OPT') is "thumb":
|
|
if target_is_armv7(d):
|
|
f.append('+thumb2')
|
|
f.append("+thumb-mode")
|
|
|
|
if 'cortexa5' in feat:
|
|
f.append("+a5")
|
|
if 'cortexa7' in feat:
|
|
f.append("+a7")
|
|
if 'cortexa9' in feat:
|
|
f.append("+a9")
|
|
if 'cortexa15' in feat:
|
|
f.append("+a15")
|
|
if 'cortexa17' in feat:
|
|
f.append("+a17")
|
|
if ('riscv64' in feat) or ('riscv32' in feat):
|
|
f.append("+a,+c,+d,+f,+m")
|
|
return f
|
|
|
|
# TARGET_CC_ARCH changes from build/cross/target so it'll do the right thing
|
|
# this should go away when https://github.com/rust-lang/rust/pull/31709 is
|
|
# stable (1.9.0?)
|
|
def llvm_features_from_cc_arch(d):
|
|
f = []
|
|
feat = d.getVar('TARGET_CC_ARCH')
|
|
if not feat:
|
|
return []
|
|
feat = frozenset(feat.split())
|
|
|
|
if '-mmmx' in feat:
|
|
f.append("+mmx")
|
|
if '-msse' in feat:
|
|
f.append("+sse")
|
|
if '-msse2' in feat:
|
|
f.append("+sse2")
|
|
if '-msse3' in feat:
|
|
f.append("+sse3")
|
|
if '-mssse3' in feat:
|
|
f.append("+ssse3")
|
|
if '-msse4.1' in feat:
|
|
f.append("+sse4.1")
|
|
if '-msse4.2' in feat:
|
|
f.append("+sse4.2")
|
|
if '-msse4a' in feat:
|
|
f.append("+sse4a")
|
|
if '-mavx' in feat:
|
|
f.append("+avx")
|
|
if '-mavx2' in feat:
|
|
f.append("+avx2")
|
|
|
|
return f
|
|
|
|
def llvm_features_from_target_fpu(d):
|
|
# TARGET_FPU can be hard or soft. +soft-float tell llvm to use soft float
|
|
# ABI. There is no option for hard.
|
|
|
|
fpu = d.getVar('TARGET_FPU', True)
|
|
return ["+soft-float"] if fpu == "soft" else []
|
|
|
|
def llvm_features(d):
|
|
return ','.join(llvm_features_from_tune(d) +
|
|
llvm_features_from_cc_arch(d) +
|
|
llvm_features_from_target_fpu(d))
|
|
|
|
## arm-unknown-linux-gnueabihf
|
|
DATA_LAYOUT[arm] = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
|
|
LLVM_TARGET[arm] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[arm] = "little"
|
|
TARGET_POINTER_WIDTH[arm] = "32"
|
|
TARGET_C_INT_WIDTH[arm] = "32"
|
|
MAX_ATOMIC_WIDTH[arm] = "64"
|
|
FEATURES[arm] = "+v6,+vfp2"
|
|
|
|
## armv7-unknown-linux-gnueabihf
|
|
DATA_LAYOUT[armv7] = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
|
|
LLVM_TARGET[armv7] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[armv7] = "little"
|
|
TARGET_POINTER_WIDTH[armv7] = "32"
|
|
TARGET_C_INT_WIDTH[armv7] = "32"
|
|
MAX_ATOMIC_WIDTH[armv7] = "64"
|
|
FEATURES[armv7] = "+v7,+vfp2,+thumb2"
|
|
|
|
## aarch64-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[aarch64] = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
|
|
LLVM_TARGET[aarch64] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[aarch64] = "little"
|
|
TARGET_POINTER_WIDTH[aarch64] = "64"
|
|
TARGET_C_INT_WIDTH[aarch64] = "32"
|
|
MAX_ATOMIC_WIDTH[aarch64] = "128"
|
|
|
|
## x86_64-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[x86_64] = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
|
LLVM_TARGET[x86_64] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[x86_64] = "little"
|
|
TARGET_POINTER_WIDTH[x86_64] = "64"
|
|
TARGET_C_INT_WIDTH[x86_64] = "32"
|
|
MAX_ATOMIC_WIDTH[x86_64] = "64"
|
|
|
|
## i686-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[i686] = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
|
|
LLVM_TARGET[i686] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[i686] = "little"
|
|
TARGET_POINTER_WIDTH[i686] = "32"
|
|
TARGET_C_INT_WIDTH[i686] = "32"
|
|
MAX_ATOMIC_WIDTH[i686] = "64"
|
|
|
|
## XXX: a bit of a hack so qemux86 builds, clone of i686-unknown-linux-{gnu, musl} above
|
|
DATA_LAYOUT[i586] = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
|
|
LLVM_TARGET[i586] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[i586] = "little"
|
|
TARGET_POINTER_WIDTH[i586] = "32"
|
|
TARGET_C_INT_WIDTH[i586] = "32"
|
|
MAX_ATOMIC_WIDTH[i586] = "64"
|
|
|
|
## mips-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[mips] = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
|
|
LLVM_TARGET[mips] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[mips] = "big"
|
|
TARGET_POINTER_WIDTH[mips] = "32"
|
|
TARGET_C_INT_WIDTH[mips] = "32"
|
|
MAX_ATOMIC_WIDTH[mips] = "32"
|
|
|
|
## mipsel-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[mipsel] = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
|
|
LLVM_TARGET[mipsel] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[mipsel] = "little"
|
|
TARGET_POINTER_WIDTH[mipsel] = "32"
|
|
TARGET_C_INT_WIDTH[mipsel] = "32"
|
|
MAX_ATOMIC_WIDTH[mipsel] = "32"
|
|
|
|
## mips64-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[mips64] = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
|
|
LLVM_TARGET[mips64] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[mips64] = "big"
|
|
TARGET_POINTER_WIDTH[mips64] = "64"
|
|
TARGET_C_INT_WIDTH[mips64] = "64"
|
|
MAX_ATOMIC_WIDTH[mips64] = "64"
|
|
|
|
## mips64el-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[mips64el] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
|
|
LLVM_TARGET[mips64el] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[mips64el] = "little"
|
|
TARGET_POINTER_WIDTH[mips64el] = "64"
|
|
TARGET_C_INT_WIDTH[mips64el] = "64"
|
|
MAX_ATOMIC_WIDTH[mips64el] = "64"
|
|
|
|
## powerpc-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[powerpc] = "E-m:e-p:32:32-i64:64-n32"
|
|
LLVM_TARGET[powerpc] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[powerpc] = "big"
|
|
TARGET_POINTER_WIDTH[powerpc] = "32"
|
|
TARGET_C_INT_WIDTH[powerpc] = "32"
|
|
MAX_ATOMIC_WIDTH[powerpc] = "32"
|
|
|
|
## riscv32-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128"
|
|
LLVM_TARGET[riscv32] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[riscv32] = "little"
|
|
TARGET_POINTER_WIDTH[riscv32] = "32"
|
|
TARGET_C_INT_WIDTH[riscv32] = "32"
|
|
MAX_ATOMIC_WIDTH[riscv32] = "32"
|
|
|
|
## riscv64-unknown-linux-{gnu, musl}
|
|
DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
|
|
LLVM_TARGET[riscv64] = "${RUST_TARGET_SYS}"
|
|
TARGET_ENDIAN[riscv64] = "little"
|
|
TARGET_POINTER_WIDTH[riscv64] = "64"
|
|
TARGET_C_INT_WIDTH[riscv64] = "64"
|
|
MAX_ATOMIC_WIDTH[riscv64] = "64"
|
|
|
|
def arch_for(d, thing):
|
|
if thing == 'TARGET' and target_is_armv7(d):
|
|
return "armv7"
|
|
else:
|
|
return d.getVar('{}_ARCH'.format(thing))
|
|
|
|
def sys_for(d, thing):
|
|
return d.getVar('{}_SYS'.format(thing))
|
|
|
|
def prefix_for(d, thing):
|
|
return d.getVar('{}_PREFIX'.format(thing))
|
|
|
|
# Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something
|
|
# rust's internals won't choke on.
|
|
def arch_to_rust_target_arch(arch):
|
|
if arch == "i586" or arch == "i686":
|
|
return "x86"
|
|
elif arch == "mipsel":
|
|
return "mips"
|
|
elif arch == "mip64sel":
|
|
return "mips64"
|
|
elif arch == "armv7":
|
|
return "arm"
|
|
else:
|
|
return arch
|
|
|
|
# generates our target CPU value
|
|
def llvm_cpu(d):
|
|
cpu = d.getVar('PACKAGE_ARCH')
|
|
target = d.getVar('TRANSLATED_TARGET_ARCH')
|
|
|
|
trans = {}
|
|
trans['corei7-64'] = "corei7"
|
|
trans['core2-32'] = "core2"
|
|
trans['x86-64'] = "x86-64"
|
|
trans['i686'] = "i686"
|
|
trans['i586'] = "i586"
|
|
trans['powerpc'] = "powerpc"
|
|
trans['mips64'] = "mips64"
|
|
trans['mips64el'] = "mips64"
|
|
trans['riscv64'] = "generic-rv64"
|
|
trans['riscv32'] = "generic-rv32"
|
|
|
|
if target in ["mips", "mipsel"]:
|
|
feat = frozenset(d.getVar('TUNE_FEATURES').split())
|
|
if "mips32r2" in feat:
|
|
trans['mipsel'] = "mips32r2"
|
|
trans['mips'] = "mips32r2"
|
|
elif "mips32" in feat:
|
|
trans['mipsel'] = "mips32"
|
|
trans['mips'] = "mips32"
|
|
|
|
try:
|
|
return trans[cpu]
|
|
except:
|
|
return trans.get(target, "generic")
|
|
|
|
TARGET_LLVM_CPU="${@llvm_cpu(d)}"
|
|
TARGET_LLVM_FEATURES = "${@llvm_features(d)}"
|
|
|
|
# class-native implies TARGET=HOST, and TUNE_FEATURES only describes the real
|
|
# (original) target.
|
|
TARGET_LLVM_FEATURES_class-native = "${@','.join(llvm_features_from_cc_arch(d))}"
|
|
|
|
def rust_gen_target(d, thing, wd, features, cpu):
|
|
import json
|
|
from distutils.version import LooseVersion
|
|
arch = arch_for(d, thing)
|
|
sys = sys_for(d, thing)
|
|
prefix = prefix_for(d, thing)
|
|
|
|
features = features or d.getVarFlag('FEATURES', arch) or ""
|
|
features = features.strip()
|
|
|
|
# build tspec
|
|
tspec = {}
|
|
tspec['llvm-target'] = d.getVarFlag('LLVM_TARGET', arch)
|
|
tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch)
|
|
tspec['max-atomic-width'] = int(d.getVarFlag('MAX_ATOMIC_WIDTH', arch))
|
|
tspec['target-pointer-width'] = d.getVarFlag('TARGET_POINTER_WIDTH', arch)
|
|
tspec['target-c-int-width'] = d.getVarFlag('TARGET_C_INT_WIDTH', arch)
|
|
tspec['target-endian'] = d.getVarFlag('TARGET_ENDIAN', arch)
|
|
tspec['arch'] = arch_to_rust_target_arch(arch)
|
|
tspec['os'] = "linux"
|
|
if "musl" in tspec['llvm-target']:
|
|
tspec['env'] = "musl"
|
|
else:
|
|
tspec['env'] = "gnu"
|
|
if "riscv64" in tspec['llvm-target']:
|
|
tspec['llvm-abiname'] = "lp64d"
|
|
if "riscv32" in tspec['llvm-target']:
|
|
tspec['llvm-abiname'] = "ilp32d"
|
|
tspec['vendor'] = "unknown"
|
|
tspec['target-family'] = "unix"
|
|
tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix)
|
|
tspec['ar'] = "{}ar".format(prefix)
|
|
tspec['cpu'] = cpu
|
|
if features is not "":
|
|
tspec['features'] = features
|
|
tspec['dynamic-linking'] = True
|
|
tspec['executables'] = True
|
|
tspec['linker-is-gnu'] = True
|
|
tspec['linker-flavor'] = "gcc"
|
|
tspec['has-rpath'] = True
|
|
tspec['has-elf-tls'] = True
|
|
tspec['position-independent-executables'] = True
|
|
tspec['panic-strategy'] = d.getVar("RUST_PANIC_STRATEGY")
|
|
|
|
# Don't use jemalloc as it doesn't work for many targets.
|
|
# https://github.com/rust-lang/rust/pull/37392
|
|
# From 1.20.0 and forward, system allocator is the default.
|
|
if LooseVersion(d.getVar("PV")) < LooseVersion("1.20.0"):
|
|
tspec['exe-allocation-crate'] = "alloc_system"
|
|
tspec['lib-allocation-crate'] = "alloc_system"
|
|
|
|
# write out the target spec json file
|
|
with open(wd + sys + '.json', 'w') as f:
|
|
json.dump(tspec, f, indent=4)
|
|
|
|
python do_rust_gen_targets () {
|
|
wd = d.getVar('WORKDIR') + '/targets/'
|
|
rust_gen_target(d, 'BUILD', wd, "", "generic")
|
|
}
|
|
|
|
addtask rust_gen_targets after do_patch before do_compile
|
|
do_rust_gen_targets[dirs] += "${WORKDIR}/targets"
|
|
|
|
do_rust_setup_snapshot () {
|
|
for installer in "${WORKDIR}/rust-snapshot-components/"*"/install.sh"; do
|
|
"${installer}" --prefix="${WORKDIR}/rust-snapshot" --disable-ldconfig
|
|
done
|
|
|
|
# Some versions of rust (e.g. 1.18.0) tries to find cargo in stage0/bin/cargo
|
|
# and fail without it there.
|
|
mkdir -p ${RUSTSRC}/build/${BUILD_SYS}
|
|
ln -sf ${WORKDIR}/rust-snapshot/ ${RUSTSRC}/build/${BUILD_SYS}/stage0
|
|
}
|
|
addtask rust_setup_snapshot after do_unpack before do_configure
|
|
do_rust_setup_snapshot[dirs] += "${WORKDIR}/rust-snapshot"
|
|
|
|
|
|
python do_configure() {
|
|
import json
|
|
from distutils.version import LooseVersion
|
|
try:
|
|
import configparser
|
|
except ImportError:
|
|
import ConfigParser as configparser
|
|
|
|
# toml is rather similar to standard ini like format except it likes values
|
|
# that look more JSON like. So for our purposes simply escaping all values
|
|
# as JSON seem to work fine.
|
|
|
|
e = lambda s: json.dumps(s)
|
|
|
|
config = configparser.RawConfigParser()
|
|
|
|
# [target.ARCH-poky-linux]
|
|
target_section = "target.{}".format(d.getVar('TARGET_SYS', True))
|
|
config.add_section(target_section)
|
|
|
|
llvm_config = d.expand("${YOCTO_ALTERNATE_EXE_PATH}")
|
|
config.set(target_section, "llvm-config", e(llvm_config))
|
|
|
|
config.set(target_section, "cxx", e(d.expand("${RUST_TARGET_CXX}")))
|
|
config.set(target_section, "cc", e(d.expand("${RUST_TARGET_CC}")))
|
|
|
|
# If we don't do this rust-native will compile it's own llvm for BUILD.
|
|
# [target.${BUILD_ARCH}-unknown-linux-gnu]
|
|
target_section = "target.{}".format(d.getVar('SNAPSHOT_BUILD_SYS', True))
|
|
config.add_section(target_section)
|
|
|
|
config.set(target_section, "llvm-config", e(llvm_config))
|
|
|
|
config.set(target_section, "cxx", e(d.expand("${RUST_BUILD_CXX}")))
|
|
config.set(target_section, "cc", e(d.expand("${RUST_BUILD_CC}")))
|
|
|
|
# [rust]
|
|
config.add_section("rust")
|
|
config.set("rust", "rpath", e(True))
|
|
config.set("rust", "channel", e("stable"))
|
|
|
|
if LooseVersion(d.getVar("PV")) < LooseVersion("1.32.0"):
|
|
config.set("rust", "use-jemalloc", e(False))
|
|
|
|
# Whether or not to optimize the compiler and standard library
|
|
config.set("rust", "optimize", e(True))
|
|
|
|
# [build]
|
|
config.add_section("build")
|
|
config.set("build", "submodules", e(False))
|
|
config.set("build", "docs", e(False))
|
|
|
|
rustc = d.expand("${WORKDIR}/rust-snapshot/bin/rustc")
|
|
config.set("build", "rustc", e(rustc))
|
|
|
|
cargo = d.expand("${WORKDIR}/rust-snapshot/bin/cargo")
|
|
config.set("build", "cargo", e(cargo))
|
|
|
|
config.set("build", "vendor", e(True))
|
|
|
|
targets = [d.getVar("TARGET_SYS", True)]
|
|
config.set("build", "target", e(targets))
|
|
|
|
hosts = [d.getVar("HOST_SYS", True)]
|
|
config.set("build", "host", e(targets))
|
|
|
|
# We can't use BUILD_SYS since that is something the rust snapshot knows
|
|
# nothing about when trying to build some stage0 tools (like fabricate)
|
|
config.set("build", "build", e(d.getVar("SNAPSHOT_BUILD_SYS", True)))
|
|
|
|
# [install]
|
|
config.add_section("install")
|
|
# ./x.py install doesn't have any notion of "destdir"
|
|
# but we can prepend ${D} to all the directories instead
|
|
config.set("install", "prefix", e(d.getVar("D", True) + d.getVar("prefix", True)))
|
|
config.set("install", "bindir", e(d.getVar("D", True) + d.getVar("bindir", True)))
|
|
config.set("install", "libdir", e(d.getVar("D", True) + d.getVar("libdir", True)))
|
|
config.set("install", "datadir", e(d.getVar("D", True) + d.getVar("datadir", True)))
|
|
config.set("install", "mandir", e(d.getVar("D", True) + d.getVar("mandir", True)))
|
|
|
|
with open("config.toml", "w") as f:
|
|
f.write('changelog-seen = 2\n\n')
|
|
config.write(f)
|
|
|
|
# set up ${WORKDIR}/cargo_home
|
|
bb.build.exec_func("setup_cargo_environment", d)
|
|
}
|
|
|
|
|
|
rust_runx () {
|
|
echo "COMPILE ${PN}" "$@"
|
|
|
|
# CFLAGS, LDFLAGS, CXXFLAGS, CPPFLAGS are used by rust's build for a
|
|
# wide range of targets (not just TARGET). Yocto's settings for them will
|
|
# be inappropriate, avoid using.
|
|
unset CFLAGS
|
|
unset LDFLAGS
|
|
unset CXXFLAGS
|
|
unset CPPFLAGS
|
|
|
|
oe_cargo_fix_env
|
|
|
|
python3 src/bootstrap/bootstrap.py ${@oe.utils.parallel_make_argument(d, '-j %d')} "$@" --verbose
|
|
}
|
|
rust_runx[vardepsexclude] += "PARALLEL_MAKE"
|
|
|
|
do_compile () {
|
|
rust_runx build
|
|
}
|
|
|
|
rust_do_install () {
|
|
mkdir -p ${D}${bindir}
|
|
cp build/${HOST_SYS}/stage2/bin/* ${D}${bindir}
|
|
|
|
mkdir -p ${D}${libdir}/rustlib
|
|
cp -pRd build/${HOST_SYS}/stage2/lib/* ${D}${libdir}
|
|
# Remove absolute symlink so bitbake doesn't complain
|
|
rm -f ${D}${libdir}/rustlib/src/rust
|
|
}
|
|
|
|
rust_install_targets() {
|
|
# Install our custom target.json files
|
|
local td="${D}${libdir}/rustlib/"
|
|
install -d "$td"
|
|
for tgt in "${WORKDIR}/targets/"* ; do
|
|
install -m 0644 "$tgt" "$td"
|
|
done
|
|
}
|
|
|
|
|
|
do_install () {
|
|
rust_do_install
|
|
rust_install_targets
|
|
}
|
|
# ex: sts=4 et sw=4 ts=8
|