From 8a249fc1c57ab01a78996e33e74a71757a9448b1 Mon Sep 17 00:00:00 2001
From: Syed Mohammed Khasim <khasim@ti.com>
Date: Tue, 12 Jan 2010 23:57:28 +0530
Subject: [PATCH 07/16] OMAP3: Add DSS driver for OMAP3

Supports dynamic panel configuration
Supports dynamic tv standard selection
Adds support for DSS register access through generic APIs

Incorporated DSS register access using structures.

Previous discussions are here
http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html
---
v2 updates:
  * Enable panel output for BeagleBoard
  * BeagleBoard: Update DVI-D orange screen frequencies for xM

Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
---
 arch/arm/include/asm/arch-omap3/dss.h |  173 +++++++++++++++++++++++++++++++++
 board/ti/beagle/beagle.c              |   22 ++++
 board/ti/beagle/beagle.h              |   26 +++++
 drivers/video/Makefile                |    2 +
 drivers/video/omap3_dss.c             |  130 +++++++++++++++++++++++++
 5 files changed, 353 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-omap3/dss.h
 create mode 100644 drivers/video/omap3_dss.c

diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
new file mode 100644
index 0000000..e5e3b0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Referred to Linux DSS driver files for OMAP3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef DSS_H
+#define DSS_H
+
+/*
+ * DSS Base Registers
+ */
+#define OMAP3_DSS_BASE		0x48050040
+#define OMAP3_DISPC_BASE	0x48050440
+#define OMAP3_VENC_BASE		0x48050C00
+
+/* DSS Registers */
+struct dss_regs {
+	u32 control;				/* 0x40 */
+	u32 sdi_control;			/* 0x44 */
+	u32 pll_control;			/* 0x48 */
+};
+
+/* DISPC Registers */
+struct dispc_regs {
+	u32 control;				/* 0x40 */
+	u32 config;				/* 0x44 */
+	u32 reserve_2;				/* 0x48 */
+	u32 default_color0;			/* 0x4C */
+	u32 default_color1;			/* 0x50 */
+	u32 trans_color0;			/* 0x54 */
+	u32 trans_color1;			/* 0x58 */
+	u32 line_status;			/* 0x5C */
+	u32 line_number;			/* 0x60 */
+	u32 timing_h;				/* 0x64 */
+	u32 timing_v;				/* 0x68 */
+	u32 pol_freq;				/* 0x6C */
+	u32 divisor;				/* 0x70 */
+	u32 global_alpha;			/* 0x74 */
+	u32 size_dig;				/* 0x78 */
+	u32 size_lcd;				/* 0x7C */
+};
+
+/* VENC Registers */
+struct venc_regs {
+	u32 rev_id;				/* 0x00 */
+	u32 status;				/* 0x04 */
+	u32 f_control;				/* 0x08 */
+	u32 reserve_1;				/* 0x0C */
+	u32 vidout_ctrl;			/* 0x10 */
+	u32 sync_ctrl;				/* 0x14 */
+	u32 reserve_2;				/* 0x18 */
+	u32 llen;				/* 0x1C */
+	u32 flens;				/* 0x20 */
+	u32 hfltr_ctrl;				/* 0x24 */
+	u32 cc_carr_wss_carr;			/* 0x28 */
+	u32 c_phase;				/* 0x2C */
+	u32 gain_u;				/* 0x30 */
+	u32 gain_v;				/* 0x34 */
+	u32 gain_y;				/* 0x38 */
+	u32 black_level;			/* 0x3C */
+	u32 blank_level;			/* 0x40 */
+	u32 x_color;				/* 0x44 */
+	u32 m_control;				/* 0x48 */
+	u32 bstamp_wss_data;			/* 0x4C */
+	u32 s_carr;				/* 0x50 */
+	u32 line21;				/* 0x54 */
+	u32 ln_sel;				/* 0x58 */
+	u32 l21__wc_ctl;			/* 0x5C */
+	u32 htrigger_vtrigger;			/* 0x60 */
+	u32 savid__eavid;			/* 0x64 */
+	u32 flen__fal;				/* 0x68 */
+	u32 lal__phase_reset;			/* 0x6C */
+	u32 hs_int_start_stop_x;		/* 0x70 */
+	u32 hs_ext_start_stop_x;		/* 0x74 */
+	u32 vs_int_start_x;			/* 0x78 */
+	u32 vs_int_stop_x__vs_int_start_y;	/* 0x7C */
+	u32 vs_int_stop_y__vs_ext_start_x;	/* 0x80 */
+	u32 vs_ext_stop_x__vs_ext_start_y;	/* 0x84 */
+	u32 vs_ext_stop_y;			/* 0x88 */
+	u32 reserve_3;				/* 0x8C */
+	u32 avid_start_stop_x;			/* 0x90 */
+	u32 avid_start_stop_y;			/* 0x94 */
+	u32 reserve_4;				/* 0x98 */
+	u32 reserve_5;				/* 0x9C */
+	u32 fid_int_start_x__fid_int_start_y;	/* 0xA0 */
+	u32 fid_int_offset_y__fid_ext_start_x;	/* 0xA4 */
+	u32 fid_ext_start_y__fid_ext_offset_y;	/* 0xA8 */
+	u32 reserve_6;				/* 0xAC */
+	u32 tvdetgp_int_start_stop_x;		/* 0xB0 */
+	u32 tvdetgp_int_start_stop_y;		/* 0xB4 */
+	u32 gen_ctrl;				/* 0xB8 */
+	u32 reserve_7;				/* 0xBC */
+	u32 reserve_8;				/* 0xC0 */
+	u32 output_control;			/* 0xC4 */
+	u32 dac_b__dac_c;			/* 0xC8 */
+	u32 height_width;			/* 0xCC */
+};
+
+/* Few Register Offsets */
+#define FRAME_MODE_SHIFT			1
+#define TFTSTN_SHIFT				3
+#define DATALINES_SHIFT				8
+
+/* Enabling Display controller */
+#define LCD_ENABLE				1
+#define DIG_ENABLE				(1 << 1)
+#define GO_LCD					(1 << 5)
+#define GO_DIG					(1 << 6)
+#define GP_OUT0					(1 << 15)
+#define GP_OUT1					(1 << 16)
+
+#define DISPC_ENABLE				(LCD_ENABLE | \
+						 DIG_ENABLE | \
+						 GO_LCD | \
+						 GO_DIG | \
+						 GP_OUT0| \
+						 GP_OUT1)
+
+/* Configure VENC DSS Params */
+#define VENC_CLK_ENABLE				(1 << 3)
+#define DAC_DEMEN				(1 << 4)
+#define DAC_POWERDN				(1 << 5)
+#define VENC_OUT_SEL				(1 << 6)
+#define DIG_LPP_SHIFT				16
+#define VENC_DSS_CONFIG				(VENC_CLK_ENABLE | \
+						 DAC_DEMEN | \
+						 DAC_POWERDN | \
+						 VENC_OUT_SEL)
+/*
+ * Panel Configuration
+ */
+struct panel_config {
+	u32 timing_h;
+	u32 timing_v;
+	u32 pol_freq;
+	u32 divisor;
+	u32 lcd_size;
+	u32 panel_type;
+	u32 data_lines;
+	u32 load_mode;
+	u32 panel_color;
+};
+
+/*
+ * Generic DSS Functions
+ */
+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
+			u32 height, u32 width);
+void omap3_dss_panel_config(const struct panel_config *panel_cfg);
+void omap3_dss_enable(void);
+
+#endif /* DSS_H */
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 97e9e12..56e7afc 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -146,6 +146,27 @@ unsigned int get_expansion_id(void)
 }
 
 /*
+ * Configure DSS to display background color on DVID
+ * Configure VENC to display color bar on S-Video
+ */
+void display_init(void)
+{
+	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
+	switch (get_board_revision()) {
+	case REVISION_AXBX:
+	case REVISION_CX:
+	case REVISION_C4:
+		omap3_dss_panel_config(&dvid_cfg);
+		break;
+	case REVISION_XM_A:
+	case REVISION_XM_B:
+	default:
+		omap3_dss_panel_config(&dvid_cfg_xm);
+		break;
+	}
+}
+
+/*
  * Routine: misc_init_r
  * Description: Configure board specific parts
  */
@@ -282,6 +303,7 @@ int misc_init_r(void)
 
 	twl4030_power_init();
 	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+	display_init();
 
 	/* Set GPIO states before they are made outputs */
 	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index 0f21790..48228dc 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -470,4 +470,30 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MMC2_DAT6),      (IDIS | PTU | EN  | M4)) /*GPIO_138 BT_EN*/\
 	MUX_VAL(CP(MMC2_DAT7),      (IDIS | PTU | EN  | M4)) /*GPIO_139 WLAN_EN*/
 
+/*
+ * Configure Timings for DVI D
+ */
+static const struct panel_config dvid_cfg = {
+	.timing_h	= 0x0ff03f31, /* Horizantal timing */
+	.timing_v	= 0x01400504, /* Vertical timing */
+	.pol_freq	= 0x00007028, /* Pol Freq */
+	.divisor	= 0x00010006, /* 72Mhz Pixel Clock */
+	.lcd_size	= 0x02ff03ff, /* 1024x768 */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BEAGLE_ORANGE_COL /* ORANGE */
+};
+
+static const struct panel_config dvid_cfg_xm = {
+	.timing_h	= 0x1a4024c9, /* Horizantal timing */
+	.timing_v	= 0x02c00509, /* Vertical timing */
+	.pol_freq	= 0x00007028, /* Pol Freq */
+	.divisor	= 0x00010001, /* 96MHz Pixel Clock */
+	.lcd_size	= 0x02ff03ff, /* 1024x768 */
+	.panel_type	= 0x01, /* TFT */
+	.data_lines	= 0x03, /* 24 Bit RGB */
+	.load_mode	= 0x02, /* Frame Mode */
+	.panel_color	= DVI_BEAGLE_ORANGE_COL /* ORANGE */
+};
 #endif
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 2c53a6f..6baa7ca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -41,6 +41,8 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
 COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
+COBJS-y += videomodes.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
new file mode 100644
index 0000000..69c705a
--- /dev/null
+++ b/drivers/video/omap3_dss.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Referred to Linux DSS driver files for OMAP3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dss.h>
+
+/*
+ * Configure VENC for a given Mode (NTSC / PAL)
+ */
+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
+				u32 height, u32 width)
+{
+	struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
+	struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+
+	writel(venc_cfg->status, &venc->status);
+	writel(venc_cfg->f_control, &venc->f_control);
+	writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
+	writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
+	writel(venc_cfg->llen, &venc->llen);
+	writel(venc_cfg->flens, &venc->flens);
+	writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
+	writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
+	writel(venc_cfg->c_phase, &venc->c_phase);
+	writel(venc_cfg->gain_u, &venc->gain_u);
+	writel(venc_cfg->gain_v, &venc->gain_v);
+	writel(venc_cfg->gain_y, &venc->gain_y);
+	writel(venc_cfg->black_level, &venc->black_level);
+	writel(venc_cfg->blank_level, &venc->blank_level);
+	writel(venc_cfg->x_color, &venc->x_color);
+	writel(venc_cfg->m_control, &venc->m_control);
+	writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
+	writel(venc_cfg->s_carr, &venc->s_carr);
+	writel(venc_cfg->line21, &venc->line21);
+	writel(venc_cfg->ln_sel, &venc->ln_sel);
+	writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
+	writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
+	writel(venc_cfg->savid__eavid, &venc->savid__eavid);
+	writel(venc_cfg->flen__fal, &venc->flen__fal);
+	writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
+	writel(venc_cfg->hs_int_start_stop_x,
+				&venc->hs_int_start_stop_x);
+	writel(venc_cfg->hs_ext_start_stop_x,
+				&venc->hs_ext_start_stop_x);
+	writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
+	writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
+			&venc->vs_int_stop_x__vs_int_start_y);
+	writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
+			&venc->vs_int_stop_y__vs_ext_start_x);
+	writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
+			&venc->vs_ext_stop_x__vs_ext_start_y);
+	writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
+	writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
+	writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
+	writel(venc_cfg->fid_int_start_x__fid_int_start_y,
+				&venc->fid_int_start_x__fid_int_start_y);
+	writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
+				&venc->fid_int_offset_y__fid_ext_start_x);
+	writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
+				&venc->fid_ext_start_y__fid_ext_offset_y);
+	writel(venc_cfg->tvdetgp_int_start_stop_x,
+				&venc->tvdetgp_int_start_stop_x);
+	writel(venc_cfg->tvdetgp_int_start_stop_y,
+				&venc->tvdetgp_int_start_stop_y);
+	writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
+	writel(venc_cfg->output_control, &venc->output_control);
+	writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
+
+	/* Configure DSS for VENC Settings */
+	writel(VENC_DSS_CONFIG, &dss->control);
+
+	/* Configure height and width for Digital out */
+	writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
+}
+
+/*
+ * Configure Panel Specific Parameters
+ */
+void omap3_dss_panel_config(const struct panel_config *panel_cfg)
+{
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+
+	writel(panel_cfg->timing_h, &dispc->timing_h);
+	writel(panel_cfg->timing_v, &dispc->timing_v);
+	writel(panel_cfg->pol_freq, &dispc->pol_freq);
+	writel(panel_cfg->divisor, &dispc->divisor);
+	writel(panel_cfg->lcd_size, &dispc->size_lcd);
+	writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
+	writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
+		(panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
+	writel(panel_cfg->panel_color, &dispc->default_color0);
+}
+
+/*
+ * Enable LCD and DIGITAL OUT in DSS
+ */
+void omap3_dss_enable(void)
+{
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+	u32 l = 0;
+
+	l = readl(&dispc->control);
+	l |= DISPC_ENABLE;
+	writel(l, &dispc->control);
+}
-- 
1.6.6.1

