diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-Added-Crane-Board-support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-Added-Crane-Board-support.patch deleted file mode 100644 index 25a7d610..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-Added-Crane-Board-support.patch +++ /dev/null @@ -1,5237 +0,0 @@ -From 65b68a814742181e9a709949b8e3f06fb08e749b Mon Sep 17 00:00:00 2001 -From: Srinath -Date: Thu, 5 Aug 2010 12:03:25 +0530 -Subject: [PATCH] Added Crane Board support - ---- - arch/arm/configs/am3517_crane_defconfig | 1768 ++++++++++++++++++++++++++ - arch/arm/mach-omap2/Kconfig | 6 + - arch/arm/mach-omap2/Makefile | 2 + - arch/arm/mach-omap2/board-am3517crane.c | 773 +++++++++++ - arch/arm/mach-omap2/mmc-am3517crane.c | 267 ++++ - arch/arm/mach-omap2/mmc-am3517crane.h | 22 + - arch/arm/mach-omap2/tps65910-pmic.c | 195 +++ - arch/arm/tools/mach-types | 1 + - drivers/gpio/Makefile | 1 + - drivers/i2c/busses/i2c-omap.c | 3 +- - drivers/mfd/Kconfig | 13 + - drivers/mfd/Makefile | 4 +- - drivers/mfd/tps65910-core.c | 741 +++++++++++ - drivers/rtc/Kconfig | 8 + - drivers/rtc/Makefile | 1 + - drivers/rtc/rtc-tps65910.c | 657 ++++++++++ - drivers/usb/host/ehci-hub.c | 9 +- - drivers/usb/musb/Kconfig | 6 +- - drivers/usb/musb/Makefile | 3 +- - drivers/usb/musb/musb_core.c | 2 +- - drivers/usb/musb/musb_core.h | 2 +- - drivers/usb/musb/musb_gadget.c | 2 +- - drivers/usb/musb/musb_gadget_ep0.c | 2 +- - drivers/usb/musb/musb_io.h | 5 +- - drivers/usb/musb/musb_virthub.c | 8 +- - drivers/video/omap2/displays/panel-generic.c | 9 + - drivers/video/omap2/dss/venc.c | 15 +- - include/linux/i2c/tps65910.h | 278 ++++ - 28 files changed, 4779 insertions(+), 24 deletions(-) - create mode 100644 arch/arm/configs/am3517_crane_defconfig - create mode 100644 arch/arm/mach-omap2/board-am3517crane.c - create mode 100644 arch/arm/mach-omap2/mmc-am3517crane.c - create mode 100644 arch/arm/mach-omap2/mmc-am3517crane.h - create mode 100644 arch/arm/mach-omap2/tps65910-pmic.c - create mode 100644 drivers/mfd/tps65910-core.c - create mode 100644 drivers/rtc/rtc-tps65910.c - create mode 100644 include/linux/i2c/tps65910.h - -diff --git a/arch/arm/configs/am3517_crane_defconfig b/arch/arm/configs/am3517_crane_defconfig -new file mode 100644 -index 0000000..24ffc83 ---- /dev/null -+++ b/arch/arm/configs/am3517_crane_defconfig -@@ -0,0 +1,1768 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.32 -+# Fri Nov 26 17:48:55 2010 -+# -+CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y -+CONFIG_GENERIC_TIME=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_HAVE_LATENCYTOP_SUPPORT=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+CONFIG_ARCH_HAS_CPUFREQ=y -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+CONFIG_CONSTRUCTORS=y -+ -+# -+# General setup -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_LOCALVERSION="" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+CONFIG_BSD_PROCESS_ACCT=y -+# CONFIG_BSD_PROCESS_ACCT_V3 is not set -+# CONFIG_TASKSTATS is not set -+# CONFIG_AUDIT is not set -+ -+# -+# RCU Subsystem -+# -+CONFIG_TREE_RCU=y -+# CONFIG_TREE_PREEMPT_RCU is not set -+# CONFIG_TINY_RCU is not set -+# CONFIG_RCU_TRACE is not set -+CONFIG_RCU_FANOUT=32 -+# CONFIG_RCU_FANOUT_EXACT is not set -+# CONFIG_TREE_RCU_TRACE is not set -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_LOG_BUF_SHIFT=14 -+CONFIG_GROUP_SCHED=y -+CONFIG_FAIR_GROUP_SCHED=y -+# CONFIG_RT_GROUP_SCHED is not set -+CONFIG_USER_SCHED=y -+# CONFIG_CGROUP_SCHED is not set -+# CONFIG_CGROUPS is not set -+CONFIG_SYSFS_DEPRECATED=y -+CONFIG_SYSFS_DEPRECATED_V2=y -+# CONFIG_RELAY is not set -+# CONFIG_NAMESPACES is not set -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_RD_GZIP=y -+# CONFIG_RD_BZIP2 is not set -+# CONFIG_RD_LZMA is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_ANON_INODES=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+# CONFIG_SYSCTL_SYSCALL is not set -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+CONFIG_KALLSYMS_EXTRA_PASS=y -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_AIO=y -+ -+# -+# Kernel Performance Events And Counters -+# -+CONFIG_VM_EVENT_COUNTERS=y -+CONFIG_COMPAT_BRK=y -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+# CONFIG_PROFILING is not set -+CONFIG_HAVE_OPROFILE=y -+# CONFIG_KPROBES is not set -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+CONFIG_HAVE_CLK=y -+ -+# -+# GCOV-based kernel profiling -+# -+# CONFIG_SLOW_WORK is not set -+CONFIG_HAVE_GENERIC_DMA_COHERENT=y -+CONFIG_SLABINFO=y -+CONFIG_RT_MUTEXES=y -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+# CONFIG_MODULE_FORCE_LOAD is not set -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_BLOCK=y -+CONFIG_LBDAF=y -+# CONFIG_BLK_DEV_BSG is not set -+# CONFIG_BLK_DEV_INTEGRITY is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+# CONFIG_INLINE_SPIN_TRYLOCK is not set -+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -+# CONFIG_INLINE_SPIN_LOCK is not set -+# CONFIG_INLINE_SPIN_LOCK_BH is not set -+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -+CONFIG_INLINE_SPIN_UNLOCK=y -+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -+# CONFIG_INLINE_READ_TRYLOCK is not set -+# CONFIG_INLINE_READ_LOCK is not set -+# CONFIG_INLINE_READ_LOCK_BH is not set -+# CONFIG_INLINE_READ_LOCK_IRQ is not set -+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -+CONFIG_INLINE_READ_UNLOCK=y -+# CONFIG_INLINE_READ_UNLOCK_BH is not set -+CONFIG_INLINE_READ_UNLOCK_IRQ=y -+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -+# CONFIG_INLINE_WRITE_TRYLOCK is not set -+# CONFIG_INLINE_WRITE_LOCK is not set -+# CONFIG_INLINE_WRITE_LOCK_BH is not set -+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -+CONFIG_INLINE_WRITE_UNLOCK=y -+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -+# CONFIG_MUTEX_SPIN_ON_OWNER is not set -+CONFIG_FREEZER=y -+ -+# -+# System Type -+# -+CONFIG_MMU=y -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_GEMINI is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_STMP3XXX is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_NOMADIK is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IXP23XX is not set -+# CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_DOVE is not set -+# CONFIG_ARCH_KIRKWOOD is not set -+# CONFIG_ARCH_LOKI is not set -+# CONFIG_ARCH_MV78XX0 is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_MMP is not set -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_NS9XXX is not set -+# CONFIG_ARCH_W90X900 is not set -+# CONFIG_ARCH_PNX4008 is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_MSM is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_S3C64XX is not set -+# CONFIG_ARCH_S5PC1XX is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_U300 is not set -+# CONFIG_ARCH_DAVINCI is not set -+CONFIG_ARCH_OMAP=y -+# CONFIG_ARCH_BCMRING is not set -+# CONFIG_ARCH_U8500 is not set -+ -+# -+# TI OMAP Implementations -+# -+CONFIG_ARCH_OMAP_OTG=y -+# CONFIG_ARCH_OMAP1 is not set -+# CONFIG_ARCH_OMAP2 is not set -+CONFIG_ARCH_OMAP3=y -+# CONFIG_ARCH_OMAP4 is not set -+ -+# -+# OMAP Feature Selections -+# -+CONFIG_OMAP_RESET_CLOCKS=y -+CONFIG_OMAP_MUX=y -+# CONFIG_OMAP_MUX_DEBUG is not set -+CONFIG_OMAP_MUX_WARNINGS=y -+CONFIG_OMAP_MCBSP=y -+# CONFIG_OMAP_MBOX_FWK is not set -+# CONFIG_OMAP_MPU_TIMER is not set -+CONFIG_OMAP_32K_TIMER=y -+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -+CONFIG_OMAP_32K_TIMER_HZ=128 -+CONFIG_OMAP_DM_TIMER=y -+# CONFIG_OMAP_LL_DEBUG_UART1 is not set -+# CONFIG_OMAP_LL_DEBUG_UART2 is not set -+CONFIG_OMAP_LL_DEBUG_UART3=y -+# CONFIG_OMAP_LL_DEBUG_NONE is not set -+# CONFIG_OMAP_PM_NONE is not set -+CONFIG_OMAP_PM_NOOP=y -+# CONFIG_OMAP_PM_SRF is not set -+CONFIG_ARCH_OMAP34XX=y -+CONFIG_ARCH_OMAP3430=y -+CONFIG_OMAP_PACKAGE_CBB=y -+ -+# -+# OMAP Board Type -+# -+# CONFIG_MACH_OMAP3_BEAGLE is not set -+# CONFIG_MACH_OMAP_LDP is not set -+# CONFIG_MACH_OVERO is not set -+# CONFIG_MACH_OMAP3EVM is not set -+# CONFIG_MACH_OMAP3517EVM is not set -+CONFIG_MACH_CRANEBOARD=y -+# CONFIG_MACH_OMAP3_PANDORA is not set -+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -+# CONFIG_MACH_OMAP_3430SDP is not set -+# CONFIG_MACH_NOKIA_RX51 is not set -+# CONFIG_MACH_OMAP_ZOOM2 is not set -+# CONFIG_MACH_OMAP_ZOOM3 is not set -+# CONFIG_MACH_CM_T35 is not set -+# CONFIG_MACH_IGEP0020 is not set -+# CONFIG_MACH_OMAP_3630SDP is not set -+# CONFIG_OMAP3_EMU is not set -+# CONFIG_OMAP3_SDRC_AC_TIMING is not set -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_32v6K=y -+CONFIG_CPU_V7=y -+CONFIG_CPU_32v7=y -+CONFIG_CPU_ABRT_EV7=y -+CONFIG_CPU_PABRT_V7=y -+CONFIG_CPU_CACHE_V7=y -+CONFIG_CPU_CACHE_VIPT=y -+CONFIG_CPU_COPY_V6=y -+CONFIG_CPU_TLB_V7=y -+CONFIG_CPU_HAS_ASID=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+CONFIG_ARM_THUMB=y -+# CONFIG_ARM_THUMBEE is not set -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_DISABLE is not set -+# CONFIG_CPU_BPREDICT_DISABLE is not set -+CONFIG_HAS_TLS_REG=y -+CONFIG_ARM_L1_CACHE_SHIFT=6 -+CONFIG_ARM_ERRATA_430973=y -+CONFIG_ARM_ERRATA_458693=y -+CONFIG_ARM_ERRATA_460075=y -+CONFIG_COMMON_CLKDEV=y -+ -+# -+# Bus support -+# -+# CONFIG_PCI_SYSCALL is not set -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -+CONFIG_VMSPLIT_3G=y -+# CONFIG_VMSPLIT_2G is not set -+# CONFIG_VMSPLIT_1G is not set -+CONFIG_PAGE_OFFSET=0xC0000000 -+CONFIG_PREEMPT_NONE=y -+# CONFIG_PREEMPT_VOLUNTARY is not set -+# CONFIG_PREEMPT is not set -+CONFIG_HZ=128 -+# CONFIG_THUMB2_KERNEL is not set -+CONFIG_AEABI=y -+CONFIG_OABI_COMPAT=y -+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -+# CONFIG_HIGHMEM is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+CONFIG_PAGEFLAGS_EXTENDED=y -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+# CONFIG_PHYS_ADDR_T_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=0 -+CONFIG_VIRT_TO_BUS=y -+# CONFIG_KSM is not set -+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -+# CONFIG_LEDS is not set -+CONFIG_ALIGNMENT_TRAP=y -+# CONFIG_UACCESS_WITH_MEMCPY is not set -+ -+# -+# Boot options -+# -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -+# CONFIG_XIP_KERNEL is not set -+# CONFIG_KEXEC is not set -+ -+# -+# CPU Power Management -+# -+# CONFIG_CPU_FREQ is not set -+# CONFIG_CPU_IDLE is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+CONFIG_FPE_NWFPE=y -+# CONFIG_FPE_NWFPE_XP is not set -+# CONFIG_FPE_FASTFPE is not set -+CONFIG_VFP=y -+CONFIG_VFPv3=y -+CONFIG_NEON=y -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_HAVE_AOUT=y -+# CONFIG_BINFMT_AOUT is not set -+CONFIG_BINFMT_MISC=y -+ -+# -+# Power management options -+# -+CONFIG_PM=y -+CONFIG_PM_DEBUG=y -+# CONFIG_PM_VERBOSE is not set -+CONFIG_CAN_PM_TRACE=y -+CONFIG_PM_SLEEP=y -+CONFIG_SUSPEND=y -+# CONFIG_PM_TEST_SUSPEND is not set -+CONFIG_SUSPEND_FREEZER=y -+# CONFIG_APM_EMULATION is not set -+# CONFIG_PM_RUNTIME is not set -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+# CONFIG_PACKET_MMAP is not set -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+# CONFIG_XFRM_STATISTICS is not set -+CONFIG_NET_KEY=y -+# CONFIG_NET_KEY_MIGRATE is not set -+CONFIG_INET=y -+# CONFIG_IP_MULTICAST is not set -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IP_PNP_RARP=y -+# CONFIG_NET_IPIP is not set -+# CONFIG_NET_IPGRE is not set -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+# CONFIG_INET_AH is not set -+# CONFIG_INET_ESP is not set -+# CONFIG_INET_IPCOMP is not set -+# CONFIG_INET_XFRM_TUNNEL is not set -+# CONFIG_INET_TUNNEL is not set -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+# CONFIG_INET_LRO is not set -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+# CONFIG_IPV6 is not set -+# CONFIG_NETWORK_SECMARK is not set -+# CONFIG_NETFILTER is not set -+# CONFIG_IP_DCCP is not set -+# CONFIG_IP_SCTP is not set -+# CONFIG_RDS is not set -+# CONFIG_TIPC is not set -+# CONFIG_ATM is not set -+# CONFIG_BRIDGE is not set -+# CONFIG_NET_DSA is not set -+# CONFIG_VLAN_8021Q is not set -+# CONFIG_DECNET is not set -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+# CONFIG_WAN_ROUTER is not set -+# CONFIG_PHONET is not set -+# CONFIG_IEEE802154 is not set -+# CONFIG_NET_SCHED is not set -+# CONFIG_DCB is not set -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_HAMRADIO is not set -+CONFIG_CAN=y -+CONFIG_CAN_RAW=y -+CONFIG_CAN_BCM=y -+ -+# -+# CAN Device Drivers -+# -+CONFIG_CAN_VCAN=y -+CONFIG_CAN_DEV=y -+CONFIG_CAN_CALC_BITTIMING=y -+CONFIG_CAN_TI_HECC=y -+# CONFIG_CAN_SJA1000 is not set -+ -+# -+# CAN USB interfaces -+# -+# CONFIG_CAN_EMS_USB is not set -+CONFIG_CAN_DEBUG_DEVICES=y -+# CONFIG_IRDA is not set -+# CONFIG_BT is not set -+# CONFIG_AF_RXRPC is not set -+CONFIG_WIRELESS=y -+# CONFIG_CFG80211 is not set -+# CONFIG_LIB80211 is not set -+ -+# -+# CFG80211 needs to be enabled for MAC80211 -+# -+# CONFIG_WIMAX is not set -+# CONFIG_RFKILL is not set -+# CONFIG_NET_9P is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+# CONFIG_DEVTMPFS is not set -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+# CONFIG_FW_LOADER is not set -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+# CONFIG_MTD_TESTS is not set -+CONFIG_MTD_CONCAT=y -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_MTD_OOPS is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+# CONFIG_MTD_CFI is not set -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+# CONFIG_MTD_NAND_VERIFY_WRITE is not set -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+# CONFIG_MTD_NAND_GPIO is not set -+CONFIG_MTD_NAND_OMAP2=y -+# CONFIG_MTD_NAND_OMAP_PREFETCH is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+# CONFIG_MTD_NAND_PLATFORM is not set -+# CONFIG_MTD_ALAUDA is not set -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# LPDDR flash memory drivers -+# -+# CONFIG_MTD_LPDDR is not set -+ -+# -+# UBI - Unsorted block images -+# -+# CONFIG_MTD_UBI is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=y -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+ -+# -+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -+# -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_UB is not set -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=32768 -+# CONFIG_BLK_DEV_XIP is not set -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+# CONFIG_MG_DISK is not set -+# CONFIG_MISC_DEVICES is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+CONFIG_SCSI_PROC_FS=y -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+# CONFIG_BLK_DEV_SR is not set -+# CONFIG_CHR_DEV_SG is not set -+# CONFIG_CHR_DEV_SCH is not set -+# CONFIG_SCSI_MULTI_LUN is not set -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+# CONFIG_SCSI_ISCSI_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+CONFIG_SCSI_LOWLEVEL=y -+# CONFIG_ISCSI_TCP is not set -+# CONFIG_LIBFC is not set -+# CONFIG_LIBFCOE is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_DH is not set -+# CONFIG_SCSI_OSD_INITIATOR is not set -+# CONFIG_ATA is not set -+# CONFIG_MD is not set -+CONFIG_NETDEVICES=y -+# CONFIG_DUMMY is not set -+# CONFIG_BONDING is not set -+# CONFIG_MACVLAN is not set -+# CONFIG_EQUALIZER is not set -+# CONFIG_TUN is not set -+# CONFIG_VETH is not set -+CONFIG_PHYLIB=y -+ -+# -+# MII PHY device drivers -+# -+# CONFIG_MARVELL_PHY is not set -+# CONFIG_DAVICOM_PHY is not set -+# CONFIG_QSEMI_PHY is not set -+# CONFIG_LXT_PHY is not set -+# CONFIG_CICADA_PHY is not set -+# CONFIG_VITESSE_PHY is not set -+# CONFIG_SMSC_PHY is not set -+# CONFIG_BROADCOM_PHY is not set -+# CONFIG_ICPLUS_PHY is not set -+# CONFIG_REALTEK_PHY is not set -+# CONFIG_NATIONAL_PHY is not set -+# CONFIG_STE10XP is not set -+# CONFIG_LSI_ET1011C_PHY is not set -+# CONFIG_FIXED_PHY is not set -+# CONFIG_MDIO_BITBANG is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_AX88796 is not set -+# CONFIG_SMC91X is not set -+CONFIG_TI_DAVINCI_EMAC=y -+# CONFIG_DM9000 is not set -+# CONFIG_ETHOC is not set -+# CONFIG_SMC911X is not set -+# CONFIG_SMSC911X is not set -+# CONFIG_DNET is not set -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -+# CONFIG_B44 is not set -+# CONFIG_KS8842 is not set -+# CONFIG_KS8851_MLL is not set -+CONFIG_NETDEV_1000=y -+CONFIG_NETDEV_10000=y -+CONFIG_WLAN=y -+# CONFIG_USB_ZD1201 is not set -+# CONFIG_HOSTAP is not set -+ -+# -+# Enable WiMAX (Networking options) to see the WiMAX drivers -+# -+ -+# -+# USB Network Adapters -+# -+# CONFIG_USB_CATC is not set -+# CONFIG_USB_KAWETH is not set -+# CONFIG_USB_PEGASUS is not set -+# CONFIG_USB_RTL8150 is not set -+CONFIG_USB_USBNET=y -+# CONFIG_USB_NET_AX8817X is not set -+CONFIG_USB_NET_CDCETHER=y -+# CONFIG_USB_NET_CDC_EEM is not set -+CONFIG_USB_NET_DM9601=y -+# CONFIG_USB_NET_SMSC95XX is not set -+# CONFIG_USB_NET_GL620A is not set -+# CONFIG_USB_NET_NET1080 is not set -+# CONFIG_USB_NET_PLUSB is not set -+# CONFIG_USB_NET_MCS7830 is not set -+# CONFIG_USB_NET_RNDIS_HOST is not set -+# CONFIG_USB_NET_CDC_SUBSET is not set -+# CONFIG_USB_NET_ZAURUS is not set -+# CONFIG_USB_NET_INT51X1 is not set -+# CONFIG_WAN is not set -+# CONFIG_PPP is not set -+# CONFIG_SLIP is not set -+# CONFIG_NETCONSOLE is not set -+# CONFIG_NETPOLL is not set -+# CONFIG_NET_POLL_CONTROLLER is not set -+# CONFIG_ISDN is not set -+# CONFIG_PHONE is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+# CONFIG_INPUT_FF_MEMLESS is not set -+# CONFIG_INPUT_POLLDEV is not set -+# CONFIG_INPUT_SPARSEKMAP is not set -+ -+# -+# Userland interfaces -+# -+# CONFIG_INPUT_MOUSEDEV is not set -+# CONFIG_INPUT_JOYDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+# CONFIG_INPUT_MISC is not set -+ -+# -+# Hardware I/O ports -+# -+CONFIG_SERIO=y -+CONFIG_SERIO_SERPORT=y -+CONFIG_SERIO_LIBPS2=y -+# CONFIG_SERIO_RAW is not set -+# CONFIG_SERIO_ALTERA_PS2 is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_CONSOLE_TRANSLATIONS=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+# CONFIG_VT_HW_CONSOLE_BINDING is not set -+CONFIG_DEVKMEM=y -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_NR_UARTS=32 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_MANY_PORTS=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DETECT_IRQ=y -+CONFIG_SERIAL_8250_RSA=y -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+CONFIG_UNIX98_PTYS=y -+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_HW_RANDOM=y -+# CONFIG_HW_RANDOM_TIMERIOMEM is not set -+# CONFIG_R3964 is not set -+# CONFIG_RAW_DRIVER is not set -+# CONFIG_TCG_TPM is not set -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_COMPAT=y -+# CONFIG_I2C_CHARDEV is not set -+CONFIG_I2C_HELPER_AUTO=y -+ -+# -+# I2C Hardware Bus support -+# -+ -+# -+# I2C system bus drivers (mostly embedded / system-on-chip) -+# -+# CONFIG_I2C_DESIGNWARE is not set -+# CONFIG_I2C_GPIO is not set -+# CONFIG_I2C_OCORES is not set -+CONFIG_I2C_OMAP=y -+# CONFIG_I2C_SIMTEC is not set -+ -+# -+# External I2C/SMBus adapter drivers -+# -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_TINY_USB is not set -+ -+# -+# Other I2C/SMBus bus drivers -+# -+# CONFIG_I2C_PCA_PLATFORM is not set -+# CONFIG_I2C_STUB is not set -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+# CONFIG_SPI is not set -+ -+# -+# PPS support -+# -+# CONFIG_PPS is not set -+CONFIG_ARCH_REQUIRE_GPIOLIB=y -+CONFIG_GPIOLIB=y -+# CONFIG_DEBUG_GPIO is not set -+CONFIG_GPIO_SYSFS=y -+ -+# -+# Memory mapped GPIO expanders: -+# -+ -+# -+# I2C GPIO expanders: -+# -+# CONFIG_GPIO_MAX732X is not set -+# CONFIG_GPIO_PCA953X is not set -+# CONFIG_GPIO_PCF857X is not set -+# CONFIG_GPIO_TPS65910 is not set -+ -+# -+# PCI GPIO expanders: -+# -+ -+# -+# SPI GPIO expanders: -+# -+ -+# -+# AC97 GPIO expanders: -+# -+# CONFIG_W1 is not set -+# CONFIG_POWER_SUPPLY is not set -+# CONFIG_HWMON is not set -+# CONFIG_THERMAL is not set -+CONFIG_WATCHDOG=y -+CONFIG_WATCHDOG_NOWAYOUT=y -+ -+# -+# Watchdog Device Drivers -+# -+# CONFIG_SOFT_WATCHDOG is not set -+CONFIG_OMAP_WATCHDOG=y -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_SSB_POSSIBLE=y -+ -+# -+# Sonics Silicon Backplane -+# -+# CONFIG_SSB is not set -+ -+# -+# Multifunction device drivers -+# -+# CONFIG_MFD_CORE is not set -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_HTC_EGPIO is not set -+# CONFIG_HTC_PASIC3 is not set -+# CONFIG_TPS65010 is not set -+# CONFIG_TWL4030_CORE is not set -+CONFIG_TPS65910_CORE=y -+# CONFIG_MFD_TMIO is not set -+# CONFIG_MFD_T7L66XB is not set -+# CONFIG_MFD_TC6387XB is not set -+# CONFIG_MFD_TC6393XB is not set -+# CONFIG_PMIC_DA903X is not set -+# CONFIG_PMIC_ADP5520 is not set -+# CONFIG_MFD_WM8400 is not set -+# CONFIG_MFD_WM831X is not set -+# CONFIG_MFD_WM8350_I2C is not set -+# CONFIG_MFD_PCF50633 is not set -+# CONFIG_AB3100_CORE is not set -+# CONFIG_MFD_88PM8607 is not set -+CONFIG_REGULATOR=y -+# CONFIG_REGULATOR_DEBUG is not set -+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -+# CONFIG_REGULATOR_BQ24022 is not set -+# CONFIG_REGULATOR_MAX1586 is not set -+# CONFIG_REGULATOR_TPS65910 is not set -+# CONFIG_REGULATOR_LP3971 is not set -+# CONFIG_REGULATOR_TPS65023 is not set -+# CONFIG_REGULATOR_TPS6507X is not set -+CONFIG_MEDIA_SUPPORT=y -+ -+# -+# Multimedia core support -+# -+CONFIG_VIDEO_DEV=y -+CONFIG_VIDEO_V4L2_COMMON=y -+CONFIG_VIDEO_ALLOW_V4L1=y -+CONFIG_VIDEO_V4L1_COMPAT=y -+# CONFIG_DVB_CORE is not set -+CONFIG_VIDEO_MEDIA=y -+ -+# -+# Multimedia drivers -+# -+# CONFIG_MEDIA_ATTACH is not set -+CONFIG_MEDIA_TUNER=y -+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -+CONFIG_MEDIA_TUNER_SIMPLE=y -+CONFIG_MEDIA_TUNER_TDA8290=y -+CONFIG_MEDIA_TUNER_TDA9887=y -+CONFIG_MEDIA_TUNER_TEA5761=y -+CONFIG_MEDIA_TUNER_TEA5767=y -+CONFIG_MEDIA_TUNER_MT20XX=y -+CONFIG_MEDIA_TUNER_XC2028=y -+CONFIG_MEDIA_TUNER_XC5000=y -+CONFIG_MEDIA_TUNER_MC44S803=y -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_V4L1=y -+# CONFIG_VIDEO_CAPTURE_DRIVERS is not set -+# CONFIG_RADIO_ADAPTERS is not set -+# CONFIG_DAB is not set -+ -+# -+# Graphics support -+# -+# CONFIG_VGASTATE is not set -+# CONFIG_VIDEO_OUTPUT_CONTROL is not set -+CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB_DDC is not set -+# CONFIG_FB_BOOT_VESA_SUPPORT is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -+# CONFIG_FB_SYS_FILLRECT is not set -+# CONFIG_FB_SYS_COPYAREA is not set -+# CONFIG_FB_SYS_IMAGEBLIT is not set -+# CONFIG_FB_FOREIGN_ENDIAN is not set -+# CONFIG_FB_SYS_FOPS is not set -+# CONFIG_FB_SVGALIB is not set -+# CONFIG_FB_MACMODES is not set -+# CONFIG_FB_BACKLIGHT is not set -+# CONFIG_FB_MODE_HELPERS is not set -+# CONFIG_FB_TILEBLITTING is not set -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_VIRTUAL is not set -+# CONFIG_FB_METRONOME is not set -+# CONFIG_FB_MB862XX is not set -+# CONFIG_FB_BROADSHEET is not set -+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -+CONFIG_OMAP2_VRAM=y -+CONFIG_OMAP2_VRFB=y -+CONFIG_OMAP2_DSS=y -+CONFIG_OMAP2_VRAM_SIZE=4 -+# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -+# CONFIG_OMAP2_DSS_RFBI is not set -+CONFIG_OMAP2_DSS_VENC=y -+# CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO is not set -+CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE=y -+# CONFIG_OMAP2_DSS_SDI is not set -+# CONFIG_OMAP2_DSS_DSI is not set -+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 -+CONFIG_FB_OMAP2=y -+# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -+CONFIG_FB_OMAP2_NUM_FBS=1 -+ -+# -+# OMAP2/3 Display Device Drivers -+# -+CONFIG_PANEL_GENERIC=y -+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set -+# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Display device support -+# -+# CONFIG_DISPLAY_SUPPORT is not set -+ -+# -+# Console display driver support -+# -+# CONFIG_VGA_CONSOLE is not set -+CONFIG_DUMMY_CONSOLE=y -+# CONFIG_FRAMEBUFFER_CONSOLE is not set -+CONFIG_LOGO=y -+CONFIG_LOGO_LINUX_MONO=y -+CONFIG_LOGO_LINUX_VGA16=y -+CONFIG_LOGO_LINUX_CLUT224=y -+# CONFIG_SOUND is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+# CONFIG_HIDRAW is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_HID_PID is not set -+# CONFIG_USB_HIDDEV is not set -+ -+# -+# Special HID drivers -+# -+# CONFIG_HID_A4TECH is not set -+# CONFIG_HID_APPLE is not set -+# CONFIG_HID_BELKIN is not set -+# CONFIG_HID_CHERRY is not set -+# CONFIG_HID_CHICONY is not set -+# CONFIG_HID_CYPRESS is not set -+# CONFIG_HID_DRAGONRISE is not set -+# CONFIG_HID_EZKEY is not set -+# CONFIG_HID_KYE is not set -+# CONFIG_HID_GYRATION is not set -+# CONFIG_HID_TWINHAN is not set -+# CONFIG_HID_KENSINGTON is not set -+# CONFIG_HID_LOGITECH is not set -+# CONFIG_HID_MICROSOFT is not set -+# CONFIG_HID_MONTEREY is not set -+# CONFIG_HID_NTRIG is not set -+# CONFIG_HID_PANTHERLORD is not set -+# CONFIG_HID_PETALYNX is not set -+# CONFIG_HID_SAMSUNG is not set -+# CONFIG_HID_SONY is not set -+# CONFIG_HID_SUNPLUS is not set -+# CONFIG_HID_GREENASIA is not set -+# CONFIG_HID_SMARTJOYPLUS is not set -+# CONFIG_HID_TOPSEED is not set -+# CONFIG_HID_THRUSTMASTER is not set -+# CONFIG_HID_ZEROPLUS is not set -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+CONFIG_USB_ARCH_HAS_EHCI=y -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+CONFIG_USB_DEVICE_CLASS=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+CONFIG_USB_SUSPEND=y -+CONFIG_USB_OTG=y -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set -+# CONFIG_USB_MON is not set -+# CONFIG_USB_WUSB is not set -+# CONFIG_USB_WUSB_CBAF is not set -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+CONFIG_USB_EHCI_HCD=y -+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+# CONFIG_USB_OXU210HP_HCD is not set -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set -+# CONFIG_USB_ISP1362_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_HWA_HCD is not set -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_MUSB_SOC=y -+ -+# -+# OMAP 343x high speed USB support -+# -+# CONFIG_USB_MUSB_HOST is not set -+# CONFIG_USB_MUSB_PERIPHERAL is not set -+CONFIG_USB_MUSB_OTG=y -+CONFIG_USB_GADGET_MUSB_HDRC=y -+CONFIG_USB_MUSB_HDRC_HCD=y -+# CONFIG_MUSB_PIO_ONLY is not set -+# CONFIG_USB_TI_CPPI_DMA is not set -+CONFIG_USB_TI_CPPI41_DMA=y -+CONFIG_USB_MUSB_DEBUG=y -+ -+# -+# USB Device Class drivers -+# -+# CONFIG_USB_ACM is not set -+# CONFIG_USB_PRINTER is not set -+# CONFIG_USB_WDM is not set -+# CONFIG_USB_TMC is not set -+ -+# -+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -+# -+ -+# -+# also be needed; see USB_STORAGE Help for more info -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+# CONFIG_USB_STORAGE_DATAFAB is not set -+# CONFIG_USB_STORAGE_FREECOM is not set -+# CONFIG_USB_STORAGE_ISD200 is not set -+# CONFIG_USB_STORAGE_USBAT is not set -+# CONFIG_USB_STORAGE_SDDR09 is not set -+# CONFIG_USB_STORAGE_SDDR55 is not set -+# CONFIG_USB_STORAGE_JUMPSHOT is not set -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -+# CONFIG_USB_LIBUSUAL is not set -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+ -+# -+# USB port drivers -+# -+# CONFIG_USB_SERIAL is not set -+ -+# -+# USB Miscellaneous drivers -+# -+# CONFIG_USB_EMI62 is not set -+# CONFIG_USB_EMI26 is not set -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_SEVSEG is not set -+# CONFIG_USB_RIO500 is not set -+# CONFIG_USB_LEGOTOWER is not set -+# CONFIG_USB_LCD is not set -+# CONFIG_USB_BERRY_CHARGE is not set -+# CONFIG_USB_LED is not set -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+# CONFIG_USB_CYTHERM is not set -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+# CONFIG_USB_APPLEDISPLAY is not set -+# CONFIG_USB_SISUSBVGA is not set -+# CONFIG_USB_LD is not set -+# CONFIG_USB_TRANCEVIBRATOR is not set -+# CONFIG_USB_IOWARRIOR is not set -+CONFIG_USB_TEST=y -+# CONFIG_USB_ISIGHTFW is not set -+# CONFIG_USB_VST is not set -+CONFIG_USB_GADGET=y -+# CONFIG_USB_GADGET_DEBUG is not set -+# CONFIG_USB_GADGET_DEBUG_FILES is not set -+CONFIG_USB_GADGET_VBUS_DRAW=2 -+CONFIG_USB_GADGET_SELECTED=y -+# CONFIG_USB_GADGET_AT91 is not set -+# CONFIG_USB_GADGET_ATMEL_USBA is not set -+# CONFIG_USB_GADGET_FSL_USB2 is not set -+# CONFIG_USB_GADGET_LH7A40X is not set -+# CONFIG_USB_GADGET_OMAP is not set -+# CONFIG_USB_GADGET_PXA25X is not set -+# CONFIG_USB_GADGET_R8A66597 is not set -+# CONFIG_USB_GADGET_PXA27X is not set -+# CONFIG_USB_GADGET_S3C_HSOTG is not set -+# CONFIG_USB_GADGET_IMX is not set -+# CONFIG_USB_GADGET_S3C2410 is not set -+# CONFIG_USB_GADGET_M66592 is not set -+# CONFIG_USB_GADGET_AMD5536UDC is not set -+# CONFIG_USB_GADGET_FSL_QE is not set -+# CONFIG_USB_GADGET_CI13XXX is not set -+# CONFIG_USB_GADGET_NET2280 is not set -+# CONFIG_USB_GADGET_GOKU is not set -+# CONFIG_USB_GADGET_LANGWELL is not set -+# CONFIG_USB_GADGET_DUMMY_HCD is not set -+CONFIG_USB_GADGET_DUALSPEED=y -+# CONFIG_USB_ZERO is not set -+# CONFIG_USB_AUDIO is not set -+# CONFIG_USB_ETH is not set -+# CONFIG_USB_GADGETFS is not set -+CONFIG_USB_FILE_STORAGE=m -+# CONFIG_USB_FILE_STORAGE_TEST is not set -+CONFIG_USB_MASS_STORAGE=m -+# CONFIG_USB_G_SERIAL is not set -+# CONFIG_USB_MIDI_GADGET is not set -+# CONFIG_USB_G_PRINTER is not set -+# CONFIG_USB_CDC_COMPOSITE is not set -+# CONFIG_USB_G_MULTI is not set -+ -+# -+# OTG and related infrastructure -+# -+CONFIG_USB_OTG_UTILS=y -+# CONFIG_USB_GPIO_VBUS is not set -+# CONFIG_ISP1301_OMAP is not set -+# CONFIG_USB_ULPI is not set -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_MMC=y -+# CONFIG_MMC_DEBUG is not set -+# CONFIG_MMC_UNSAFE_RESUME is not set -+ -+# -+# MMC/SD/SDIO Card Drivers -+# -+CONFIG_MMC_BLOCK=y -+CONFIG_MMC_BLOCK_BOUNCE=y -+# CONFIG_SDIO_UART is not set -+# CONFIG_MMC_TEST is not set -+ -+# -+# MMC/SD/SDIO Host Controller Drivers -+# -+# CONFIG_MMC_SDHCI is not set -+# CONFIG_MMC_OMAP is not set -+CONFIG_MMC_OMAP_HS=y -+# CONFIG_MMC_AT91 is not set -+# CONFIG_MMC_ATMELMCI is not set -+# CONFIG_MEMSTICK is not set -+# CONFIG_NEW_LEDS is not set -+# CONFIG_ACCESSIBILITY is not set -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_HCTOSYS=y -+CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -+# CONFIG_RTC_DEBUG is not set -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1374 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+# CONFIG_RTC_DRV_M41T80 is not set -+CONFIG_RTC_DRV_TPS65910=y -+# CONFIG_RTC_DRV_S35390A is not set -+# CONFIG_RTC_DRV_FM3130 is not set -+# CONFIG_RTC_DRV_RX8581 is not set -+# CONFIG_RTC_DRV_RX8025 is not set -+ -+# -+# SPI RTC drivers -+# -+ -+# -+# Platform RTC drivers -+# -+# CONFIG_RTC_DRV_CMOS is not set -+# CONFIG_RTC_DRV_DS1286 is not set -+# CONFIG_RTC_DRV_DS1511 is not set -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_STK17TA8 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T35 is not set -+# CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_MSM6242 is not set -+# CONFIG_RTC_DRV_BQ4802 is not set -+# CONFIG_RTC_DRV_RP5C01 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+# CONFIG_DMADEVICES is not set -+# CONFIG_AUXDISPLAY is not set -+# CONFIG_UIO is not set -+ -+# -+# TI VLYNQ -+# -+# CONFIG_STAGING is not set -+ -+# -+# CBUS support -+# -+# CONFIG_CBUS is not set -+ -+# -+# File systems -+# -+CONFIG_FS_JOURNAL_INFO=y -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -+# CONFIG_EXT3_FS_XATTR is not set -+# CONFIG_EXT4_FS is not set -+CONFIG_JBD=y -+# CONFIG_REISERFS_FS is not set -+# CONFIG_JFS_FS is not set -+# CONFIG_FS_POSIX_ACL is not set -+# CONFIG_XFS_FS is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+# CONFIG_BTRFS_FS is not set -+# CONFIG_NILFS2_FS is not set -+CONFIG_FILE_LOCKING=y -+CONFIG_FSNOTIFY=y -+CONFIG_DNOTIFY=y -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+CONFIG_QUOTA=y -+# CONFIG_QUOTA_NETLINK_INTERFACE is not set -+CONFIG_PRINT_QUOTA_WARNING=y -+CONFIG_QUOTA_TREE=y -+# CONFIG_QFMT_V1 is not set -+CONFIG_QFMT_V2=y -+CONFIG_QUOTACTL=y -+# CONFIG_AUTOFS_FS is not set -+# CONFIG_AUTOFS4_FS is not set -+# CONFIG_FUSE_FS is not set -+ -+# -+# Caches -+# -+# CONFIG_FSCACHE is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+# CONFIG_ISO9660_FS is not set -+# CONFIG_UDF_FS is not set -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_PROC_PAGE_MONITOR=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+# CONFIG_TMPFS_POSIX_ACL is not set -+# CONFIG_HUGETLB_PAGE is not set -+# CONFIG_CONFIGFS_FS is not set -+CONFIG_MISC_FILESYSTEMS=y -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_HFS_FS is not set -+# CONFIG_HFSPLUS_FS is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y -+CONFIG_JFFS2_ZLIB=y -+# CONFIG_JFFS2_LZO is not set -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+# CONFIG_JFFS2_CMODE_NONE is not set -+CONFIG_JFFS2_CMODE_PRIORITY=y -+# CONFIG_JFFS2_CMODE_SIZE is not set -+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -+# CONFIG_CRAMFS is not set -+# CONFIG_SQUASHFS is not set -+# CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_OMFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_ROMFS_FS is not set -+# CONFIG_SYSV_FS is not set -+# CONFIG_UFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+CONFIG_NFS_V4=y -+# CONFIG_NFS_V4_1 is not set -+CONFIG_ROOT_NFS=y -+# CONFIG_NFSD is not set -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+CONFIG_SUNRPC_GSS=y -+CONFIG_RPCSEC_GSS_KRB5=y -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+# CONFIG_SMB_FS is not set -+# CONFIG_CIFS is not set -+# CONFIG_NCP_FS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+# CONFIG_MAC_PARTITION is not set -+CONFIG_MSDOS_PARTITION=y -+# CONFIG_BSD_DISKLABEL is not set -+# CONFIG_MINIX_SUBPARTITION is not set -+# CONFIG_SOLARIS_X86_PARTITION is not set -+# CONFIG_UNIXWARE_DISKLABEL is not set -+# CONFIG_LDM_PARTITION is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+# CONFIG_NLS_CODEPAGE_737 is not set -+# CONFIG_NLS_CODEPAGE_775 is not set -+# CONFIG_NLS_CODEPAGE_850 is not set -+# CONFIG_NLS_CODEPAGE_852 is not set -+# CONFIG_NLS_CODEPAGE_855 is not set -+# CONFIG_NLS_CODEPAGE_857 is not set -+# CONFIG_NLS_CODEPAGE_860 is not set -+# CONFIG_NLS_CODEPAGE_861 is not set -+# CONFIG_NLS_CODEPAGE_862 is not set -+# CONFIG_NLS_CODEPAGE_863 is not set -+# CONFIG_NLS_CODEPAGE_864 is not set -+# CONFIG_NLS_CODEPAGE_865 is not set -+# CONFIG_NLS_CODEPAGE_866 is not set -+# CONFIG_NLS_CODEPAGE_869 is not set -+# CONFIG_NLS_CODEPAGE_936 is not set -+# CONFIG_NLS_CODEPAGE_950 is not set -+# CONFIG_NLS_CODEPAGE_932 is not set -+# CONFIG_NLS_CODEPAGE_949 is not set -+# CONFIG_NLS_CODEPAGE_874 is not set -+# CONFIG_NLS_ISO8859_8 is not set -+# CONFIG_NLS_CODEPAGE_1250 is not set -+# CONFIG_NLS_CODEPAGE_1251 is not set -+# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_ISO8859_1=y -+# CONFIG_NLS_ISO8859_2 is not set -+# CONFIG_NLS_ISO8859_3 is not set -+# CONFIG_NLS_ISO8859_4 is not set -+# CONFIG_NLS_ISO8859_5 is not set -+# CONFIG_NLS_ISO8859_6 is not set -+# CONFIG_NLS_ISO8859_7 is not set -+# CONFIG_NLS_ISO8859_9 is not set -+# CONFIG_NLS_ISO8859_13 is not set -+# CONFIG_NLS_ISO8859_14 is not set -+# CONFIG_NLS_ISO8859_15 is not set -+# CONFIG_NLS_KOI8_R is not set -+# CONFIG_NLS_KOI8_U is not set -+# CONFIG_NLS_UTF8 is not set -+# CONFIG_DLM is not set -+ -+# -+# Kernel hacking -+# -+# CONFIG_PRINTK_TIME is not set -+CONFIG_ENABLE_WARN_DEPRECATED=y -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_STRIP_ASM_SYMS is not set -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_DEBUG_FS is not set -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -+CONFIG_DETECT_HUNG_TASK=y -+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_SCHEDSTATS is not set -+# CONFIG_TIMER_STATS is not set -+# CONFIG_DEBUG_OBJECTS is not set -+# CONFIG_DEBUG_SLAB is not set -+# CONFIG_DEBUG_KMEMLEAK is not set -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+CONFIG_DEBUG_MUTEXES=y -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_WRITECOUNT is not set -+# CONFIG_DEBUG_MEMORY_INIT is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_SG is not set -+# CONFIG_DEBUG_NOTIFIERS is not set -+# CONFIG_DEBUG_CREDENTIALS is not set -+# CONFIG_BOOT_PRINTK_DELAY is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_RCU_CPU_STALL_DETECTOR is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -+# CONFIG_FAULT_INJECTION is not set -+# CONFIG_LATENCYTOP is not set -+# CONFIG_SYSCTL_SYSCALL_CHECK is not set -+# CONFIG_PAGE_POISONING is not set -+CONFIG_HAVE_FUNCTION_TRACER=y -+CONFIG_TRACING_SUPPORT=y -+CONFIG_FTRACE=y -+# CONFIG_FUNCTION_TRACER is not set -+# CONFIG_IRQSOFF_TRACER is not set -+# CONFIG_SCHED_TRACER is not set -+# CONFIG_ENABLE_DEFAULT_TRACERS is not set -+# CONFIG_BOOT_TRACER is not set -+CONFIG_BRANCH_PROFILE_NONE=y -+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -+# CONFIG_PROFILE_ALL_BRANCHES is not set -+# CONFIG_STACK_TRACER is not set -+# CONFIG_KMEMTRACE is not set -+# CONFIG_WORKQUEUE_TRACER is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_SAMPLES is not set -+CONFIG_HAVE_ARCH_KGDB=y -+# CONFIG_KGDB is not set -+CONFIG_ARM_UNWIND=y -+# CONFIG_DEBUG_USER is not set -+# CONFIG_DEBUG_ERRORS is not set -+# CONFIG_DEBUG_STACK_USAGE is not set -+CONFIG_DEBUG_LL=y -+# CONFIG_EARLY_PRINTK is not set -+# CONFIG_DEBUG_ICEDCC is not set -+# CONFIG_OC_ETM is not set -+ -+# -+# Security options -+# -+# CONFIG_KEYS is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITYFS is not set -+# CONFIG_DEFAULT_SECURITY_SELINUX is not set -+# CONFIG_DEFAULT_SECURITY_SMACK is not set -+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -+CONFIG_DEFAULT_SECURITY_DAC=y -+CONFIG_DEFAULT_SECURITY="" -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_ALGAPI2=y -+CONFIG_CRYPTO_AEAD2=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_BLKCIPHER2=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_HASH2=y -+CONFIG_CRYPTO_RNG2=y -+CONFIG_CRYPTO_PCOMP=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_MANAGER2=y -+# CONFIG_CRYPTO_GF128MUL is not set -+# CONFIG_CRYPTO_NULL is not set -+CONFIG_CRYPTO_WORKQUEUE=y -+# CONFIG_CRYPTO_CRYPTD is not set -+# CONFIG_CRYPTO_AUTHENC is not set -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+# CONFIG_CRYPTO_CCM is not set -+# CONFIG_CRYPTO_GCM is not set -+# CONFIG_CRYPTO_SEQIV is not set -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=y -+# CONFIG_CRYPTO_CTR is not set -+# CONFIG_CRYPTO_CTS is not set -+CONFIG_CRYPTO_ECB=m -+# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_PCBC=m -+# CONFIG_CRYPTO_XTS is not set -+ -+# -+# Hash modes -+# -+# CONFIG_CRYPTO_HMAC is not set -+# CONFIG_CRYPTO_XCBC is not set -+# CONFIG_CRYPTO_VMAC is not set -+ -+# -+# Digest -+# -+CONFIG_CRYPTO_CRC32C=y -+# CONFIG_CRYPTO_GHASH is not set -+# CONFIG_CRYPTO_MD4 is not set -+CONFIG_CRYPTO_MD5=y -+# CONFIG_CRYPTO_MICHAEL_MIC is not set -+# CONFIG_CRYPTO_RMD128 is not set -+# CONFIG_CRYPTO_RMD160 is not set -+# CONFIG_CRYPTO_RMD256 is not set -+# CONFIG_CRYPTO_RMD320 is not set -+# CONFIG_CRYPTO_SHA1 is not set -+# CONFIG_CRYPTO_SHA256 is not set -+# CONFIG_CRYPTO_SHA512 is not set -+# CONFIG_CRYPTO_TGR192 is not set -+# CONFIG_CRYPTO_WP512 is not set -+ -+# -+# Ciphers -+# -+# CONFIG_CRYPTO_AES is not set -+# CONFIG_CRYPTO_ANUBIS is not set -+# CONFIG_CRYPTO_ARC4 is not set -+# CONFIG_CRYPTO_BLOWFISH is not set -+# CONFIG_CRYPTO_CAMELLIA is not set -+# CONFIG_CRYPTO_CAST5 is not set -+# CONFIG_CRYPTO_CAST6 is not set -+CONFIG_CRYPTO_DES=y -+# CONFIG_CRYPTO_FCRYPT is not set -+# CONFIG_CRYPTO_KHAZAD is not set -+# CONFIG_CRYPTO_SALSA20 is not set -+# CONFIG_CRYPTO_SEED is not set -+# CONFIG_CRYPTO_SERPENT is not set -+# CONFIG_CRYPTO_TEA is not set -+# CONFIG_CRYPTO_TWOFISH is not set -+ -+# -+# Compression -+# -+# CONFIG_CRYPTO_DEFLATE is not set -+# CONFIG_CRYPTO_ZLIB is not set -+# CONFIG_CRYPTO_LZO is not set -+ -+# -+# Random Number Generation -+# -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_HW=y -+# CONFIG_BINARY_PRINTF is not set -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+CONFIG_GENERIC_FIND_LAST_BIT=y -+CONFIG_CRC_CCITT=y -+# CONFIG_CRC16 is not set -+# CONFIG_CRC_T10DIF is not set -+# CONFIG_CRC_ITU_T is not set -+CONFIG_CRC32=y -+# CONFIG_CRC7 is not set -+CONFIG_LIBCRC32C=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_DECOMPRESS_GZIP=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y -+CONFIG_NLATTR=y -diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig -index b72ae06..d965d58 100644 ---- a/arch/arm/mach-omap2/Kconfig -+++ b/arch/arm/mach-omap2/Kconfig -@@ -96,6 +96,11 @@ config MACH_OMAP3517EVM - depends on ARCH_OMAP3 && ARCH_OMAP34XX - select OMAP_PACKAGE_CBB - -+config MACH_CRANEBOARD -+ bool "AM3517/05 Crane board" -+ depends on ARCH_OMAP3 && ARCH_OMAP34XX -+ select OMAP_PACKAGE_CBB -+ - config PMIC_TPS65023 - bool "TPS65023 Power Module" - default y -@@ -171,6 +176,7 @@ config MACH_OMAP_4430SDP - bool "OMAP 4430 SDP board" - depends on ARCH_OMAP4 - -+ - config OMAP3_EMU - bool "OMAP3 debugging peripherals" - depends on ARCH_OMAP3 -diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile -index fa01859..9042317 100644 ---- a/arch/arm/mach-omap2/Makefile -+++ b/arch/arm/mach-omap2/Makefile -@@ -130,6 +130,8 @@ obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o - obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \ - mmc-am3517evm.o - -+obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o \ -+ mmc-am3517crane.o - # Platform specific device init code - obj-y += usb-musb.o - obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o -diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c -new file mode 100644 -index 0000000..0bf4f60 ---- /dev/null -+++ b/arch/arm/mach-omap2/board-am3517crane.c -@@ -0,0 +1,773 @@ -+/* -+ * linux/arch/arm/mach-omap2/board-am3517crane.c -+ * -+ * Copyright (C) 2010 Mistral Solutions Pvt LtD -+ * Author: Srinath.R -+ * -+ * Based on mach-omap2/board-am3517evm.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, -+ * whether express or implied; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mmc-am3517crane.h" -+#include "mux.h" -+ -+#define GPMC_CS0_BASE 0x60 -+#define GPMC_CS_SIZE 0x30 -+ -+#define NAND_BLOCK_SIZE SZ_128K -+ -+static struct mtd_partition am3517crane_nand_partitions[] = { -+ /* All the partition sizes are listed in terms of NAND block size */ -+ { -+ .name = "xloader-nand", -+ .offset = 0, -+ .size = 4*(SZ_128K), -+ .mask_flags = MTD_WRITEABLE -+ }, -+ { -+ .name = "uboot-nand", -+ .offset = MTDPART_OFS_APPEND, -+ .size = 28*(SZ_128K), -+ .mask_flags = MTD_WRITEABLE -+ }, -+ { -+ .name = "params-nand", -+ .offset = MTDPART_OFS_APPEND, -+ .size = 4*(SZ_128K) -+ }, -+ { -+ .name = "linux-nand", -+ .offset = MTDPART_OFS_APPEND, -+ .size = 80*(SZ_128K) -+ }, -+ { -+ .name = "jffs2-nand", -+ .size = MTDPART_SIZ_FULL, -+ .offset = MTDPART_OFS_APPEND, -+ }, -+}; -+ -+static struct omap_nand_platform_data am3517crane_nand_data = { -+ .parts = am3517crane_nand_partitions, -+ .nr_parts = ARRAY_SIZE(am3517crane_nand_partitions), -+ .nand_setup = NULL, -+ .dma_channel = -1, /* disable DMA in OMAP NAND driver */ -+ .dev_ready = NULL, -+}; -+ -+static struct resource am3517crane_nand_resource = { -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct platform_device am3517crane_nand_device = { -+ .name = "omap2-nand", -+ .id = 0, -+ .dev = { -+ .platform_data = &am3517crane_nand_data, -+ }, -+ .num_resources = 1, -+ .resource = &am3517crane_nand_resource, -+}; -+ -+void __init am3517crane_flash_init(void) -+{ -+ u8 cs = 0; -+ u8 nandcs = GPMC_CS_NUM + 1; -+ u32 gpmc_base_add = OMAP34XX_GPMC_VIRT; -+ -+ while (cs < GPMC_CS_NUM) { -+ u32 ret = 0; -+ ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); -+ -+ if ((ret & 0xC00) == 0x800) { -+ /* Found it!! */ -+ if (nandcs > GPMC_CS_NUM) -+ nandcs = cs; -+ } -+ cs++; -+ } -+ if (nandcs > GPMC_CS_NUM) { -+ printk(KERN_INFO "NAND: Unable to find configuration " -+ " in GPMC\n "); -+ return; -+ } -+ -+ if (nandcs < GPMC_CS_NUM) { -+ am3517crane_nand_data.cs = nandcs; -+ am3517crane_nand_data.gpmc_cs_baseaddr = -+ (void *)(gpmc_base_add + GPMC_CS0_BASE + nandcs*GPMC_CS_SIZE); -+ -+ am3517crane_nand_data.gpmc_baseaddr = (void *)(gpmc_base_add); -+ -+ if (platform_device_register(&am3517crane_nand_device) < 0) -+ printk(KERN_ERR "Unable to register NAND device\n"); -+ -+ } -+} -+ -+ -+#define AM35XX_EVM_PHY_MASK (0xF) -+#define AM35XX_EVM_MDIO_FREQUENCY (1000000) -+ -+static struct emac_platform_data am3517_crane_emac_pdata = { -+ .phy_mask = AM35XX_EVM_PHY_MASK, -+ .mdio_max_freq = AM35XX_EVM_MDIO_FREQUENCY, -+ .rmii_en = 1, -+}; -+ -+static int __init eth_addr_setup(char *str) -+{ -+ int i; -+ -+ if (str == NULL) -+ return 0; -+ for (i = 0; i < ETH_ALEN; i++) -+ am3517_crane_emac_pdata.mac_addr[i] = simple_strtol(&str[i*3], -+ (char **)NULL, 16); -+ return 1; -+} -+ -+/* Get MAC address from kernel boot parameter eth=AA:BB:CC:DD:EE:FF */ -+__setup("eth=", eth_addr_setup); -+ -+static struct resource am3517_emac_resources[] = { -+ { -+ .start = AM35XX_IPSS_EMAC_BASE, -+ .end = AM35XX_IPSS_EMAC_BASE + 0x3FFFF, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = INT_35XX_EMAC_C0_RXTHRESH_IRQ, -+ .end = INT_35XX_EMAC_C0_RXTHRESH_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .start = INT_35XX_EMAC_C0_RX_PULSE_IRQ, -+ .end = INT_35XX_EMAC_C0_RX_PULSE_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .start = INT_35XX_EMAC_C0_TX_PULSE_IRQ, -+ .end = INT_35XX_EMAC_C0_TX_PULSE_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .start = INT_35XX_EMAC_C0_MISC_PULSE_IRQ, -+ .end = INT_35XX_EMAC_C0_MISC_PULSE_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device am3517_emac_device = { -+ .name = "davinci_emac", -+ .id = -1, -+ .num_resources = ARRAY_SIZE(am3517_emac_resources), -+ .resource = am3517_emac_resources, -+}; -+ -+static void am3517_enable_ethernet_int(void) -+{ -+ u32 regval; -+ -+ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -+ regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | -+ AM35XX_CPGMAC_C0_TX_PULSE_CLR | -+ AM35XX_CPGMAC_C0_MISC_PULSE_CLR | -+ AM35XX_CPGMAC_C0_RX_THRESH_CLR); -+ -+ omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); -+ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -+} -+ -+static void am3517_disable_ethernet_int(void) -+{ -+ u32 regval; -+ -+ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -+ regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | -+ AM35XX_CPGMAC_C0_TX_PULSE_CLR); -+ omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); -+ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -+} -+ -+void am3517_crane_ethernet_init(struct emac_platform_data *pdata) -+{ -+ unsigned int regval; -+ -+ pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET; -+ pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET; -+ pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET; -+ pdata->mdio_reg_offset = AM35XX_EMAC_MDIO_OFFSET; -+ pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE; -+ pdata->version = EMAC_VERSION_2; -+ pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR; -+ pdata->interrupt_enable = am3517_enable_ethernet_int; -+ pdata->interrupt_disable = am3517_disable_ethernet_int; -+ am3517_emac_device.dev.platform_data = pdata; -+ platform_device_register(&am3517_emac_device); -+ -+ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -+ regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); -+ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); -+ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -+ -+ return ; -+} -+ -+static void __init am3517_crane_display_init(void) -+{ -+ omap_mux_init_gpio(52, OMAP_PIN_OUTPUT); -+ gpio_request(52, "dvi_enable"); -+ gpio_direction_output(52, 1); -+} -+ -+ -+ -+static struct omap_dss_device am3517_crane_tv_device = { -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .name = "tv", -+ .driver_name = "venc", -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, -+ .platform_enable = NULL, -+ .platform_disable = NULL, -+}; -+ -+static int am3517_crane_panel_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ gpio_set_value(52, 1); -+ return 0; -+} -+ -+static void am3517_crane_panel_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ gpio_set_value(52, 0); -+} -+ -+static struct omap_dss_device am3517_crane_dvi_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "dvi", -+ .driver_name = "generic_panel", -+ .phy.dpi.data_lines = 24, -+ .platform_enable = am3517_crane_panel_enable_dvi, -+ .platform_disable = am3517_crane_panel_disable_dvi, -+}; -+ -+static struct omap_dss_device *am3517_crane_dss_devices[] = { -+ &am3517_crane_tv_device, -+ &am3517_crane_dvi_device, -+}; -+ -+static struct omap_dss_board_info am3517_crane_dss_data = { -+ .num_devices = ARRAY_SIZE(am3517_crane_dss_devices), -+ .devices = am3517_crane_dss_devices, -+ .default_device = &am3517_crane_dvi_device, -+}; -+ -+struct platform_device am3517_crane_dss_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = &am3517_crane_dss_data, -+ }, -+}; -+ -+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); -+static struct resource dm644x_ccdc_resource[] = { -+ /* CCDC Base address */ -+ { -+ .start = AM35XX_IPSS_VPFE_BASE, -+ .end = AM35XX_IPSS_VPFE_BASE + 0xffff, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device dm644x_ccdc_dev = { -+ .name = "dm644x_ccdc", -+ .id = -1, -+ .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), -+ .resource = dm644x_ccdc_resource, -+ .dev = { -+ .dma_mask = &vpfe_capture_dma_mask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+}; -+ -+static struct regulator_consumer_supply am3517_crane_vdd1_supplies[] = { -+ { -+ .supply = "vdd_core", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vdd1 = { -+ .constraints = { -+ .min_uV = 1200000, -+ .max_uV = 1200000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vdd1_supplies), -+ .consumer_supplies = am3517_crane_vdd1_supplies, -+}; -+ -+static struct regulator_consumer_supply am3517_crane_vdd2_supplies[] = { -+ { -+ .supply = "vddshv", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vdd2 = { -+ .constraints = { -+ .min_uV = 3300000, -+ .max_uV = 3300000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vdd2_supplies), -+ .consumer_supplies = am3517_crane_vdd2_supplies, -+}; -+ -+ -+static struct regulator_consumer_supply am3517_crane_vio_supplies[] = { -+ { -+ .supply = "vdds", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vio = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vio_supplies), -+ .consumer_supplies = am3517_crane_vio_supplies, -+}; -+ -+ -+static struct regulator_consumer_supply am3517_crane_vaux1_supplies[] = { -+ { -+ .supply = "vdd_sram_mpu", -+ }, -+ { -+ .supply = "vdd_sram_core_bg0", -+ }, -+ { -+ .supply = "vddsosc", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vaux1 = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vaux1_supplies), -+ .consumer_supplies = am3517_crane_vaux1_supplies, -+}; -+ -+ -+static struct regulator_consumer_supply am3517_crane_vaux2_supplies[] = { -+ { -+ .supply = "vdda1p8v_usbphy", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vaux2 = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vaux2_supplies), -+ .consumer_supplies = am3517_crane_vaux2_supplies, -+}; -+ -+ -+static struct regulator_consumer_supply am3517_crane_vdac_supplies[] = { -+ { -+ .supply = "vdda_dac", -+ .dev = &am3517_crane_dss_device.dev, -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vdac = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vdac_supplies), -+ .consumer_supplies = am3517_crane_vdac_supplies, -+}; -+ -+static struct regulator_consumer_supply am3517_crane_vmmc_supplies[] = { -+ { -+ .supply = "vdda3p3v_usbphy", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vmmc = { -+ .constraints = { -+ .min_uV = 3300000, -+ .max_uV = 3300000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vmmc_supplies), -+ .consumer_supplies = am3517_crane_vmmc_supplies, -+}; -+ -+ -+static struct regulator_consumer_supply am3517_crane_vpll_supplies[] = { -+ { -+ .supply = "vdds_dpll_mpu_usbhost", -+ }, -+ { -+ .supply = "vdds_dpll_per_core", -+ }, -+}; -+ -+static struct regulator_init_data am3517_crane_regulator_vpll = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL, -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(am3517_crane_vpll_supplies), -+ .consumer_supplies = am3517_crane_vpll_supplies, -+}; -+ -+static int am3517_crane_tps65910_config(struct tps65910_platform_data *pdata) -+{ -+ u8 val = 0; -+ int i = 0; -+ int err = -1; -+ -+ -+ /* Configure TPS65910 for am3517_crane board needs */ -+ -+ /* Set sleep state active high */ -+ val |= (TPS65910_DEV2_SLEEPSIG_POL); -+ -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_DEVCTRL2); -+ if (err) { -+ printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL2 reg\n"); -+ return -EIO; -+ } -+ -+ /* Mask ALL interrupts */ -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, 0xFF, -+ TPS65910_REG_INT_MSK); -+ if (err) { -+ printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK reg\n"); -+ return -EIO; -+ } -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, 0x03, -+ TPS65910_REG_INT_MSK2); -+ if (err) { -+ printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK2 reg\n"); -+ return -EIO; -+ } -+ -+ /* Set RTC regulator on during sleep */ -+ -+ val = TPS65910_VRTC_OFFMASK; -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_VRTC); -+ -+ if (err) { -+ printk(KERN_ERR "Unable to write TPS65910_REG_VRTC reg\n"); -+ return -EIO; -+ } -+ /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */ -+ val = 0; -+ val &= ~TPS65910_RTC_PWDNN; -+ val |= (TPS65910_CK32K_CTRL | TPS65910_SR_CTL_I2C_SEL); -+ -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_DEVCTRL); -+ if (err) { -+ printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL reg\n"); -+ return -EIO; -+ } -+ -+ /* Enable and set back-up battery charger control*/ -+ -+ tps65910_enable_bbch(TPS65910_BBSEL_2P52); -+ -+ err = tps65910_i2c_read_u8(TPS65910_I2C_ID0, &val, -+ TPS65910_REG_VRTC); -+ if (err) { -+ printk(KERN_ERR "Unable to read TPS65910_REG_VRTC reg\n"); -+ return -EIO; -+ } -+ val = TPS65910_VRTC_OFFMASK; -+ -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_VRTC); -+ if (err) { -+ printk(KERN_ERR "Unable to write TPS65910_REG_VRTC reg\n"); -+ return -EIO; -+ } -+ -+ /* Disable SmartReflex control */ -+ val &= 0; -+ val &= ~TPS65910_RTC_PWDNN; -+ val |= (TPS65910_CK32K_CTRL | TPS65910_SR_CTL_I2C_SEL); -+ -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_DEVCTRL); -+ if (err) { -+ printk(KERN_ERR "Unabale to write TPS65910_REG_DEVCTRL reg\n"); -+ return -EIO; -+ } -+ -+ /* initilize all ISR work as NULL, specific driver will -+ * assign function(s) later. -+ */ -+ for (i = 0; i < TPS65910_MAX_IRQS; i++) -+ pdata->handlers[i] = NULL; -+ -+ return 0; -+} -+ -+struct tps65910_platform_data am3517_crane_tps65910_data = { -+ .irq_num = (unsigned)TPS65910_HOST_IRQ, -+ .gpio = NULL, -+ .vio = &am3517_crane_regulator_vio, -+ .vdd1 = &am3517_crane_regulator_vdd1, -+ .vdd2 = &am3517_crane_regulator_vdd2, -+ .vdd3 = NULL, -+ .vdig1 = NULL, -+ .vdig2 = NULL, -+ .vaux33 = NULL, -+ .vmmc = &am3517_crane_regulator_vmmc, -+ .vaux1 = &am3517_crane_regulator_vaux1, -+ .vaux2 = &am3517_crane_regulator_vaux2, -+ .vdac = &am3517_crane_regulator_vdac, -+ .vpll = &am3517_crane_regulator_vpll, -+ .board_tps65910_config = am3517_crane_tps65910_config, -+}; -+ -+static struct i2c_board_info __initdata am3517crane_i2c1_boardinfo[] = { -+ { -+ I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID0), -+ .flags = I2C_CLIENT_WAKE, -+ .irq = TPS65910_HOST_IRQ, -+ .platform_data = &am3517_crane_tps65910_data, -+ }, -+}; -+ -+ -+static int __init am3517_crane_i2c_init(void) -+{ -+ omap_register_i2c_bus(1, 400, am3517crane_i2c1_boardinfo, -+ ARRAY_SIZE(am3517crane_i2c1_boardinfo)); -+ omap_register_i2c_bus(2, 400, NULL, 0); -+ omap_register_i2c_bus(3, 400, NULL, 0); -+ -+ return 0; -+} -+ -+/* -+ * HECC information -+ */ -+static struct resource am3517_hecc_resources[] = { -+ { -+ .start = AM35XX_IPSS_HECC_BASE, -+ .end = AM35XX_IPSS_HECC_BASE + 0x3FFF, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = INT_35XX_HECC0_IRQ, -+ .end = INT_35XX_HECC0_IRQ, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device am3517_hecc_device = { -+ .name = "ti_hecc", -+ .id = 1, -+ .num_resources = ARRAY_SIZE(am3517_hecc_resources), -+ .resource = am3517_hecc_resources, -+}; -+ -+static struct ti_hecc_platform_data am3517_crane_hecc_pdata = { -+ .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET, -+ .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET, -+ .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET, -+ .mbx_offset = AM35XX_HECC_MBOX_OFFSET, -+ .int_line = AM35XX_HECC_INT_LINE, -+ .version = AM35XX_HECC_VERSION, -+}; -+ -+static void am3517_crane_hecc_init(struct ti_hecc_platform_data *pdata) -+{ -+ am3517_hecc_device.dev.platform_data = pdata; -+ platform_device_register(&am3517_hecc_device); -+} -+ -+ -+/* -+ * Board initialization -+ */ -+static struct omap_board_config_kernel am3517_crane_config[] __initdata = { -+}; -+ -+static struct platform_device *am3517_crane_devices[] __initdata = { -+ &dm644x_ccdc_dev, -+ &am3517_crane_dss_device, -+}; -+ -+static void __init am3517_crane_init_irq(void) -+{ -+ omap_board_config = am3517_crane_config; -+ omap_board_config_size = ARRAY_SIZE(am3517_crane_config); -+ -+ omap2_init_common_hw(NULL, NULL, NULL, NULL, NULL); -+ omap_init_irq(); -+ omap_gpio_init(); -+} -+ -+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { -+ .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, -+ .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -+ -+ .phy_reset = true, -+ .reset_gpio_port[0] = 38, -+ .reset_gpio_port[1] = -EINVAL, -+ .reset_gpio_port[2] = -EINVAL -+}; -+ -+#ifdef CONFIG_OMAP_MUX -+static struct omap_board_mux board_mux[] __initdata = { -+ /* USB OTG DRVVBUS offset = 0x212 */ -+ OMAP3_MUX(CHASSIS_DMAREQ3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), -+ OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN), -+ { .reg_offset = OMAP_MUX_TERMINATOR }, -+}; -+#else -+#define board_mux NULL -+#endif -+ -+static struct am3517_hsmmc_info mmc[] = { -+ { -+ .mmc = 1, -+ .wires = 8, -+ .gpio_cd = 41, -+ .gpio_wp = 40, -+ }, -+ {} /* Terminator */ -+}; -+ -+static void __init am3517_crane_init(void) -+{ -+ -+ am3517_crane_i2c_init(); -+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ platform_add_devices(am3517_crane_devices, -+ ARRAY_SIZE(am3517_crane_devices)); -+ -+ omap_serial_init(); -+ am3517crane_flash_init(); -+ usb_musb_init(); -+ -+ /* Configure GPIO for EHCI port */ -+ omap_mux_init_gpio(35, OMAP_PIN_OUTPUT); -+ gpio_request(35, "usb_ehci_enable"); -+ gpio_direction_output(35, 1); -+ gpio_set_value(35, 1); -+ omap_mux_init_gpio(38, OMAP_PIN_OUTPUT); -+ usb_ehci_init(&ehci_pdata); -+ -+ /* DSS */ -+ am3517_crane_display_init(); -+ -+ /*Ethernet*/ -+ am3517_crane_ethernet_init(&am3517_crane_emac_pdata); -+ am3517_crane_hecc_init(&am3517_crane_hecc_pdata); -+ -+ /* MMC init function */ -+ am3517_mmc_init(mmc); -+ -+} -+ -+static void __init am3517_crane_map_io(void) -+{ -+ omap2_set_globals_343x(); -+ omap2_map_common_io(); -+} -+ -+MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") -+ .phys_io = 0x48000000, -+ .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, -+ .boot_params = 0x80000100, -+ .map_io = am3517_crane_map_io, -+ .init_irq = am3517_crane_init_irq, -+ .init_machine = am3517_crane_init, -+ .timer = &omap_timer, -+MACHINE_END -diff --git a/arch/arm/mach-omap2/mmc-am3517crane.c b/arch/arm/mach-omap2/mmc-am3517crane.c -new file mode 100644 -index 0000000..80ad8ae ---- /dev/null -+++ b/arch/arm/mach-omap2/mmc-am3517crane.c -@@ -0,0 +1,267 @@ -+/* -+ * linux/arch/arm/mach-omap2/mmc-crane.c -+ * -+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd -+ * Author: Srinath.R -+ * -+ * Based on linux/arch/arm/mach-omap2/mmc-am3517evm.c -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mmc-am3517crane.h" -+ -+#define LDO_CLR 0x00 -+#define VSEL_S2_CLR 0x40 -+ -+#define VMMC1_DEV_GRP 0x27 -+#define VMMC1_CLR 0x00 -+#define VMMC1_315V 0x03 -+#define VMMC1_300V 0x02 -+#define VMMC1_285V 0x01 -+#define VMMC1_185V 0x00 -+#define VMMC1_DEDICATED 0x2A -+ -+#define VMMC2_DEV_GRP 0x2B -+#define VMMC2_CLR 0x40 -+#define VMMC2_315V 0x0c -+#define VMMC2_300V 0x0b -+#define VMMC2_285V 0x0a -+#define VMMC2_260V 0x08 -+#define VMMC2_185V 0x06 -+#define VMMC2_DEDICATED 0x2E -+ -+#define VMMC_DEV_GRP_P1 0x20 -+ -+#define HSMMC_NAME_LEN 9 -+ -+#if defined(CONFIG_REGULATOR) || \ -+ (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ -+ defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)) -+ -+/* -+ * MMC definitions -+ * -+ */ -+static struct mmc_controller { -+ struct omap_mmc_platform_data *mmc; -+ u8 vmmc_dev_grp; -+ u8 vmmc_dedicated; -+ char name[HSMMC_NAME_LEN]; -+} hsmmc[] = { -+ { -+ .vmmc_dev_grp = VMMC1_DEV_GRP, -+ .vmmc_dedicated = VMMC1_DEDICATED, -+ }, -+ { -+ .vmmc_dev_grp = VMMC2_DEV_GRP, -+ .vmmc_dedicated = VMMC2_DEDICATED, -+ }, -+}; -+ -+static int mmc_card_detect(int irq) -+{ -+ unsigned i; -+ -+ for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { -+ struct omap_mmc_platform_data *mmc; -+ -+ mmc = hsmmc[i].mmc; -+ if (!mmc) -+ continue; -+ if (irq != mmc->slots[0].card_detect_irq) -+ continue; -+ -+ /* NOTE: assumes card detect signal is active-low */ -+ return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); -+ } -+ return -ENOSYS; -+} -+ -+static int mmc_get_ro(struct device *dev, int slot) -+{ -+ struct omap_mmc_platform_data *mmc = dev->platform_data; -+ -+ /* NOTE: assumes write protect signal is active-high */ -+ return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); -+} -+ -+/* -+ * MMC Slot Initialization. -+ */ -+static int mmc_late_init(struct device *dev) -+{ -+ struct omap_mmc_platform_data *mmc = dev->platform_data; -+ int ret = 0; -+ int i; -+ -+ ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd"); -+ if (ret) -+ goto done; -+ ret = gpio_direction_input(mmc->slots[0].switch_pin); -+ if (ret) -+ goto err; -+ -+ for (i = 0; i < ARRAY_SIZE(hsmmc); i++) { -+ if (hsmmc[i].name == mmc->slots[0].name) { -+ hsmmc[i].mmc = mmc; -+ break; -+ } -+ } -+ -+ return 0; -+ -+err: -+ gpio_free(mmc->slots[0].switch_pin); -+done: -+ mmc->slots[0].card_detect_irq = 0; -+ mmc->slots[0].card_detect = NULL; -+ -+ dev_err(dev, "err %d configuring card detect\n", ret); -+ return ret; -+} -+ -+static void mmc_cleanup(struct device *dev) -+{ -+ struct omap_mmc_platform_data *mmc = dev->platform_data; -+ -+ gpio_free(mmc->slots[0].switch_pin); -+} -+ -+#ifdef CONFIG_PM -+ -+static int mmc_suspend(struct device *dev, int slot) -+{ -+ struct omap_mmc_platform_data *mmc = dev->platform_data; -+ -+ disable_irq(mmc->slots[0].card_detect_irq); -+ return 0; -+} -+ -+static int mmc_resume(struct device *dev, int slot) -+{ -+ struct omap_mmc_platform_data *mmc = dev->platform_data; -+ -+ enable_irq(mmc->slots[0].card_detect_irq); -+ return 0; -+} -+ -+#else -+#define mmc_suspend NULL -+#define mmc_resume NULL -+#endif -+ -+/* -+ * the MMC power setting function -+ */ -+ -+static int mmc1_set_power(struct device *dev, int slot, int power_on, -+ int vdd) -+{ -+ return 0; -+} -+ -+static int mmc2_set_power(struct device *dev, int slot, int power_on, int vdd) -+{ -+ return 0; -+} -+ -+static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; -+ -+void __init am3517_mmc_init(struct am3517_hsmmc_info *controllers) -+{ -+ struct am3517_hsmmc_info *c; -+ int nr_hsmmc = ARRAY_SIZE(hsmmc_data); -+ -+ for (c = controllers; c->mmc; c++) { -+ struct mmc_controller *mmc_control = hsmmc + c->mmc - 1; -+ struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; -+ -+ if (!c->mmc || c->mmc > nr_hsmmc) { -+ pr_debug("MMC%d: no such controller\n", c->mmc); -+ continue; -+ } -+ if (mmc) { -+ pr_debug("MMC%d: already configured\n", c->mmc); -+ continue; -+ } -+ -+ mmc = kzalloc(sizeof(struct omap_mmc_platform_data), -+ GFP_KERNEL); -+ if (!mmc) { -+ pr_err("Cannot allocate memory for mmc device!\n"); -+ return; -+ } -+ -+ sprintf(mmc_control->name, "mmc%islot%i", c->mmc, 1); -+ mmc->slots[0].name = mmc_control->name; -+ mmc->nr_slots = 1; -+ mmc->slots[0].ocr_mask = MMC_VDD_165_195 | -+ MMC_VDD_26_27 | MMC_VDD_27_28 | -+ MMC_VDD_29_30 | -+ MMC_VDD_30_31 | MMC_VDD_31_32; -+ mmc->slots[0].wires = c->wires; -+ mmc->slots[0].internal_clock = !c->ext_clock; -+ mmc->dma_mask = 0xffffffff; -+ -+ if (1) { -+ mmc->init = mmc_late_init; -+ mmc->cleanup = mmc_cleanup; -+ mmc->suspend = mmc_suspend; -+ mmc->resume = mmc_resume; -+ -+ mmc->slots[0].switch_pin = c->gpio_cd; -+ mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); -+ mmc->slots[0].card_detect = mmc_card_detect; -+ } else -+ mmc->slots[0].switch_pin = -EINVAL; -+ -+ /* write protect normally uses an OMAP gpio */ -+ if (gpio_is_valid(c->gpio_wp)) { -+ gpio_request(c->gpio_wp, "mmc_wp"); -+ gpio_direction_input(c->gpio_wp); -+ -+ mmc->slots[0].gpio_wp = c->gpio_wp; -+ mmc->slots[0].get_ro = mmc_get_ro; -+ } else -+ mmc->slots[0].gpio_wp = -EINVAL; -+ -+ /* NOTE: we assume OMAP's MMC1 and MMC2 use -+ * the TWL4030's VMMC1 and VMMC2, respectively; -+ * and that OMAP's MMC3 isn't used. -+ */ -+ -+ switch (c->mmc) { -+ case 1: -+ mmc->slots[0].set_power = mmc1_set_power; -+ break; -+ case 2: -+ mmc->slots[0].set_power = mmc2_set_power; -+ break; -+ default: -+ pr_err("MMC%d configuration not supported!\n", c->mmc); -+ continue; -+ } -+ hsmmc_data[c->mmc - 1] = mmc; -+ } -+ -+ omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); -+} -+#else -+inline void am3517_mmc_init(struct craneboard_hsmmc_info *info) -+{ -+} -+#endif -diff --git a/arch/arm/mach-omap2/mmc-am3517crane.h b/arch/arm/mach-omap2/mmc-am3517crane.h -new file mode 100644 -index 0000000..97fd872 ---- /dev/null -+++ b/arch/arm/mach-omap2/mmc-am3517crane.h -@@ -0,0 +1,22 @@ -+/* -+ * MMC definitions for craneboard AM3517/05 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+struct am3517_hsmmc_info { -+ u8 mmc; /* controller 1/2/3 */ -+ u8 wires; /* 1/4/8 wires */ -+ bool transceiver; /* MMC-2 option */ -+ bool ext_clock; /* use external pin for input clock */ -+ bool cover_only; /* No card detect - just cover switch */ -+ int gpio_cd; /* or -EINVAL */ -+ int gpio_wp; /* or -EINVAL */ -+ char *name; /* or NULL for default */ -+ struct device *dev; /* returned: pointer to mmc adapter */ -+ int ocr_mask; /* temporary HACK */ -+}; -+ -+void am3517_mmc_init(struct am3517_hsmmc_info *); -diff --git a/arch/arm/mach-omap2/tps65910-pmic.c b/arch/arm/mach-omap2/tps65910-pmic.c -new file mode 100644 -index 0000000..b17d662 ---- /dev/null -+++ b/arch/arm/mach-omap2/tps65910-pmic.c -@@ -0,0 +1,195 @@ -+/* -+ * tps65910-pmic.c -+ * -+ * Common regulator supplies and init data structs for TPS65910 -+ * PMIC for AM35xx based EVMs. They can be used in various board-evm -+ * files for Am35xx based platforms using TPS65910. -+ * -+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd -+ * -+ * Based on arch/arm/mach-omap2/twl4030-pmic.c -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, -+ * whether express or implied; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+/* Power domain maping for TPS65910 and AM35XX -+ -+ 1.8V -+ VIO -----------> VDDS -+ -+ 1.8V -+ VAUX1 ---------> VDDS_SRAM_CORE_BG -+ | -+ -------> VDDS_SRAM_MPU -+ | -+ -------> VDDOSC -+ -+ 3.3V -+ VDD2 ----------> VDDSHV -+ -+ 1.2V -+ VDD1 ----------> VDD_CORE -+ -+ 1.8V -+ VPLL ----------> VDDS_DPLL_PRE_CORE -+ | -+ -------> VDDSPLL_MPU_USBHOST -+ -+ 1.8V -+ VDAC ----------> VDDA_DAC -+ -+ 1.8V -+ VAUX2 ----------> VDDA1P8V_USBPHY -+ -+ 3.3V -+ VMMC ----------> VDDA3P3V_USBPHY -+ -+*/ -+#include -+ -+/* VIO */ -+struct regulator_consumer_supply tps65910_vio_supply = { -+ .supply = "vdds", -+}; -+ -+ -+/* VAUX1 */ -+struct regulator_consumer_supply tps65910_vaux1_supply[] = { -+ { -+ .supply = "vdds_sram_core_bg", -+ }, -+ { -+ .supply = "vdds_sram_mpu", -+ }, -+ { -+ .supply = "vddosc", -+ }, -+}; -+ -+/* VPLL */ -+struct regulator_consumer_supply tps65910_vpll_supply[] = { -+ { -+ .supply = "vdds_dpll_pre_core", -+ }, -+ { -+ .supply = "vddspll_mpu_usbhost", -+ }, -+ -+}; -+ -+/* VDAC */ -+struct regulator_consumer_supply tps65910_vdac_supply = { -+ .supply = "vdda_dac", -+}; -+ -+/* VAUX2 */ -+struct regulator_consumer_supply tps65910_vaux2_supply = { -+ .supply = "vdda1p8v_usbphy", -+}; -+ -+ -+/* VMMC */ -+struct regulator_consumer_supply tps65910_vmmc_supply = { -+ .supply = "vdda3p3v_usbphy", -+}; -+ -+ -+/* Regulator initialization data */ -+ -+/* VIO LDO */ -+struct regulator_init_data vio_data = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(tps65910_vaux1_supply), -+ .consumer_supplies = &tps65910_vaux1_supply, -+}; -+ -+ -+ -+/* VAUX1 LDO */ -+struct regulator_init_data vaux1_data = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 2850000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = false, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(tps65910_vaux1_supply), -+ .consumer_supplies = &tps65910_vaux1_supply, -+}; -+ -+/* VAUX2 LDO */ -+struct regulator_init_data vaux2_data = { -+ .constraints = { -+ .min_uV = 3300000, -+ .max_uV = 3300000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = true, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(tps65910_vaux2_supply), -+ .consumer_supplies = &tps65910_vaux2_supply, -+ -+}; -+ -+/* VMMC LDO */ -+struct regulator_init_data vmmc_data = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 3300000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = false, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(tps65910_vmmc_supply), -+ .consumer_supplies = &tps65910_vmmc_supply, -+ -+}; -+ -+/* VPLL LDO */ -+struct regulator_init_data vpll_data = { -+ .constraints = { -+ .min_uV = 100000, -+ .max_uV = 2500000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = false, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(tps65910_vpll_supply), -+ .consumer_supplies = &tps65910_vpll_supply, -+}; -+ -+/* VDAC LDO */ -+struct regulator_init_data vdac_data = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 2850000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ .always_on = true, -+ .apply_uV = false, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(tps65910_vdac_supply), -+ .consumer_supplies = &tps65910_vdac_supply, -+ -+}; -+ -+ -diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types -index 07b976d..2c9a874 100644 ---- a/arch/arm/tools/mach-types -+++ b/arch/arm/tools/mach-types -@@ -2536,3 +2536,4 @@ c3ax03 MACH_C3AX03 C3AX03 2549 - mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 - esyx MACH_ESYX ESYX 2551 - bulldog MACH_BULLDOG BULLDOG 2553 -+craneboard MACH_CRANEBOARD CRANEBOARD 2932 -diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile -index 270b6d7..b7ae0c4 100644 ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -20,3 +20,4 @@ obj-$(CONFIG_GPIO_CS5535) += cs5535-gpio.o - obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o - obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o - obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o -+ -diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c -index bbea8a0..48273d7 100644 ---- a/drivers/i2c/busses/i2c-omap.c -+++ b/drivers/i2c/busses/i2c-omap.c -@@ -801,7 +801,7 @@ complete: - "data to send\n"); - break; - } -- -+#ifndef CONFIG_CRANEBOARD - /* - * OMAP3430 Errata 1.153: When an XRDY/XDR - * is hit, wait for XUDF before writing data -@@ -821,6 +821,7 @@ complete: - stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); - } - } -+#endif - - omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); - } -diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index 8782978..306b346 100644 ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -129,12 +129,25 @@ config TWL4030_POWER - and load scripts controling which resources are switched off/on - or reset when a sleep, wakeup or warm reset event occurs. - -+config TPS65910_CORE -+ bool "Texas Instruments TPS65910 Support" -+ depends on I2C=y && GENERIC_HARDIRQS -+ help -+ Say yes here if you have TPS65910 family chip on your board. -+ This core driver provides register access and registers devices -+ for the various functions so that function-specific drivers can -+ bind to them. -+ -+ These multi-function chips are found on many AM35xx boards, -+ providing power management, RTC, GPIO features. -+ - config TWL4030_CODEC - bool - depends on TWL4030_CORE - select MFD_CORE - default n - -+ - config MFD_TMIO - bool - default n -diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile -index ca2f2c4..85dc3a7 100644 ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -30,6 +30,8 @@ obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o - obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o - obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o - -+obj-$(CONFIG_TPS65910_CORE) += tps65910-core.o -+ - obj-$(CONFIG_MFD_MC13783) += mc13783-core.o - - obj-$(CONFIG_MFD_CORE) += mfd-core.o -@@ -55,4 +57,4 @@ obj-$(CONFIG_AB3100_CORE) += ab3100-core.o - obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o - obj-$(CONFIG_AB4500_CORE) += ab4500-core.o - obj-$(CONFIG_MFD_88PM8607) += 88pm8607.o --obj-$(CONFIG_PMIC_ADP5520) += adp5520.o -\ No newline at end of file -+obj-$(CONFIG_PMIC_ADP5520) += adp5520.o -diff --git a/drivers/mfd/tps65910-core.c b/drivers/mfd/tps65910-core.c -new file mode 100644 -index 0000000..9ffccc7 ---- /dev/null -+++ b/drivers/mfd/tps65910-core.c -@@ -0,0 +1,741 @@ -+/* -+ * tps65910-core.c -- Multifunction core driver for TPS65910x chips -+ * -+ * Copyright (C) 2010 Mistral solutions Pvt Ltd -+ * -+ * Based on twl-core.c -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -+#include -+#endif -+ -+#define DRIVER_NAME "tps65910" -+ -+#if defined(CONFIG_GPIO_TPS65910) -+#define tps65910_has_gpio() true -+#else -+#define tps65910_has_gpio() false -+#endif -+ -+#if defined(CONFIG_REGULATOR_TPS65910) -+#define tps65910_has_regulator() true -+#else -+#define tps65910_has_regulator() false -+#endif -+ -+#if defined(CONFIG_RTC_DRV_TPS65910) -+#define tps65910_has_rtc() true -+#else -+#define tps65910_has_rtc() false -+#endif -+ -+#define TPS65910_GENERAL 0 -+#define TPS65910_SMARTREFLEX 1 -+ -+ -+struct tps65910_platform_data *the_tps65910; -+ -+enum tps65910x_model { -+ TPS65910, /* TI processors OMAP3 family */ -+ TPS659101, /* Samsung - S5PV210, S5PC1xx */ -+ TPS659102, /* Samsung - S3C64xx */ -+ TPS659103, /* Reserved */ -+ TPS659104, /* Reserved */ -+ TPS659105, /* TI processors - DM643x, DM644x */ -+ TPS659106, /* Reserved */ -+ TPS659107, /* Reserved */ -+ TPS659108, /* Reserved */ -+ TPS659109, /* Freescale - i.MX51 */ -+ -+}; -+ -+static bool inuse; -+static struct work_struct core_work; -+static struct mutex work_lock; -+ -+/* Structure for each TPS65910 Slave */ -+struct tps65910_client { -+ struct i2c_client *client; -+ u8 address; -+ /* max numb of i2c_msg required for read = 2 */ -+ struct i2c_msg xfer_msg[2]; -+ /* To lock access to xfer_msg */ -+ struct mutex xfer_lock; -+}; -+static struct tps65910_client tps65910_modules[TPS65910_NUM_SLAVES]; -+ -+/* bbch = Back-up battery charger control register */ -+int tps65910_enable_bbch(u8 voltage) -+{ -+ -+ u8 val = 0; -+ int err; -+ -+ if (voltage == TPS65910_BBSEL_3P0 || voltage == TPS65910_BBSEL_2P52 || -+ voltage == TPS65910_BBSEL_3P15 || -+ voltage == TPS65910_BBSEL_VBAT) { -+ val = (voltage | TPS65910_BBCHEN); -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_BBCH); -+ if (err) { -+ printk(KERN_ERR "Unable write TPS65910_REG_BBCH reg\n"); -+ return -EIO; -+ } -+ } else { -+ printk(KERN_ERR"Invalid argumnet for %s \n", __func__); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(tps65910_enable_bbch); -+ -+int tps65910_disable_bbch(void) -+{ -+ -+ u8 val = 0; -+ int err; -+ -+ err = tps65910_i2c_read_u8(TPS65910_I2C_ID0, &val, TPS65910_REG_BBCH); -+ -+ if (!err) { -+ val &= ~TPS65910_BBCHEN; -+ -+ err = tps65910_i2c_write_u8(TPS65910_I2C_ID0, val, -+ TPS65910_REG_BBCH); -+ if (err) { -+ printk(KERN_ERR "Unable write TPS65910_REG_BBCH \ -+ reg\n"); -+ return -EIO; -+ } -+ } else { -+ printk(KERN_ERR "Unable to read TPS65910_REG_BBCH reg\n"); -+ return -EIO; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(tps65910_disable_bbch); -+ -+int tps65910_i2c_read(u8 slave_addr, u8 *value, u8 reg, unsigned num_bytes) -+{ -+ u8 val; -+ u32 ret; -+ struct tps65910_client *tps65910; -+ struct i2c_msg *msg; -+ -+ switch (slave_addr) { -+ case TPS65910_I2C_ID0: -+ tps65910 = &tps65910_modules[0]; -+ tps65910->address = TPS65910_I2C_ID0; -+ break; -+ case TPS65910_I2C_ID1: -+ tps65910 = &tps65910_modules[1]; -+ tps65910->address = TPS65910_I2C_ID1; -+ break; -+ default: -+ printk(KERN_ERR "Invalid Slave address for TPS65910\n"); -+ return -ENODEV; -+ } -+ mutex_lock(&tps65910->xfer_lock); -+ /* [MSG1] fill the register address data */ -+ msg = &tps65910->xfer_msg[0]; -+ msg->addr = tps65910->address; -+ msg->len = 1; -+ msg->flags = 0; -+ val = reg; -+ msg->buf = &val; -+ /* [MSG2] fill the data rx buffer */ -+ msg = &tps65910->xfer_msg[1]; -+ msg->addr = tps65910->address; -+ msg->flags = I2C_M_RD; /* Read the register value */ -+ msg->len = num_bytes; /* only n bytes */ -+ msg->buf = value; -+ -+ ret = i2c_transfer(tps65910->client->adapter, tps65910->xfer_msg, 2); -+ mutex_unlock(&tps65910->xfer_lock); -+ -+ /* i2c_transfer returns number of messages transferred */ -+ if (ret != 2) { -+ pr_err("%s: i2c_read failed to transfer all messages\n", -+ "TPS65910C"); -+ return -EIO; -+ } else { -+ return 0; -+ } -+} -+EXPORT_SYMBOL(tps65910_i2c_read); -+ -+ -+int tps65910_i2c_write(u8 slave_addr, u8 *value, u8 reg, unsigned num_bytes) -+{ -+ int ret; -+ struct tps65910_client *tps65910; -+ struct i2c_msg *msg; -+ u8 write_buf[66]; /* Max 65 Regs + offset*/ -+ -+ switch (slave_addr) { -+ case TPS65910_I2C_ID0: -+ tps65910 = &tps65910_modules[0]; -+ tps65910->address = TPS65910_I2C_ID0; -+ break; -+ case TPS65910_I2C_ID1: -+ tps65910 = &tps65910_modules[1]; -+ tps65910->address = TPS65910_I2C_ID1; -+ break; -+ default: -+ printk(KERN_ERR "Invalid Slave address for TPS65910\n"); -+ return -ENODEV; -+ } -+ -+ mutex_lock(&tps65910->xfer_lock); -+ /* [MSG1]: fill the register address data fill the data Tx buffer */ -+ msg = &tps65910->xfer_msg[0]; -+ msg->addr = tps65910->address; -+ msg->len = num_bytes + 1; -+ msg->flags = 0; -+ write_buf[0] = reg; -+ memcpy(&write_buf[1], value, num_bytes); -+ msg->buf = &write_buf[0]; -+ ret = i2c_transfer(tps65910->client->adapter, tps65910->xfer_msg, 1); -+ mutex_unlock(&tps65910->xfer_lock); -+ -+ /* i2c_transfer returns number of messages transferred */ -+ if (ret != 1) { -+ pr_err("%s: i2c_write failed to transfer all messages\n", -+ __func__); -+ return -EIO; -+ } else { -+ return 0; -+ } -+} -+EXPORT_SYMBOL(tps65910_i2c_write); -+ -+int tps65910_i2c_read_u8(u8 mod_no, u8 *value, u8 reg) -+{ -+ struct tps65910_client *tps65910; -+ -+ switch (mod_no) { -+ case TPS65910_I2C_ID0: -+ tps65910 = &tps65910_modules[0]; -+ tps65910->address = TPS65910_I2C_ID0; -+ break; -+ case TPS65910_I2C_ID1: -+ tps65910 = &tps65910_modules[1]; -+ tps65910->address = TPS65910_I2C_ID1; -+ break; -+ default: -+ printk(KERN_ERR "Invalid Slave address for TPS65910\n"); -+ return -ENODEV; -+ } -+ -+ (*value) = i2c_smbus_read_byte_data(tps65910->client, reg); -+ mdelay(10); -+ if (*value < 0) -+ return -EIO; -+ else -+ return 0; -+} -+EXPORT_SYMBOL(tps65910_i2c_read_u8); -+ -+int tps65910_i2c_write_u8(u8 slave_addr, u8 value, u8 reg) -+{ -+ int ret; -+ struct tps65910_client *tps65910; -+ -+ switch (slave_addr) { -+ case TPS65910_I2C_ID0: -+ tps65910 = &tps65910_modules[0]; -+ tps65910->address = TPS65910_I2C_ID0; -+ break; -+ case TPS65910_I2C_ID1: -+ tps65910 = &tps65910_modules[1]; -+ tps65910->address = TPS65910_I2C_ID1; -+ break; -+ default: -+ printk(KERN_ERR "Invalid Slave address for TPS65910\n"); -+ return -ENODEV; -+ } -+ ret = i2c_smbus_write_byte_data(tps65910->client, reg, value); -+ if (ret < 0) -+ return -EIO; -+ else -+ return 0; -+} -+EXPORT_SYMBOL(tps65910_i2c_write_u8); -+ -+ -+int tps65910_enable_irq(int irq) -+{ -+ u8 mask = 0x00; -+ -+ if (irq > 7) { -+ irq -= 8; -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, -+ &mask, TPS65910_REG_INT_MSK2); -+ mask &= ~(1 << irq); -+ return tps65910_i2c_write_u8(TPS65910_I2C_ID0, -+ mask, TPS65910_REG_INT_MSK2); -+ } else { -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, -+ &mask, TPS65910_REG_INT_MSK); -+ mask &= ~(1 << irq); -+ return tps65910_i2c_write_u8(TPS65910_I2C_ID0, -+ mask, TPS65910_REG_INT_MSK); -+ } -+} -+EXPORT_SYMBOL(tps65910_enable_irq); -+ -+int tps65910_disable_irq(int irq) -+{ -+ u8 mask = 0x00; -+ -+ if (irq > 7) { -+ irq -= 8; -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, -+ &mask, TPS65910_REG_INT_MSK2); -+ mask |= (1 << irq); -+ return tps65910_i2c_write_u8(TPS65910_I2C_ID0, -+ mask, TPS65910_REG_INT_MSK2); -+ } else { -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, -+ &mask, TPS65910_REG_INT_MSK); -+ mask = (1 << irq); -+ return tps65910_i2c_write_u8(TPS65910_I2C_ID0, -+ mask, TPS65910_REG_INT_MSK); -+ } -+} -+EXPORT_SYMBOL(tps65910_disable_irq); -+ -+int tps65910_add_irq_work(int irq, -+ void (*handler)(void *data)) -+{ -+ int ret = 0; -+ the_tps65910->handlers[irq] = handler; -+ ret = tps65910_enable_irq(irq); -+ -+ return ret; -+} -+EXPORT_SYMBOL(tps65910_add_irq_work); -+ -+int tps65910_remove_irq_work(int irq) -+{ -+ int ret = 0; -+ ret = tps65910_disable_irq(irq); -+ the_tps65910->handlers[irq] = NULL; -+ return ret; -+} -+EXPORT_SYMBOL(tps65910_remove_irq_work); -+ -+static void tps65910_core_work(struct work_struct *work) -+{ -+ /* Read the status register and take action */ -+ u8 status = 0x00; -+ u8 status2 = 0x00; -+ u8 mask = 0x00; -+ u8 mask2 = 0x00; -+ u16 isr = 0x00; -+ u16 irq = 0; -+ void (*handler)(void *data) = NULL; -+ -+ mutex_lock(&work_lock); -+ while (1) { -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, &status2, -+ TPS65910_REG_INT_STS2); -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, &mask2, -+ TPS65910_REG_INT_MSK2); -+ status2 &= (~mask2); -+ isr = (status2 << 8); -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, &status, -+ TPS65910_REG_INT_STS); -+ tps65910_i2c_read_u8(TPS65910_I2C_ID0, &mask, -+ TPS65910_REG_INT_MSK); -+ status &= ~(mask); -+ isr |= status; -+ if (!isr) -+ break; -+ -+ while (isr) { -+ irq = fls(isr) - 1; -+ isr &= ~(1 << irq); -+ handler = the_tps65910->handlers[irq]; -+ if (handler) -+ handler(the_tps65910); -+ } -+ } -+ enable_irq(the_tps65910->irq_num); -+ mutex_unlock(&work_lock); -+} -+ -+ -+static irqreturn_t tps65910_isr(int irq, void *data) -+{ -+ -+#ifdef CONFIG_LOCKDEP -+ /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which -+ * we don't want and can't tolerate. Although it might be -+ * friendlier not to borrow this thread context... -+ */ -+ local_irq_enable(); -+#endif -+ disable_irq_nosync(irq); -+ (void) schedule_work(&core_work); -+ return IRQ_HANDLED; -+} -+ -+ -+static struct device *add_numbered_child(unsigned chip, const char *name, -+ int num, void *pdata, unsigned pdata_len, bool can_wakeup, int irq) -+{ -+ -+ struct platform_device *pdev; -+ struct tps65910_client *tps65910 = &tps65910_modules[chip]; -+ int status; -+ -+ pdev = platform_device_alloc(name, num); -+ if (!pdev) { -+ dev_dbg(&tps65910->client->dev, "can't alloc dev\n"); -+ status = -ENOMEM; -+ goto err; -+ } -+ device_init_wakeup(&pdev->dev, can_wakeup); -+ pdev->dev.parent = &tps65910->client->dev; -+ -+ if (pdata) { -+ status = platform_device_add_data(pdev, pdata, pdata_len); -+ if (status < 0) { -+ dev_dbg(&pdev->dev, "can't add platform_data\n"); -+ goto err; -+ } -+ } -+ status = platform_device_add(pdev); -+ -+err: -+ if (status < 0) { -+ platform_device_put(pdev); -+ dev_err(&tps65910->client->dev, "can't add %s dev\n", name); -+ return ERR_PTR(status); -+ } -+ return &pdev->dev; -+ -+} -+ -+static inline struct device *add_child(unsigned chip, const char *name, -+ void *pdata, unsigned pdata_len, -+ bool can_wakeup, int irq) -+{ -+ return add_numbered_child(chip, name, -1, pdata, pdata_len, -+ can_wakeup, irq); -+} -+ static -+struct device *add_regulator_linked(int num, struct regulator_init_data *pdata, -+ struct regulator_consumer_supply *consumers, -+ unsigned num_consumers) -+{ -+ /* regulator framework demands init_data */ -+ if (!pdata) -+ return NULL; -+ -+ if (consumers) { -+ pdata->consumer_supplies = consumers; -+ pdata->num_consumer_supplies = num_consumers; -+ } -+ return add_numbered_child(TPS65910_GENERAL, "tps65910_regulator", num, -+ pdata, sizeof(*pdata), false, TPS65910_HOST_IRQ); -+} -+ -+ static struct device * -+add_regulator(int num, struct regulator_init_data *pdata) -+{ -+ return add_regulator_linked(num, pdata, NULL, 0); -+} -+ -+ static int -+add_children(struct tps65910_platform_data *pdata, unsigned long features) -+{ -+ int status; -+ struct device *child; -+ -+ struct platform_device *pdev = NULL; -+ -+ if (tps65910_has_gpio() && (pdata->gpio != NULL)) { -+ -+ pdev = platform_device_alloc("tps65910_gpio", -1); -+ if (!pdev) { -+ status = -ENOMEM; -+ goto err; -+ } -+ pdev->dev.parent = &tps65910_modules[0].client->dev; -+ device_init_wakeup(&pdev->dev, 0); -+ if (pdata) { -+ status = platform_device_add_data(pdev, pdata, -+ sizeof(*pdata)); -+ if (status < 0) { -+ dev_dbg(&pdev->dev, -+ "can't add platform_data\n"); -+ goto err; -+ } -+ } -+ } -+ if (tps65910_has_rtc()) { -+ child = add_child(TPS65910_GENERAL, "tps65910_rtc", -+ NULL, 0, true, pdata->irq_num); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ } -+ -+ if (tps65910_has_regulator()) { -+ -+ child = add_regulator(TPS65910_VIO, pdata->vio); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VDD1, pdata->vdd1); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VDD2, pdata->vdd2); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VDD3, pdata->vdd3); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VDIG1, pdata->vdig1); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VDIG2, pdata->vdig2); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VAUX33, pdata->vaux33); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VMMC, pdata->vmmc); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VAUX1, pdata->vaux1); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VAUX2, pdata->vaux2); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VDAC, pdata->vdac); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ -+ child = add_regulator(TPS65910_VPLL, pdata->vpll); -+ if (IS_ERR(child)) -+ return PTR_ERR(child); -+ } -+ return 0; -+ -+err: -+ return -1; -+ -+} -+ -+static int tps65910_remove(struct i2c_client *client) -+{ -+ unsigned i; -+ -+ for (i = 0; i < TPS65910_NUM_SLAVES; i++) { -+ -+ struct tps65910_client *tps65910 = &tps65910_modules[i]; -+ -+ if (tps65910->client && tps65910->client != client) -+ i2c_unregister_device(tps65910->client); -+ -+ tps65910_modules[i].client = NULL; -+ } -+ inuse = false; -+ return 0; -+} -+ -+static int __init -+tps65910_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) -+{ -+ int status; -+ unsigned i; -+ struct tps65910_platform_data *pdata; -+ -+ pdata = client->dev.platform_data; -+ the_tps65910 = pdata; -+ -+ if (!pdata) { -+ dev_dbg(&client->dev, "no platform data?\n"); -+ return -EINVAL; -+ } -+ -+ if (i2c_check_functionality(client->adapter, -+ (I2C_FUNC_I2C | I2C_FUNC_SMBUS_BYTE)) == 0) { -+ dev_dbg(&client->dev, "can't talk I2C?\n"); -+ return -EIO; -+ } -+ -+ if (inuse) { -+ dev_dbg(&client->dev, "driver is already in use\n"); -+ return -EBUSY; -+ } -+ -+ for (i = 0; i < TPS65910_NUM_SLAVES; i++) { -+ -+ struct tps65910_client *tps65910 = &tps65910_modules[i]; -+ -+ tps65910->address = client->addr + i; -+ -+ if (i == 0) -+ tps65910->client = client; -+ else { -+ tps65910->client = i2c_new_dummy(client->adapter, -+ tps65910->address); -+ -+ if (!tps65910->client) { -+ dev_err(&client->dev, -+ "can't attach client %d\n", i); -+ status = -ENOMEM; -+ goto fail; -+ } -+ } -+ mutex_init(&tps65910->xfer_lock); -+ } -+ -+ inuse = true; -+ -+ if (pdata->board_tps65910_config != NULL) -+ pdata->board_tps65910_config(pdata); -+ -+ -+ if (pdata->irq_num) { -+ /* TPS65910 power ON interrupt(s) would have already been -+ * occured, immediately after request_irq the control will be -+ * transfered to tps65910_isr, if we do work initialization -+ * after requesting IRQ, the system crashes (does not boot), -+ * to avoid this we do work initialization before requesting -+ * IRQ -+ */ -+ mutex_init(&work_lock); -+ INIT_WORK(&core_work, tps65910_core_work); -+ -+ status = request_irq(pdata->irq_num, tps65910_isr, -+ IRQF_DISABLED, "tps65910", pdata); -+ if (status < 0) { -+ pr_err("tps65910: could not claim irq%d: %d\n", -+ pdata->irq_num, status); -+ goto fail; -+ } -+ } -+ -+ status = add_children(pdata, 0x00); -+ if (status < 0) -+ goto fail; -+ -+ return 0; -+ -+fail: -+ if (status < 0) -+ tps65910_remove(client); -+ -+ return status; -+} -+ -+ -+static int tps65910_i2c_remove(struct i2c_client *client) -+{ -+ unsigned i; -+ -+ for (i = 0; i < TPS65910_NUM_SLAVES; i++) { -+ -+ struct tps65910_client *tps65910 = &tps65910_modules[i]; -+ -+ if (tps65910->client && tps65910->client != client) -+ i2c_unregister_device(tps65910->client); -+ -+ tps65910_modules[i].client = NULL; -+ } -+ inuse = false; -+ return 0; -+} -+ -+/* chip-specific feature flags, for i2c_device_id.driver_data */ -+static const struct i2c_device_id tps65910_i2c_ids[] = { -+ { "tps65910", TPS65910 }, -+ { "tps659101", TPS659101 }, -+ { "tps659102", TPS659102 }, -+ { "tps659103", TPS659103 }, -+ { "tps659104", TPS659104 }, -+ { "tps659105", TPS659105 }, -+ { "tps659106", TPS659106 }, -+ { "tps659107", TPS659107 }, -+ { "tps659108", TPS659108 }, -+ { "tps659109", TPS659109 }, -+ {/* end of list */ }, -+}; -+MODULE_DEVICE_TABLE(i2c, tps65910_i2c_ids); -+ -+/* One Client Driver ,3 Clients - Regulator, RTC , GPIO */ -+static struct i2c_driver tps65910_i2c_driver = { -+ .driver.name = DRIVER_NAME, -+ .id_table = tps65910_i2c_ids, -+ .probe = tps65910_i2c_probe, -+ .remove = tps65910_i2c_remove, -+}; -+ -+static int __init tps65910_init(void) -+{ -+ int res; -+ -+ res = i2c_add_driver(&tps65910_i2c_driver); -+ if (res < 0) { -+ pr_err(DRIVER_NAME ": driver registration failed\n"); -+ return res; -+ } -+ -+ return 0; -+} -+subsys_initcall(tps65910_init); -+ -+static void __exit tps65910_exit(void) -+{ -+ i2c_del_driver(&tps65910_i2c_driver); -+} -+module_exit(tps65910_exit); -+ -+MODULE_AUTHOR("Mistral Solutions Pvt Ltd"); -+MODULE_DESCRIPTION("I2C Core interface for TPS65910"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig -index 71fbd6e..0ddf4c2 100644 ---- a/drivers/rtc/Kconfig -+++ b/drivers/rtc/Kconfig -@@ -267,6 +267,14 @@ config RTC_DRV_TWL4030 - This driver can also be built as a module. If so, the module - will be called rtc-twl. - -+config RTC_DRV_TPS65910 -+ boolean "TI TPS65910" -+ depends on RTC_CLASS && TPS65910_CORE -+ help -+ If you say yes here you get support for the RTC on the -+ TPS65910 family chips, used mostly with OMAP3/AM35xx platforms. -+ -+ - config RTC_DRV_S35390A - tristate "Seiko Instruments S-35390A" - select BITREVERSE -diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile -index 7da6efb..8fcfe49 100644 ---- a/drivers/rtc/Makefile -+++ b/drivers/rtc/Makefile -@@ -81,6 +81,7 @@ obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o - obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o - obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o - obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o -+obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o - obj-$(CONFIG_RTC_DRV_TX4939) += rtc-tx4939.o - obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o - obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o -diff --git a/drivers/rtc/rtc-tps65910.c b/drivers/rtc/rtc-tps65910.c -new file mode 100644 -index 0000000..7e7ed4b ---- /dev/null -+++ b/drivers/rtc/rtc-tps65910.c -@@ -0,0 +1,657 @@ -+/* -+ * rtc-tps65910.c -- TPS65910 Real Time Clock interface -+ * -+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd. -+ * Author: Umesh K -+ * -+ * Based on rtc-twl.c -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* RTC Definitions */ -+/* RTC_CTRL_REG bitfields */ -+#define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01 -+#define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02 -+#define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04 -+#define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08 -+#define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10 -+#define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20 -+#define BIT_RTC_CTRL_REG_GET_TIME_M 0x40 -+#define BIT_RTC_CTRL_REG_RTC_V_OPT_M 0x80 -+ -+/* RTC_STATUS_REG bitfields */ -+#define BIT_RTC_STATUS_REG_RUN_M 0x02 -+#define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04 -+#define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08 -+#define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10 -+#define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20 -+#define BIT_RTC_STATUS_REG_ALARM_M 0x40 -+#define BIT_RTC_STATUS_REG_POWER_UP_M 0x80 -+ -+/* RTC_INTERRUPTS_REG bitfields */ -+#define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03 -+#define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04 -+#define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08 -+ -+/* DEVCTRL bitfields */ -+#define BIT_RTC_PWDN 0x40 -+ -+/* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */ -+#define ALL_TIME_REGS 6 -+ -+/* -+ * Supports 1 byte read from TPS65910 RTC register. -+ */ -+static int tps65910_rtc_read_u8(u8 *data, u8 reg) -+{ -+ int ret; -+ -+ ret = tps65910_i2c_read_u8(TPS65910_I2C_ID0, data, reg); -+ -+ if (ret < 0) -+ pr_err("tps65910_rtc: Could not read TPS65910" -+ "register %X - error %d\n", reg, ret); -+ return ret; -+} -+ -+/* -+ * Supports 1 byte write to TPS65910 RTC registers. -+ */ -+static int tps65910_rtc_write_u8(u8 data, u8 reg) -+{ -+ int ret; -+ -+ ret = tps65910_i2c_write_u8(TPS65910_I2C_ID0, data, reg); -+ if (ret < 0) -+ pr_err("tps65910_rtc: Could not write TPS65910" -+ "register %X - error %d\n", reg, ret); -+ return ret; -+} -+ -+/* -+ * Cache the value for timer/alarm interrupts register; this is -+ * only changed by callers holding rtc ops lock (or resume). -+ */ -+static unsigned char rtc_irq_bits; -+ -+/* -+ * Enable 1/second update and/or alarm interrupts. -+ */ -+static int set_rtc_irq_bit(unsigned char bit) -+{ -+ unsigned char val; -+ int ret; -+ -+ val = rtc_irq_bits | bit; -+ val |= bit; -+ ret = tps65910_rtc_write_u8(val, TPS65910_REG_RTC_INTERRUPTS); -+ if (ret == 0) -+ rtc_irq_bits = val; -+ -+ return ret; -+} -+ -+/* -+ * Disable update and/or alarm interrupts. -+ */ -+static int mask_rtc_irq_bit(unsigned char bit) -+{ -+ unsigned char val; -+ int ret; -+ -+ val = rtc_irq_bits & ~bit; -+ ret = tps65910_rtc_write_u8(val, TPS65910_REG_RTC_INTERRUPTS); -+ if (ret == 0) -+ rtc_irq_bits = val; -+ -+ return ret; -+} -+ -+static int tps65910_rtc_alarm_irq_enable(struct device *dev, unsigned enabled) -+{ -+ int ret; -+ -+ if (enabled) -+ ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); -+ else -+ ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); -+ -+ return ret; -+} -+ -+static int tps65910_rtc_update_irq_enable(struct device *dev, unsigned enabled) -+{ -+ int ret; -+ -+ if (enabled) -+ ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); -+ else -+ ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); -+ -+ return ret; -+} -+ -+#if 1 /* Debugging periodic interrupts */ -+/* -+ * We will just handle setting the frequency and make use the framework for -+ * reading the periodic interupts. -+ * -+ * @freq: Current periodic IRQ freq: -+ * bit 0: every second -+ * bit 1: every minute -+ * bit 2: every hour -+ * bit 3: every day -+ */ -+ -+static int tps65910_rtc_irq_set_freq(struct device *dev, int freq) -+{ -+ struct rtc_device *rtc = dev_get_drvdata(dev); -+ -+ if (freq < 0 || freq > 3) -+ return -EINVAL; -+ -+ rtc->irq_freq = freq; -+ /* set rtc irq freq to user defined value */ -+ set_rtc_irq_bit(freq); -+ -+ return 0; -+} -+#endif -+ -+/* -+ * Gets current TPS65910 RTC time and date parameters. -+ * -+ * The RTC's time/alarm representation is not what gmtime(3) requires -+ * Linux to use: -+ * -+ * - Months are 1..12 vs Linux 0-11 -+ * - Years are 0..99 vs Linux 1900..N (we assume 21st century) -+ */ -+static int tps65910_rtc_read_time(struct device *dev, struct rtc_time *tm) -+{ -+ unsigned char rtc_data[ALL_TIME_REGS + 1]; -+ int ret; -+ u8 save_control; -+ -+ tps65910_rtc_read_u8(&save_control, TPS65910_REG_RTC_CTRL); -+ ret = tps65910_rtc_read_u8(&save_control, TPS65910_REG_RTC_CTRL); -+ if (ret < 0) -+ return ret; -+ -+ save_control &= ~BIT_RTC_CTRL_REG_RTC_V_OPT_M; -+ -+ ret = tps65910_rtc_write_u8(save_control, TPS65910_REG_RTC_CTRL); -+ if (ret < 0) -+ return ret; -+ -+ ret = tps65910_rtc_read_u8(&rtc_data[0], TPS65910_REG_SECONDS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[1], TPS65910_REG_MINUTES); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[2], TPS65910_REG_HOURS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[3], TPS65910_REG_DAYS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[4], TPS65910_REG_MONTHS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[5], TPS65910_REG_YEARS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ -+ tm->tm_sec = bcd2bin(rtc_data[0]); -+ tm->tm_min = bcd2bin(rtc_data[1]); -+ tm->tm_hour = bcd2bin(rtc_data[2]); -+ tm->tm_mday = bcd2bin(rtc_data[3]); -+ tm->tm_mon = bcd2bin(rtc_data[4]) - 1; -+ tm->tm_year = bcd2bin(rtc_data[5]) + 100; -+ -+ return ret; -+} -+ -+static int tps65910_rtc_set_time(struct device *dev, struct rtc_time *tm) -+{ -+ unsigned char save_control; -+ unsigned char rtc_data[ALL_TIME_REGS + 1]; -+ int ret; -+ -+ rtc_data[1] = bin2bcd(tm->tm_sec); -+ rtc_data[2] = bin2bcd(tm->tm_min); -+ rtc_data[3] = bin2bcd(tm->tm_hour); -+ rtc_data[4] = bin2bcd(tm->tm_mday); -+ rtc_data[5] = bin2bcd(tm->tm_mon + 1); -+ rtc_data[6] = bin2bcd(tm->tm_year - 100); -+ -+ /*Dummy read*/ -+ ret = tps65910_rtc_read_u8(&save_control, TPS65910_REG_RTC_CTRL); -+ -+ /* Stop RTC while updating the TC registers */ -+ ret = tps65910_rtc_read_u8(&save_control, TPS65910_REG_RTC_CTRL); -+ if (ret < 0) -+ goto out; -+ -+ save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M; -+ -+ tps65910_rtc_write_u8(save_control, TPS65910_REG_RTC_CTRL); -+ -+ /* update all the time registers in one shot */ -+ ret = tps65910_rtc_write_u8(rtc_data[1], TPS65910_REG_SECONDS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(rtc_data[2], TPS65910_REG_MINUTES); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(rtc_data[3], TPS65910_REG_HOURS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(rtc_data[4], TPS65910_REG_DAYS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(rtc_data[5], TPS65910_REG_MONTHS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(rtc_data[6], TPS65910_REG_YEARS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ -+ /*Dummy read*/ -+ ret = tps65910_rtc_read_u8(&save_control, TPS65910_REG_RTC_CTRL); -+ -+ ret = tps65910_rtc_read_u8(&save_control, TPS65910_REG_RTC_CTRL); -+ if (ret < 0) -+ goto out; -+ /* Start back RTC */ -+ save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M; -+ ret = tps65910_rtc_write_u8(save_control, TPS65910_REG_RTC_CTRL); -+ -+out: -+ return ret; -+} -+ -+/* -+ * Gets current TPS65910 RTC alarm time. -+ */ -+static int tps65910_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) -+{ -+ unsigned char rtc_data[ALL_TIME_REGS + 1]; -+ int ret; -+ -+ ret = tps65910_rtc_read_u8(&rtc_data[0], TPS65910_REG_ALARM_SECONDS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[1], TPS65910_REG_ALARM_MINUTES); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[2], TPS65910_REG_ALARM_HOURS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[3], TPS65910_REG_ALARM_DAYS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[4], TPS65910_REG_ALARM_MONTHS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_read_u8(&rtc_data[5], TPS65910_REG_ALARM_YEARS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_read_time error %d\n", ret); -+ return ret; -+ } -+ -+ /* some of these fields may be wildcard/"match all" */ -+ alm->time.tm_sec = bcd2bin(rtc_data[0]); -+ alm->time.tm_min = bcd2bin(rtc_data[1]); -+ alm->time.tm_hour = bcd2bin(rtc_data[2]); -+ alm->time.tm_mday = bcd2bin(rtc_data[3]); -+ alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1; -+ alm->time.tm_year = bcd2bin(rtc_data[5]) + 100; -+ -+ /* report cached alarm enable state */ -+ if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M) -+ alm->enabled = 1; -+ -+ return ret; -+} -+ -+static int tps65910_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) -+{ -+ unsigned char alarm_data[ALL_TIME_REGS + 1]; -+ int ret; -+ -+ ret = tps65910_rtc_alarm_irq_enable(dev, 0); -+ if (ret) -+ goto out; -+ -+ alarm_data[1] = bin2bcd(alm->time.tm_sec); -+ alarm_data[2] = bin2bcd(alm->time.tm_min); -+ alarm_data[3] = bin2bcd(alm->time.tm_hour); -+ alarm_data[4] = bin2bcd(alm->time.tm_mday); -+ alarm_data[5] = bin2bcd(alm->time.tm_mon + 1); -+ alarm_data[6] = bin2bcd(alm->time.tm_year - 100); -+ -+ /* update all the alarm registers in one shot */ -+ ret = tps65910_rtc_write_u8(alarm_data[1], TPS65910_REG_ALARM_SECONDS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(alarm_data[2], TPS65910_REG_ALARM_MINUTES); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(alarm_data[3], TPS65910_REG_ALARM_HOURS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(alarm_data[4], TPS65910_REG_ALARM_DAYS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(alarm_data[5], TPS65910_REG_ALARM_MONTHS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ ret = tps65910_rtc_write_u8(alarm_data[6], TPS65910_REG_ALARM_YEARS); -+ if (ret < 0) { -+ dev_err(dev, "rtc_write_time error %d\n", ret); -+ return ret; -+ } -+ -+ if (alm->enabled) -+ ret = tps65910_rtc_alarm_irq_enable(dev, 1); -+out: -+ return ret; -+} -+ -+ -+struct work_struct rtc_wq; -+unsigned long rtc_events; -+struct rtc_device *global_rtc; -+ -+void rtc_work(void *data) -+{ -+ -+ int res; -+ u8 rd_reg; -+ unsigned long events = 0; -+ -+ res = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_INT_STS); -+ -+ if (res < 0) -+ goto out; -+ /* -+ * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG. -+ * only one (ALARM or RTC) interrupt source may be enabled -+ * at time, we also could check our results -+ * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM] -+ */ -+ if (rd_reg & TPS65910_RTC_ALARM_IT) { -+ res = tps65910_rtc_write_u8(rd_reg | TPS65910_RTC_ALARM_IT, -+ TPS65910_REG_INT_STS); -+ if (res < 0) -+ goto out; -+ -+ /*Dummy read -- mandatory for status register*/ -+ res = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_STATUS); -+ mdelay(100); -+ res = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_STATUS); -+ res = tps65910_rtc_write_u8(rd_reg, TPS65910_REG_RTC_STATUS); -+ -+ rtc_events |= RTC_IRQF | RTC_AF; -+ } else if (rd_reg & TPS65910_RTC_PERIOD_IT) { -+ res = tps65910_rtc_write_u8(rd_reg | TPS65910_RTC_PERIOD_IT, -+ TPS65910_REG_INT_STS); -+ if (res < 0) -+ goto out; -+ -+ /*Dummy read -- mandatory for status register*/ -+ res = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_STATUS); -+ mdelay(100); -+ res = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_STATUS); -+ rd_reg &= 0xC3; -+ res = tps65910_rtc_write_u8(rd_reg, TPS65910_REG_RTC_STATUS); -+ rtc_events |= RTC_IRQF | RTC_UF; -+ } -+out: -+ /* Notify RTC core on event */ -+ events = rtc_events; -+ rtc_update_irq(global_rtc, 1, events); -+} -+ -+static struct rtc_class_ops tps65910_rtc_ops = { -+ .read_time = tps65910_rtc_read_time, -+ .set_time = tps65910_rtc_set_time, -+ .read_alarm = tps65910_rtc_read_alarm, -+ .set_alarm = tps65910_rtc_set_alarm, -+ .alarm_irq_enable = tps65910_rtc_alarm_irq_enable, -+ .update_irq_enable = tps65910_rtc_update_irq_enable, -+ .irq_set_freq = tps65910_rtc_irq_set_freq, -+}; -+ -+static int __devinit tps65910_rtc_probe(struct platform_device *pdev) -+{ -+ struct rtc_device *rtc; -+ int ret = 0; -+ u8 rd_reg; -+ -+ rtc = rtc_device_register(pdev->name, -+ &pdev->dev, &tps65910_rtc_ops, THIS_MODULE); -+ -+ if (IS_ERR(rtc)) { -+ ret = PTR_ERR(rtc); -+ dev_err(&pdev->dev, "can't register TPS65910 RTC device,\ -+ err %ld\n", PTR_ERR(rtc)); -+ goto out0; -+ -+ } -+ printk(KERN_INFO "TPS65910 RTC device successfully registered\n"); -+ -+ platform_set_drvdata(pdev, rtc); -+ -+ /* Take rtc out of reset */ -+ tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_DEVCTRL); -+ rd_reg &= ~BIT_RTC_PWDN; -+ ret = tps65910_rtc_write_u8(rd_reg, TPS65910_REG_DEVCTRL); -+ -+ /* Dummy read to ensure that the register gets updated. -+ * Please refer tps65910 TRM table:25 for details -+ */ -+ tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_STATUS); -+ -+ ret = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_STATUS); -+ if (ret < 0) { -+ printk(KERN_ERR "TPS65910 RTC STATUS REG READ FAILED\n"); -+ goto out1; -+ } -+ -+ if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M) -+ dev_warn(&pdev->dev, "Power up reset detected.\n"); -+ -+ if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M) -+ dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n"); -+ -+ /* Clear RTC Power up reset and pending alarm interrupts */ -+ ret = tps65910_rtc_write_u8(rd_reg, TPS65910_REG_RTC_STATUS); -+ if (ret < 0) -+ goto out1; -+ ret = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_INT_STS); -+ if (ret < 0) { -+ printk(KERN_ERR "TPS65910 RTC STATUS REG READ FAILED\n"); -+ goto out1; -+ } -+ -+ if (rd_reg & 0x40) { -+ printk(KERN_INFO "pending alarm interrupt!!! clearing!!!"); -+ tps65910_rtc_write_u8(rd_reg, TPS65910_REG_INT_STS); -+ } -+ -+ global_rtc = rtc; -+ -+ /* Link RTC IRQ handler to TPS65910 Core */ -+ tps65910_add_irq_work(TPS65910_RTC_ALARM_IRQ, rtc_work); -+ tps65910_add_irq_work(TPS65910_RTC_PERIOD_IRQ, rtc_work); -+ -+ /* Check RTC module status, Enable if it is off */ -+ ret = tps65910_rtc_read_u8(&rd_reg, TPS65910_REG_RTC_CTRL); -+ if (ret < 0) -+ goto out1; -+ -+ if (!(rd_reg & BIT_RTC_CTRL_REG_STOP_RTC_M)) { -+ dev_info(&pdev->dev, "Enabling TPS65910-RTC.\n"); -+ rd_reg |= BIT_RTC_CTRL_REG_STOP_RTC_M; -+ ret = tps65910_rtc_write_u8(rd_reg, TPS65910_REG_RTC_CTRL); -+ if (ret < 0) -+ goto out1; -+ } -+ -+ /* init cached IRQ enable bits */ -+ ret = tps65910_rtc_read_u8(&rtc_irq_bits, TPS65910_REG_RTC_INTERRUPTS); -+ if (ret < 0) -+ goto out1; -+ -+ tps65910_rtc_write_u8(0x3F, TPS65910_REG_INT_MSK); -+ return ret; -+ -+out1: -+ rtc_device_unregister(rtc); -+out0: -+ return ret; -+} -+ -+/* -+ * Disable all TPS65910 RTC module interrupts. -+ * Sets status flag to free. -+ */ -+static int __devexit tps65910_rtc_remove(struct platform_device *pdev) -+{ -+ /* leave rtc running, but disable irqs */ -+ struct rtc_device *rtc = platform_get_drvdata(pdev); -+ int irq = platform_get_irq(pdev, 0); -+ -+ mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M); -+ mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); -+ -+ -+ free_irq(irq, rtc); -+ -+ rtc_device_unregister(rtc); -+ platform_set_drvdata(pdev, NULL); -+ return 0; -+} -+ -+static void tps65910_rtc_shutdown(struct platform_device *pdev) -+{ -+ /* mask timer interrupts, but leave alarm interrupts on to enable -+ * power-on when alarm is triggered -+ */ -+ mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); -+} -+ -+#ifdef CONFIG_PM -+ -+static unsigned char irqstat; -+ -+ static -+int tps65910_rtc_suspend(struct platform_device *pdev, pm_message_t state) -+{ -+ irqstat = rtc_irq_bits; -+ mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M); -+ return 0; -+} -+ -+static int tps65910_rtc_resume(struct platform_device *pdev) -+{ -+ set_rtc_irq_bit(irqstat); -+ return 0; -+} -+ -+#else -+#define tps65910_rtc_suspend NULL -+#define tps65910_rtc_resume NULL -+#endif -+ -+ -+static struct platform_driver tps65910rtc_driver = { -+ .probe = tps65910_rtc_probe, -+ .remove = __devexit_p(tps65910_rtc_remove), -+ .shutdown = tps65910_rtc_shutdown, -+ .suspend = tps65910_rtc_suspend, -+ .resume = tps65910_rtc_resume, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "tps65910_rtc", -+ }, -+}; -+static int __init tps65910_rtc_init(void) -+{ -+ return platform_driver_register(&tps65910rtc_driver); -+} -+module_init(tps65910_rtc_init); -+ -+static void __exit tps65910_rtc_exit(void) -+{ -+ platform_driver_unregister(&tps65910rtc_driver); -+} -+module_exit(tps65910_rtc_exit); -+ -+MODULE_ALIAS("platform:tps65910_rtc"); -+MODULE_AUTHOR("Umesh K companion\n", - wIndex + 1); --#if !defined(CONFIG_MACH_OMAP3EVM) && !defined(CONFIG_MACH_OMAP3517EVM) -+#if !defined(CONFIG_MACH_OMAP3EVM) && !defined(CONFIG_MACH_OMAP3517EVM) && \ -+ !defined(CONFIG_MACH_CRANEBOARD) - temp |= PORT_OWNER; - #endif - } else { -@@ -978,7 +980,8 @@ error_exit: - - static void ehci_relinquish_port(struct usb_hcd *hcd, int portnum) - { --#if !defined(CONFIG_MACH_OMAP3EVM) && !defined(CONFIG_MACH_OMAP3517EVM) -+#if !defined(CONFIG_MACH_OMAP3EVM) && !defined(CONFIG_MACH_OMAP3517EVM) && \ -+ !defined(CONFIG_MACH_CRANEBOARD) - struct ehci_hcd *ehci = hcd_to_ehci(hcd); - - if (ehci_is_TDI(ehci)) -diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig -index dd1edfd..5ac688d 100644 ---- a/drivers/usb/musb/Kconfig -+++ b/drivers/usb/musb/Kconfig -@@ -10,7 +10,7 @@ comment "Enable Host or Gadget support to see Inventra options" - config USB_MUSB_HDRC - depends on (USB || USB_GADGET) - depends on (ARM || (BF54x && !BF544) || (BF52x && !BF522 && !BF523)) -- select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN || MACH_OMAP3517EVM) -+ select NOP_USB_XCEIV if (ARCH_DAVINCI || MACH_OMAP3EVM || BLACKFIN || MACH_OMAP3517EVM || MACH_CRANEBOARD) - select TWL4030_USB if MACH_OMAP_3430SDP - select USB_OTG_UTILS - tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)' -@@ -152,7 +152,7 @@ config MUSB_PIO_ONLY - - config USB_INVENTRA_DMA - bool -- depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY && !MACH_OMAP3517EVM -+ depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY && !MACH_OMAP3517EVM && !MACH_CRANEBOARD - default ARCH_OMAP2430 || ARCH_OMAP34XX || BLACKFIN - help - Enable DMA transfers using Mentor's engine. -@@ -182,7 +182,7 @@ config USB_TI_CPPI_DMA - config USB_TI_CPPI41_DMA - bool - depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY -- default ARCH_DAVINCI_DA830 || MACH_OMAP3517EVM -+ default ARCH_DAVINCI_DA830 || MACH_OMAP3517EVM || MACH_CRANEBOARD - select CPPI41 - help - Enable DMA transfers when TI CPPI 4.1 DMA is available. -diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile -index 01de383..daf3415 100644 ---- a/drivers/usb/musb/Makefile -+++ b/drivers/usb/musb/Makefile -@@ -19,7 +19,8 @@ ifeq ($(CONFIG_ARCH_OMAP2430),y) - endif - - ifeq ($(CONFIG_ARCH_OMAP3430),y) -- ifeq ($(CONFIG_MACH_OMAP3517EVM),y) -+ -+ ifeq ($(CONFIG_MACH_CRANEBOARD),y) - musb_hdrc-objs += am3517.o - else - musb_hdrc-objs += omap2430.o -diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c -index 98874c5..71ec7e8 100644 ---- a/drivers/usb/musb/musb_core.c -+++ b/drivers/usb/musb/musb_core.c -@@ -1019,7 +1019,7 @@ static void musb_shutdown(struct platform_device *pdev) - */ - #if defined(CONFIG_USB_TUSB6010) || \ - defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) || \ -- defined(CONFIG_MACH_OMAP3517EVM) -+ defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - static ushort __initdata fifo_mode = 4; - #else - static ushort __initdata fifo_mode = 2; -diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h -index 0b19d0b..d7850c7 100644 ---- a/drivers/usb/musb/musb_core.h -+++ b/drivers/usb/musb/musb_core.h -@@ -380,7 +380,7 @@ struct musb { - void __iomem *sync_va; - #endif - --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - /* Backup registers required for the workaround of AM3517 bytewise - * read issue. FADDR, POWER, INTRTXE, INTRRXE and INTRUSBE register - * read would actually clear the interrupt registers and would cause -diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c -index c0e2efc..bb93de7 100644 ---- a/drivers/usb/musb/musb_gadget.c -+++ b/drivers/usb/musb/musb_gadget.c -@@ -2024,7 +2024,7 @@ __acquires(musb->lock) - - - /* what speed did we negotiate? */ --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - musb->read_mask &= ~AM3517_READ_ISSUE_POWER; - #endif - power = musb_readb(mbase, MUSB_POWER); -diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c -index 7a9dc1e..bcc754d 100644 ---- a/drivers/usb/musb/musb_gadget_ep0.c -+++ b/drivers/usb/musb/musb_gadget_ep0.c -@@ -770,7 +770,7 @@ setup: - printk(KERN_NOTICE "%s: peripheral reset " - "irq lost!\n", - musb_driver_name); --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - musb->read_mask &= ~AM3517_READ_ISSUE_POWER; - #endif - power = musb_readb(mbase, MUSB_POWER); -diff --git a/drivers/usb/musb/musb_io.h b/drivers/usb/musb/musb_io.h -index 0969d88..e578061 100644 ---- a/drivers/usb/musb/musb_io.h -+++ b/drivers/usb/musb/musb_io.h -@@ -56,7 +56,8 @@ static inline void writesb(const void __iomem *addr, const void *buf, int len) - - #endif - --#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_MACH_OMAP3517EVM) -+#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_MACH_OMAP3517EVM) && \ -+ !defined(CONFIG_MACH_CRANEBOARD) - - /* NOTE: these offsets are all in bytes */ - -@@ -136,7 +137,7 @@ static inline void musb_writew(void __iomem *addr, unsigned offset, u16 data) - static inline void musb_writel(void __iomem *addr, unsigned offset, u32 data) - { bfin_write16(addr + offset, (u16) data); } - --#elif defined(CONFIG_MACH_OMAP3517EVM) -+#elif (defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD)) - - /* AM3517 has a limitation on read operation. Only 32 bit read is - * allowed and thus 8bit and 16bit read has to be handled differently -diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c -index 0200a62..c1570b6 100644 ---- a/drivers/usb/musb/musb_virthub.c -+++ b/drivers/usb/musb/musb_virthub.c -@@ -68,12 +68,12 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend) - musb_writeb(mbase, MUSB_POWER, power); - - /* Needed for OPT A tests */ --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - musb->read_mask &= ~AM3517_READ_ISSUE_POWER; - #endif - power = musb_readb(mbase, MUSB_POWER); - while (power & MUSB_POWER_SUSPENDM) { --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - musb->read_mask &= ~AM3517_READ_ISSUE_POWER; - #endif - power = musb_readb(mbase, MUSB_POWER); -@@ -135,7 +135,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset) - /* NOTE: caller guarantees it will turn off the reset when - * the appropriate amount of time has passed - */ --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - musb->read_mask &= ~AM3517_READ_ISSUE_POWER; - #endif - power = musb_readb(mbase, MUSB_POWER); -@@ -171,7 +171,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset) - - musb->ignore_disconnect = false; - --#ifdef CONFIG_MACH_OMAP3517EVM -+#if defined(CONFIG_MACH_OMAP3517EVM) || defined(CONFIG_MACH_CRANEBOARD) - musb->read_mask &= ~AM3517_READ_ISSUE_POWER; - #endif - power = musb_readb(mbase, MUSB_POWER); -diff --git a/drivers/video/omap2/displays/panel-generic.c b/drivers/video/omap2/displays/panel-generic.c -index eb48d1a..ad9ecc2 100644 ---- a/drivers/video/omap2/displays/panel-generic.c -+++ b/drivers/video/omap2/displays/panel-generic.c -@@ -26,7 +26,11 @@ static struct omap_video_timings generic_panel_timings = { - /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ - .x_res = 640, - .y_res = 480, -+#ifdef CONFIG_MACH_CRANEBOARD -+ .pixel_clock = 24000, -+#else - .pixel_clock = 23500, -+#endif - .hfp = 48, - .hsw = 32, - .hbp = 80, -@@ -37,7 +41,12 @@ static struct omap_video_timings generic_panel_timings = { - - static int generic_panel_probe(struct omap_dss_device *dssdev) - { -+#ifdef CONFIG_MACH_CRANEBOARD -+ dssdev->panel.config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC); -+#else - dssdev->panel.config = OMAP_DSS_LCD_TFT; -+#endif - dssdev->panel.timings = generic_panel_timings; - - return 0; -diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c -index 1127e85..8be116f 100644 ---- a/drivers/video/omap2/dss/venc.c -+++ b/drivers/video/omap2/dss/venc.c -@@ -292,7 +292,9 @@ static struct { - void __iomem *base; - struct mutex venc_lock; - u32 wss_data; -+#ifndef CONFIG_MACH_CRANEBOARD - struct regulator *vdda_dac_reg; -+#endif - } venc; - - static inline void venc_write_reg(int idx, u32 val) -@@ -503,13 +505,14 @@ int venc_init(struct platform_device *pdev) - return -ENOMEM; - } - -+#ifndef CONFIG_MACH_CRANEBOARD - venc.vdda_dac_reg = regulator_get(&pdev->dev, "vdda_dac"); - if (IS_ERR(venc.vdda_dac_reg)) { - iounmap(venc.base); - DSSERR("can't get VDDA_DAC regulator\n"); - return PTR_ERR(venc.vdda_dac_reg); - } -- -+#endif - venc_enable_clocks(1); - - rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); -@@ -523,9 +526,9 @@ int venc_init(struct platform_device *pdev) - void venc_exit(void) - { - omap_dss_unregister_driver(&venc_driver); -- -+#ifndef CONFIG_MACH_CRANEBOARD - regulator_put(venc.vdda_dac_reg); -- -+#endif - iounmap(venc.base); - } - -@@ -576,8 +579,9 @@ static int venc_power_on(struct omap_dss_device *dssdev) - dispc_set_digit_size(dssdev->panel.timings.x_res, - dssdev->panel.timings.y_res/2); - -+#ifndef CONFIG_MACH_CRANEBOARD - regulator_enable(venc.vdda_dac_reg); -- -+#endif - if (dssdev->platform_enable) - dssdev->platform_enable(dssdev); - -@@ -604,8 +608,9 @@ static void venc_power_off(struct omap_dss_device *dssdev) - if (dssdev->platform_disable) - dssdev->platform_disable(dssdev); - -+#ifndef CONFIG_MACH_CRANEBOARD - regulator_disable(venc.vdda_dac_reg); -- -+#endif - #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dsi_pll_uninit(); - dss_clk_disable(DSS_CLK_FCK2); -diff --git a/include/linux/i2c/tps65910.h b/include/linux/i2c/tps65910.h -new file mode 100644 -index 0000000..1362de4 ---- /dev/null -+++ b/include/linux/i2c/tps65910.h -@@ -0,0 +1,278 @@ -+/* linux/i2c/tps65910.h -+ * -+ * TPS65910 Power Management Device Definitions. -+ * -+ * Based on include/linux/i2c/twl.h -+ * -+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN -+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF -+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef __LINUX_I2C_TPS65910_H -+#define __LINUX_I2C_TPS65910_H -+ -+#define TPS65910_NUM_SLAVES 2 -+/* I2C Slave Address 7-bit */ -+#define TPS65910_I2C_ID0 0x2D /* general-purpose */ -+#define TPS65910_I2C_ID1 0x12 /* Smart Reflex */ -+ -+/* TPS65910 to host IRQ */ -+#define TPS65910_HOST_IRQ INT_34XX_SYS_NIRQ -+ -+/* TPS65910 MAX GPIOs */ -+#define TPS65910_GPIO_MAX 1 -+ -+/* -+ * ---------------------------------------------------------------------------- -+ * Registers, all 8 bits -+ * ---------------------------------------------------------------------------- -+ */ -+#define TPS65910_REG_SECONDS 0x00 -+#define TPS65910_REG_MINUTES 0x01 -+#define TPS65910_REG_HOURS 0x02 -+#define TPS65910_REG_DAYS 0x03 -+#define TPS65910_REG_MONTHS 0x04 -+#define TPS65910_REG_YEARS 0x05 -+#define TPS65910_REG_WEEKS 0x06 -+#define TPS65910_REG_ALARM_SECONDS 0x08 -+#define TPS65910_REG_ALARM_MINUTES 0x09 -+#define TPS65910_REG_ALARM_HOURS 0x0A -+#define TPS65910_REG_ALARM_DAYS 0x0B -+#define TPS65910_REG_ALARM_MONTHS 0x0C -+#define TPS65910_REG_ALARM_YEARS 0x0D -+ -+#define TPS65910_REG_RTC_CTRL 0x10 -+#define TPS65910_REG_RTC_STATUS 0x11 -+#define TPS65910_REG_RTC_INTERRUPTS 0x12 -+#define TPS65910_REG_RTC_COMP_LSB 0x13 -+#define TPS65910_REG_RTC_COMP_MSB 0x14 -+#define TPS65910_REG_RTC_RES_PROG 0x15 -+#define TPS65910_REG_RTC_RESET_STATUS 0x16 -+#define TPS65910_REG_BCK1 0x17 -+#define TPS65910_REG_BCK2 0x18 -+#define TPS65910_REG_BCK3 0x19 -+#define TPS65910_REG_BCK4 0x1A -+#define TPS65910_REG_BCK5 0x1B -+#define TPS65910_REG_PUADEN 0x1C -+#define TPS65910_REG_REF 0x1D -+#define TPS65910_REG_VRTC 0x1E -+ -+#define TPS65910_REG_VIO 0x20 -+#define TPS65910_REG_VDD1 0x21 -+#define TPS65910_REG_VDD1_OP 0x22 -+#define TPS65910_REG_VDD1_SR 0x23 -+#define TPS65910_REG_VDD2 0x24 -+#define TPS65910_REG_VDD2_OP 0x25 -+#define TPS65910_REG_VDD2_SR 0x26 -+#define TPS65910_REG_VDD3 0x27 -+ -+#define TPS65910_REG_VDIG1 0x30 -+#define TPS65910_REG_VDIG2 0x31 -+#define TPS65910_REG_VAUX1 0x32 -+#define TPS65910_REG_VAUX2 0x33 -+#define TPS65910_REG_VAUX33 0x34 -+#define TPS65910_REG_VMMC 0x35 -+#define TPS65910_REG_VPLL 0x36 -+#define TPS65910_REG_VDAC 0x37 -+#define TPS65910_REG_THERM 0x38 -+#define TPS65910_REG_BBCH 0x39 -+ -+#define TPS65910_REG_DCDCCTRL 0x3E -+#define TPS65910_REG_DEVCTRL 0x3F -+#define TPS65910_REG_DEVCTRL2 0x40 -+#define TPS65910_REG_SLEEP_KEEP_LDO_ON 0x41 -+#define TPS65910_REG_SLEEP_KEEP_RES_ON 0x42 -+#define TPS65910_REG_SLEEP_SET_LDO_OFF 0x43 -+#define TPS65910_REG_SLEEP_SET_RES_OFF 0x44 -+#define TPS65910_REG_EN1_LDO_ASS 0x45 -+#define TPS65910_REG_EN1_SMPS_ASS 0x46 -+#define TPS65910_REG_EN2_LDO_ASS 0x47 -+#define TPS65910_REG_EN2_SMPS_ASS 0x48 -+#define TPS65910_REG_EN3_LDO_ASS 0x49 -+#define TPS65910_REG_SPARE 0x4A -+ -+#define TPS65910_REG_INT_STS 0x50 -+#define TPS65910_REG_INT_MSK 0x51 -+#define TPS65910_REG_INT_STS2 0x52 -+#define TPS65910_REG_INT_MSK2 0x53 -+#define TPS65910_REG_INT_STS3 0x54 -+#define TPS65910_REG_INT_MSK3 0x55 -+ -+#define TPS65910_REG_GPIO0 0x60 -+ -+#define TPS65910_REG_JTAGVERNUM 0x80 -+ -+/* TPS65910 GPIO Specific flags */ -+#define TPS65910_GPIO_INT_FALLING 0 -+#define TPS65910_GPIO_INT_RISING 1 -+ -+#define TPS65910_DEBOUNCE_91_5_MS 0 -+#define TPS65910_DEBOUNCE_150_MS 1 -+ -+#define TPS65910_GPIO_PUDIS (1 << 3) -+#define TPS65910_GPIO_CFG_OUTPUT (1 << 2) -+ -+ -+ -+/* TPS65910 Interrupt events */ -+ -+/* RTC Driver */ -+#define TPS65910_RTC_ALARM_IT 0x80 -+#define TPS65910_RTC_PERIOD_IT 0x40 -+ -+/*Core Driver */ -+#define TPS65910_HOT_DIE_IT 0x20 -+#define TPS65910_PWRHOLD_IT 0x10 -+#define TPS65910_PWRON_LP_IT 0x08 -+#define TPS65910_PWRON_IT 0x04 -+#define TPS65910_VMBHI_IT 0x02 -+#define TPS65910_VMBGCH_IT 0x01 -+ -+/* GPIO driver */ -+#define TPS65910_GPIO_F_IT 0x02 -+#define TPS65910_GPIO_R_IT 0x01 -+ -+ -+#define TPS65910_VRTC_OFFMASK (1<<3) -+ -+/* Back-up battery charger control */ -+#define TPS65910_BBCHEN 0x01 -+ -+/* Back-up battery charger voltage */ -+#define TPS65910_BBSEL_3P0 0x00 -+#define TPS65910_BBSEL_2P52 0x02 -+#define TPS65910_BBSEL_3P15 0x04 -+#define TPS65910_BBSEL_VBAT 0x06 -+ -+/* DEVCTRL_REG flags */ -+#define TPS65910_RTC_PWDNN 0x40 -+#define TPS65910_CK32K_CTRL 0x20 -+#define TPS65910_SR_CTL_I2C_SEL 0x10 -+#define TPS65910_DEV_OFF_RST 0x08 -+#define TPS65910_DEV_ON 0x04 -+#define TPS65910_DEV_SLP 0x02 -+#define TPS65910_DEV_OFF 0x01 -+ -+/* DEVCTRL2_REG flags */ -+#define TPS65910_DEV2_TSLOT_LENGTH 0x30 -+#define TPS65910_DEV2_SLEEPSIG_POL 0x08 -+#define TPS65910_DEV2_PWON_LP_OFF 0x04 -+#define TPS65910_DEV2_PWON_LP_RST 0x02 -+#define TPS65910_DEV2_IT_POL 0x01 -+ -+/* TPS65910 SMPS/LDO's */ -+#define TPS65910_VIO 0 -+#define TPS65910_VDD1 1 -+#define TPS65910_VDD2 2 -+#define TPS65910_VDD3 3 -+/* LDOs */ -+#define TPS65910_VDIG1 4 -+#define TPS65910_VDIG2 5 -+#define TPS65910_VAUX33 6 -+#define TPS65910_VMMC 7 -+#define TPS65910_VAUX1 8 -+#define TPS65910_VAUX2 9 -+#define TPS65910_VDAC 10 -+#define TPS65910_VPLL 11 -+/* Internal LDO */ -+#define TPS65910_VRTC 12 -+ -+/* Number of step-down/up converters available */ -+#define TPS65910_NUM_DCDC 4 -+ -+/* Number of LDO voltage regulators available */ -+#define TPS65910_NUM_LDO 9 -+ -+/* Number of total regulators available */ -+#define TPS65910_NUM_REGULATOR (TPS65910_NUM_DCDC + TPS65910_NUM_LDO) -+ -+ -+/* Regulator Supply state */ -+#define SUPPLY_STATE_FLAG 0x03 -+/* OFF States */ -+#define TPS65910_REG_OFF_00 0x00 -+#define TPS65910_REG_OFF_10 0x02 -+/* OHP - on High Power */ -+#define TPS65910_REG_OHP 0x01 -+/* OLP - on Low Power */ -+#define TPS65910_REG_OLP 0x03 -+ -+#define TPS65910_MAX_IRQS 10 -+#define TPS65910_VMBDCH_IRQ 0 -+#define TPS65910_VMBHI_IRQ 1 -+#define TPS65910_PWRON_IRQ 2 -+#define TPS65910_PWRON_LP_IRQ 3 -+#define TPS65910_PWRHOLD_IRQ 4 -+#define TPS65910_HOTDIE_IRQ 5 -+#define TPS65910_RTC_ALARM_IRQ 6 -+#define TPS65910_RTC_PERIOD_IRQ 7 -+#define TPS65910_GPIO0_R_IRQ 8 -+#define TPS65910_GPIO0_F_IRQ 9 -+ -+/* TPS65910 has 1 GPIO */ -+struct tps65910_gpio { -+ u8 debounce; -+ u8 pullup_pulldown; -+ u8 gpio_config; /* Input or output */ -+ u8 gpio_val; /* Output value */ -+ int (*gpio_setup)(struct tps65910_gpio *pdata); -+ int (*gpio_taredown)(struct tps65910_gpio *pdata); -+}; -+ -+struct tps65910_platform_data { -+ -+ unsigned irq_num; /* TPS65910 to Host IRQ Number */ -+ struct tps65910_gpio *gpio; -+ -+ /* plaform specific data to be initialised in board file */ -+ struct regulator_init_data *vio; -+ struct regulator_init_data *vdd1; -+ struct regulator_init_data *vdd2; -+ struct regulator_init_data *vdd3; -+ struct regulator_init_data *vdig1; -+ struct regulator_init_data *vdig2; -+ struct regulator_init_data *vaux33; -+ struct regulator_init_data *vmmc; -+ struct regulator_init_data *vaux1; -+ struct regulator_init_data *vaux2; -+ struct regulator_init_data *vdac; -+ struct regulator_init_data *vpll; -+ -+ void (*handlers[TPS65910_MAX_IRQS]) (void *data); -+ /* Configure TP65910 to board specific usage*/ -+ int (*board_tps65910_config)(struct tps65910_platform_data *pdata); -+}; -+ -+int tps65910_enable_bbch(u8 voltage); -+int tps65910_disable_bbch(void); -+ -+int tps65910_remove_irq_work(int irq); -+int tps65910_add_irq_work(int irq, void (*handler)(void *data)); -+ -+int tps65910_i2c_write_u8(u8 slave_addr, u8 val, u8 reg); -+int tps65910_i2c_read_u8(u8 slave_addr, u8 *val, u8 reg); -+ -+int tps65910_i2c_write(u8 slave_addr, u8 *value, u8 reg, unsigned num_bytes); -+int tps65910_i2c_read(u8 slave_addr, u8 *value, u8 reg, unsigned num_bytes); -+ -+#endif /* __LINUX_I2C_TPS65910_H */ -+ --- -1.7.0.4 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-BeagleBoard-Adjust-USER-button-pin-for-xM.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-BeagleBoard-Adjust-USER-button-pin-for-xM.patch deleted file mode 100644 index a9c297d4..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-BeagleBoard-Adjust-USER-button-pin-for-xM.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 1c63789190687e20ddbed3084e7ae893176d0dd6 Mon Sep 17 00:00:00 2001 -From: Jason Kridner -Date: Sat, 17 Jul 2010 14:28:22 -0500 -Subject: [PATCH] BeagleBoard: Adjust USER button pin for xM - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 5 +++++ - 1 files changed, 5 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 1e8b77b..2677b41 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -854,6 +854,11 @@ static void __init omap3_beagle_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3_beagle_i2c_init(); -+ -+ if (cpu_is_omap3630()) { -+ gpio_buttons[0].gpio = 4; -+ } -+ - platform_add_devices(omap3_beagle_devices, - ARRAY_SIZE(omap3_beagle_devices)); - omap_serial_init(); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-OMAP3-craneboard-print-expansionboard-name-detected-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-OMAP3-craneboard-print-expansionboard-name-detected-.patch deleted file mode 100644 index be7c4d7b..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-OMAP3-craneboard-print-expansionboard-name-detected-.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e618eb6ab097d2f655ee6094d5e3c0dc603d7242 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Wed, 19 Jan 2011 16:30:06 +0100 -Subject: [PATCH 1/2] OMAP3: craneboard: print expansionboard name detected from uboot - -Signed-off-by: Koen Kooi ---- - arch/arm/mach-omap2/board-am3517crane.c | 13 +++++++++++++ - 1 files changed, 13 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c -index 0bf4f60..300a79d 100644 ---- a/arch/arm/mach-omap2/board-am3517crane.c -+++ b/arch/arm/mach-omap2/board-am3517crane.c -@@ -55,6 +55,8 @@ - - #define NAND_BLOCK_SIZE SZ_128K - -+char expansionboard_name[16]; -+ - static struct mtd_partition am3517crane_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { -@@ -724,6 +726,15 @@ static struct am3517_hsmmc_info mmc[] = { - {} /* Terminator */ - }; - -+static int __init expansionboard_setup(char *str) -+{ -+ if (!str) -+ return -EINVAL; -+ strncpy(expansionboard_name, str, 16); -+ printk(KERN_INFO "Crane expansionboard: %s\n", expansionboard_name); -+ return 0; -+} -+ - static void __init am3517_crane_init(void) - { - -@@ -762,6 +773,8 @@ static void __init am3517_crane_map_io(void) - omap2_map_common_io(); - } - -+early_param("buddy", expansionboard_setup); -+ - MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") - .phys_io = 0x48000000, - .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-PSP-3.0.1.6-kernel-source-patched-with-OCF-Linux.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-PSP-3.0.1.6-kernel-source-patched-with-OCF-Linux.patch deleted file mode 100644 index 561670e9..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-PSP-3.0.1.6-kernel-source-patched-with-OCF-Linux.patch +++ /dev/null @@ -1,88333 +0,0 @@ -From 8e1595675e4f2ad795faecb30e0657ac556913d1 Mon Sep 17 00:00:00 2001 -From: Greg Turner -Date: Wed, 19 Jan 2011 16:19:37 +0100 -Subject: [PATCH] PSP 3.0.1.6 kernel source patched with OCF-Linux - ---- - crypto/Kconfig | 3 + - crypto/Makefile | 2 + - crypto/modules.builtin | 22 + - crypto/ocf/Config.in | 36 + - crypto/ocf/Kconfig | 119 + - crypto/ocf/Makefile | 124 + - crypto/ocf/README | 167 ++ - crypto/ocf/c7108/Makefile | 12 + - crypto/ocf/c7108/aes-7108.c | 839 ++++++ - crypto/ocf/c7108/aes-7108.h | 134 + - crypto/ocf/criov.c | 215 ++ - crypto/ocf/crypto.c | 1784 +++++++++++ - crypto/ocf/cryptocteon/Makefile | 17 + - crypto/ocf/cryptocteon/cavium_crypto.c | 2283 ++++++++++++++ - crypto/ocf/cryptocteon/cryptocteon.c | 574 ++++ - crypto/ocf/cryptodev.c | 1061 +++++++ - crypto/ocf/cryptodev.h | 479 +++ - crypto/ocf/cryptosoft.c | 1210 ++++++++ - crypto/ocf/ep80579/Makefile | 119 + - crypto/ocf/ep80579/icp_asym.c | 1334 +++++++++ - crypto/ocf/ep80579/icp_common.c | 773 +++++ - crypto/ocf/ep80579/icp_ocf.h | 376 +++ - crypto/ocf/ep80579/icp_sym.c | 1153 ++++++++ - crypto/ocf/hifn/Makefile | 13 + - crypto/ocf/hifn/hifn7751.c | 2976 +++++++++++++++++++ - crypto/ocf/hifn/hifn7751reg.h | 540 ++++ - crypto/ocf/hifn/hifn7751var.h | 369 +++ - crypto/ocf/hifn/hifnHIPP.c | 420 +++ - crypto/ocf/hifn/hifnHIPPreg.h | 46 + - crypto/ocf/hifn/hifnHIPPvar.h | 93 + - crypto/ocf/ixp4xx/Makefile | 104 + - crypto/ocf/ixp4xx/ixp4xx.c | 1324 +++++++++ - crypto/ocf/kirkwood/Makefile | 19 + - crypto/ocf/kirkwood/cesa/AES/mvAes.h | 62 + - crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c | 317 ++ - crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h | 19 + - crypto/ocf/kirkwood/cesa/AES/mvAesApi.c | 312 ++ - crypto/ocf/kirkwood/cesa/mvCesa.c | 3126 ++++++++++++++++++++ - crypto/ocf/kirkwood/cesa/mvCesa.h | 412 +++ - crypto/ocf/kirkwood/cesa/mvCesaDebug.c | 484 +++ - crypto/ocf/kirkwood/cesa/mvCesaRegs.h | 357 +++ - crypto/ocf/kirkwood/cesa/mvCesaTest.c | 3096 +++++++++++++++++++ - crypto/ocf/kirkwood/cesa/mvLru.c | 158 + - crypto/ocf/kirkwood/cesa/mvLru.h | 112 + - crypto/ocf/kirkwood/cesa/mvMD5.c | 349 +++ - crypto/ocf/kirkwood/cesa/mvMD5.h | 93 + - crypto/ocf/kirkwood/cesa/mvSHA1.c | 239 ++ - crypto/ocf/kirkwood/cesa/mvSHA1.h | 88 + - crypto/ocf/kirkwood/cesa_ocf_drv.c | 1296 ++++++++ - crypto/ocf/kirkwood/mvHal/common/mv802_3.h | 213 ++ - crypto/ocf/kirkwood/mvHal/common/mvCommon.c | 277 ++ - crypto/ocf/kirkwood/mvHal/common/mvCommon.h | 308 ++ - crypto/ocf/kirkwood/mvHal/common/mvDebug.c | 326 ++ - crypto/ocf/kirkwood/mvHal/common/mvDebug.h | 178 ++ - crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h | 225 ++ - crypto/ocf/kirkwood/mvHal/common/mvHalVer.h | 73 + - crypto/ocf/kirkwood/mvHal/common/mvStack.c | 100 + - crypto/ocf/kirkwood/mvHal/common/mvStack.h | 140 + - crypto/ocf/kirkwood/mvHal/common/mvTypes.h | 245 ++ - crypto/ocf/kirkwood/mvHal/dbg-trace.c | 110 + - crypto/ocf/kirkwood/mvHal/dbg-trace.h | 24 + - .../mvHal/kw_family/boardEnv/mvBoardEnvLib.c | 2513 ++++++++++++++++ - .../mvHal/kw_family/boardEnv/mvBoardEnvLib.h | 376 +++ - .../mvHal/kw_family/boardEnv/mvBoardEnvSpec.c | 848 ++++++ - .../mvHal/kw_family/boardEnv/mvBoardEnvSpec.h | 262 ++ - crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c | 320 ++ - crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h | 99 + - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c | 296 ++ - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h | 203 ++ - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h | 98 + - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c | 1825 ++++++++++++ - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h | 185 ++ - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h | 419 +++ - .../mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h | 257 ++ - .../mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c | 1048 +++++++ - .../mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h | 130 + - .../mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h | 143 + - .../kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c | 1036 +++++++ - .../kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h | 120 + - .../mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h | 304 ++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c | 324 ++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h | 123 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c | 382 +++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h | 100 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysDram.c | 348 +++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysDram.h | 80 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c | 658 ++++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h | 113 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysPex.c | 1697 +++++++++++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysPex.h | 348 +++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysSata.c | 430 +++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysSata.h | 128 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c | 427 +++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h | 125 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c | 462 +++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h | 106 + - .../kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.c | 591 ++++ - .../kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h | 110 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c | 497 ++++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysUsb.h | 125 + - .../mvHal/kw_family/ctrlEnv/sys/mvSysXor.c | 662 +++++ - .../mvHal/kw_family/ctrlEnv/sys/mvSysXor.h | 140 + - .../ocf/kirkwood/mvHal/kw_family/device/mvDevice.c | 75 + - .../ocf/kirkwood/mvHal/kw_family/device/mvDevice.h | 74 + - .../kirkwood/mvHal/kw_family/device/mvDeviceRegs.h | 101 + - crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c | 211 ++ - crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h | 423 +++ - crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h | 158 + - crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h | 375 +++ - crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c | 376 +++ - crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h | 121 + - .../ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h | 121 + - crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c | 207 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h | 213 ++ - .../ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c | 143 + - .../ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h | 151 + - crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c | 1479 +++++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h | 191 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c | 1599 ++++++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h | 179 ++ - .../kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h | 192 ++ - .../kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h | 306 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c | 1855 ++++++++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h | 172 ++ - .../kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h | 157 + - .../ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h | 423 +++ - .../mvHal/mv_hal/ddr2/mvDramIfStaticInit.h | 179 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c | 1474 +++++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h | 192 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c | 2952 ++++++++++++++++++ - .../ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c | 748 +++++ - .../ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h | 146 + - .../ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h | 751 +++++ - .../ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h | 700 +++++ - crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h | 356 +++ - crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c | 362 +++ - crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h | 118 + - crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h | 116 + - crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c | 669 +++++ - crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h | 134 + - .../ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h | 245 ++ - .../mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c | 1006 +++++++ - .../mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h | 323 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c | 1047 +++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h | 185 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h | 411 +++ - crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c | 1143 +++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h | 168 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h | 751 +++++ - crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c | 313 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h | 82 + - crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c | 1522 ++++++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h | 166 ++ - .../kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h | 233 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c | 576 ++++ - crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h | 94 + - crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c | 249 ++ - crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h | 82 + - crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h | 98 + - crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c | 1023 +++++++ - crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h | 121 + - crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h | 160 + - crypto/ocf/ocf-bench.c | 436 +++ - crypto/ocf/ocf-compat.h | 294 ++ - crypto/ocf/ocfnull/Makefile | 12 + - crypto/ocf/ocfnull/ocfnull.c | 203 ++ - crypto/ocf/pasemi/Makefile | 12 + - crypto/ocf/pasemi/pasemi.c | 1009 +++++++ - crypto/ocf/pasemi/pasemi_fnu.h | 410 +++ - crypto/ocf/random.c | 322 ++ - crypto/ocf/rndtest.c | 300 ++ - crypto/ocf/rndtest.h | 54 + - crypto/ocf/safe/Makefile | 12 + - crypto/ocf/safe/md5.c | 308 ++ - crypto/ocf/safe/md5.h | 76 + - crypto/ocf/safe/safe.c | 2288 ++++++++++++++ - crypto/ocf/safe/safereg.h | 421 +++ - crypto/ocf/safe/safevar.h | 230 ++ - crypto/ocf/safe/sha1.c | 279 ++ - crypto/ocf/safe/sha1.h | 72 + - crypto/ocf/talitos/Makefile | 12 + - crypto/ocf/talitos/talitos.c | 1359 +++++++++ - crypto/ocf/talitos/talitos_dev.h | 277 ++ - crypto/ocf/talitos/talitos_soft.h | 77 + - crypto/ocf/uio.h | 54 + - drivers/char/random.c | 65 + - fs/fcntl.c | 1 + - include/linux/miscdevice.h | 1 + - include/linux/random.h | 29 + - kernel/pid.c | 1 + - 190 files changed, 86748 insertions(+), 0 deletions(-) - create mode 100644 crypto/modules.builtin - create mode 100644 crypto/ocf/Config.in - create mode 100644 crypto/ocf/Kconfig - create mode 100644 crypto/ocf/Makefile - create mode 100644 crypto/ocf/README - create mode 100644 crypto/ocf/c7108/Makefile - create mode 100644 crypto/ocf/c7108/aes-7108.c - create mode 100644 crypto/ocf/c7108/aes-7108.h - create mode 100644 crypto/ocf/criov.c - create mode 100644 crypto/ocf/crypto.c - create mode 100644 crypto/ocf/cryptocteon/Makefile - create mode 100644 crypto/ocf/cryptocteon/cavium_crypto.c - create mode 100644 crypto/ocf/cryptocteon/cryptocteon.c - create mode 100644 crypto/ocf/cryptodev.c - create mode 100644 crypto/ocf/cryptodev.h - create mode 100644 crypto/ocf/cryptosoft.c - create mode 100644 crypto/ocf/ep80579/Makefile - create mode 100644 crypto/ocf/ep80579/icp_asym.c - create mode 100644 crypto/ocf/ep80579/icp_common.c - create mode 100644 crypto/ocf/ep80579/icp_ocf.h - create mode 100644 crypto/ocf/ep80579/icp_sym.c - create mode 100644 crypto/ocf/hifn/Makefile - create mode 100644 crypto/ocf/hifn/hifn7751.c - create mode 100644 crypto/ocf/hifn/hifn7751reg.h - create mode 100644 crypto/ocf/hifn/hifn7751var.h - create mode 100644 crypto/ocf/hifn/hifnHIPP.c - create mode 100644 crypto/ocf/hifn/hifnHIPPreg.h - create mode 100644 crypto/ocf/hifn/hifnHIPPvar.h - create mode 100644 crypto/ocf/ixp4xx/Makefile - create mode 100644 crypto/ocf/ixp4xx/ixp4xx.c - create mode 100644 crypto/ocf/kirkwood/Makefile - create mode 100644 crypto/ocf/kirkwood/cesa/AES/mvAes.h - create mode 100644 crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c - create mode 100644 crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h - create mode 100644 crypto/ocf/kirkwood/cesa/AES/mvAesApi.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvCesa.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvCesa.h - create mode 100644 crypto/ocf/kirkwood/cesa/mvCesaDebug.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvCesaRegs.h - create mode 100644 crypto/ocf/kirkwood/cesa/mvCesaTest.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvLru.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvLru.h - create mode 100644 crypto/ocf/kirkwood/cesa/mvMD5.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvMD5.h - create mode 100644 crypto/ocf/kirkwood/cesa/mvSHA1.c - create mode 100644 crypto/ocf/kirkwood/cesa/mvSHA1.h - create mode 100644 crypto/ocf/kirkwood/cesa_ocf_drv.c - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mv802_3.h - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvCommon.c - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvCommon.h - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvDebug.c - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvDebug.h - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvHalVer.h - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvStack.c - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvStack.h - create mode 100644 crypto/ocf/kirkwood/mvHal/common/mvTypes.h - create mode 100644 crypto/ocf/kirkwood/mvHal/dbg-trace.c - create mode 100644 crypto/ocf/kirkwood/mvHal/dbg-trace.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h - create mode 100644 crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c - create mode 100644 crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfStaticInit.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/eth/mvEth.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h - create mode 100644 crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h - create mode 100644 crypto/ocf/ocf-bench.c - create mode 100644 crypto/ocf/ocf-compat.h - create mode 100644 crypto/ocf/ocfnull/Makefile - create mode 100644 crypto/ocf/ocfnull/ocfnull.c - create mode 100644 crypto/ocf/pasemi/Makefile - create mode 100644 crypto/ocf/pasemi/pasemi.c - create mode 100644 crypto/ocf/pasemi/pasemi_fnu.h - create mode 100644 crypto/ocf/random.c - create mode 100644 crypto/ocf/rndtest.c - create mode 100644 crypto/ocf/rndtest.h - create mode 100644 crypto/ocf/safe/Makefile - create mode 100644 crypto/ocf/safe/md5.c - create mode 100644 crypto/ocf/safe/md5.h - create mode 100644 crypto/ocf/safe/safe.c - create mode 100644 crypto/ocf/safe/safereg.h - create mode 100644 crypto/ocf/safe/safevar.h - create mode 100644 crypto/ocf/safe/sha1.c - create mode 100644 crypto/ocf/safe/sha1.h - create mode 100644 crypto/ocf/talitos/Makefile - create mode 100644 crypto/ocf/talitos/talitos.c - create mode 100644 crypto/ocf/talitos/talitos_dev.h - create mode 100644 crypto/ocf/talitos/talitos_soft.h - create mode 100644 crypto/ocf/uio.h - -diff --git a/crypto/Kconfig b/crypto/Kconfig -index 81c185a..9f1c30f 100644 ---- a/crypto/Kconfig -+++ b/crypto/Kconfig -@@ -822,3 +822,6 @@ config CRYPTO_ANSI_CPRNG - source "drivers/crypto/Kconfig" - - endif # if CRYPTO -+ -+source "crypto/ocf/Kconfig" -+ -diff --git a/crypto/Makefile b/crypto/Makefile -index 9e8f619..79631fc 100644 ---- a/crypto/Makefile -+++ b/crypto/Makefile -@@ -85,6 +85,8 @@ obj-$(CONFIG_CRYPTO_ANSI_CPRNG) += ansi_cprng.o - obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o - obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o - -+obj-$(CONFIG_OCF_OCF) += ocf/ -+ - # - # generic algorithms and the async_tx api - # -diff --git a/crypto/modules.builtin b/crypto/modules.builtin -new file mode 100644 -index 0000000..04825d1 ---- /dev/null -+++ b/crypto/modules.builtin -@@ -0,0 +1,22 @@ -+kernel/crypto/crypto.ko -+kernel/crypto/crypto_wq.ko -+kernel/crypto/crypto_algapi.ko -+kernel/crypto/aead.ko -+kernel/crypto/crypto_blkcipher.ko -+kernel/crypto/chainiv.ko -+kernel/crypto/eseqiv.ko -+kernel/crypto/crypto_hash.ko -+kernel/crypto/pcompress.ko -+kernel/crypto/cryptomgr.ko -+kernel/crypto/md5.ko -+kernel/crypto/ecb.ko -+kernel/crypto/cbc.ko -+kernel/crypto/des_generic.ko -+kernel/crypto/aes_generic.ko -+kernel/crypto/arc4.ko -+kernel/crypto/deflate.ko -+kernel/crypto/michael_mic.ko -+kernel/crypto/crc32c.ko -+kernel/crypto/lzo.ko -+kernel/crypto/rng.ko -+kernel/crypto/krng.ko -diff --git a/crypto/ocf/Config.in b/crypto/ocf/Config.in -new file mode 100644 -index 0000000..d722cba ---- /dev/null -+++ b/crypto/ocf/Config.in -@@ -0,0 +1,36 @@ -+############################################################################# -+ -+mainmenu_option next_comment -+comment 'OCF Configuration' -+tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF -+dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ -+ CONFIG_OCF_FIPS $CONFIG_OCF_OCF -+dep_mbool ' enable harvesting entropy for /dev/random' \ -+ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF -+dep_tristate ' cryptodev (user space support)' \ -+ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF -+dep_tristate ' cryptosoft (software crypto engine)' \ -+ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF -+dep_tristate ' safenet (HW crypto engine)' \ -+ CONFIG_OCF_SAFE $CONFIG_OCF_OCF -+dep_tristate ' IXP4xx (HW crypto engine)' \ -+ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF -+dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ -+ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX -+dep_tristate ' hifn (HW crypto engine)' \ -+ CONFIG_OCF_HIFN $CONFIG_OCF_OCF -+dep_tristate ' talitos (HW crypto engine)' \ -+ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF -+dep_tristate ' pasemi (HW crypto engine)' \ -+ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF -+dep_tristate ' ep80579 (HW crypto engine)' \ -+ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF -+dep_tristate ' Micronas c7108 (HW crypto engine)' \ -+ CONFIG_OCF_C7108 $CONFIG_OCF_OCF -+dep_tristate ' ocfnull (does no crypto)' \ -+ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF -+dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ -+ CONFIG_OCF_BENCH $CONFIG_OCF_OCF -+endmenu -+ -+############################################################################# -diff --git a/crypto/ocf/Kconfig b/crypto/ocf/Kconfig -new file mode 100644 -index 0000000..b9c24ff ---- /dev/null -+++ b/crypto/ocf/Kconfig -@@ -0,0 +1,119 @@ -+menu "OCF Configuration" -+ -+config OCF_OCF -+ tristate "OCF (Open Cryptograhic Framework)" -+ help -+ A linux port of the OpenBSD/FreeBSD crypto framework. -+ -+config OCF_RANDOMHARVEST -+ bool "crypto random --- harvest entropy for /dev/random" -+ depends on OCF_OCF -+ help -+ Includes code to harvest random numbers from devices that support it. -+ -+config OCF_FIPS -+ bool "enable fips RNG checks" -+ depends on OCF_OCF && OCF_RANDOMHARVEST -+ help -+ Run all RNG provided data through a fips check before -+ adding it /dev/random's entropy pool. -+ -+config OCF_CRYPTODEV -+ tristate "cryptodev (user space support)" -+ depends on OCF_OCF -+ help -+ The user space API to access crypto hardware. -+ -+config OCF_CRYPTOSOFT -+ tristate "cryptosoft (software crypto engine)" -+ depends on OCF_OCF -+ help -+ A software driver for the OCF framework that uses -+ the kernel CryptoAPI. -+ -+config OCF_SAFE -+ tristate "safenet (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ A driver for a number of the safenet Excel crypto accelerators. -+ Currently tested and working on the 1141 and 1741. -+ -+config OCF_IXP4XX -+ tristate "IXP4xx (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ XScale IXP4xx crypto accelerator driver. Requires the -+ Intel Access library. -+ -+config OCF_IXP4XX_SHA1_MD5 -+ bool "IXP4xx SHA1 and MD5 Hashing" -+ depends on OCF_IXP4XX -+ help -+ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. -+ Note: this is MUCH slower than using cryptosoft (software crypto engine). -+ -+config OCF_HIFN -+ tristate "hifn (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN based crypto accelerators. -+ (7951, 7955, 7956, 7751, 7811) -+ -+config OCF_HIFNHIPP -+ tristate "Hifn HIPP (HW packet crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN (HIPP) based crypto accelerators -+ (7855) -+ -+config OCF_TALITOS -+ tristate "talitos (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for Freescale's security engine (SEC/talitos). -+ -+config OCF_PASEMI -+ tristate "pasemi (HW crypto engine)" -+ depends on OCF_OCF && PPC_PASEMI -+ help -+ OCF driver for the PA Semi PWRficient DMA Engine -+ -+config OCF_EP80579 -+ tristate "ep80579 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Intel EP80579 Integrated Processor Product Line. -+ -+config OCF_CRYPTOCTEON -+ tristate "cryptocteon (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Cavium OCTEON Processors. -+ -+config OCF_KIRKWOOD -+ tristate "kirkwood (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. -+ -+config OCF_C7108 -+ tristate "Micronas 7108 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Microna 7108 Cipher processors. -+ -+config OCF_OCFNULL -+ tristate "ocfnull (fake crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for measuring ipsec overheads (does no crypto) -+ -+config OCF_BENCH -+ tristate "ocf-bench (HW crypto in-kernel benchmark)" -+ depends on OCF_OCF -+ help -+ A very simple encryption test for the in-kernel interface -+ of OCF. Also includes code to benchmark the IXP Access library -+ for comparison. -+ -+endmenu -diff --git a/crypto/ocf/Makefile b/crypto/ocf/Makefile -new file mode 100644 -index 0000000..fa951f4 ---- /dev/null -+++ b/crypto/ocf/Makefile -@@ -0,0 +1,124 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+OCF_OBJS = crypto.o criov.o -+ -+ifdef CONFIG_OCF_RANDOMHARVEST -+ OCF_OBJS += random.o -+endif -+ -+ifdef CONFIG_OCF_FIPS -+ OCF_OBJS += rndtest.o -+endif -+ -+# Add in autoconf.h to get #defines for CONFIG_xxx -+AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h -+ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) -+ EXTRA_CFLAGS += -include $(AUTOCONF_H) -+ export EXTRA_CFLAGS -+endif -+ -+ifndef obj -+ obj ?= . -+ _obj = subdir -+ mod-subdirs := safe hifn ixp4xx talitos ocfnull -+ export-objs += crypto.o criov.o random.o -+ list-multi += ocf.o -+ _slash := -+else -+ _obj = obj -+ _slash := / -+endif -+ -+EXTRA_CFLAGS += -I$(obj)/. -+ -+obj-$(CONFIG_OCF_OCF) += ocf.o -+obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o -+obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o -+obj-$(CONFIG_OCF_BENCH) += ocf-bench.o -+ -+$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) -+$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) -+$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) -+$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) -+$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) -+$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) -+$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) -+$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) -+$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) -+$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) -+ -+ocf-objs := $(OCF_OBJS) -+ -+$(list-multi) dummy1: $(ocf-objs) -+ $(LD) -r -o $@ $(ocf-objs) -+ -+.PHONY: -+clean: -+ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c -+ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -+# -+# release gen targets -+# -+ -+.PHONY: patch -+patch: -+ REL=`date +%Y%m%d`; \ -+ patch=ocf-linux-$$REL.patch; \ -+ patch24=ocf-linux-24-$$REL.patch; \ -+ patch26=ocf-linux-26-$$REL.patch; \ -+ ( \ -+ find . -name Makefile; \ -+ find . -name Config.in; \ -+ find . -name Kconfig; \ -+ find . -name README; \ -+ find . -name '*.[ch]' | grep -v '.mod.c'; \ -+ ) | while read t; do \ -+ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ -+ done > $$patch; \ -+ cat patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ -+ cat patches/linux-2.6.33-ocf.patch $$patch > $$patch26 -+ -+.PHONY: tarball -+tarball: -+ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ -+ CURDIR=`pwd`; \ -+ rm -rf /tmp/ocf-linux-$$REL*; \ -+ mkdir -p $$RELDIR/tools; \ -+ cp README* $$RELDIR; \ -+ cp patches/openss*.patch $$RELDIR; \ -+ cp patches/crypto-tools.patch $$RELDIR; \ -+ cp tools/[!C]* $$RELDIR/tools; \ -+ cd ..; \ -+ tar cvf $$RELDIR/ocf-linux.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=*.ko \ -+ --exclude=*.mod.* \ -+ --exclude=README* \ -+ --exclude=ocf-*.patch \ -+ --exclude=ocf/patches/openss*.patch \ -+ --exclude=ocf/patches/crypto-tools.patch \ -+ --exclude=ocf/tools \ -+ ocf; \ -+ gzip -9 $$RELDIR/ocf-linux.tar; \ -+ cd /tmp; \ -+ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ -+ gzip -9 ocf-linux-$$REL.tar; \ -+ cd $$CURDIR/../../user; \ -+ rm -rf /tmp/crypto-tools-$$REL*; \ -+ tar cvf /tmp/crypto-tools-$$REL.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=cryptotest \ -+ --exclude=cryptokeytest \ -+ crypto-tools; \ -+ gzip -9 /tmp/crypto-tools-$$REL.tar -+ -diff --git a/crypto/ocf/README b/crypto/ocf/README -new file mode 100644 -index 0000000..ba0a7de ---- /dev/null -+++ b/crypto/ocf/README -@@ -0,0 +1,167 @@ -+README - ocf-linux-20100325 -+--------------------------- -+ -+This README provides instructions for getting ocf-linux compiled and -+operating in a generic linux environment. For other information you -+might like to visit the home page for this project: -+ -+ http://ocf-linux.sourceforge.net/ -+ -+Adding OCF to linux -+------------------- -+ -+ Not much in this file for now, just some notes. I usually build -+ the ocf support as modules but it can be built into the kernel as -+ well. To use it: -+ -+ * mknod /dev/crypto c 10 70 -+ -+ * to add OCF to your kernel source, you have two options. Apply -+ the kernel specific patch: -+ -+ cd linux-2.4*; gunzip < ocf-linux-24-XXXXXXXX.patch.gz | patch -p1 -+ cd linux-2.6*; gunzip < ocf-linux-26-XXXXXXXX.patch.gz | patch -p1 -+ -+ if you do one of the above, then you can proceed to the next step, -+ or you can do the above process by hand with using the patches against -+ linux-2.4.35 and 2.6.33 to include the ocf code under crypto/ocf. -+ Here's how to add it: -+ -+ for 2.4.35 (and later) -+ -+ cd linux-2.4.35/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.4.35-ocf.patch -+ -+ for 2.6.23 (and later), find the kernel patch specific (or nearest) -+ to your kernel versions and then: -+ -+ cd linux-2.6.NN/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.6.NN-ocf.patch -+ -+ It should be easy to take this patch and apply it to other more -+ recent versions of the kernels. The same patches should also work -+ relatively easily on kernels as old as 2.6.11 and 2.4.18. -+ -+ * under 2.4 if you are on a non-x86 platform, you may need to: -+ -+ cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY -+ -+ so that you can build the kernel crypto support needed for the cryptosoft -+ driver. -+ -+ * For simplicity you should enable all the crypto support in your kernel -+ except for the test driver. Likewise for the OCF options. Do not -+ enable OCF crypto drivers for HW that you do not have (for example -+ ixp4xx will not compile on non-Xscale systems). -+ -+ * make sure that cryptodev.h (from ocf-linux.tar.gz) is installed as -+ crypto/cryptodev.h in an include directory that is used for building -+ applications for your platform. For example on a host system that -+ might be: -+ -+ /usr/include/crypto/cryptodev.h -+ -+ * patch your openssl-0.9.8n code with the openssl-0.9.8n.patch. -+ (NOTE: there is no longer a need to patch ssh). The patch is against: -+ openssl-0_9_8e -+ -+ If you need a patch for an older version of openssl, you should look -+ to older OCF releases. This patch is unlikely to work on older -+ openssl versions. -+ -+ openssl-0.9.8n.patch -+ - enables --with-cryptodev for non BSD systems -+ - adds -cpu option to openssl speed for calculating CPU load -+ under linux -+ - fixes null pointer in openssl speed multi thread output. -+ - fixes test keys to work with linux crypto's more stringent -+ key checking. -+ - adds MD5/SHA acceleration (Ronen Shitrit), only enabled -+ with the --with-cryptodev-digests option -+ - fixes bug in engine code caching. -+ -+ * build crypto-tools-XXXXXXXX.tar.gz if you want to try some of the BSD -+ tools for testing OCF (ie., cryptotest). -+ -+How to load the OCF drivers -+--------------------------- -+ -+ First insert the base modules: -+ -+ insmod ocf -+ insmod cryptodev -+ -+ You can then install the software OCF driver with: -+ -+ insmod cryptosoft -+ -+ and one or more of the OCF HW drivers with: -+ -+ insmod safe -+ insmod hifn7751 -+ insmod ixp4xx -+ ... -+ -+ all the drivers take a debug option to enable verbose debug so that -+ you can see what is going on. For debug you load them as: -+ -+ insmod ocf crypto_debug=1 -+ insmod cryptodev cryptodev_debug=1 -+ insmod cryptosoft swcr_debug=1 -+ -+ You may load more than one OCF crypto driver but then there is no guarantee -+ as to which will be used. -+ -+ You can also enable debug at run time on 2.6 systems with the following: -+ -+ echo 1 > /sys/module/ocf/parameters/crypto_debug -+ echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug -+ echo 1 > /sys/module/cryptosoft/parameters/swcr_debug -+ echo 1 > /sys/module/hifn7751/parameters/hifn_debug -+ echo 1 > /sys/module/safe/parameters/safe_debug -+ echo 1 > /sys/module/ixp4xx/parameters/ixp_debug -+ ... -+ -+Testing the OCF support -+----------------------- -+ -+ run "cryptotest", it should do a short test for a couple of -+ des packets. If it does everything is working. -+ -+ If this works, then ssh will use the driver when invoked as: -+ -+ ssh -c 3des username@host -+ -+ to see for sure that it is operating, enable debug as defined above. -+ -+ To get a better idea of performance run: -+ -+ cryptotest 100 4096 -+ -+ There are more options to cryptotest, see the help. -+ -+ It is also possible to use openssl to test the speed of the crypto -+ drivers. -+ -+ openssl speed -evp des -engine cryptodev -elapsed -+ openssl speed -evp des3 -engine cryptodev -elapsed -+ openssl speed -evp aes128 -engine cryptodev -elapsed -+ -+ and multiple threads (10) with: -+ -+ openssl speed -evp des -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp des3 -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10 -+ -+ for public key testing you can try: -+ -+ cryptokeytest -+ openssl speed -engine cryptodev rsa -elapsed -+ openssl speed -engine cryptodev dsa -elapsed -+ -+David McCullough -+david_mccullough@mcafee.com -diff --git a/crypto/ocf/c7108/Makefile b/crypto/ocf/c7108/Makefile -new file mode 100644 -index 0000000..e7e634b ---- /dev/null -+++ b/crypto/ocf/c7108/Makefile -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_C7108) += aes-7108.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/c7108/aes-7108.c b/crypto/ocf/c7108/aes-7108.c -new file mode 100644 -index 0000000..6dbc515 ---- /dev/null -+++ b/crypto/ocf/c7108/aes-7108.c -@@ -0,0 +1,839 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Runtime mode */ -+static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ -+static int32_t c7108_id = -1; -+static struct cipher_7108 **c7108_sessions = NULL; -+static u_int32_t c7108_sesnum = 0; -+static unsigned long iobar; -+ -+/* Crypto entry points */ -+static int c7108_process(void *, struct cryptop *, int); -+static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); -+static int c7108_freesession(void *, u_int64_t); -+ -+/* Globals */ -+static int debug = 0; -+static spinlock_t csr_mutex; -+ -+/* Generic controller-based lock */ -+#define AES_LOCK()\ -+ spin_lock(&csr_mutex) -+#define AES_UNLOCK()\ -+ spin_unlock(&csr_mutex) -+ -+/* 7108 AES register access */ -+#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) -+#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) -+#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) -+#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) -+#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) -+#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) -+ -+static int -+c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) -+{ -+ int i, nw=0; -+ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); -+ for ( i = 0; i < nw; i++) { -+ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | -+ (k8ptr[i+1] << 8) | k8ptr[i]; -+ -+ } -+ return 0; -+} -+ -+static int -+c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) -+{ -+ int i, nb=0; -+ u8* ptr = (u8*)k32ptr; -+ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); -+ for ( i = 0; i < nb; i++) -+ k8ptr[i] = ptr[i]; -+ return 0; -+} -+ -+static int -+c7108_aes_setup_dma(u32 src, u32 dst, u32 len) -+{ -+ if (len < 16) { -+ printk("len < 16\n"); -+ return -10; -+ } -+ if (len % 16) { -+ printk("len not multiple of 16\n"); -+ return -11; -+ } -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); -+ -+ return 0; -+} -+ -+static int -+c7108_aes_set_hw_iv(u8 iv[16]) -+{ -+ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); -+ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); -+ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); -+ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); -+ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); -+ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); -+ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); -+ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); -+ -+ return 0; -+} -+ -+static void -+c7108_aes_read_dkey(u32 * dkey) -+{ -+ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY0_LO); -+ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY1_LO); -+ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY2_LO); -+ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY3_LO); -+ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY4_LO); -+ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY5_LO); -+ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY6_LO); -+ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY7_LO); -+} -+ -+static int -+c7108_aes_cipher(int op, -+ u32 dst, -+ u32 src, -+ u32 len, -+ int klen, -+ u16 mode, -+ u32 key[8], -+ u8 iv[16]) -+{ -+ int rv = 0, cnt=0; -+ u16 ctrl = 0, stat = 0; -+ -+ AES_LOCK(); -+ -+ /* Setup key length */ -+ if (klen == 128) { -+ ctrl |= C7108_AES_KEY_LEN_128; -+ } else if (klen == 192) { -+ ctrl |= C7108_AES_KEY_LEN_192; -+ } else if (klen == 256) { -+ ctrl |= C7108_AES_KEY_LEN_256; -+ } else { -+ AES_UNLOCK(); -+ return -3; -+ } -+ -+ /* Check opcode */ -+ if (C7108_AES_ENCRYPT == op) { -+ ctrl |= C7108_AES_ENCRYPT; -+ } else if (C7108_AES_DECRYPT == op) { -+ ctrl |= C7108_AES_DECRYPT; -+ } else { -+ AES_UNLOCK(); -+ return -4; -+ } -+ -+ /* check mode */ -+ if ( (mode != C7108_AES_CTRL_MODE_CBC) && -+ (mode != C7108_AES_CTRL_MODE_CFB) && -+ (mode != C7108_AES_CTRL_MODE_OFB) && -+ (mode != C7108_AES_CTRL_MODE_CTR) && -+ (mode != C7108_AES_CTRL_MODE_ECB) ) { -+ AES_UNLOCK(); -+ return -5; -+ } -+ -+ /* Now set mode */ -+ ctrl |= mode; -+ -+ /* For CFB, OFB, and CTR, neither backward key -+ * expansion nor key inversion is required. -+ */ -+ if ( (C7108_AES_DECRYPT == op) && -+ (C7108_AES_CTRL_MODE_CBC == mode || -+ C7108_AES_CTRL_MODE_ECB == mode ) ){ -+ -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); -+ -+ -+ if (192 == klen) { -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); -+ -+ } else if (256 == klen) { -+ /* 256 */ -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); -+ -+ } -+ -+ } else { -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); -+ -+ } -+ -+ /* Set IV always */ -+ c7108_aes_set_hw_iv(iv); -+ -+ /* Program DMA addresses */ -+ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { -+ AES_UNLOCK(); -+ return rv; -+ } -+ -+ -+ /* Start AES cipher */ -+ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); -+ -+ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); -+ do { -+ /* TODO: interrupt mode */ -+ // printk("aes_stat=0x%x\n", stat); -+ //udelay(100); -+ } while ((cnt++ < 1000000) && -+ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); -+ -+ -+ if ((mode == C7108_AES_CTRL_MODE_ECB)|| -+ (mode == C7108_AES_CTRL_MODE_CBC)) { -+ /* Save out key when the lock is held ... */ -+ c7108_aes_read_dkey(key); -+ } -+ -+ AES_UNLOCK(); -+ return 0; -+ -+} -+ -+/* -+ * Generate a new crypto device session. -+ */ -+static int -+c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cipher_7108 **swd; -+ u_int32_t i; -+ char *algo; -+ int mode, xfm_type; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (c7108_sessions) { -+ for (i = 1; i < c7108_sesnum; i++) -+ if (c7108_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (c7108_sessions == NULL || i == c7108_sesnum) { -+ if (c7108_sessions == NULL) { -+ i = 1; /* We leave c7108_sessions[0] empty */ -+ c7108_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ c7108_sesnum *= 2; -+ -+ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), -+ GFP_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (c7108_sesnum == CRYPTO_SW_SESSIONS) -+ c7108_sesnum = 0; -+ else -+ c7108_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); -+ -+ /* Copy existing sessions */ -+ if (c7108_sessions) { -+ memcpy(swd, c7108_sessions, -+ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); -+ kfree(c7108_sessions); -+ } -+ -+ c7108_sessions = swd; -+ -+ } -+ -+ swd = &c7108_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct cipher_7108 *) -+ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); -+ if (*swd == NULL) { -+ c7108_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct cipher_7108)); -+ -+ algo = NULL; -+ mode = 0; -+ xfm_type = HW_TYPE_CIPHER; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_AES_CBC: -+ algo = "aes"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ break; -+#if 0 -+ case CRYPTO_AES_CTR: -+ algo = "aes_ctr"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+ break; -+ case CRYPTO_AES_ECB: -+ algo = "aes_ecb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; -+ break; -+ case CRYPTO_AES_OFB: -+ algo = "aes_ofb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; -+ break; -+ case CRYPTO_AES_CFB: -+ algo = "aes_cfb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; -+ break; -+#endif -+ default: -+ printk("unsupported crypto algorithm: %d\n", -+ cri->cri_alg); -+ return -EINVAL; -+ break; -+ } -+ -+ -+ if (!algo || !*algo) { -+ printk("cypher_7108_crypto: Unknown algo 0x%x\n", -+ cri->cri_alg); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (xfm_type == HW_TYPE_CIPHER) { -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i]); -+ dprintk("\n"); -+ } -+ -+ } else if (xfm_type == SW_TYPE_HMAC || -+ xfm_type == SW_TYPE_HASH) { -+ printk("cypher_7108_crypto: HMAC unsupported!\n"); -+ return -EINVAL; -+ c7108_freesession(NULL, i); -+ } else { -+ printk("cypher_7108_crypto: " -+ "Unhandled xfm_type %d\n", xfm_type); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->cri_alg = cri->cri_alg; -+ (*swd)->xfm_type = xfm_type; -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+c7108_freesession(void *arg, u_int64_t tid) -+{ -+ struct cipher_7108 *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > c7108_sesnum || c7108_sessions == NULL || -+ c7108_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = c7108_sessions[sid]) != NULL) { -+ c7108_sessions[sid] = swd->next; -+ kfree(swd); -+ } -+ return 0; -+} -+ -+/* -+ * Process a hardware request. -+ */ -+static int -+c7108_process(void *arg, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct cipher_7108 *sw; -+ u_int32_t lid; -+ int type; -+ u32 hwkey[8]; -+ -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len, skip; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || -+ c7108_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV -+ * processing this leaves us with valid skb or uiop pointers -+ * for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = c7108_sessions[lid]; -+ sw && sw->cri_alg != crd->crd_alg; -+ sw = sw->next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ type = CRYPTO_BUF_SKBUF; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ //sg[sg_num].page = virt_to_page(skb->data + skip); -+ //sg[sg_num].offset = offset_in_page(skb->data + skip); -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; -+ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ type = CRYPTO_BUF_IOV; -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip < uiop->uio_iov[sg_num].iov_len) { -+ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); -+ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += sg[sg_num].length; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ type = CRYPTO_BUF_CONTIG; -+ //sg[0].page = virt_to_page(crp->crp_buf + skip); -+ //sg[0].offset = offset_in_page(crp->crp_buf + skip); -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ //sg[0].length = sg_len; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ -+ switch (sw->xfm_type) { -+ -+ case HW_TYPE_CIPHER: { -+ -+ unsigned char iv[64]; -+ unsigned char *ivp = iv; -+ int i; -+ int ivsize = 16; /* fixed for AES */ -+ int blocksize = 16; /* fixed for AES */ -+ -+ if (sg_len < blocksize) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", -+ __FILE__, __LINE__, -+ sg_len, -+ blocksize); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_buf, -+ crd->crd_inject, -+ ivsize, -+ (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Encrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_ENCRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ -+ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| -+ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { -+ /* Read back expanded key and cache it in key -+ * context. -+ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) -+ * where you set the key once. -+ */ -+ c7108_cache_key(crd->crd_klen, -+ (u32*)hwkey, (u8*)crd->crd_key); -+#if 0 -+ printk("%s expanded key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ printk("%s0x%02x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i]); -+ printk("\n"); -+#endif -+ } -+ } -+ } -+ else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_buf, crd->crd_inject, -+ ivsize, (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Decrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, -+ sg_len, DMA_BIDIRECTIONAL); -+ -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_DECRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ } -+ } -+ } break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ case SW_TYPE_COMP: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static struct { -+ softc_device_decl sc_dev; -+} a7108dev; -+ -+static device_method_t a7108_methods = { -+/* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, c7108_newsession), -+ DEVMETHOD(cryptodev_freesession, c7108_freesession), -+ DEVMETHOD(cryptodev_process, c7108_process), -+ DEVMETHOD(cryptodev_kprocess, NULL) -+}; -+ -+static int -+cypher_7108_crypto_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); -+ -+ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); -+ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", -+ iobar, CCU_AES_REG_BASE, -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); -+ csr_mutex = SPIN_LOCK_UNLOCKED; -+ -+ memset(&a7108dev, 0, sizeof(a7108dev)); -+ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); -+ -+ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); -+ if (c7108_id < 0) -+ panic("7108: crypto device cannot initialize!"); -+ -+// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); -+ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); -+ -+ return(0); -+} -+ -+static void -+cypher_7108_crypto_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(c7108_id); -+ c7108_id = -1; -+} -+ -+module_init(cypher_7108_crypto_init); -+module_exit(cypher_7108_crypto_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); -diff --git a/crypto/ocf/c7108/aes-7108.h b/crypto/ocf/c7108/aes-7108.h -new file mode 100644 -index 0000000..48711b4 ---- /dev/null -+++ b/crypto/ocf/c7108/aes-7108.h -@@ -0,0 +1,134 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __AES_7108_H__ -+#define __AES_7108_H__ -+ -+/* Cypher 7108 AES Controller Hardware */ -+#define CCU_REG_BASE 0x1b500000 -+#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) -+#define C7108_AES_KEY0_LO (0x0000) -+#define C7108_AES_KEY0_HI (0x0004) -+#define C7108_AES_KEY1_LO (0x0008) -+#define C7108_AES_KEY1_HI (0x000c) -+#define C7108_AES_KEY2_LO (0x0010) -+#define C7108_AES_KEY2_HI (0x0014) -+#define C7108_AES_KEY3_LO (0x0018) -+#define C7108_AES_KEY3_HI (0x001c) -+#define C7108_AES_KEY4_LO (0x0020) -+#define C7108_AES_KEY4_HI (0x0024) -+#define C7108_AES_KEY5_LO (0x0028) -+#define C7108_AES_KEY5_HI (0x002c) -+#define C7108_AES_KEY6_LO (0x0030) -+#define C7108_AES_KEY6_HI (0x0034) -+#define C7108_AES_KEY7_LO (0x0038) -+#define C7108_AES_KEY7_HI (0x003c) -+#define C7108_AES_IV0_LO (0x0040) -+#define C7108_AES_IV0_HI (0x0044) -+#define C7108_AES_IV1_LO (0x0048) -+#define C7108_AES_IV1_HI (0x004c) -+#define C7108_AES_IV2_LO (0x0050) -+#define C7108_AES_IV2_HI (0x0054) -+#define C7108_AES_IV3_LO (0x0058) -+#define C7108_AES_IV3_HI (0x005c) -+ -+#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ -+#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ -+#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ -+#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ -+#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ -+ -+/* AES/Copy engine control register */ -+#define C7108_AES_CTRL (0x007c) /* AES control */ -+#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ -+ -+/* AES Cipher mode, controlled by setting Bits 2:0 */ -+#define C7108_AES_CTRL_MODE_CBC 0 -+#define C7108_AES_CTRL_MODE_CFB (1<<0) -+#define C7108_AES_CTRL_MODE_OFB (1<<1) -+#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) -+#define C7108_AES_CTRL_MODE_ECB (1<<2) -+ -+/* AES Key length , Bits 5:4 */ -+#define C7108_AES_KEY_LEN_128 0 /* 00 */ -+#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ -+#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ -+ -+/* AES Operation (crypt/decrypt), Bit 3 */ -+#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ -+#define C7108_AES_ENCRYPT 0 -+#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ -+#define C7108_AES_GO (1<<14) /* Run */ -+#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ -+ -+ -+/* Expanded key registers */ -+#define C7108_AES_EKEY0_LO (0x0080) -+#define C7108_AES_EKEY0_HI (0x0084) -+#define C7108_AES_EKEY1_LO (0x0088) -+#define C7108_AES_EKEY1_HI (0x008c) -+#define C7108_AES_EKEY2_LO (0x0090) -+#define C7108_AES_EKEY2_HI (0x0094) -+#define C7108_AES_EKEY3_LO (0x0098) -+#define C7108_AES_EKEY3_HI (0x009c) -+#define C7108_AES_EKEY4_LO (0x00a0) -+#define C7108_AES_EKEY4_HI (0x00a4) -+#define C7108_AES_EKEY5_LO (0x00a8) -+#define C7108_AES_EKEY5_HI (0x00ac) -+#define C7108_AES_EKEY6_LO (0x00b0) -+#define C7108_AES_EKEY6_HI (0x00b4) -+#define C7108_AES_EKEY7_LO (0x00b8) -+#define C7108_AES_EKEY7_HI (0x00bc) -+#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+/* Software session entry */ -+ -+#define HW_TYPE_CIPHER 0 -+#define SW_TYPE_HMAC 1 -+#define SW_TYPE_AUTH2 2 -+#define SW_TYPE_HASH 3 -+#define SW_TYPE_COMP 4 -+ -+struct cipher_7108 { -+ int xfm_type; -+ int cri_alg; -+ union { -+ struct { -+ char sw_key[HMAC_BLOCK_LEN]; -+ int sw_klen; -+ int sw_authlen; -+ } hmac; -+ } u; -+ struct cipher_7108 *next; -+}; -+ -+ -+ -+#endif /* __C7108_AES_7108_H__ */ -diff --git a/crypto/ocf/criov.c b/crypto/ocf/criov.c -new file mode 100644 -index 0000000..d04b984 ---- /dev/null -+++ b/crypto/ocf/criov.c -@@ -0,0 +1,215 @@ -+/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ -+ -+/* -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 1999 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* -+ * This macro is only for avoiding code duplication, as we need to skip -+ * given number of bytes in the same way in three functions below. -+ */ -+#define CUIO_SKIP() do { \ -+ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ -+ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ -+ while (off > 0) { \ -+ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ -+ if (off < iov->iov_len) \ -+ break; \ -+ off -= iov->iov_len; \ -+ iol--; \ -+ iov++; \ -+ } \ -+} while (0) -+ -+void -+cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+void -+cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(((caddr_t)iov->iov_base) + off, cp, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+/* -+ * Return a pointer to iov/offset of location in iovec list. -+ */ -+struct iovec * -+cuio_getptr(struct uio *uio, int loc, int *off) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ -+ while (loc >= 0) { -+ /* Normal end of search */ -+ if (loc < iov->iov_len) { -+ *off = loc; -+ return (iov); -+ } -+ -+ loc -= iov->iov_len; -+ if (iol == 0) { -+ if (loc == 0) { -+ /* Point at the end of valid data */ -+ *off = iov->iov_len; -+ return (iov); -+ } else -+ return (NULL); -+ } else { -+ iov++, iol--; -+ } -+ } -+ -+ return (NULL); -+} -+ -+EXPORT_SYMBOL(cuio_copyback); -+EXPORT_SYMBOL(cuio_copydata); -+EXPORT_SYMBOL(cuio_getptr); -+ -+ -+static void -+skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) -+{ -+ int i; -+ if (offset < skb_headlen(skb)) { -+ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); -+ len -= skb_headlen(skb); -+ cp += skb_headlen(skb); -+ } -+ offset -= skb_headlen(skb); -+ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { -+ if (offset < skb_shinfo(skb)->frags[i].size) { -+ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); -+ len -= skb_shinfo(skb)->frags[i].size; -+ cp += skb_shinfo(skb)->frags[i].size; -+ } -+ offset -= skb_shinfo(skb)->frags[i].size; -+ } -+} -+ -+void -+crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copyback((struct uio *)buf, off, size, in); -+ else -+ bcopy(in, buf + off, size); -+} -+ -+void -+crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits((struct sk_buff *)buf, off, out, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copydata((struct uio *)buf, off, size, out); -+ else -+ bcopy(buf + off, out, size); -+} -+ -+int -+crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg) -+{ -+#if 0 -+ int error; -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ error = cuio_apply((struct uio *)buf, off, len, f, arg); -+ else -+ error = (*f)(arg, buf + off, len); -+ return (error); -+#else -+ KASSERT(0, ("crypto_apply not implemented!\n")); -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(crypto_copyback); -+EXPORT_SYMBOL(crypto_copydata); -+EXPORT_SYMBOL(crypto_apply); -+ -diff --git a/crypto/ocf/crypto.c b/crypto/ocf/crypto.c -new file mode 100644 -index 0000000..1adbaa7 ---- /dev/null -+++ b/crypto/ocf/crypto.c -@@ -0,0 +1,1784 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. -+ * -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); -+#endif -+ -+/* -+ * Cryptographic Subsystem. -+ * -+ * This code is derived from the Openbsd Cryptographic Framework (OCF) -+ * that has the copyright shown below. Very little of the original -+ * code remains. -+ */ -+/*- -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000, 2001 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * keep track of whether or not we have been initialised, a big -+ * issue if we are linked into the kernel and a driver gets started before -+ * us -+ */ -+static int crypto_initted = 0; -+ -+/* -+ * Crypto drivers register themselves by allocating a slot in the -+ * crypto_drivers table with crypto_get_driverid() and then registering -+ * each algorithm they support with crypto_register() and crypto_kregister(). -+ */ -+ -+/* -+ * lock on driver table -+ * we track its state as spin_is_locked does not do anything on non-SMP boxes -+ */ -+static spinlock_t crypto_drivers_lock; -+static int crypto_drivers_locked; /* for non-SMP boxes */ -+ -+#define CRYPTO_DRIVER_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ -+ crypto_drivers_locked = 1; \ -+ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_DRIVER_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ -+ crypto_drivers_locked = 0; \ -+ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ -+ }) -+#define CRYPTO_DRIVER_ASSERT() \ -+ ({ \ -+ if (!crypto_drivers_locked) { \ -+ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ -+ } \ -+ }) -+ -+/* -+ * Crypto device/driver capabilities structure. -+ * -+ * Synchronization: -+ * (d) - protected by CRYPTO_DRIVER_LOCK() -+ * (q) - protected by CRYPTO_Q_LOCK() -+ * Not tagged fields are read-only. -+ */ -+struct cryptocap { -+ device_t cc_dev; /* (d) device/driver */ -+ u_int32_t cc_sessions; /* (d) # of sessions */ -+ u_int32_t cc_koperations; /* (d) # os asym operations */ -+ /* -+ * Largest possible operator length (in bits) for each type of -+ * encryption algorithm. XXX not used -+ */ -+ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; -+ -+ int cc_flags; /* (d) flags */ -+#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ -+ int cc_qblocked; /* (q) symmetric q blocked */ -+ int cc_kqblocked; /* (q) asymmetric q blocked */ -+ -+ int cc_unqblocked; /* (q) symmetric q blocked */ -+ int cc_unkqblocked; /* (q) asymmetric q blocked */ -+}; -+static struct cryptocap *crypto_drivers = NULL; -+static int crypto_drivers_num = 0; -+ -+/* -+ * There are two queues for crypto requests; one for symmetric (e.g. -+ * cipher) operations and one for asymmetric (e.g. MOD)operations. -+ * A single mutex is used to lock access to both queues. We could -+ * have one per-queue but having one simplifies handling of block/unblock -+ * operations. -+ */ -+static int crp_sleep = 0; -+static LIST_HEAD(crp_q); /* request queues */ -+static LIST_HEAD(crp_kq); -+ -+static spinlock_t crypto_q_lock; -+ -+int crypto_all_qblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_qblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); -+ -+int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_kqblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); -+ -+#define CRYPTO_Q_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_q_lock, q_flags); \ -+ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_Q_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ -+ }) -+ -+/* -+ * There are two queues for processing completed crypto requests; one -+ * for the symmetric and one for the asymmetric ops. We only need one -+ * but have two to avoid type futzing (cryptop vs. cryptkop). A single -+ * mutex is used to lock access to both queues. Note that this lock -+ * must be separate from the lock on request queues to insure driver -+ * callbacks don't generate lock order reversals. -+ */ -+static LIST_HEAD(crp_ret_q); /* callback queues */ -+static LIST_HEAD(crp_ret_kq); -+ -+static spinlock_t crypto_ret_q_lock; -+#define CRYPTO_RETQ_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ -+ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_RETQ_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ -+ }) -+#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *cryptop_zone; -+static kmem_cache_t *cryptodesc_zone; -+#else -+static struct kmem_cache *cryptop_zone; -+static struct kmem_cache *cryptodesc_zone; -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+#define debug crypto_debug -+int crypto_debug = 0; -+module_param(crypto_debug, int, 0644); -+MODULE_PARM_DESC(crypto_debug, "Enable debug"); -+EXPORT_SYMBOL(crypto_debug); -+ -+/* -+ * Maximum number of outstanding crypto requests before we start -+ * failing requests. We need this to prevent DOS when too many -+ * requests are arriving for us to keep up. Otherwise we will -+ * run the system out of memory. Since crypto is slow, we are -+ * usually the bottleneck that needs to say, enough is enough. -+ * -+ * We cannot print errors when this condition occurs, we are already too -+ * slow, printing anything will just kill us -+ */ -+ -+static int crypto_q_cnt = 0; -+module_param(crypto_q_cnt, int, 0444); -+MODULE_PARM_DESC(crypto_q_cnt, -+ "Current number of outstanding crypto requests"); -+ -+static int crypto_q_max = 1000; -+module_param(crypto_q_max, int, 0644); -+MODULE_PARM_DESC(crypto_q_max, -+ "Maximum number of outstanding crypto requests"); -+ -+#define bootverbose crypto_verbose -+static int crypto_verbose = 0; -+module_param(crypto_verbose, int, 0644); -+MODULE_PARM_DESC(crypto_verbose, -+ "Enable verbose crypto startup"); -+ -+int crypto_usercrypto = 1; /* userland may do crypto reqs */ -+module_param(crypto_usercrypto, int, 0644); -+MODULE_PARM_DESC(crypto_usercrypto, -+ "Enable/disable user-mode access to crypto support"); -+ -+int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ -+module_param(crypto_userasymcrypto, int, 0644); -+MODULE_PARM_DESC(crypto_userasymcrypto, -+ "Enable/disable user-mode access to asymmetric crypto support"); -+ -+int crypto_devallowsoft = 0; /* only use hardware crypto */ -+module_param(crypto_devallowsoft, int, 0644); -+MODULE_PARM_DESC(crypto_devallowsoft, -+ "Enable/disable use of software crypto support"); -+ -+/* -+ * This parameter controls the maximum number of crypto operations to -+ * do consecutively in the crypto kernel thread before scheduling to allow -+ * other processes to run. Without it, it is possible to get into a -+ * situation where the crypto thread never allows any other processes to run. -+ * Default to 1000 which should be less than one second. -+ */ -+static int crypto_max_loopcount = 1000; -+module_param(crypto_max_loopcount, int, 0644); -+MODULE_PARM_DESC(crypto_max_loopcount, -+ "Maximum number of crypto ops to do before yielding to other processes"); -+ -+static pid_t cryptoproc = (pid_t) -1; -+static struct completion cryptoproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); -+static pid_t cryptoretproc = (pid_t) -1; -+static struct completion cryptoretproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); -+ -+static int crypto_proc(void *arg); -+static int crypto_ret_proc(void *arg); -+static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); -+static int crypto_kinvoke(struct cryptkop *krp, int flags); -+static void crypto_exit(void); -+static int crypto_init(void); -+ -+static struct cryptostats cryptostats; -+ -+static struct cryptocap * -+crypto_checkdriver(u_int32_t hid) -+{ -+ if (crypto_drivers == NULL) -+ return NULL; -+ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); -+} -+ -+/* -+ * Compare a driver's list of supported algorithms against another -+ * list; return non-zero if all algorithms are supported. -+ */ -+static int -+driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) -+{ -+ const struct cryptoini *cr; -+ -+ /* See if all the algorithms are supported. */ -+ for (cr = cri; cr; cr = cr->cri_next) -+ if (cap->cc_alg[cr->cri_alg] == 0) -+ return 0; -+ return 1; -+} -+ -+/* -+ * Select a driver for a new session that supports the specified -+ * algorithms and, optionally, is constrained according to the flags. -+ * The algorithm we use here is pretty stupid; just use the -+ * first driver that supports all the algorithms we need. If there -+ * are multiple drivers we choose the driver with the fewest active -+ * sessions. We prefer hardware-backed drivers to software ones. -+ * -+ * XXX We need more smarts here (in real life too, but that's -+ * XXX another story altogether). -+ */ -+static struct cryptocap * -+crypto_select_driver(const struct cryptoini *cri, int flags) -+{ -+ struct cryptocap *cap, *best; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (driver_suitable(cap, cri)) { -+ if (best == NULL || -+ cap->cc_sessions < best->cc_sessions) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Create a new session. The crid argument specifies a crypto -+ * driver to use or constraints on a driver to select (hardware -+ * only, software only, either). Whatever driver is selected -+ * must be capable of the requested crypto algorithms. -+ */ -+int -+crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid, lid; -+ int err; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ /* -+ * Use specified driver; verify it is capable. -+ */ -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL && !driver_suitable(cap, cri)) -+ cap = NULL; -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ cap = crypto_select_driver(cri, crid); -+ /* -+ * if NULL then can't do everything in one session. -+ * XXX Fix this. We need to inject a "virtual" session -+ * XXX layer right about here. -+ */ -+ } -+ if (cap != NULL) { -+ /* Call the driver initialization routine. */ -+ hid = cap - crypto_drivers; -+ lid = hid; /* Pass the driver ID. */ -+ cap->cc_sessions++; -+ CRYPTO_DRIVER_UNLOCK(); -+ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); -+ CRYPTO_DRIVER_LOCK(); -+ if (err == 0) { -+ (*sid) = (cap->cc_flags & 0xff000000) -+ | (hid & 0x00ffffff); -+ (*sid) <<= 32; -+ (*sid) |= (lid & 0xffffffff); -+ } else -+ cap->cc_sessions--; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+crypto_remove(struct cryptocap *cap) -+{ -+ CRYPTO_DRIVER_ASSERT(); -+ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) -+ bzero(cap, sizeof(*cap)); -+} -+ -+/* -+ * Delete an existing session (or a reserved session on an unregistered -+ * driver). -+ */ -+int -+crypto_freesession(u_int64_t sid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int err = 0; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ if (crypto_drivers == NULL) { -+ err = EINVAL; -+ goto done; -+ } -+ -+ /* Determine two IDs. */ -+ hid = CRYPTO_SESID2HID(sid); -+ -+ if (hid >= crypto_drivers_num) { -+ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); -+ err = ENOENT; -+ goto done; -+ } -+ cap = &crypto_drivers[hid]; -+ -+ if (cap->cc_dev) { -+ CRYPTO_DRIVER_UNLOCK(); -+ /* Call the driver cleanup routine, if available, unlocked. */ -+ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); -+ CRYPTO_DRIVER_LOCK(); -+ } -+ -+ if (cap->cc_sessions) -+ cap->cc_sessions--; -+ -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ -+done: -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Return an unused driver id. Used by drivers prior to registering -+ * support for the algorithms they handle. -+ */ -+int32_t -+crypto_get_driverid(device_t dev, int flags) -+{ -+ struct cryptocap *newdrv; -+ int i; -+ unsigned long d_flags; -+ -+ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ printf("%s: no flags specified when registering driver\n", -+ device_get_nameunit(dev)); -+ return -1; -+ } -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ for (i = 0; i < crypto_drivers_num; i++) { -+ if (crypto_drivers[i].cc_dev == NULL && -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { -+ break; -+ } -+ } -+ -+ /* Out of entries, allocate some more. */ -+ if (i == crypto_drivers_num) { -+ /* Be careful about wrap-around. */ -+ if (2 * crypto_drivers_num <= crypto_drivers_num) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: driver count wraparound!\n"); -+ return -1; -+ } -+ -+ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (newdrv == NULL) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: no space to expand driver table!\n"); -+ return -1; -+ } -+ -+ memcpy(newdrv, crypto_drivers, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ memset(&newdrv[crypto_drivers_num], 0, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ crypto_drivers_num *= 2; -+ -+ kfree(crypto_drivers); -+ crypto_drivers = newdrv; -+ } -+ -+ /* NB: state is zero'd on free */ -+ crypto_drivers[i].cc_sessions = 1; /* Mark */ -+ crypto_drivers[i].cc_dev = dev; -+ crypto_drivers[i].cc_flags = flags; -+ if (bootverbose) -+ printf("crypto: assign %s driver id %u, flags %u\n", -+ device_get_nameunit(dev), i, flags); -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return i; -+} -+ -+/* -+ * Lookup a driver by name. We match against the full device -+ * name and unit, and against just the name. The latter gives -+ * us a simple widlcarding by device name. On success return the -+ * driver/hardware identifier; otherwise return -1. -+ */ -+int -+crypto_find_driver(const char *match) -+{ -+ int i, len = strlen(match); -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (i = 0; i < crypto_drivers_num; i++) { -+ device_t dev = crypto_drivers[i].cc_dev; -+ if (dev == NULL || -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) -+ continue; -+ if (strncmp(match, device_get_nameunit(dev), len) == 0 || -+ strncmp(match, device_get_name(dev), len) == 0) -+ break; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ return i < crypto_drivers_num ? i : -1; -+} -+ -+/* -+ * Return the device_t for the specified driver or NULL -+ * if the driver identifier is invalid. -+ */ -+device_t -+crypto_find_device_byhid(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_dev : NULL; -+} -+ -+/* -+ * Return the device/driver capabilities. -+ */ -+int -+crypto_getcaps(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_flags : 0; -+} -+ -+/* -+ * Register support for a key-related algorithm. This routine -+ * is called once for each algorithm supported a driver. -+ */ -+int -+crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ if (bootverbose) -+ printf("crypto: %s registers key alg %u flags %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , kalg -+ , flags -+ ); -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Register support for a non-key-related algorithm. This routine -+ * is called once for each such algorithm supported by a driver. -+ */ -+int -+crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, -+ driverid, alg, maxoplen, flags); -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ /* NB: algorithms are in the range [1..max] */ -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ cap->cc_max_op_len[alg] = maxoplen; -+ if (bootverbose) -+ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , alg -+ , flags -+ , maxoplen -+ ); -+ cap->cc_sessions = 0; /* Unmark */ -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+driver_finis(struct cryptocap *cap) -+{ -+ u_int32_t ses, kops; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ ses = cap->cc_sessions; -+ kops = cap->cc_koperations; -+ bzero(cap, sizeof(*cap)); -+ if (ses != 0 || kops != 0) { -+ /* -+ * If there are pending sessions, -+ * just mark as invalid. -+ */ -+ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; -+ cap->cc_sessions = ses; -+ cap->cc_koperations = kops; -+ } -+} -+ -+/* -+ * Unregister a crypto driver. If there are pending sessions using it, -+ * leave enough information around so that subsequent calls using those -+ * sessions will correctly detect the driver has been unregistered and -+ * reroute requests. -+ */ -+int -+crypto_unregister(u_int32_t driverid, int alg) -+{ -+ struct cryptocap *cap; -+ int i, err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && -+ cap->cc_alg[alg] != 0) { -+ cap->cc_alg[alg] = 0; -+ cap->cc_max_op_len[alg] = 0; -+ -+ /* Was this the last algorithm ? */ -+ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) -+ if (cap->cc_alg[i] != 0) -+ break; -+ -+ if (i == CRYPTO_ALGORITHM_MAX + 1) -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Unregister all algorithms associated with a crypto driver. -+ * If there are pending sessions using it, leave enough information -+ * around so that subsequent calls using those sessions will -+ * correctly detect the driver has been unregistered and reroute -+ * requests. -+ */ -+int -+crypto_unregister_all(u_int32_t driverid) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return err; -+} -+ -+/* -+ * Clear blockage on a driver. The what parameter indicates whether -+ * the driver is now ready for cryptop's and/or cryptokop's. -+ */ -+int -+crypto_unblock(u_int32_t driverid, int what) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ if (what & CRYPTO_SYMQ) { -+ cap->cc_qblocked = 0; -+ cap->cc_unqblocked = 0; -+ crypto_all_qblocked = 0; -+ } -+ if (what & CRYPTO_ASYMQ) { -+ cap->cc_kqblocked = 0; -+ cap->cc_unkqblocked = 0; -+ crypto_all_kqblocked = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock -+ -+ return err; -+} -+ -+/* -+ * Add a crypto request to a queue, to be processed by the kernel thread. -+ */ -+int -+crypto_dispatch(struct cryptop *crp) -+{ -+ struct cryptocap *cap; -+ int result = -1; -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cryptostats.cs_ops++; -+ -+ CRYPTO_Q_LOCK(); -+ if (crypto_q_cnt >= crypto_q_max) { -+ CRYPTO_Q_UNLOCK(); -+ cryptostats.cs_drops++; -+ return ENOMEM; -+ } -+ crypto_q_cnt++; -+ -+ /* make sure we are starting a fresh run on this crp. */ -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+ crp->crp_etype = 0; -+ -+ /* -+ * Caller marked the request to be processed immediately; dispatch -+ * it directly to the driver unless the driver is currently blocked. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { -+ int hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* Driver cannot disappear when there is an active session. */ -+ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); -+ if (!cap->cc_qblocked) { -+ crypto_all_qblocked = 0; -+ crypto_drivers[hid].cc_unqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_invoke(cap, crp, 0); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked = 1; -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ } -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ list_add(&crp->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ result = 0; -+ } else if (result == -1) { -+ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); -+ result = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ return result; -+} -+ -+/* -+ * Add an asymetric crypto request to a queue, -+ * to be processed by the kernel thread. -+ */ -+int -+crypto_kdispatch(struct cryptkop *krp) -+{ -+ int error; -+ unsigned long q_flags; -+ -+ cryptostats.cs_kops++; -+ -+ error = crypto_kinvoke(krp, krp->krp_crid); -+ if (error == ERESTART) { -+ CRYPTO_Q_LOCK(); -+ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ error = 0; -+ } -+ return error; -+} -+ -+/* -+ * Verify a driver is suitable for the specified operation. -+ */ -+static __inline int -+kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) -+{ -+ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; -+} -+ -+/* -+ * Select a driver for an asym operation. The driver must -+ * support the necessary algorithm. The caller can constrain -+ * which device is selected with the flags parameter. The -+ * algorithm we use here is pretty stupid; just use the first -+ * driver that supports the algorithms we need. If there are -+ * multiple suitable drivers we choose the driver with the -+ * fewest active operations. We prefer hardware-backed -+ * drivers to software ones when either may be used. -+ */ -+static struct cryptocap * -+crypto_select_kdriver(const struct cryptkop *krp, int flags) -+{ -+ struct cryptocap *cap, *best, *blocked; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+ blocked = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (kdriver_suitable(cap, krp)) { -+ if (best == NULL || -+ cap->cc_koperations < best->cc_koperations) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Dispatch an assymetric crypto request. -+ */ -+static int -+crypto_kinvoke(struct cryptkop *krp, int crid) -+{ -+ struct cryptocap *cap = NULL; -+ int error; -+ unsigned long d_flags; -+ -+ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); -+ KASSERT(krp->krp_callback != NULL, -+ ("%s: krp->crp_callback == NULL", __func__)); -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL) { -+ /* -+ * Driver present, it must support the necessary -+ * algorithm and, if s/w drivers are excluded, -+ * it must be registered as hardware-backed. -+ */ -+ if (!kdriver_suitable(cap, krp) || -+ (!crypto_devallowsoft && -+ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) -+ cap = NULL; -+ } -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ -+ crid &= ~CRYPTOCAP_F_SOFTWARE; -+ cap = crypto_select_kdriver(krp, crid); -+ } -+ if (cap != NULL && !cap->cc_kqblocked) { -+ krp->krp_hid = cap - crypto_drivers; -+ cap->cc_koperations++; -+ CRYPTO_DRIVER_UNLOCK(); -+ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); -+ CRYPTO_DRIVER_LOCK(); -+ if (error == ERESTART) { -+ cap->cc_koperations--; -+ CRYPTO_DRIVER_UNLOCK(); -+ return (error); -+ } -+ /* return the actual device used */ -+ krp->krp_crid = krp->krp_hid; -+ } else { -+ /* -+ * NB: cap is !NULL if device is blocked; in -+ * that case return ERESTART so the operation -+ * is resubmitted if possible. -+ */ -+ error = (cap == NULL) ? ENODEV : ERESTART; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ if (error) { -+ krp->krp_status = error; -+ crypto_kdone(krp); -+ } -+ return 0; -+} -+ -+ -+/* -+ * Dispatch a crypto request to the appropriate crypto devices. -+ */ -+static int -+crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) -+{ -+ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); -+ KASSERT(crp->crp_callback != NULL, -+ ("%s: crp->crp_callback == NULL", __func__)); -+ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CRYPTO_TIMING -+ if (crypto_timing) -+ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); -+#endif -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { -+ struct cryptodesc *crd; -+ u_int64_t nid; -+ -+ /* -+ * Driver has unregistered; migrate the session and return -+ * an error to the caller so they'll resubmit the op. -+ * -+ * XXX: What if there are more already queued requests for this -+ * session? -+ */ -+ crypto_freesession(crp->crp_sid); -+ -+ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) -+ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); -+ -+ /* XXX propagate flags from initial session? */ -+ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) -+ crp->crp_sid = nid; -+ -+ crp->crp_etype = EAGAIN; -+ crypto_done(crp); -+ return 0; -+ } else { -+ /* -+ * Invoke the driver to process the request. -+ */ -+ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); -+ } -+} -+ -+/* -+ * Release a set of crypto descriptors. -+ */ -+void -+crypto_freereq(struct cryptop *crp) -+{ -+ struct cryptodesc *crd; -+ -+ if (crp == NULL) -+ return; -+ -+#ifdef DIAGNOSTIC -+ { -+ struct cryptop *crp2; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the crypto queue (%p).", -+ crp)); -+ } -+ CRYPTO_Q_UNLOCK(); -+ CRYPTO_RETQ_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the return queue (%p).", -+ crp)); -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ } -+#endif -+ -+ while ((crd = crp->crp_desc) != NULL) { -+ crp->crp_desc = crd->crd_next; -+ kmem_cache_free(cryptodesc_zone, crd); -+ } -+ kmem_cache_free(cryptop_zone, crp); -+} -+ -+/* -+ * Acquire a set of crypto descriptors. -+ */ -+struct cryptop * -+crypto_getreq(int num) -+{ -+ struct cryptodesc *crd; -+ struct cryptop *crp; -+ -+ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); -+ if (crp != NULL) { -+ memset(crp, 0, sizeof(*crp)); -+ INIT_LIST_HEAD(&crp->crp_next); -+ init_waitqueue_head(&crp->crp_waitq); -+ while (num--) { -+ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); -+ if (crd == NULL) { -+ crypto_freereq(crp); -+ return NULL; -+ } -+ memset(crd, 0, sizeof(*crd)); -+ crd->crd_next = crp->crp_desc; -+ crp->crp_desc = crd; -+ } -+ } -+ return crp; -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_done(struct cryptop *crp) -+{ -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { -+ crp->crp_flags |= CRYPTO_F_DONE; -+ CRYPTO_Q_LOCK(); -+ crypto_q_cnt--; -+ CRYPTO_Q_UNLOCK(); -+ } else -+ printk("crypto: crypto_done op already done, flags 0x%x", -+ crp->crp_flags); -+ if (crp->crp_etype != 0) -+ cryptostats.cs_errs++; -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * CBIFSYNC means do the callback immediately only if the -+ * operation was done synchronously. Both are used to avoid -+ * doing extraneous context switches; the latter is mostly -+ * used with the software crypto driver. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_CBIMM) || -+ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && -+ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ crp->crp_callback(crp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_kdone(struct cryptkop *krp) -+{ -+ struct cryptocap *cap; -+ unsigned long d_flags; -+ -+ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) -+ printk("crypto: crypto_kdone op already done, flags 0x%x", -+ krp->krp_flags); -+ krp->krp_flags |= CRYPTO_KF_DONE; -+ if (krp->krp_status != 0) -+ cryptostats.cs_kerrs++; -+ -+ CRYPTO_DRIVER_LOCK(); -+ /* XXX: What if driver is loaded in the meantime? */ -+ if (krp->krp_hid < crypto_drivers_num) { -+ cap = &crypto_drivers[krp->krp_hid]; -+ cap->cc_koperations--; -+ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * This is used to avoid doing extraneous context switches -+ */ -+ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ krp->krp_callback(krp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+int -+crypto_getfeat(int *featp) -+{ -+ int hid, kalg, feat = 0; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ -+ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && -+ !crypto_devallowsoft) { -+ continue; -+ } -+ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) -+ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) -+ feat |= 1 << kalg; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ *featp = feat; -+ return (0); -+} -+ -+/* -+ * Crypto thread, dispatches crypto requests. -+ */ -+static int -+crypto_proc(void *arg) -+{ -+ struct cryptop *crp, *submit; -+ struct cryptkop *krp, *krpp; -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int result, hint; -+ unsigned long q_flags; -+ int loopcount = 0; -+ -+ ocf_daemonize("crypto"); -+ -+ CRYPTO_Q_LOCK(); -+ for (;;) { -+ /* -+ * we need to make sure we don't get into a busy loop with nothing -+ * to do, the two crypto_all_*blocked vars help us find out when -+ * we are all full and can do nothing on any driver or Q. If so we -+ * wait for an unblock. -+ */ -+ crypto_all_qblocked = !list_empty(&crp_q); -+ -+ /* -+ * Find the first element in the queue that can be -+ * processed and look-ahead to see if multiple ops -+ * are ready for the same driver. -+ */ -+ submit = NULL; -+ hint = 0; -+ list_for_each_entry(crp, &crp_q, crp_next) { -+ hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* -+ * Driver cannot disappear when there is an active -+ * session. -+ */ -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* Op needs to be migrated, process it. */ -+ if (submit == NULL) -+ submit = crp; -+ break; -+ } -+ if (!cap->cc_qblocked) { -+ if (submit != NULL) { -+ /* -+ * We stop on finding another op, -+ * regardless whether its for the same -+ * driver or not. We could keep -+ * searching the queue but it might be -+ * better to just use a per-driver -+ * queue instead. -+ */ -+ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) -+ hint = CRYPTO_HINT_MORE; -+ break; -+ } else { -+ submit = crp; -+ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) -+ break; -+ /* keep scanning for more are q'd */ -+ } -+ } -+ } -+ if (submit != NULL) { -+ hid = CRYPTO_SESID2HID(submit->crp_sid); -+ crypto_all_qblocked = 0; -+ list_del(&submit->crp_next); -+ crypto_drivers[hid].cc_unqblocked = 1; -+ cap = crypto_checkdriver(hid); -+ CRYPTO_Q_UNLOCK(); -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ result = crypto_invoke(cap, submit, hint); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&submit->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked=0; -+ crypto_drivers[hid].cc_unqblocked=0; -+ } -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ -+ crypto_all_kqblocked = !list_empty(&crp_kq); -+ -+ /* As above, but for key ops */ -+ krp = NULL; -+ list_for_each_entry(krpp, &crp_kq, krp_next) { -+ cap = crypto_checkdriver(krpp->krp_hid); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* -+ * Operation needs to be migrated, invalidate -+ * the assigned device so it will reselect a -+ * new one below. Propagate the original -+ * crid selection flags if supplied. -+ */ -+ krp->krp_hid = krp->krp_crid & -+ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); -+ if (krp->krp_hid == 0) -+ krp->krp_hid = -+ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; -+ break; -+ } -+ if (!cap->cc_kqblocked) { -+ krp = krpp; -+ break; -+ } -+ } -+ if (krp != NULL) { -+ crypto_all_kqblocked = 0; -+ list_del(&krp->krp_next); -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_kinvoke(krp, krp->krp_hid); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptkop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&krp->krp_next, &crp_kq); -+ cryptostats.cs_kblocks++; -+ } else -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; -+ } -+ -+ if (submit == NULL && krp == NULL) { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more ops to process. -+ * This happens either by submission or by a driver -+ * becoming unblocked and notifying us through -+ * crypto_unblock. Note that when we wakeup we -+ * start processing each queue again from the -+ * front. It's not clear that it's important to -+ * preserve this ordering since ops may finish -+ * out of order if dispatched to different devices -+ * and some become blocked while others do not. -+ */ -+ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", -+ __FUNCTION__, -+ list_empty(&crp_q), crypto_all_qblocked, -+ list_empty(&crp_kq), crypto_all_kqblocked); -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ crp_sleep = 1; -+ wait_event_interruptible(cryptoproc_wait, -+ !(list_empty(&crp_q) || crypto_all_qblocked) || -+ !(list_empty(&crp_kq) || crypto_all_kqblocked) || -+ cryptoproc == (pid_t) -1); -+ crp_sleep = 0; -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_Q_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoproc == (pid_t) -1) -+ break; -+ cryptostats.cs_intrs++; -+ } else if (loopcount > crypto_max_loopcount) { -+ /* -+ * Give other processes a chance to run if we've -+ * been using the CPU exclusively for a while. -+ */ -+ loopcount = 0; -+ schedule(); -+ } -+ loopcount++; -+ } -+ CRYPTO_Q_UNLOCK(); -+ complete_and_exit(&cryptoproc_exited, 0); -+} -+ -+/* -+ * Crypto returns thread, does callbacks for processed crypto requests. -+ * Callbacks are done here, rather than in the crypto drivers, because -+ * callbacks typically are expensive and would slow interrupt handling. -+ */ -+static int -+crypto_ret_proc(void *arg) -+{ -+ struct cryptop *crpt; -+ struct cryptkop *krpt; -+ unsigned long r_flags; -+ -+ ocf_daemonize("crypto_ret"); -+ -+ CRYPTO_RETQ_LOCK(); -+ for (;;) { -+ /* Harvest return q's for completed ops */ -+ crpt = NULL; -+ if (!list_empty(&crp_ret_q)) -+ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); -+ if (crpt != NULL) -+ list_del(&crpt->crp_next); -+ -+ krpt = NULL; -+ if (!list_empty(&crp_ret_kq)) -+ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); -+ if (krpt != NULL) -+ list_del(&krpt->krp_next); -+ -+ if (crpt != NULL || krpt != NULL) { -+ CRYPTO_RETQ_UNLOCK(); -+ /* -+ * Run callbacks unlocked. -+ */ -+ if (crpt != NULL) -+ crpt->crp_callback(crpt); -+ if (krpt != NULL) -+ krpt->krp_callback(krpt); -+ CRYPTO_RETQ_LOCK(); -+ } else { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more returns to process. -+ */ -+ dprintk("%s - sleeping\n", __FUNCTION__); -+ CRYPTO_RETQ_UNLOCK(); -+ wait_event_interruptible(cryptoretproc_wait, -+ cryptoretproc == (pid_t) -1 || -+ !list_empty(&crp_ret_q) || -+ !list_empty(&crp_ret_kq)); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_RETQ_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoretproc == (pid_t) -1) { -+ dprintk("%s - EXITING!\n", __FUNCTION__); -+ break; -+ } -+ cryptostats.cs_rets++; -+ } -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ complete_and_exit(&cryptoretproc_exited, 0); -+} -+ -+ -+#if 0 /* should put this into /proc or something */ -+static void -+db_show_drivers(void) -+{ -+ int hid; -+ -+ db_printf("%12s %4s %4s %8s %2s %2s\n" -+ , "Device" -+ , "Ses" -+ , "Kops" -+ , "Flags" -+ , "QB" -+ , "KB" -+ ); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ if (cap->cc_dev == NULL) -+ continue; -+ db_printf("%-12s %4u %4u %08x %2u %2u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , cap->cc_sessions -+ , cap->cc_koperations -+ , cap->cc_flags -+ , cap->cc_qblocked -+ , cap->cc_kqblocked -+ ); -+ } -+} -+ -+DB_SHOW_COMMAND(crypto, db_show_crypto) -+{ -+ struct cryptop *crp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", -+ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", -+ "Desc", "Callback"); -+ TAILQ_FOREACH(crp, &crp_q, crp_next) { -+ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) -+ , crp->crp_ilen, crp->crp_olen -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_desc -+ , crp->crp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("\n%4s %4s %4s %8s\n", -+ "HID", "Etype", "Flags", "Callback"); -+ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { -+ db_printf("%4u %4u %04x %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_callback -+ ); -+ } -+ } -+} -+ -+DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) -+{ -+ struct cryptkop *krp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", -+ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_kq, krp_next) { -+ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_iparams, krp->krp_oparams -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("%4s %5s %8s %4s %8s\n", -+ "Op", "Status", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { -+ db_printf("%4u %5u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ } -+} -+#endif -+ -+ -+static int -+crypto_init(void) -+{ -+ int error; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); -+ -+ if (crypto_initted) -+ return 0; -+ crypto_initted = 1; -+ -+ spin_lock_init(&crypto_drivers_lock); -+ spin_lock_init(&crypto_q_lock); -+ spin_lock_init(&crypto_ret_q_lock); -+ -+ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { -+ printk("crypto: crypto_init cannot setup crypto zones\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; -+ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (crypto_drivers == NULL) { -+ printk("crypto: crypto_init cannot setup crypto drivers\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ init_completion(&cryptoproc_exited); -+ init_completion(&cryptoretproc_exited); -+ -+ cryptoproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoproc = kernel_thread(crypto_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoproc < 0) { -+ error = cryptoproc; -+ printk("crypto: crypto_init cannot start crypto thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ cryptoretproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoretproc = kernel_thread(crypto_ret_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoretproc < 0) { -+ error = cryptoretproc; -+ printk("crypto: crypto_init cannot start cryptoret thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ return 0; -+bad: -+ crypto_exit(); -+ return error; -+} -+ -+ -+static void -+crypto_exit(void) -+{ -+ pid_t p; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Terminate any crypto threads. -+ */ -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoproc; -+ cryptoproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoproc_exited); -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoretproc; -+ cryptoretproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoretproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoretproc_exited); -+ -+ /* XXX flush queues??? */ -+ -+ /* -+ * Reclaim dynamically allocated resources. -+ */ -+ if (crypto_drivers != NULL) -+ kfree(crypto_drivers); -+ -+ if (cryptodesc_zone != NULL) -+ kmem_cache_destroy(cryptodesc_zone); -+ if (cryptop_zone != NULL) -+ kmem_cache_destroy(cryptop_zone); -+} -+ -+ -+EXPORT_SYMBOL(crypto_newsession); -+EXPORT_SYMBOL(crypto_freesession); -+EXPORT_SYMBOL(crypto_get_driverid); -+EXPORT_SYMBOL(crypto_kregister); -+EXPORT_SYMBOL(crypto_register); -+EXPORT_SYMBOL(crypto_unregister); -+EXPORT_SYMBOL(crypto_unregister_all); -+EXPORT_SYMBOL(crypto_unblock); -+EXPORT_SYMBOL(crypto_dispatch); -+EXPORT_SYMBOL(crypto_kdispatch); -+EXPORT_SYMBOL(crypto_freereq); -+EXPORT_SYMBOL(crypto_getreq); -+EXPORT_SYMBOL(crypto_done); -+EXPORT_SYMBOL(crypto_kdone); -+EXPORT_SYMBOL(crypto_getfeat); -+EXPORT_SYMBOL(crypto_userasymcrypto); -+EXPORT_SYMBOL(crypto_getcaps); -+EXPORT_SYMBOL(crypto_find_driver); -+EXPORT_SYMBOL(crypto_find_device_byhid); -+ -+module_init(crypto_init); -+module_exit(crypto_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); -diff --git a/crypto/ocf/cryptocteon/Makefile b/crypto/ocf/cryptocteon/Makefile -new file mode 100644 -index 0000000..eeed0d6 ---- /dev/null -+++ b/crypto/ocf/cryptocteon/Makefile -@@ -0,0 +1,17 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef CONFIG_OCF_CRYPTOCTEON -+# you need the cavium crypto component installed -+EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include -+endif -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/cryptocteon/cavium_crypto.c b/crypto/ocf/cryptocteon/cavium_crypto.c -new file mode 100644 -index 0000000..0254b9b ---- /dev/null -+++ b/crypto/ocf/cryptocteon/cavium_crypto.c -@@ -0,0 +1,2283 @@ -+/* -+ * Copyright (c) 2009 David McCullough -+ * -+ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights -+ * reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Cavium Networks -+ * 4. Cavium Networks' name may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * This Software, including technical data, may be subject to U.S. export -+ * control laws, including the U.S. Export Administration Act and its -+ * associated regulations, and may be subject to export or import regulations -+ * in other countries. You warrant that You will comply strictly in all -+ * respects with all such regulations and acknowledge that you have the -+ * responsibility to obtain licenses to export, re-export or import the -+ * Software. -+ * -+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND -+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, -+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE -+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR -+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM -+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, -+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF -+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR -+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR -+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. -+*/ -+/****************************************************************************/ -+ -+#include -+#include -+#include "octeon-asm.h" -+ -+/****************************************************************************/ -+ -+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); -+extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); -+ -+#define SG_INIT(s, p, i, l) \ -+ { \ -+ (i) = 0; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt((s)); \ -+ CVMX_PREFETCH0((p)); \ -+ } -+ -+#define SG_CONSUME(s, p, i, l) \ -+ { \ -+ (p)++; \ -+ (l) -= sizeof(*(p)); \ -+ if ((l) < 0) { \ -+ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ -+ } else if ((l) == 0) { \ -+ (i)++; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt(s); \ -+ CVMX_PREFETCH0((p)); \ -+ } \ -+ } -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+#define AES_CBC_IV_LENGTH 16 -+#define ESP_HMAC_LEN 12 -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_SHA_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTSHA (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_MD5_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTMD5 (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+static inline uint64_t -+swap64(uint64_t a) -+{ -+ return ((a >> 56) | -+ (((a >> 48) & 0xfful) << 8) | -+ (((a >> 40) & 0xfful) << 16) | -+ (((a >> 32) & 0xfful) << 24) | -+ (((a >> 24) & 0xfful) << 32) | -+ (((a >> 16) & 0xfful) << 40) | -+ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); -+} -+ -+/****************************************************************************/ -+ -+void -+octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) -+{ -+ uint8_t hash_key[64]; -+ uint64_t *key1; -+ register uint64_t xor1 = 0x3636363636363636ULL; -+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ flags = octeon_crypto_enable(&state); -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); -+ -+ CVMX_MF_HSH_IV(inner[0], 0); -+ CVMX_MF_HSH_IV(inner[1], 1); -+ if (auth) { -+ inner[2] = 0; -+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); -+ } -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); -+ -+ CVMX_MF_HSH_IV(outer[0], 0); -+ CVMX_MF_HSH_IV(outer[1], 1); -+ if (auth) { -+ outer[2] = 0; -+ CVMX_MF_HSH_IV(outer[2], 2); -+ } -+ octeon_crypto_disable(&state, flags); -+ return; -+} -+ -+/****************************************************************************/ -+/* DES functions */ -+ -+int -+octo_des_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_des_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES functions */ -+ -+int -+octo_aes_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_ENC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_aes_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_DEC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* MD5 */ -+ -+int -+octo_null_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* SHA1 */ -+ -+int -+octo_null_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES MD5 */ -+ -+int -+octo_des_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES SHA */ -+ -+int -+octo_des_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES MD5 */ -+ -+int -+octo_aes_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish any left over hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish left over hash if any */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES SHA1 */ -+ -+int -+octo_aes_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and leftover hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -diff --git a/crypto/ocf/cryptocteon/cryptocteon.c b/crypto/ocf/cryptocteon/cryptocteon.c -new file mode 100644 -index 0000000..9940f59 ---- /dev/null -+++ b/crypto/ocf/cryptocteon/cryptocteon.c -@@ -0,0 +1,574 @@ -+/* -+ * Octeon Crypto for OCF -+ * -+ * Written by David McCullough -+ * Copyright (C) 2009-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} octo_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+struct octo_sess { -+ int octo_encalg; -+ #define MAX_CIPHER_KEYLEN 64 -+ char octo_enckey[MAX_CIPHER_KEYLEN]; -+ int octo_encklen; -+ -+ int octo_macalg; -+ #define MAX_HASH_KEYLEN 64 -+ char octo_mackey[MAX_HASH_KEYLEN]; -+ int octo_macklen; -+ int octo_mackey_set; -+ -+ int octo_mlen; -+ int octo_ivsize; -+ -+#if 0 -+ int (*octo_decrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+ -+ int (*octo_encrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+#else -+ int (*octo_encrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ int (*octo_decrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+#endif -+ -+ uint64_t octo_hminner[3]; -+ uint64_t octo_hmouter[3]; -+}; -+ -+int32_t octo_id = -1; -+module_param(octo_id, int, 0444); -+MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); -+ -+static struct octo_sess **octo_sessions = NULL; -+static u_int32_t octo_sesnum = 0; -+ -+static int octo_process(device_t, struct cryptop *, int); -+static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int octo_freesession(device_t, u_int64_t); -+ -+static device_method_t octo_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, octo_newsession), -+ DEVMETHOD(cryptodev_freesession,octo_freesession), -+ DEVMETHOD(cryptodev_process, octo_process), -+}; -+ -+#define debug octo_debug -+int octo_debug = 0; -+module_param(octo_debug, int, 0644); -+MODULE_PARM_DESC(octo_debug, "Enable debug"); -+ -+ -+#include "cavium_crypto.c" -+ -+ -+/* -+ * Generate a new octo session. We artifically limit it to a single -+ * hash/cipher or hash-cipher combo just to make it easier, most callers -+ * do not expect more than this anyway. -+ */ -+static int -+octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct octo_sess **ocd; -+ int i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * To keep it simple, we only handle hash, cipher or hash/cipher in a -+ * session, you cannot currently do multiple ciphers/hashes in one -+ * session even though it would be possibel to code this driver to -+ * handle it. -+ */ -+ for (i = 0, c = cri; c && i < 2; i++) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) { -+ break; -+ } -+ macini = c; -+ } -+ if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) { -+ break; -+ } -+ encini = c; -+ } -+ c = c->cri_next; -+ } -+ if (!macini && !encini) { -+ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ if (c) { -+ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * So we have something we can do, lets setup the session -+ */ -+ -+ if (octo_sessions) { -+ for (i = 1; i < octo_sesnum; i++) -+ if (octo_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (octo_sessions == NULL || i == octo_sesnum) { -+ if (octo_sessions == NULL) { -+ i = 1; /* We leave octo_sessions[0] empty */ -+ octo_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ octo_sesnum *= 2; -+ -+ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); -+ if (ocd == NULL) { -+ /* Reset session number */ -+ if (octo_sesnum == CRYPTO_SW_SESSIONS) -+ octo_sesnum = 0; -+ else -+ octo_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); -+ -+ /* Copy existing sessions */ -+ if (octo_sessions) { -+ memcpy(ocd, octo_sessions, -+ (octo_sesnum / 2) * sizeof(struct octo_sess *)); -+ kfree(octo_sessions); -+ } -+ -+ octo_sessions = ocd; -+ } -+ -+ ocd = &octo_sessions[i]; -+ *sid = i; -+ -+ -+ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); -+ if (*ocd == NULL) { -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*ocd, 0, sizeof(struct octo_sess)); -+ -+ if (encini && encini->cri_key) { -+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); -+ } -+ -+ if (macini && macini->cri_key) { -+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); -+ } -+ -+ (*ocd)->octo_mlen = 0; -+ if (encini && encini->cri_mlen) -+ (*ocd)->octo_mlen = encini->cri_mlen; -+ else if (macini && macini->cri_mlen) -+ (*ocd)->octo_mlen = macini->cri_mlen; -+ else -+ (*ocd)->octo_mlen = 12; -+ -+ /* -+ * point c at the enc if it exists, otherwise the mac -+ */ -+ c = encini ? encini : macini; -+ -+ switch (c->cri_alg) { -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ (*ocd)->octo_ivsize = 8; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ (*ocd)->octo_ivsize = 16; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_null_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_null_md5_encrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; -+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; -+ -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+octo_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > octo_sesnum || octo_sessions == NULL || -+ octo_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ if (octo_sessions[sid]) -+ kfree(octo_sessions[sid]); -+ octo_sessions[sid] = NULL; -+ return 0; -+} -+ -+/* -+ * Process a request. -+ */ -+static int -+octo_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct octo_sess *od; -+ u_int32_t lid; -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ struct cryptodesc *enccrd = NULL, *maccrd = NULL; -+ unsigned char *ivp = NULL; -+ unsigned char iv_data[HASH_MAX_LEN]; -+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || -+ octo_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ od = octo_sessions[lid]; -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* point our enccrd and maccrd appropriately */ -+ crd = crp->crp_desc; -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ if (crd) { -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ } -+ if (crd) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: ENOENT - descriptors do not match session\n", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = enccrd->crd_iv; -+ } else { -+ ivp = iv_data; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); -+ } -+ -+ if (maccrd) { -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ crypt_off = enccrd->crd_skip; -+ crypt_len = enccrd->crd_len; -+ } else { /* if (maccrd) */ -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ -+ /* -+ * setup the SG list to cover the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ len = skb_headlen(skb); -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, -+ offset_in_page(skb->data)); -+ sg_len += len; -+ sg_num++; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; -+ i++) { -+ len = skb_shinfo(skb)->frags[i].size; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, -+ len, skb_shinfo(skb)->frags[i].page_offset); -+ sg_len += len; -+ sg_num++; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crp->crp_ilen && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ len = uiop->uio_iov[sg_num].iov_len; -+ sg_set_page(&sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base)); -+ sg_len += len; -+ } -+ } else { -+ sg_len = crp->crp_ilen; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, -+ offset_in_page(crp->crp_buf)); -+ sg_num = 1; -+ } -+ -+ -+ /* -+ * setup a new explicit key -+ */ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_encklen = (enccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); -+ } -+ } -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_macklen = (maccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); -+ od->octo_mackey_set = 0; -+ } -+ if (!od->octo_mackey_set) { -+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, -+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); -+ od->octo_mackey_set = 1; -+ } -+ } -+ -+ -+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) -+ (*od->octo_encrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ else -+ (*od->octo_decrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static int -+cryptocteon_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); -+ -+ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); -+ -+ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); -+ if (octo_id < 0) { -+ printk("Cryptocteon device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); -+ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); -+ //crypto_register(octo_id, CRYPTO_MD5, 0,0); -+ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); -+ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); -+ -+ return(0); -+} -+ -+static void -+cryptocteon_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(octo_id); -+ octo_id = -1; -+} -+ -+module_init(cryptocteon_init); -+module_exit(cryptocteon_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); -diff --git a/crypto/ocf/cryptodev.c b/crypto/ocf/cryptodev.c -new file mode 100644 -index 0000000..d20da17 ---- /dev/null -+++ b/crypto/ocf/cryptodev.c -@@ -0,0 +1,1061 @@ -+/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+extern asmlinkage long sys_dup(unsigned int fildes); -+ -+#define debug cryptodev_debug -+int cryptodev_debug = 0; -+module_param(cryptodev_debug, int, 0644); -+MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); -+ -+struct csession_info { -+ u_int16_t blocksize; -+ u_int16_t minkey, maxkey; -+ -+ u_int16_t keysize; -+ /* u_int16_t hashsize; */ -+ u_int16_t authsize; -+ u_int16_t authkey; -+ /* u_int16_t ctxsize; */ -+}; -+ -+struct csession { -+ struct list_head list; -+ u_int64_t sid; -+ u_int32_t ses; -+ -+ wait_queue_head_t waitq; -+ -+ u_int32_t cipher; -+ -+ u_int32_t mac; -+ -+ caddr_t key; -+ int keylen; -+ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; -+ -+ caddr_t mackey; -+ int mackeylen; -+ -+ struct csession_info info; -+ -+ struct iovec iovec; -+ struct uio uio; -+ int error; -+}; -+ -+struct fcrypt { -+ struct list_head csessions; -+ int sesn; -+}; -+ -+static struct csession *csefind(struct fcrypt *, u_int); -+static int csedelete(struct fcrypt *, struct csession *); -+static struct csession *cseadd(struct fcrypt *, struct csession *); -+static struct csession *csecreate(struct fcrypt *, u_int64_t, -+ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); -+static int csefree(struct csession *); -+ -+static int cryptodev_op(struct csession *, struct crypt_op *); -+static int cryptodev_key(struct crypt_kop *); -+static int cryptodev_find(struct crypt_find_op *); -+ -+static int cryptodev_cb(void *); -+static int cryptodev_open(struct inode *inode, struct file *filp); -+ -+/* -+ * Check a crypto identifier to see if it requested -+ * a valid crid and it's capabilities match. -+ */ -+static int -+checkcrid(int crid) -+{ -+ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int caps = 0; -+ -+ /* if the user hasn't selected a driver, then just call newsession */ -+ if (hid == 0 && typ != 0) -+ return 0; -+ -+ caps = crypto_getcaps(hid); -+ -+ /* didn't find anything with capabilities */ -+ if (caps == 0) { -+ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); -+ return EINVAL; -+ } -+ -+ /* the user didn't specify SW or HW, so the driver is ok */ -+ if (typ == 0) -+ return 0; -+ -+ /* if the type specified didn't match */ -+ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { -+ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, -+ hid, typ, caps); -+ return EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+cryptodev_op(struct csession *cse, struct crypt_op *cop) -+{ -+ struct cryptop *crp = NULL; -+ struct cryptodesc *crde = NULL, *crda = NULL; -+ int error = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (cop->len > CRYPTO_MAX_DATA_LEN) { -+ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); -+ return (E2BIG); -+ } -+ -+ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { -+ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, -+ cop->len); -+ return (EINVAL); -+ } -+ -+ cse->uio.uio_iov = &cse->iovec; -+ cse->uio.uio_iovcnt = 1; -+ cse->uio.uio_offset = 0; -+#if 0 -+ cse->uio.uio_resid = cop->len; -+ cse->uio.uio_segflg = UIO_SYSSPACE; -+ cse->uio.uio_rw = UIO_WRITE; -+ cse->uio.uio_td = td; -+#endif -+ cse->uio.uio_iov[0].iov_len = cop->len; -+ if (cse->info.authsize) -+ cse->uio.uio_iov[0].iov_len += cse->info.authsize; -+ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, -+ GFP_KERNEL); -+ -+ if (cse->uio.uio_iov[0].iov_base == NULL) { -+ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, -+ (int)cse->uio.uio_iov[0].iov_len); -+ return (ENOMEM); -+ } -+ -+ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); -+ if (crp == NULL) { -+ dprintk("%s: ENOMEM\n", __FUNCTION__); -+ error = ENOMEM; -+ goto bail; -+ } -+ -+ if (cse->info.authsize && cse->info.blocksize) { -+ if (cop->op == COP_ENCRYPT) { -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ } else { -+ crda = crp->crp_desc; -+ crde = crda->crd_next; -+ } -+ } else if (cse->info.authsize) { -+ crda = crp->crp_desc; -+ } else if (cse->info.blocksize) { -+ crde = crp->crp_desc; -+ } else { -+ dprintk("%s: bad request\n", __FUNCTION__); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, -+ cop->len))) { -+ dprintk("%s: bad copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (crda) { -+ crda->crd_skip = 0; -+ crda->crd_len = cop->len; -+ crda->crd_inject = cop->len; -+ -+ crda->crd_alg = cse->mac; -+ crda->crd_key = cse->mackey; -+ crda->crd_klen = cse->mackeylen * 8; -+ } -+ -+ if (crde) { -+ if (cop->op == COP_ENCRYPT) -+ crde->crd_flags |= CRD_F_ENCRYPT; -+ else -+ crde->crd_flags &= ~CRD_F_ENCRYPT; -+ crde->crd_len = cop->len; -+ crde->crd_inject = 0; -+ -+ crde->crd_alg = cse->cipher; -+ crde->crd_key = cse->key; -+ crde->crd_klen = cse->keylen * 8; -+ } -+ -+ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; -+ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM -+ | (cop->flags & COP_F_BATCH); -+ crp->crp_buf = (caddr_t)&cse->uio; -+ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; -+ crp->crp_sid = cse->sid; -+ crp->crp_opaque = (void *)cse; -+ -+ if (cop->iv) { -+ if (crde == NULL) { -+ error = EINVAL; -+ dprintk("%s no crde\n", __FUNCTION__); -+ goto bail; -+ } -+ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ error = EINVAL; -+ dprintk("%s arc4 with IV\n", __FUNCTION__); -+ goto bail; -+ } -+ if ((error = copy_from_user(cse->tmp_iv, cop->iv, -+ cse->info.blocksize))) { -+ dprintk("%s bad iv copy\n", __FUNCTION__); -+ goto bail; -+ } -+ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); -+ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; -+ crde->crd_skip = 0; -+ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ crde->crd_skip = 0; -+ } else if (crde) { -+ crde->crd_flags |= CRD_F_IV_PRESENT; -+ crde->crd_skip = cse->info.blocksize; -+ crde->crd_len -= cse->info.blocksize; -+ } -+ -+ if (cop->mac && crda == NULL) { -+ error = EINVAL; -+ dprintk("%s no crda\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ /* -+ * Let the dispatch run unlocked, then, interlock against the -+ * callback before checking if the operation completed and going -+ * to sleep. This insures drivers don't inherit our lock which -+ * results in a lock order reversal between crypto_dispatch forced -+ * entry and the crypto_done callback into us. -+ */ -+ error = crypto_dispatch(crp); -+ if (error) { -+ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ dprintk("%s about to WAIT\n", __FUNCTION__); -+ /* -+ * we really need to wait for driver to complete to maintain -+ * state, luckily interrupts will be remembered -+ */ -+ do { -+ error = wait_event_interruptible(crp->crp_waitq, -+ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ if (crp->crp_etype != 0) { -+ error = crp->crp_etype; -+ dprintk("%s error in crp processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cse->error) { -+ error = cse->error; -+ dprintk("%s error in cse processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->dst && (error = copy_to_user(cop->dst, -+ cse->uio.uio_iov[0].iov_base, cop->len))) { -+ dprintk("%s bad dst copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->mac && -+ (error=copy_to_user(cop->mac, -+ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, -+ cse->info.authsize))) { -+ dprintk("%s bad mac copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+bail: -+ if (crp) -+ crypto_freereq(crp); -+ if (cse->uio.uio_iov[0].iov_base) -+ kfree(cse->uio.uio_iov[0].iov_base); -+ -+ return (error); -+} -+ -+static int -+cryptodev_cb(void *op) -+{ -+ struct cryptop *crp = (struct cryptop *) op; -+ struct csession *cse = (struct csession *)crp->crp_opaque; -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crp->crp_etype; -+ if (error == EAGAIN) { -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+#ifdef NOTYET -+ /* -+ * DAVIDM I am fairly sure that we should turn this into a batch -+ * request to stop bad karma/lockup, revisit -+ */ -+ crp->crp_flags |= CRYPTO_F_BATCH; -+#endif -+ return crypto_dispatch(crp); -+ } -+ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { -+ cse->error = error; -+ wake_up_interruptible(&crp->crp_waitq); -+ } -+ return (0); -+} -+ -+static int -+cryptodevkey_cb(void *op) -+{ -+ struct cryptkop *krp = (struct cryptkop *) op; -+ dprintk("%s()\n", __FUNCTION__); -+ wake_up_interruptible(&krp->krp_waitq); -+ return (0); -+} -+ -+static int -+cryptodev_key(struct crypt_kop *kop) -+{ -+ struct cryptkop *krp = NULL; -+ int error = EINVAL; -+ int in, out, size, i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { -+ dprintk("%s params too big\n", __FUNCTION__); -+ return (EFBIG); -+ } -+ -+ in = kop->crk_iparams; -+ out = kop->crk_oparams; -+ switch (kop->crk_op) { -+ case CRK_MOD_EXP: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_MOD_EXP_CRT: -+ if (in == 6 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_DSA_SIGN: -+ if (in == 5 && out == 2) -+ break; -+ return (EINVAL); -+ case CRK_DSA_VERIFY: -+ if (in == 7 && out == 0) -+ break; -+ return (EINVAL); -+ case CRK_DH_COMPUTE_KEY: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ default: -+ return (EINVAL); -+ } -+ -+ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); -+ if (!krp) -+ return (ENOMEM); -+ bzero(krp, sizeof *krp); -+ krp->krp_op = kop->crk_op; -+ krp->krp_status = kop->crk_status; -+ krp->krp_iparams = kop->crk_iparams; -+ krp->krp_oparams = kop->crk_oparams; -+ krp->krp_crid = kop->crk_crid; -+ krp->krp_status = 0; -+ krp->krp_flags = CRYPTO_KF_CBIMM; -+ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; -+ init_waitqueue_head(&krp->krp_waitq); -+ -+ for (i = 0; i < CRK_MAXPARAM; i++) -+ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; -+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); -+ if (i >= krp->krp_iparams) -+ continue; -+ error = copy_from_user(krp->krp_param[i].crp_p, -+ kop->crk_param[i].crp_p, size); -+ if (error) -+ goto fail; -+ } -+ -+ error = crypto_kdispatch(krp); -+ if (error) -+ goto fail; -+ -+ do { -+ error = wait_event_interruptible(krp->krp_waitq, -+ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); -+ -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ kop->crk_crid = krp->krp_crid; /* device that did the work */ -+ if (krp->krp_status != 0) { -+ error = krp->krp_status; -+ goto fail; -+ } -+ -+ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, -+ size); -+ if (error) -+ goto fail; -+ } -+ -+fail: -+ if (krp) { -+ kop->crk_status = krp->krp_status; -+ for (i = 0; i < CRK_MAXPARAM; i++) { -+ if (krp->krp_param[i].crp_p) -+ kfree(krp->krp_param[i].crp_p); -+ } -+ kfree(krp); -+ } -+ return (error); -+} -+ -+static int -+cryptodev_find(struct crypt_find_op *find) -+{ -+ device_t dev; -+ -+ if (find->crid != -1) { -+ dev = crypto_find_device_byhid(find->crid); -+ if (dev == NULL) -+ return (ENOENT); -+ strlcpy(find->name, device_get_nameunit(dev), -+ sizeof(find->name)); -+ } else { -+ find->crid = crypto_find_driver(find->name); -+ if (find->crid == -1) -+ return (ENOENT); -+ } -+ return (0); -+} -+ -+static struct csession * -+csefind(struct fcrypt *fcr, u_int ses) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) -+ if (cse->ses == ses) -+ return (cse); -+ return (NULL); -+} -+ -+static int -+csedelete(struct fcrypt *fcr, struct csession *cse_del) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) { -+ if (cse == cse_del) { -+ list_del(&cse->list); -+ return (1); -+ } -+ } -+ return (0); -+} -+ -+static struct csession * -+cseadd(struct fcrypt *fcr, struct csession *cse) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ list_add_tail(&cse->list, &fcr->csessions); -+ cse->ses = fcr->sesn++; -+ return (cse); -+} -+ -+static struct csession * -+csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, -+ struct cryptoini *cria, struct csession_info *info) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); -+ if (cse == NULL) -+ return NULL; -+ memset(cse, 0, sizeof(struct csession)); -+ -+ INIT_LIST_HEAD(&cse->list); -+ init_waitqueue_head(&cse->waitq); -+ -+ cse->key = crie->cri_key; -+ cse->keylen = crie->cri_klen/8; -+ cse->mackey = cria->cri_key; -+ cse->mackeylen = cria->cri_klen/8; -+ cse->sid = sid; -+ cse->cipher = crie->cri_alg; -+ cse->mac = cria->cri_alg; -+ cse->info = *info; -+ cseadd(fcr, cse); -+ return (cse); -+} -+ -+static int -+csefree(struct csession *cse) -+{ -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crypto_freesession(cse->sid); -+ if (cse->key) -+ kfree(cse->key); -+ if (cse->mackey) -+ kfree(cse->mackey); -+ kfree(cse); -+ return(error); -+} -+ -+static int -+cryptodev_ioctl( -+ struct inode *inode, -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct cryptoini cria, crie; -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse; -+ struct csession_info info; -+ struct session2_op sop; -+ struct crypt_op cop; -+ struct crypt_kop kop; -+ struct crypt_find_op fop; -+ u_int64_t sid; -+ u_int32_t ses = 0; -+ int feat, fd, error = 0, crid; -+ mm_segment_t fs; -+ -+ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); -+ -+ switch (cmd) { -+ -+ case CRIOGET: { -+ dprintk("%s(CRIOGET)\n", __FUNCTION__); -+ fs = get_fs(); -+ set_fs(get_ds()); -+ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) -+ if (files_fdtable(current->files)->fd[fd] == filp) -+ break; -+ fd = sys_dup(fd); -+ set_fs(fs); -+ put_user(fd, (int *) arg); -+ return IS_ERR_VALUE(fd) ? fd : 0; -+ } -+ -+#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") -+ case CIOCGSESSION: -+ case CIOCGSESSION2: -+ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&info, 0, sizeof(info)); -+ memset(&sop, 0, sizeof(sop)); -+ -+ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ -+ switch (sop.cipher) { -+ case 0: -+ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_CBC: -+ info.blocksize = NULL_BLOCK_LEN; -+ info.minkey = NULL_MIN_KEY_LEN; -+ info.maxkey = NULL_MAX_KEY_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ info.blocksize = DES_BLOCK_LEN; -+ info.minkey = DES_MIN_KEY_LEN; -+ info.maxkey = DES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ info.blocksize = DES3_BLOCK_LEN; -+ info.minkey = DES3_MIN_KEY_LEN; -+ info.maxkey = DES3_MAX_KEY_LEN; -+ break; -+ case CRYPTO_BLF_CBC: -+ info.blocksize = BLOWFISH_BLOCK_LEN; -+ info.minkey = BLOWFISH_MIN_KEY_LEN; -+ info.maxkey = BLOWFISH_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAST_CBC: -+ info.blocksize = CAST128_BLOCK_LEN; -+ info.minkey = CAST128_MIN_KEY_LEN; -+ info.maxkey = CAST128_MAX_KEY_LEN; -+ break; -+ case CRYPTO_SKIPJACK_CBC: -+ info.blocksize = SKIPJACK_BLOCK_LEN; -+ info.minkey = SKIPJACK_MIN_KEY_LEN; -+ info.maxkey = SKIPJACK_MAX_KEY_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ info.blocksize = AES_BLOCK_LEN; -+ info.minkey = AES_MIN_KEY_LEN; -+ info.maxkey = AES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_ARC4: -+ info.blocksize = ARC4_BLOCK_LEN; -+ info.minkey = ARC4_MIN_KEY_LEN; -+ info.maxkey = ARC4_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAMELLIA_CBC: -+ info.blocksize = CAMELLIA_BLOCK_LEN; -+ info.minkey = CAMELLIA_MIN_KEY_LEN; -+ info.maxkey = CAMELLIA_MAX_KEY_LEN; -+ break; -+ default: -+ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ switch (sop.mac) { -+ case 0: -+ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_HMAC: -+ info.authsize = NULL_HASH_LEN; -+ break; -+ case CRYPTO_MD5: -+ info.authsize = MD5_HASH_LEN; -+ break; -+ case CRYPTO_SHA1: -+ info.authsize = SHA1_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_256: -+ info.authsize = SHA2_256_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_384: -+ info.authsize = SHA2_384_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_512: -+ info.authsize = SHA2_512_HASH_LEN; -+ break; -+ case CRYPTO_RIPEMD160: -+ info.authsize = RIPEMD160_HASH_LEN; -+ break; -+ case CRYPTO_MD5_HMAC: -+ info.authsize = MD5_HASH_LEN; -+ info.authkey = 16; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ info.authsize = SHA1_HASH_LEN; -+ info.authkey = 20; -+ break; -+ case CRYPTO_SHA2_256_HMAC: -+ info.authsize = SHA2_256_HASH_LEN; -+ info.authkey = 32; -+ break; -+ case CRYPTO_SHA2_384_HMAC: -+ info.authsize = SHA2_384_HASH_LEN; -+ info.authkey = 48; -+ break; -+ case CRYPTO_SHA2_512_HMAC: -+ info.authsize = SHA2_512_HASH_LEN; -+ info.authkey = 64; -+ break; -+ case CRYPTO_RIPEMD160_HMAC: -+ info.authsize = RIPEMD160_HASH_LEN; -+ info.authkey = 20; -+ break; -+ default: -+ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (info.blocksize) { -+ crie.cri_alg = sop.cipher; -+ crie.cri_klen = sop.keylen * 8; -+ if ((info.maxkey && sop.keylen > info.maxkey) || -+ sop.keylen < info.minkey) { -+ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); -+ if (copy_from_user(crie.cri_key, sop.key, -+ crie.cri_klen/8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ if (info.authsize) -+ crie.cri_next = &cria; -+ } -+ -+ if (info.authsize) { -+ cria.cri_alg = sop.mac; -+ cria.cri_klen = sop.mackeylen * 8; -+ if (info.authkey && sop.mackeylen != info.authkey) { -+ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, -+ CIOCGSESSSTR, sop.mackeylen, info.authkey); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (cria.cri_klen) { -+ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); -+ if (copy_from_user(cria.cri_key, sop.mackey, -+ cria.cri_klen / 8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ } -+ } -+ -+ /* NB: CIOGSESSION2 has the crid */ -+ if (cmd == CIOCGSESSION2) { -+ crid = sop.crid; -+ error = checkcrid(crid); -+ if (error) { -+ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, -+ CIOCGSESSSTR, error); -+ goto bail; -+ } -+ } else { -+ /* allow either HW or SW to be used */ -+ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); -+ if (error) { -+ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); -+ goto bail; -+ } -+ -+ cse = csecreate(fcr, sid, &crie, &cria, &info); -+ if (cse == NULL) { -+ crypto_freesession(sid); -+ error = EINVAL; -+ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); -+ goto bail; -+ } -+ sop.ses = cse->ses; -+ -+ if (cmd == CIOCGSESSION2) { -+ /* return hardware/driver id */ -+ sop.crid = CRYPTO_SESID2HID(cse->sid); -+ } -+ -+ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ } -+bail: -+ if (error) { -+ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); -+ if (crie.cri_key) -+ kfree(crie.cri_key); -+ if (cria.cri_key) -+ kfree(cria.cri_key); -+ } -+ break; -+ case CIOCFSESSION: -+ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); -+ get_user(ses, (uint32_t*)arg); -+ cse = csefind(fcr, ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ csedelete(fcr, cse); -+ error = csefree(cse); -+ break; -+ case CIOCCRYPT: -+ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); -+ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ cse = csefind(fcr, cop.ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ error = cryptodev_op(cse, &cop); -+ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCKEY: -+ case CIOCKEY2: -+ dprintk("%s(CIOCKEY)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) -+ return (EPERM); /* XXX compat? */ -+ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { -+ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ if (cmd == CIOCKEY) { -+ /* NB: crypto core enforces s/w driver use */ -+ kop.crk_crid = -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = cryptodev_key(&kop); -+ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { -+ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCASYMFEAT: -+ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) { -+ /* -+ * NB: if user asym crypto operations are -+ * not permitted return "no algorithms" -+ * so well-behaved applications will just -+ * fallback to doing them in software. -+ */ -+ feat = 0; -+ } else -+ error = crypto_getfeat(&feat); -+ if (!error) { -+ error = copy_to_user((void*)arg, &feat, sizeof(feat)); -+ } -+ break; -+ case CIOCFINDDEV: -+ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ error = cryptodev_find(&fop); -+ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ default: -+ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); -+ error = EINVAL; -+ break; -+ } -+ return(-error); -+} -+ -+#ifdef HAVE_UNLOCKED_IOCTL -+static long -+cryptodev_unlocked_ioctl( -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ return cryptodev_ioctl(NULL, filp, cmd, arg); -+} -+#endif -+ -+static int -+cryptodev_open(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (filp->private_data) { -+ printk("cryptodev: Private data already exists !\n"); -+ return(0); -+ } -+ -+ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); -+ if (!fcr) { -+ dprintk("%s() - malloc failed\n", __FUNCTION__); -+ return(-ENOMEM); -+ } -+ memset(fcr, 0, sizeof(*fcr)); -+ -+ INIT_LIST_HEAD(&fcr->csessions); -+ filp->private_data = fcr; -+ return(0); -+} -+ -+static int -+cryptodev_release(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse, *tmp; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (!filp) { -+ printk("cryptodev: No private data on release\n"); -+ return(0); -+ } -+ -+ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { -+ list_del(&cse->list); -+ (void)csefree(cse); -+ } -+ filp->private_data = NULL; -+ kfree(fcr); -+ return(0); -+} -+ -+static struct file_operations cryptodev_fops = { -+ .owner = THIS_MODULE, -+ .open = cryptodev_open, -+ .release = cryptodev_release, -+ .ioctl = cryptodev_ioctl, -+#ifdef HAVE_UNLOCKED_IOCTL -+ .unlocked_ioctl = cryptodev_unlocked_ioctl, -+#endif -+}; -+ -+static struct miscdevice cryptodev = { -+ .minor = CRYPTODEV_MINOR, -+ .name = "crypto", -+ .fops = &cryptodev_fops, -+}; -+ -+static int __init -+cryptodev_init(void) -+{ -+ int rc; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); -+ rc = misc_register(&cryptodev); -+ if (rc) { -+ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); -+ return(rc); -+ } -+ -+ return(0); -+} -+ -+static void __exit -+cryptodev_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ misc_deregister(&cryptodev); -+} -+ -+module_init(cryptodev_init); -+module_exit(cryptodev_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); -diff --git a/crypto/ocf/cryptodev.h b/crypto/ocf/cryptodev.h -new file mode 100644 -index 0000000..bb11a56 ---- /dev/null -+++ b/crypto/ocf/cryptodev.h -@@ -0,0 +1,479 @@ -+/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ -+/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef _CRYPTO_CRYPTO_H_ -+#define _CRYPTO_CRYPTO_H_ -+ -+/* Some initial values */ -+#define CRYPTO_DRIVERS_INITIAL 4 -+#define CRYPTO_SW_SESSIONS 32 -+ -+/* Hash values */ -+#define NULL_HASH_LEN 0 -+#define MD5_HASH_LEN 16 -+#define SHA1_HASH_LEN 20 -+#define RIPEMD160_HASH_LEN 20 -+#define SHA2_256_HASH_LEN 32 -+#define SHA2_384_HASH_LEN 48 -+#define SHA2_512_HASH_LEN 64 -+#define MD5_KPDK_HASH_LEN 16 -+#define SHA1_KPDK_HASH_LEN 20 -+/* Maximum hash algorithm result length */ -+#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ -+ -+/* HMAC values */ -+#define NULL_HMAC_BLOCK_LEN 1 -+#define MD5_HMAC_BLOCK_LEN 64 -+#define SHA1_HMAC_BLOCK_LEN 64 -+#define RIPEMD160_HMAC_BLOCK_LEN 64 -+#define SHA2_256_HMAC_BLOCK_LEN 64 -+#define SHA2_384_HMAC_BLOCK_LEN 128 -+#define SHA2_512_HMAC_BLOCK_LEN 128 -+/* Maximum HMAC block length */ -+#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ -+#define HMAC_IPAD_VAL 0x36 -+#define HMAC_OPAD_VAL 0x5C -+ -+/* Encryption algorithm block sizes */ -+#define NULL_BLOCK_LEN 1 -+#define DES_BLOCK_LEN 8 -+#define DES3_BLOCK_LEN 8 -+#define BLOWFISH_BLOCK_LEN 8 -+#define SKIPJACK_BLOCK_LEN 8 -+#define CAST128_BLOCK_LEN 8 -+#define RIJNDAEL128_BLOCK_LEN 16 -+#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN -+#define CAMELLIA_BLOCK_LEN 16 -+#define ARC4_BLOCK_LEN 1 -+#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ -+ -+/* Encryption algorithm min and max key sizes */ -+#define NULL_MIN_KEY_LEN 0 -+#define NULL_MAX_KEY_LEN 0 -+#define DES_MIN_KEY_LEN 8 -+#define DES_MAX_KEY_LEN 8 -+#define DES3_MIN_KEY_LEN 24 -+#define DES3_MAX_KEY_LEN 24 -+#define BLOWFISH_MIN_KEY_LEN 4 -+#define BLOWFISH_MAX_KEY_LEN 56 -+#define SKIPJACK_MIN_KEY_LEN 10 -+#define SKIPJACK_MAX_KEY_LEN 10 -+#define CAST128_MIN_KEY_LEN 5 -+#define CAST128_MAX_KEY_LEN 16 -+#define RIJNDAEL128_MIN_KEY_LEN 16 -+#define RIJNDAEL128_MAX_KEY_LEN 32 -+#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN -+#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN -+#define CAMELLIA_MIN_KEY_LEN 16 -+#define CAMELLIA_MAX_KEY_LEN 32 -+#define ARC4_MIN_KEY_LEN 1 -+#define ARC4_MAX_KEY_LEN 256 -+ -+/* Max size of data that can be processed */ -+#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 -+ -+#define CRYPTO_ALGORITHM_MIN 1 -+#define CRYPTO_DES_CBC 1 -+#define CRYPTO_3DES_CBC 2 -+#define CRYPTO_BLF_CBC 3 -+#define CRYPTO_CAST_CBC 4 -+#define CRYPTO_SKIPJACK_CBC 5 -+#define CRYPTO_MD5_HMAC 6 -+#define CRYPTO_SHA1_HMAC 7 -+#define CRYPTO_RIPEMD160_HMAC 8 -+#define CRYPTO_MD5_KPDK 9 -+#define CRYPTO_SHA1_KPDK 10 -+#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ -+#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ -+#define CRYPTO_ARC4 12 -+#define CRYPTO_MD5 13 -+#define CRYPTO_SHA1 14 -+#define CRYPTO_NULL_HMAC 15 -+#define CRYPTO_NULL_CBC 16 -+#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ -+#define CRYPTO_SHA2_256_HMAC 18 -+#define CRYPTO_SHA2_384_HMAC 19 -+#define CRYPTO_SHA2_512_HMAC 20 -+#define CRYPTO_CAMELLIA_CBC 21 -+#define CRYPTO_SHA2_256 22 -+#define CRYPTO_SHA2_384 23 -+#define CRYPTO_SHA2_512 24 -+#define CRYPTO_RIPEMD160 25 -+#define CRYPTO_ALGORITHM_MAX 25 /* Keep updated - see below */ -+ -+/* Algorithm flags */ -+#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ -+#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ -+#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ -+ -+/* -+ * Crypto driver/device flags. They can set in the crid -+ * parameter when creating a session or submitting a key -+ * op to affect the device/driver assigned. If neither -+ * of these are specified then the crid is assumed to hold -+ * the driver id of an existing (and suitable) device that -+ * must be used to satisfy the request. -+ */ -+#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ -+#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ -+ -+/* NB: deprecated */ -+struct session_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+}; -+ -+struct session2_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+ int crid; /* driver id + flags (rw) */ -+ int pad[4]; /* for future expansion */ -+}; -+ -+struct crypt_op { -+ u_int32_t ses; -+ u_int16_t op; /* i.e. COP_ENCRYPT */ -+#define COP_NONE 0 -+#define COP_ENCRYPT 1 -+#define COP_DECRYPT 2 -+ u_int16_t flags; -+#define COP_F_BATCH 0x0008 /* Batch op if possible */ -+ u_int len; -+ caddr_t src, dst; /* become iov[] inside kernel */ -+ caddr_t mac; /* must be big enough for chosen MAC */ -+ caddr_t iv; -+}; -+ -+/* -+ * Parameters for looking up a crypto driver/device by -+ * device name or by id. The latter are returned for -+ * created sessions (crid) and completed key operations. -+ */ -+struct crypt_find_op { -+ int crid; /* driver id + flags */ -+ char name[32]; /* device/driver name */ -+}; -+ -+/* bignum parameter, in packed bytes, ... */ -+struct crparam { -+ caddr_t crp_p; -+ u_int crp_nbits; -+}; -+ -+#define CRK_MAXPARAM 8 -+ -+struct crypt_kop { -+ u_int crk_op; /* ie. CRK_MOD_EXP or other */ -+ u_int crk_status; /* return status */ -+ u_short crk_iparams; /* # of input parameters */ -+ u_short crk_oparams; /* # of output parameters */ -+ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ -+ struct crparam crk_param[CRK_MAXPARAM]; -+}; -+#define CRK_ALGORITM_MIN 0 -+#define CRK_MOD_EXP 0 -+#define CRK_MOD_EXP_CRT 1 -+#define CRK_DSA_SIGN 2 -+#define CRK_DSA_VERIFY 3 -+#define CRK_DH_COMPUTE_KEY 4 -+#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ -+ -+#define CRF_MOD_EXP (1 << CRK_MOD_EXP) -+#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) -+#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) -+#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) -+#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) -+ -+/* -+ * done against open of /dev/crypto, to get a cloned descriptor. -+ * Please use F_SETFD against the cloned descriptor. -+ */ -+#define CRIOGET _IOWR('c', 100, u_int32_t) -+#define CRIOASYMFEAT CIOCASYMFEAT -+#define CRIOFINDDEV CIOCFINDDEV -+ -+/* the following are done against the cloned descriptor */ -+#define CIOCGSESSION _IOWR('c', 101, struct session_op) -+#define CIOCFSESSION _IOW('c', 102, u_int32_t) -+#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) -+#define CIOCKEY _IOWR('c', 104, struct crypt_kop) -+#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) -+#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) -+#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) -+#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) -+ -+struct cryptotstat { -+ struct timespec acc; /* total accumulated time */ -+ struct timespec min; /* min time */ -+ struct timespec max; /* max time */ -+ u_int32_t count; /* number of observations */ -+}; -+ -+struct cryptostats { -+ u_int32_t cs_ops; /* symmetric crypto ops submitted */ -+ u_int32_t cs_errs; /* symmetric crypto ops that failed */ -+ u_int32_t cs_kops; /* asymetric/key ops submitted */ -+ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ -+ u_int32_t cs_intrs; /* crypto swi thread activations */ -+ u_int32_t cs_rets; /* crypto return thread activations */ -+ u_int32_t cs_blocks; /* symmetric op driver block */ -+ u_int32_t cs_kblocks; /* symmetric op driver block */ -+ /* -+ * When CRYPTO_TIMING is defined at compile time and the -+ * sysctl debug.crypto is set to 1, the crypto system will -+ * accumulate statistics about how long it takes to process -+ * crypto requests at various points during processing. -+ */ -+ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ -+ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ -+ struct cryptotstat cs_cb; /* crypto_done -> callback */ -+ struct cryptotstat cs_finis; /* callback -> callback return */ -+ -+ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Standard initialization structure beginning */ -+struct cryptoini { -+ int cri_alg; /* Algorithm to use */ -+ int cri_klen; /* Key length, in bits */ -+ int cri_mlen; /* Number of bytes we want from the -+ entire hash. 0 means all. */ -+ caddr_t cri_key; /* key to use */ -+ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ -+ struct cryptoini *cri_next; -+}; -+ -+/* Describe boundaries of a single crypto operation */ -+struct cryptodesc { -+ int crd_skip; /* How many bytes to ignore from start */ -+ int crd_len; /* How many bytes to process */ -+ int crd_inject; /* Where to inject results, if applicable */ -+ int crd_flags; -+ -+#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ -+#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in -+ place, so don't copy. */ -+#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ -+#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ -+#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ -+#define CRD_F_COMP 0x0f /* Set when doing compression */ -+ -+ struct cryptoini CRD_INI; /* Initialization/context data */ -+#define crd_iv CRD_INI.cri_iv -+#define crd_key CRD_INI.cri_key -+#define crd_alg CRD_INI.cri_alg -+#define crd_klen CRD_INI.cri_klen -+#define crd_mlen CRD_INI.cri_mlen -+ -+ struct cryptodesc *crd_next; -+}; -+ -+/* Structure describing complete operation */ -+struct cryptop { -+ struct list_head crp_next; -+ wait_queue_head_t crp_waitq; -+ -+ u_int64_t crp_sid; /* Session ID */ -+ int crp_ilen; /* Input data total length */ -+ int crp_olen; /* Result total length */ -+ -+ int crp_etype; /* -+ * Error type (zero means no error). -+ * All error codes except EAGAIN -+ * indicate possible data corruption (as in, -+ * the data have been touched). On all -+ * errors, the crp_sid may have changed -+ * (reset to a new one), so the caller -+ * should always check and use the new -+ * value on future requests. -+ */ -+ int crp_flags; -+ -+#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ -+#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ -+#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ -+#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ -+#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ -+#define CRYPTO_F_DONE 0x0020 /* Operation completed */ -+#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ -+ -+ caddr_t crp_buf; /* Data to be processed */ -+ caddr_t crp_opaque; /* Opaque pointer, passed along */ -+ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ -+ -+ int (*crp_callback)(struct cryptop *); /* Callback function */ -+}; -+ -+#define CRYPTO_BUF_CONTIG 0x0 -+#define CRYPTO_BUF_IOV 0x1 -+#define CRYPTO_BUF_SKBUF 0x2 -+ -+#define CRYPTO_OP_DECRYPT 0x0 -+#define CRYPTO_OP_ENCRYPT 0x1 -+ -+/* -+ * Hints passed to process methods. -+ */ -+#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ -+ -+struct cryptkop { -+ struct list_head krp_next; -+ wait_queue_head_t krp_waitq; -+ -+ int krp_flags; -+#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ -+#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ -+ -+ u_int krp_op; /* ie. CRK_MOD_EXP or other */ -+ u_int krp_status; /* return status */ -+ u_short krp_iparams; /* # of input parameters */ -+ u_short krp_oparams; /* # of output parameters */ -+ u_int krp_crid; /* desired device, etc. */ -+ u_int32_t krp_hid; -+ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ -+ int (*krp_callback)(struct cryptkop *); -+}; -+ -+#include -+ -+/* -+ * Session ids are 64 bits. The lower 32 bits contain a "local id" which -+ * is a driver-private session identifier. The upper 32 bits contain a -+ * "hardware id" used by the core crypto code to identify the driver and -+ * a copy of the driver's capabilities that can be used by client code to -+ * optimize operation. -+ */ -+#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) -+#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) -+#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) -+ -+extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); -+extern int crypto_freesession(u_int64_t sid); -+#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE -+#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE -+#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ -+extern int32_t crypto_get_driverid(device_t dev, int flags); -+extern int crypto_find_driver(const char *); -+extern device_t crypto_find_device_byhid(int hid); -+extern int crypto_getcaps(int hid); -+extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags); -+extern int crypto_kregister(u_int32_t, int, u_int32_t); -+extern int crypto_unregister(u_int32_t driverid, int alg); -+extern int crypto_unregister_all(u_int32_t driverid); -+extern int crypto_dispatch(struct cryptop *crp); -+extern int crypto_kdispatch(struct cryptkop *); -+#define CRYPTO_SYMQ 0x1 -+#define CRYPTO_ASYMQ 0x2 -+extern int crypto_unblock(u_int32_t, int); -+extern void crypto_done(struct cryptop *crp); -+extern void crypto_kdone(struct cryptkop *); -+extern int crypto_getfeat(int *); -+ -+extern void crypto_freereq(struct cryptop *crp); -+extern struct cryptop *crypto_getreq(int num); -+ -+extern int crypto_usercrypto; /* userland may do crypto requests */ -+extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ -+extern int crypto_devallowsoft; /* only use hardware crypto */ -+ -+/* -+ * random number support, crypto_unregister_all will unregister -+ */ -+extern int crypto_rregister(u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); -+extern int crypto_runregister_all(u_int32_t driverid); -+ -+/* -+ * Crypto-related utility routines used mainly by drivers. -+ * -+ * XXX these don't really belong here; but for now they're -+ * kept apart from the rest of the system. -+ */ -+struct uio; -+extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); -+extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); -+extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); -+ -+extern void crypto_copyback(int flags, caddr_t buf, int off, int size, -+ caddr_t in); -+extern void crypto_copydata(int flags, caddr_t buf, int off, int size, -+ caddr_t out); -+extern int crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg); -+ -+#endif /* __KERNEL__ */ -+#endif /* _CRYPTO_CRYPTO_H_ */ -diff --git a/crypto/ocf/cryptosoft.c b/crypto/ocf/cryptosoft.c -new file mode 100644 -index 0000000..fa8838e ---- /dev/null -+++ b/crypto/ocf/cryptosoft.c -@@ -0,0 +1,1210 @@ -+/* -+ * An OCF module that uses the linux kernel cryptoapi, based on the -+ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * but is mostly unrecognisable, -+ * -+ * Written by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+#include -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+#include -+#endif -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} swcr_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+#define SW_TYPE_CIPHER 0x01 -+#define SW_TYPE_HMAC 0x02 -+#define SW_TYPE_HASH 0x04 -+#define SW_TYPE_COMP 0x08 -+#define SW_TYPE_BLKCIPHER 0x10 -+#define SW_TYPE_ALG_MASK 0x1f -+ -+#define SW_TYPE_ASYNC 0x8000 -+ -+/* We change some of the above if we have an async interface */ -+ -+#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) -+ -+#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) -+#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) -+#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) -+ -+#define SCATTERLIST_MAX 16 -+ -+struct swcr_data { -+ int sw_type; -+ int sw_alg; -+ struct crypto_tfm *sw_tfm; -+ union { -+ struct { -+ char *sw_key; -+ int sw_klen; -+ int sw_mlen; -+ } hmac; -+ void *sw_comp_buf; -+ } u; -+ struct swcr_data *sw_next; -+}; -+ -+struct swcr_req { -+ struct swcr_data *sw_head; -+ struct swcr_data *sw; -+ struct cryptop *crp; -+ struct cryptodesc *crd; -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ char result[HASH_MAX_LEN]; -+ void *crypto_req; -+}; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *swcr_req_cache; -+#else -+static struct kmem_cache *swcr_req_cache; -+#endif -+ -+#ifndef CRYPTO_TFM_MODE_CBC -+/* -+ * As of linux-2.6.21 this is no longer defined, and presumably no longer -+ * needed to be passed into the crypto core code. -+ */ -+#define CRYPTO_TFM_MODE_CBC 0 -+#define CRYPTO_TFM_MODE_ECB 0 -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ /* -+ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new -+ * API into old API. -+ */ -+ -+ /* Symmetric/Block Cipher */ -+ struct blkcipher_desc -+ { -+ struct crypto_tfm *tfm; -+ void *info; -+ }; -+ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB -+ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC -+ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_blkcipher_cast(X) X -+ #define crypto_blkcipher_tfm(X) X -+ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) -+ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) -+ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) -+ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_set_flags(x, y) /* nop */ -+ -+ /* Hash/HMAC/Digest */ -+ struct hash_desc -+ { -+ struct crypto_tfm *tfm; -+ }; -+ #define hmac(X) #X , 0 -+ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_hash_cast(X) X -+ #define crypto_hash_tfm(X) X -+ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) -+ #define crypto_hash_digest(W, X, Y, Z) \ -+ crypto_digest_digest((W)->tfm, X, sg_num, Z) -+ -+ /* Asymmetric Cipher */ -+ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) -+ -+ /* Compression */ -+ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_comp_tfm(X) X -+ #define crypto_comp_cast(X) X -+ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define plain(X) #X , 0 -+#else -+ #define ecb(X) "ecb(" #X ")" , 0 -+ #define cbc(X) "cbc(" #X ")" , 0 -+ #define hmac(X) "hmac(" #X ")" , 0 -+ #define plain(X) #X , 0 -+#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/* no ablkcipher in older kernels */ -+#define crypto_alloc_ablkcipher(a,b,c) (NULL) -+#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_ablkcipher_set_flags(a, b) /* nop */ -+#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) -+#define crypto_has_ablkcipher(a,b,c) (0) -+#else -+#define HAVE_ABLKCIPHER -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+/* no ahash in older kernels */ -+#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_alloc_ahash(a,b,c) (NULL) -+#define crypto_ahash_digestsize(x) 0 -+#else -+#define HAVE_AHASH -+#endif -+ -+struct crypto_details { -+ char *alg_name; -+ int mode; -+ int sw_type; -+}; -+ -+static struct crypto_details crypto_details[] = { -+ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, -+ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, -+ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, -+ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, -+ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, -+ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, -+ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, -+ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, -+}; -+ -+int32_t swcr_id = -1; -+module_param(swcr_id, int, 0444); -+MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); -+ -+int swcr_fail_if_compression_grows = 1; -+module_param(swcr_fail_if_compression_grows, int, 0644); -+MODULE_PARM_DESC(swcr_fail_if_compression_grows, -+ "Treat compression that results in more data as a failure"); -+ -+int swcr_no_ahash = 0; -+module_param(swcr_no_ahash, int, 0644); -+MODULE_PARM_DESC(swcr_no_ahash, -+ "Do not use async hash/hmac even if available"); -+ -+int swcr_no_ablk = 0; -+module_param(swcr_no_ablk, int, 0644); -+MODULE_PARM_DESC(swcr_no_ablk, -+ "Do not use async blk ciphers even if available"); -+ -+static struct swcr_data **swcr_sessions = NULL; -+static u_int32_t swcr_sesnum = 0; -+ -+static int swcr_process(device_t, struct cryptop *, int); -+static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int swcr_freesession(device_t, u_int64_t); -+ -+static device_method_t swcr_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, swcr_newsession), -+ DEVMETHOD(cryptodev_freesession,swcr_freesession), -+ DEVMETHOD(cryptodev_process, swcr_process), -+}; -+ -+#define debug swcr_debug -+int swcr_debug = 0; -+module_param(swcr_debug, int, 0644); -+MODULE_PARM_DESC(swcr_debug, "Enable debug"); -+ -+static void swcr_process_req(struct swcr_req *req); -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct swcr_data **swd; -+ u_int32_t i; -+ int error; -+ char *algo; -+ int mode; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (swcr_sessions) { -+ for (i = 1; i < swcr_sesnum; i++) -+ if (swcr_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (swcr_sessions == NULL || i == swcr_sesnum) { -+ if (swcr_sessions == NULL) { -+ i = 1; /* We leave swcr_sessions[0] empty */ -+ swcr_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ swcr_sesnum *= 2; -+ -+ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (swcr_sesnum == CRYPTO_SW_SESSIONS) -+ swcr_sesnum = 0; -+ else -+ swcr_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); -+ -+ /* Copy existing sessions */ -+ if (swcr_sessions) { -+ memcpy(swd, swcr_sessions, -+ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); -+ kfree(swcr_sessions); -+ } -+ -+ swcr_sessions = swd; -+ } -+ -+ swd = &swcr_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), -+ SLAB_ATOMIC); -+ if (*swd == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct swcr_data)); -+ -+ if (cri->cri_alg < 0 || -+ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ -+ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ algo = crypto_details[cri->cri_alg].alg_name; -+ if (!algo || !*algo) { -+ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ mode = crypto_details[cri->cri_alg].mode; -+ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; -+ (*swd)->sw_alg = cri->cri_alg; -+ -+ /* Algorithm specific configuration */ -+ switch (cri->cri_alg) { -+ case CRYPTO_NULL_CBC: -+ cri->cri_klen = 0; /* make it work with crypto API */ -+ break; -+ default: -+ break; -+ } -+ -+ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { -+ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ablk ? NULL : -+ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_blkcipher_tfm( -+ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", -+ algo,mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (debug) { -+ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", -+ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } else { -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ if (error) { -+ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, -+ (*swd)->sw_tfm->crt_flags); -+ swcr_freesession(NULL, i); -+ return error; -+ } -+ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { -+ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ahash ? NULL : -+ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s hash is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_hash_tfm( -+ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; -+ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, -+ SLAB_ATOMIC); -+ if ((*swd)->u.hmac.sw_key == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); -+ if (cri->cri_mlen) { -+ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; -+ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( -+ __crypto_ahash_cast((*swd)->sw_tfm)); -+ } else { -+ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( -+ crypto_hash_cast((*swd)->sw_tfm)); -+ } -+ } else if ((*swd)->sw_type & SW_TYPE_COMP) { -+ (*swd)->sw_tfm = crypto_comp_tfm( -+ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); -+ if ((*swd)->u.sw_comp_buf == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ } else { -+ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->sw_next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+swcr_freesession(device_t dev, u_int64_t tid) -+{ -+ struct swcr_data *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > swcr_sesnum || swcr_sessions == NULL || -+ swcr_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = swcr_sessions[sid]) != NULL) { -+ swcr_sessions[sid] = swd->sw_next; -+ if (swd->sw_tfm) { -+ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); -+ break; -+#endif -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: -+ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); -+ break; -+#endif -+ case SW_TYPE_BLKCIPHER: -+ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_COMP: -+ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); -+ default: -+ crypto_free_tfm(swd->sw_tfm); -+ break; -+ } -+ swd->sw_tfm = NULL; -+ } -+ if (swd->sw_type & SW_TYPE_COMP) { -+ if (swd->u.sw_comp_buf) -+ kfree(swd->u.sw_comp_buf); -+ } else { -+ if (swd->u.hmac.sw_key) -+ kfree(swd->u.hmac.sw_key); -+ } -+ kfree(swd); -+ } -+ return 0; -+} -+ -+#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) -+/* older kernels had no async interface */ -+ -+static void swcr_process_callback(struct crypto_async_request *creq, int err) -+{ -+ struct swcr_req *req = creq->data; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (err) { -+ if (err == -EINPROGRESS) -+ return; -+ dprintk("%s() fail %d\n", __FUNCTION__, -err); -+ req->crp->crp_etype = -err; -+ goto done; -+ } -+ -+ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, -+ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); -+ ahash_request_free(req->crypto_req); -+ break; -+ case SW_TYPE_ABLKCIPHER: -+ ablkcipher_request_free(req->crypto_req); -+ break; -+ default: -+ req->crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crd = req->crd->crd_next; -+ if (req->crd) { -+ swcr_process_req(req); -+ return; -+ } -+ -+done: -+ dprintk("%s crypto_done %p\n", __FUNCTION__, req); -+ crypto_done(req->crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ -+ -+ -+static void swcr_process_req(struct swcr_req *req) -+{ -+ struct swcr_data *sw; -+ struct cryptop *crp = req->crp; -+ struct cryptodesc *crd = req->crd; -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ int sg_num, sg_len, skip; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->sw = sw; -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(req->sg, 0, sizeof(req->sg)); -+ sg_init_table(req->sg, SCATTERLIST_MAX); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(skb->data + skip), len, -+ offset_in_page(skb->data + skip)); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ skb_shinfo(skb)->frags[i].page, -+ len, -+ skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip <= uiop->uio_iov[sg_num].iov_len) { -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), -+ len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += len; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), -+ sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+ -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ { -+ int ret; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crypto_req = -+ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ahash_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ memset(req->result, 0, sizeof(req->result)); -+ -+ if (sw->sw_type & SW_TYPE_AHMAC) -+ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), -+ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); -+ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); -+ ret = crypto_ahash_digest(req->crypto_req); -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ ahash_request_free(req->crypto_req); -+ goto done; -+ } -+ } break; -+#endif /* HAVE_AHASH */ -+ -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: { -+ int ret; -+ unsigned char *ivp = req->iv; -+ int ivsize = -+ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(req->iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->crypto_req = ablkcipher_request_alloc( -+ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ablkcipher_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ get_random_bytes(ivp, ivsize); -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_encrypt(req->crypto_req); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_decrypt(req->crypto_req); -+ } -+ -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_ABLKCIPHER */ -+ -+ case SW_TYPE_BLKCIPHER: { -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ unsigned char *ivp = iv; -+ struct blkcipher_desc desc; -+ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); -+ } -+ } break; -+ -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ { -+ char result[HASH_MAX_LEN]; -+ struct hash_desc desc; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_hash_cast(sw->sw_tfm); -+ -+ memset(result, 0, sizeof(result)); -+ -+ if (sw->sw_type & SW_TYPE_HMAC) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, -+ req->sg, sg_num, result); -+#else -+ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, -+ sw->u.hmac.sw_klen); -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+ } else { /* SW_TYPE_HASH */ -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+ } -+ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, sw->u.hmac.sw_mlen, result); -+ } -+ break; -+ -+ case SW_TYPE_COMP: { -+ void *ibuf = NULL; -+ void *obuf = sw->u.sw_comp_buf; -+ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; -+ int ret = 0; -+ -+ /* -+ * we need to use an additional copy if there is more than one -+ * input chunk since the kernel comp routines do not handle -+ * SG yet. Otherwise we just use the input buffer as is. -+ * Rather than allocate another buffer we just split the tmp -+ * buffer we already have. -+ * Perhaps we should just use zlib directly ? -+ */ -+ if (sg_num > 1) { -+ int blk; -+ -+ ibuf = obuf; -+ for (blk = 0; blk < sg_num; blk++) { -+ memcpy(obuf, sg_virt(&req->sg[blk]), -+ req->sg[blk].length); -+ obuf += req->sg[blk].length; -+ } -+ olen -= sg_len; -+ } else -+ ibuf = sg_virt(&req->sg[0]); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ -+ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && olen > crd->crd_len) { -+ dprintk("cryptosoft: ERANGE compress %d into %d\n", -+ crd->crd_len, olen); -+ if (swcr_fail_if_compression_grows) -+ ret = ERANGE; -+ } -+ } else { /* decompress */ -+ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { -+ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " -+ "space for %d,at offset %d\n", -+ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); -+ ret = ETOOSMALL; -+ } -+ } -+ if (ret) -+ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); -+ -+ /* -+ * on success copy result back, -+ * linux crpyto API returns -errno, we need to fix that -+ */ -+ crp->crp_etype = ret < 0 ? -ret : ret; -+ if (ret == 0) { -+ /* copy back the result and return it's size */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, olen, obuf); -+ crp->crp_olen = olen; -+ } -+ -+ -+ } break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+ -+ -+/* -+ * Process a crypto request. -+ */ -+static int -+swcr_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct swcr_req *req = NULL; -+ u_int32_t lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || -+ swcr_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); -+ if (req == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memset(req, 0, sizeof(*req)); -+ -+ req->sw_head = swcr_sessions[lid]; -+ req->crp = crp; -+ req->crd = crp->crp_desc; -+ -+ swcr_process_req(req); -+ return 0; -+ -+done: -+ crypto_done(crp); -+ if (req) -+ kmem_cache_free(swcr_req_cache, req); -+ return 0; -+} -+ -+ -+static int -+cryptosoft_init(void) -+{ -+ int i, sw_type, mode; -+ char *algo; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); -+ -+ swcr_req_cache = kmem_cache_create("cryptosoft_req", -+ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!swcr_req_cache) { -+ printk("cryptosoft: failed to create request cache\n"); -+ return -ENOENT; -+ } -+ -+ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); -+ -+ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), -+ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); -+ if (swcr_id < 0) { -+ printk("cryptosoft: Software crypto device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+#define REGISTER(alg) \ -+ crypto_register(swcr_id, alg, 0,0) -+ -+ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { -+ int found; -+ -+ algo = crypto_details[i].alg_name; -+ if (!algo || !*algo) { -+ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); -+ continue; -+ } -+ -+ mode = crypto_details[i].mode; -+ sw_type = crypto_details[i].sw_type; -+ -+ found = 0; -+ switch (sw_type & SW_TYPE_ALG_MASK) { -+ case SW_TYPE_CIPHER: -+ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_HMAC: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_HASH: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_COMP: -+ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_BLKCIPHER: -+ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); -+ if (!found && !swcr_no_ablk) -+ found = crypto_has_ablkcipher(algo, 0, 0); -+ break; -+ } -+ if (found) { -+ REGISTER(i); -+ } else { -+ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", -+ __FUNCTION__, sw_type, i, algo); -+ } -+ } -+ return 0; -+} -+ -+static void -+cryptosoft_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(swcr_id); -+ swcr_id = -1; -+ kmem_cache_destroy(swcr_req_cache); -+} -+ -+late_initcall(cryptosoft_init); -+module_exit(cryptosoft_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); -diff --git a/crypto/ocf/ep80579/Makefile b/crypto/ocf/ep80579/Makefile -new file mode 100644 -index 0000000..e488374 ---- /dev/null -+++ b/crypto/ocf/ep80579/Makefile -@@ -0,0 +1,119 @@ -+######################################################################### -+# -+# Targets supported -+# all - builds everything and installs -+# install - identical to all -+# depend - build dependencies -+# clean - clears derived objects except the .depend files -+# distclean- clears all derived objects and the .depend file -+# -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.2-229 -+############################################################################ -+ -+ -+####################Common variables and definitions######################## -+ -+ifndef ICP_ROOT -+$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ -+ "-> setenv ICP_ROOT ") -+all fastdep: -+ : -+else -+ -+ifndef KERNEL_SOURCE_ROOT -+$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ -+ "-> setenv KERNEL_SOURCE_ROOT ") -+endif -+ -+# Ensure The ENV_DIR environmental var is defined. -+ifndef ICP_ENV_DIR -+$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ -+ "-> setenv ICP_ENV_DIR ") -+endif -+ -+#Add your project environment Makefile -+include ${ICP_ENV_DIR}/environment.mk -+ -+#include the makefile with all the default and common Make variable definitions -+include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk -+ -+#Add the name for the executable, Library or Module output definitions -+OUTPUT_NAME= icp_ocf -+ -+# List of Source Files to be compiled -+SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c -+ -+#common includes between all supported OSes -+INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ -+-I${ICP_OCF_SRC_DIR} -+ -+# The location of the os level makefile needs to be changed. -+include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk -+ -+# On the line directly below list the outputs you wish to build for, -+# e.g "lib_static lib_shared exe module" as shown below -+install: module -+ -+###################Include rules makefiles######################## -+include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk -+###################End of Rules inclusion######################### -+ -+endif -diff --git a/crypto/ocf/ep80579/icp_asym.c b/crypto/ocf/ep80579/icp_asym.c -new file mode 100644 -index 0000000..ebdddc1 ---- /dev/null -+++ b/crypto/ocf/ep80579/icp_asym.c -@@ -0,0 +1,1334 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+#include "icp_ocf.h" -+ -+/*The following define values (containing the word 'INDEX') are used to find -+the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). -+These values were found through analysis of the OCF OpenSSL patch. If the -+calling program uses different input buffer positions, these defines will have -+to be changed.*/ -+ -+/*DIFFIE HELLMAN buffer index values*/ -+#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) -+#define ICP_DH_KRP_PARAM_BASE_INDEX (1) -+#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) -+#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP buffer index values*/ -+#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) -+#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) -+#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) -+#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP CRT buffer index values*/ -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) -+ -+/*DSA sign buffer index values*/ -+#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) -+#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) -+#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) -+ -+/*DSA verify buffer index values*/ -+#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) -+ -+/*DSA sign prime Q vs random number K size check values*/ -+#define DONT_RUN_LESS_THAN_CHECK (0) -+#define FAIL_A_IS_GREATER_THAN_B (1) -+#define FAIL_A_IS_EQUAL_TO_B (1) -+#define SUCCESS_A_IS_LESS_THAN_B (0) -+#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) -+ -+/* We need to set a cryptokp success value just in case it is set or allocated -+ and not set to zero outside of this module */ -+#define CRYPTO_OP_SUCCESS (0) -+ -+/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); -+ -+/*Function to compute a Modular Exponentiation (Mod Exp)*/ -+static int icp_ocfDrvModExp(struct cryptkop *krp); -+ -+/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp); -+ -+/*Helper function to compute whether the first big number argument is less than -+ the second big number argument */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); -+ -+/*Function to sign an input with DSA R and S keys*/ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp); -+ -+/*Function to Verify a DSA buffer signature*/ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp); -+ -+/*Callback function for DH operation*/ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); -+ -+/*Callback function for ME operation*/ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pResult); -+ -+/*Callback function for ME CRT operation*/ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData); -+ -+/*Callback function for DSA sign operation*/ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS); -+ -+/*Callback function for DSA Verify operation*/ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus); -+ -+/* Name : icp_ocfDrvPkeProcess -+ * -+ * Description : This function will choose which PKE process to follow -+ * based on the input arguments -+ */ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ if (NULL == krp) { -+ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", -+ __FUNCTION__, krp); -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ switch (krp->krp_op) { -+ case CRK_DH_COMPUTE_KEY: -+ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDHComputeKey(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " -+ "(%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP: -+ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExp(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP_CRT: -+ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExpCRT(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExpCRT " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_SIGN: -+ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaSign(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaSign " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_VERIFY: -+ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaVerify(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaVerify " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ default: -+ EPRINTK("%s(): Asymettric function not " -+ "supported (%d).\n", __FUNCTION__, krp->krp_op); -+ krp->krp_status = EOPNOTSUPP; -+ return EOPNOTSUPP; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvSwapBytes -+ * -+ * Description : This function is used to swap the byte order of a buffer. -+ * It has been seen that in general we are passed little endian byte order -+ * buffers, but LAC only accepts big endian byte order buffers. -+ */ -+static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) -+{ -+ -+ int i; -+ u_int8_t *end_ptr; -+ u_int8_t hold_val; -+ -+ end_ptr = num + (buff_len_bytes - 1); -+ buff_len_bytes = buff_len_bytes >> 1; -+ for (i = 0; i < buff_len_bytes; i++) { -+ hold_val = *num; -+ *num = *end_ptr; -+ num++; -+ *end_ptr = hold_val; -+ end_ptr--; -+ } -+} -+ -+/* Name : icp_ocfDrvDHComputeKey -+ * -+ * Description : This function will map Diffie Hellman calls from OCF -+ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and -+ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases -+ * break down to a modular exponentiation. -+ */ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ CpaFlatBuffer *pLocalOctetStringPV = NULL; -+ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; -+ -+ /* Input checks - check prime is a multiple of 8 bits to allow for -+ allocation later */ -+ dh_prime_len_bits = -+ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); -+ -+ /* LAC can reject prime lengths based on prime key sizes, we just -+ need to make sure we can allocate space for the base and -+ exponent buffers correctly */ -+ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { -+ APRINTK("%s(): Warning Prime number buffer size is not a " -+ "multiple of 8 bits\n", __FUNCTION__); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (dh_prime_len_bits != -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ DPRINTK("%s(): Return Buffer must be the same size " -+ "as the Prime buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ /* Switch to size in bytes */ -+ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); -+ -+ callbackTag = krp; -+ -+/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting -+called in interrupt context*/ -+ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); -+ if (NULL == pPhase1OpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pLocalOctetStringPV = -+ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pLocalOctetStringPV) { -+ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pPhase1OpData->primeP.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; -+ -+ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); -+ -+ pPhase1OpData->baseG.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, -+ pPhase1OpData->baseG.dataLenInBytes); -+ -+ pPhase1OpData->privateValueX.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, -+ pPhase1OpData->privateValueX.dataLenInBytes); -+ -+ /* Output parameters */ -+ pLocalOctetStringPV->pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); -+ -+ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDhP1CallBack, -+ callbackTag, pPhase1OpData, -+ pLocalOctetStringPV); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExp -+ * -+ * Description : This function will map ordinary Modular Exponentiation calls -+ * from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvModExp(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyLnModExpOpData *pModExpOpData = NULL; -+ CpaFlatBuffer *pResult = NULL; -+ -+ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % -+ NUM_BITS_IN_BYTE) != 0) { -+ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " -+ "multiple of 8 bits\n", __FUNCTION__, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ APRINTK("%s(): Return Buffer size must be the same or" -+ " greater than the Modulus buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ -+ callbackTag = krp; -+ -+ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); -+ if (NULL == pModExpOpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pResult) { -+ APRINTK("%s():Failed to get memory for ModExp result\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pModExpOpData->modulus.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, -+ pModExpOpData->modulus.dataLenInBytes); -+ -+ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); -+ pModExpOpData->base.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, -+ pModExpOpData->base.dataLenInBytes); -+ -+ pModExpOpData->exponent.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, -+ pModExpOpData->exponent.dataLenInBytes); -+ /* Output parameters */ -+ pResult->pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, -+ BITS_TO_BYTES(pResult->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCallBack, -+ callbackTag, pModExpOpData, pResult); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExpCRT -+ * -+ * Description : This function will map ordinary Modular Exponentiation Chinese -+ * Remainder Theorem implementaion calls from OCF to the LAC API. -+ * -+ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 -+ * decrypt operation. Therefore P and Q input values must always be prime -+ * numbers. Although basic primality checks are done in LAC, it is up to the -+ * user to do any correct prime number checking before passing the inputs. -+ */ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; -+ void *callbackTag = NULL; -+ CpaFlatBuffer *pOutputData = NULL; -+ -+ /*Parameter input checks are all done by LAC, no need to repeat -+ them here. */ -+ callbackTag = krp; -+ -+ rsaDecryptOpData = -+ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey -+ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { -+ APRINTK("%s():Failed to get memory for MOD EXP CRT" -+ " private key values struct\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pOutputData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT output data\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ /* Link parameters */ -+ rsaDecryptOpData->inputData.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, -+ rsaDecryptOpData->inputData.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime1P.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime2Q.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ exponent1Dp.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes); -+ -+ /* Output Parameter */ -+ pOutputData->pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pOutputData->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCRTCallBack, -+ callbackTag, rsaDecryptOpData, pOutputData); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvCheckALessThanB -+ * -+ * Description : This function will check whether the first argument is less -+ * than the second. It is used to check whether the DSA RS sign Random K -+ * value is less than the Prime Q value (as defined in the specification) -+ * -+ */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) -+{ -+ -+ uint8_t *MSB_K = pK->pData; -+ uint8_t *MSB_Q = pQ->pData; -+ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; -+ -+ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+/*Check MSBs -+if A == B, check next MSB -+if A > B, return A_IS_GREATER_THAN_B -+if A < B, return A_IS_LESS_THAN_B (success) -+*/ -+ while (*MSB_K == *MSB_Q) { -+ MSB_K++; -+ MSB_Q++; -+ -+ buffer_lengths_in_bytes--; -+ if (0 == buffer_lengths_in_bytes) { -+ DPRINTK("%s() Buffers have equal value!!\n", -+ __FUNCTION__); -+ return FAIL_A_IS_EQUAL_TO_B; -+ } -+ -+ } -+ -+ if (*MSB_K < *MSB_Q) { -+ return SUCCESS_A_IS_LESS_THAN_B; -+ } else { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+} -+ -+/* Name : icp_ocfDrvDsaSign -+ * -+ * Description : This function will map DSA RS Sign from OCF to the LAC API. -+ * -+ * NOTE: From looking at OCF patch to OpenSSL and even the number of input -+ * parameters, OCF expects us to generate the random seed value. This value -+ * is generated and passed to LAC, however the number is discared in the -+ * callback and not returned to the user. -+ */ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; -+ void *callbackTag = NULL; -+ CpaCyRandGenOpData randGenOpData; -+ int primeQSizeInBytes = 0; -+ int doCheck = 0; -+ CpaFlatBuffer randData; -+ CpaBoolean protocolStatus = CPA_FALSE; -+ CpaFlatBuffer *pR = NULL; -+ CpaFlatBuffer *pS = NULL; -+ -+ callbackTag = krp; -+ -+ BITS_TO_BYTES(primeQSizeInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { -+ APRINTK("%s(): DSA PRIME Q size not equal to the " -+ "FIPS defined 20bytes, = %d\n", -+ __FUNCTION__, primeQSizeInBytes); -+ krp->krp_status = EDOM; -+ return EDOM; -+ } -+ -+ dsaRsSignOpData = -+ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); -+ if (NULL == dsaRsSignOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ dsaRsSignOpData->K.pData = -+ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); -+ -+ if (NULL == dsaRsSignOpData->K.pData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op Random value\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pR) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature R\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pS) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature S\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /*link prime number parameter for ease of processing */ -+ dsaRsSignOpData->P.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, -+ dsaRsSignOpData->P.dataLenInBytes); -+ -+ dsaRsSignOpData->Q.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, -+ dsaRsSignOpData->Q.dataLenInBytes); -+ -+ /*generate random number with equal buffer size to Prime value Q, -+ but value less than Q */ -+ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; -+ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, -+ dsaRsSignOpData->K.dataLenInBytes, -+ &randData); -+ -+ doCheck = 0; -+ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), -+ &(dsaRsSignOpData->Q), &doCheck)) { -+ -+ if (CPA_STATUS_SUCCESS -+ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, &randGenOpData, &randData)) { -+ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" -+ "value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ doCheck++; -+ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { -+ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " -+ "value less than Q value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ } -+ /*Rand Data - no need to swap bytes for pK */ -+ -+ /* Link parameters */ -+ dsaRsSignOpData->G.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, -+ dsaRsSignOpData->G.dataLenInBytes); -+ -+ dsaRsSignOpData->X.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, -+ dsaRsSignOpData->X.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaRsSignOpData->M.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ /* Output Parameters */ -+ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pS->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. -+ crp_nbits); -+ -+ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pR->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaRSSignCallBack, -+ callbackTag, dsaRsSignOpData, -+ &protocolStatus, pR, pS); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDsaVerify -+ * -+ * Description : This function will map DSA RS Verify from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; -+ void *callbackTag = NULL; -+ CpaBoolean verifyStatus = CPA_FALSE; -+ -+ callbackTag = krp; -+ -+ dsaVerifyOpData = -+ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); -+ if (NULL == dsaVerifyOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA Verify Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ dsaVerifyOpData->P.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, -+ dsaVerifyOpData->P.dataLenInBytes); -+ -+ dsaVerifyOpData->Q.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, -+ dsaVerifyOpData->Q.dataLenInBytes); -+ -+ dsaVerifyOpData->G.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, -+ dsaVerifyOpData->G.dataLenInBytes); -+ -+ dsaVerifyOpData->Y.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, -+ dsaVerifyOpData->Y.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaVerifyOpData->M.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ dsaVerifyOpData->R.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, -+ dsaVerifyOpData->R.dataLenInBytes); -+ -+ dsaVerifyOpData->S.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, -+ dsaVerifyOpData->S.dataLenInBytes); -+ -+ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaVerifyCallBack, -+ callbackTag, dsaVerifyOpData, &verifyStatus); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); -+ krp->krp_status = ECANCELED; -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDhP1Callback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DH operation. -+ */ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; -+ -+ if (NULL == pLocalOctetStringPV) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, -+ pLocalOctetStringPV->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvModExpCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp operation. -+ */ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpdata, CpaFlatBuffer * pResult) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyLnModExpOpData *pLnModExpOpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpdata) { -+ DPRINTK("%s(): Invalid Mod Exp input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; -+ -+ if (NULL == pResult) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pResult data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp Operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); -+ -+ /*switch base size value back to original */ -+ if (pLnModExpOpData->base.pData == -+ (uint8_t *) & (krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits)) { -+ *((uint32_t *) pLnModExpOpData->base.pData) = -+ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); -+ } -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+ -+} -+ -+/* Name : icp_ocfDrvModExpCRTCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp CRT operation. -+ */ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyRsaDecryptOpData *pDecryptData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; -+ -+ if (NULL == pOutputData) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pOutputData is NULL\n", __FUNCTION__); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp CRT operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaRSSignCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA RS sign operation. -+ */ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaRSSignOpData *pSignData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pSignData = (CpaCyDsaRSSignOpData *) pOpData; -+ -+ if (NULL == pR) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pR sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (NULL == pS) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pS sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA RS Sign operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != protocolStatus) { -+ DPRINTK("%s(): LAC DSA RS Sign operation failed due " -+ "to protocol error\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ protocolStatus is set to true */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { -+ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); -+ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); -+ } -+ -+ icp_ocfDrvFreeFlatBuffer(pR); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); -+ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaVerifyCallback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA Verify operation. -+ */ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus) -+{ -+ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaVerifyOpData *pVerData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pVerData = (CpaCyDsaVerifyOpData *) pOpData; -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA Verify operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != verifyStatus) { -+ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ verifyStatus is set to true */ -+ /*Just swapping back the key values for now. Possibly all -+ swapped buffers need to be reverted */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { -+ icp_ocfDrvSwapBytes(pVerData->R.pData, -+ pVerData->R.dataLenInBytes); -+ icp_ocfDrvSwapBytes(pVerData->S.pData, -+ pVerData->S.dataLenInBytes); -+ } -+ -+ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); -+ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); -+ crypto_kdone(krp); -+ -+ return; -+} -diff --git a/crypto/ocf/ep80579/icp_common.c b/crypto/ocf/ep80579/icp_common.c -new file mode 100644 -index 0000000..06a4cf2 ---- /dev/null -+++ b/crypto/ocf/ep80579/icp_common.c -@@ -0,0 +1,773 @@ -+/************************************************************************* -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the -+ * crypto. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+#define ICP_OCF_COMP_NAME "ICP_OCF" -+#define ICP_OCF_VER_MAIN (2) -+#define ICP_OCF_VER_MJR (1) -+#define ICP_OCF_VER_MNR (0) -+ -+#define MAX_DEREG_RETRIES (100) -+#define DEFAULT_DEREG_RETRIES (10) -+#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) -+ -+/* This defines the maximum number of sessions possible between OCF -+ and the OCF EP80579 Driver. If set to zero, there is no limit. */ -+#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) -+#define NUM_SUPPORTED_CAPABILITIES (21) -+ -+/*Slab zone names*/ -+#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" -+#define ICP_OP_DATA_NAME "icp_ocf.OpDat" -+#define ICP_DH_NAME "icp_ocf.DH" -+#define ICP_MODEXP_NAME "icp_ocf.ModExp" -+#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" -+#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" -+#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" -+#define ICP_DSA_VER_NAME "icp_ocf.DSAver" -+#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" -+#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" -+ -+/*Slabs zones*/ -+icp_kmem_cache drvSessionData_zone = NULL; -+icp_kmem_cache drvOpData_zone = NULL; -+icp_kmem_cache drvDH_zone = NULL; -+icp_kmem_cache drvLnModExp_zone = NULL; -+icp_kmem_cache drvRSADecrypt_zone = NULL; -+icp_kmem_cache drvRSAPrivateKey_zone = NULL; -+icp_kmem_cache drvDSARSSign_zone = NULL; -+icp_kmem_cache drvDSARSSignKValue_zone = NULL; -+icp_kmem_cache drvDSAVerify_zone = NULL; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+icp_kmem_cache drvFlatBuffer_zone = NULL; -+ -+static inline int icp_cache_null_check(void) -+{ -+ return (drvSessionData_zone && drvOpData_zone -+ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone -+ && drvRSAPrivateKey_zone && drvDSARSSign_zone -+ && drvDSARSSign_zone && drvDSARSSignKValue_zone -+ && drvDSAVerify_zone && drvFlatBuffer_zone); -+} -+ -+/*Function to free all allocated slab caches before exiting the module*/ -+static void icp_ocfDrvFreeCaches(void); -+ -+int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+/* Module parameter - gives the number of times LAC deregistration shall be -+ re-tried */ -+int num_dereg_retries = DEFAULT_DEREG_RETRIES; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; -+ -+/* This is set when the module is removed from the system, no further -+ processing can take place if this is set */ -+icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); -+ -+/* This is used to show how many lac sessions were not deregistered*/ -+icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); -+ -+/* This is used to track the number of registered sessions between OCF and -+ * and the OCF EP80579 driver, when max_session is set to value other than -+ * zero. This ensures that the max_session set for the OCF and the driver -+ * is equal to the LAC registered sessions */ -+icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); -+ -+/* Head of linked list used to store session data */ -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+ -+icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Below pointer is only used in linux, FreeBSD uses the name to -+create its own variable name*/ -+icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; -+ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); -+ -+struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* Name : icp_ocfDrvInit -+ * -+ * Description : This function will register all the symmetric and asymmetric -+ * functionality that will be accelerated by the hardware. It will also -+ * get a unique driver ID from the OCF and initialise all slab caches -+ */ -+ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) -+{ -+ int ocfStatus = 0; -+ -+ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, -+ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); -+ -+ if (MAX_DEREG_RETRIES < num_dereg_retries) { -+ EPRINTK("Session deregistration retry count set to greater " -+ "than %d", MAX_DEREG_RETRIES); -+ icp_module_return_code(EINVAL); -+ } -+ -+ /* Initialize and Start the Cryptographic component */ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { -+ EPRINTK("Failed to initialize and start the instance " -+ "of the Cryptographic component.\n"); -+ return icp_module_return_code(EINVAL); -+ } -+ -+ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Set the default size of BufferList to allocate */ -+ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, -+ &defBuffListInfo)) { -+ EPRINTK("Failed to get bufferlist memory info.\n"); -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ /*Register OCF EP80579 Driver with OCF */ -+ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); -+ -+ if (icp_ocfDrvDriverId < 0) { -+ EPRINTK("%s : ICP driver failed to register with OCF!\n", -+ __FUNCTION__); -+ return icp_module_return_code(ENODEV); -+ } -+ -+ /*Create all the slab caches used by the OCF EP80579 Driver */ -+ drvSessionData_zone = -+ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); -+ -+ /* -+ * Allocation of the OpData includes the allocation space for meta data. -+ * The memory after the opData structure is reserved for this meta data. -+ */ -+ drvOpData_zone = -+ icp_kmem_cache_create(ICP_OP_DATA_NAME, -+ sizeof(struct icp_drvOpData) + -+ defBuffListInfo.metaSize, -+ ICP_KERNEL_CACHE_ALIGN, -+ ICP_KERNEL_CACHE_NOINIT); -+ -+ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); -+ -+ drvLnModExp_zone = -+ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); -+ -+ drvRSADecrypt_zone = -+ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); -+ -+ drvRSAPrivateKey_zone = -+ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); -+ -+ drvDSARSSign_zone = -+ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); -+ -+ /*too awkward to use a macro here */ -+ drvDSARSSignKValue_zone = -+ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, -+ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); -+ -+ drvDSAVerify_zone = -+ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); -+ -+ drvFlatBuffer_zone = -+ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); -+ -+ if (0 == icp_cache_null_check()) { -+ icp_ocfDrvFreeCaches(); -+ EPRINTK("%s() line %d: Not enough memory!\n", -+ __FUNCTION__, __LINE__); -+ return ENOMEM; -+ } -+ -+ /* Register the ICP symmetric crypto support. */ -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, -+ ocfStatus); -+ -+ /* Register the ICP asymmetric algorithm support */ -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, -+ ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); -+ -+ /* Register the ICP random number generator support */ -+ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, -+ icp_ocfDrvReadRandom, NULL, ocfStatus); -+ -+ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { -+ DPRINTK("%s: Failed to register any device capabilities\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ECANCELED); -+ } -+ -+ DPRINTK("%s: Registered %d of %d device capabilities\n", -+ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); -+ -+ /*Session data linked list used during module exit */ -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); -+ -+ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ EPRINTK("%s: Failed to create single " -+ "thread workqueue\n", __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ return icp_module_return_code(0); -+} -+ -+/* Name : icp_ocfDrvExit -+ * -+ * Description : This function will deregister all the symmetric sessions -+ * registered with the LAC component. It will also deregister all symmetric -+ * and asymmetric functionality that can be accelerated by the hardware via OCF -+ * and random number generation if it is enabled. -+ */ -+ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvSessionData *tempSessionData = NULL; -+ int i, remaining_delay_time_in_jiffies = 0; -+ -+ /* For FreeBSD the invariant macro below makes function to return */ -+ /* with EBUSY value in the case of any session which has been regi- */ -+ /* stered with LAC not being deregistered. */ -+ /* The Linux implementation is empty since it is purely to compensate */ -+ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ -+ -+ ICP_MODULE_EXIT_INV(); -+ -+ /* There is a possibility of a process or new session command being */ -+ /* sent before this variable is incremented. The aim of this variable */ -+ /* is to stop a loop of calls creating a deadlock situation which */ -+ /* would prevent the driver from exiting. */ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Existing sessions will be routed to another driver after these calls */ -+ crypto_unregister_all(icp_ocfDrvDriverId); -+ crypto_runregister_all(icp_ocfDrvDriverId); -+ -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ DPRINTK("%s: workqueue already " -+ "destroyed, therefore module exit " -+ " function already called. Exiting.\n", __FUNCTION__); -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+ } -+ /*If any sessions are waiting to be deregistered, do that. This also -+ flushes the work queue */ -+ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead, listNode) { -+ for (i = 0; i < num_dereg_retries; i++) { -+ /*No harm if bad input - LAC will handle error cases */ -+ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { -+ lacStatus = -+ cpaCySymRemoveSession -+ (CPA_INSTANCE_HANDLE_SINGLE, -+ tempSessionData->sessHandle); -+ if (CPA_STATUS_SUCCESS == lacStatus) { -+ /* Succesfully deregistered */ -+ break; -+ } else if (CPA_STATUS_RETRY != lacStatus) { -+ icp_atomic_inc -+ (&lac_session_failed_dereg_count); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if -+ * this task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = -+ dereg_retry_delay_in_jiffies; -+ while (0 > remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout -+ (&icp_ocfDrvSymSessInfoListSpinlock, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ DPRINTK -+ ("%s(): Retry %d to deregistrate the session\n", -+ __FUNCTION__, i); -+ } -+ } -+ -+ /*remove from current list */ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /*add to free mem linked list */ -+ ICP_LIST_ADD(tempSessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode); -+ -+ } -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /*set back to initial values */ -+ sessionData = NULL; -+ /*still have a reference in our list! */ -+ tempSessionData = NULL; -+ /*free memory */ -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode) { -+ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /* Free allocated CpaCySymSessionCtx */ -+ if (NULL != tempSessionData->sessHandle) { -+ icp_kfree(tempSessionData->sessHandle); -+ } -+ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); -+ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); -+ } -+ -+ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { -+ DPRINTK("%s(): %d LAC sessions were not deregistered " -+ "correctly. This is not a clean exit! \n", -+ __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+ } -+ -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Shutdown the Cryptographic component */ -+ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): Failed to stop instance of the " -+ "Cryptographic component.(status == %d)\n", -+ __FUNCTION__, lacStatus); -+ } -+ -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+} -+ -+/* Name : icp_ocfDrvFreeCaches -+ * -+ * Description : This function deregisters all slab caches -+ */ -+static void icp_ocfDrvFreeCaches(void) -+{ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Sym Zones */ -+ ICP_CACHE_DESTROY(drvSessionData_zone); -+ ICP_CACHE_DESTROY(drvOpData_zone); -+ -+ /*Asym zones */ -+ ICP_CACHE_DESTROY(drvDH_zone); -+ ICP_CACHE_DESTROY(drvLnModExp_zone); -+ ICP_CACHE_DESTROY(drvRSADecrypt_zone); -+ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); -+ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); -+ ICP_CACHE_DESTROY(drvDSARSSign_zone); -+ ICP_CACHE_DESTROY(drvDSAVerify_zone); -+ -+ /*FlatBuffer and BufferList Zones */ -+ ICP_CACHE_DESTROY(drvFlatBuffer_zone); -+ -+} -+ -+/* Name : icp_ocfDrvDeregRetry -+ * -+ * Description : This function will try to farm the session deregistration -+ * off to a work queue. If it fails, nothing more can be done and it -+ * returns an error -+ */ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ -+ DPRINTK("%s(): Retry - Deregistering session (%p)\n", -+ __FUNCTION__, sessionToDeregister); -+ -+ /*make sure the session is not available to be allocated during this -+ process */ -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ -+ /*Farm off to work queue */ -+ workstore = -+ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); -+ if (NULL == workstore) { -+ DPRINTK("%s(): unable to free session - no memory available " -+ "for work queue\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ workstore->sessionToDeregister = sessionToDeregister; -+ -+ icp_init_work(&(workstore->work), -+ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); -+ -+ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, -+ &(workstore->work)); -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ -+} -+ -+/* Name : icp_ocfDrvDeferedFreeLacSessionProcess -+ * -+ * Description : This function will retry (module input parameter) -+ * 'num_dereg_retries' times to deregister any symmetric session that recieves a -+ * CPA_STATUS_RETRY message from the LAC component. This function is run in -+ * Thread context because it is called from a worker thread -+ */ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ int i = 0; -+ int remaining_delay_time_in_jiffies = 0; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ workstore = (struct icp_ocfDrvFreeLacSession *)arg; -+ if (NULL == workstore) { -+ DPRINTK("%s() function called with null parameter \n", -+ __FUNCTION__); -+ return; -+ } -+ -+ sessionToDeregister = workstore->sessionToDeregister; -+ icp_kfree(workstore); -+ -+ /*if exiting, give deregistration one more blast only */ -+ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus != CPA_STATUS_SUCCESS) { -+ DPRINTK("%s() Failed to Dereg LAC session %p " -+ "during module exit\n", __FUNCTION__, -+ sessionToDeregister); -+ return; -+ } -+ -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ -+ for (i = 0; i <= num_dereg_retries; i++) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus == CPA_STATUS_SUCCESS) { -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ if (lacStatus != CPA_STATUS_RETRY) { -+ DPRINTK("%s() Failed to deregister session - lacStatus " -+ " = %d", __FUNCTION__, lacStatus); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if this -+ task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; -+ while (0 < remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout(NULL, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ } -+ -+ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); -+ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToFlatBuffer -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer) -+{ -+ pFlatBuffer->pData = pData; -+ pFlatBuffer->dataLenInBytes = len; -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToBufferList -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList) -+{ -+ pBufferList->numBuffers = 1; -+ pBufferList->pBuffers->pData = pDataIn; -+ pBufferList->pBuffers->dataLenInBytes = length; -+} -+ -+/* Name : icp_ocfDrvBufferListToPtrAndLen -+ * -+ * Description : This function converts Fredericksburg Scatter/Gather Buffer -+ * (CpaBufferList) format to a "pointer and length" buffer structure. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength) -+{ -+ *ppDataOut = pBufferList->pBuffers->pData; -+ *pLength = pBufferList->pBuffers->dataLenInBytes; -+} -+ -+/* Name : icp_ocfDrvBufferListMemInfo -+ * -+ * Description : This function will set the number of flat buffers in -+ * bufferlist, the size of memory to allocate for the pPrivateMetaData -+ * member of the CpaBufferList. -+ */ -+int -+icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo) -+{ -+ buffListInfo->numBuffers = numBuffers; -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ buffListInfo->numBuffers, -+ &(buffListInfo->metaSize))) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeFlatBuffer -+ * -+ * Description : This function will deallocate flat buffer. -+ */ -+inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) -+{ -+ if (pFlatBuffer != NULL) { -+ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); -+ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); -+ } -+} -+ -+/* Name : icp_ocfDrvAllocMetaData -+ * -+ * Description : This function will allocate memory for the -+ * pPrivateMetaData member of CpaBufferList. -+ */ -+inline int -+icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData) -+{ -+ Cpa32U metaSize = 0; -+ -+ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; -+ -+ if (0 == defBuffListInfo.metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ /* -+ * The meta data allocation has been included as part of the -+ * op data. It has been pre-allocated in memory just after the -+ * icp_drvOpData structure. -+ */ -+ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + -+ sizeof(struct -+ icp_drvOpData)); -+ } else { -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ pBufferList->numBuffers, -+ &metaSize)) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ if (0 == metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ -+ pBufferList->pPrivateMetaData = -+ icp_kmalloc(metaSize, ICP_M_NOWAIT); -+ } -+ if (NULL == pBufferList->pPrivateMetaData) { -+ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeMetaData -+ * -+ * Description : This function will deallocate pPrivateMetaData memory. -+ */ -+inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) -+{ -+ if (NULL == pBufferList->pPrivateMetaData) { -+ return; -+ } -+ -+ /* -+ * Only free the meta data if the BufferList has more than -+ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. -+ * Otherwise, the meta data shall be freed when the icp_drvOpData is -+ * freed. -+ */ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { -+ icp_kfree(pBufferList->pPrivateMetaData); -+ } -+} -+ -+/* Module declaration, init and exit functions */ -+ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); -+ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); -+ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); -+ICP_MODULE_LICENSE("Dual BSD/GPL"); -+ICP_MODULE_AUTHOR("Intel"); -+ -+/* Module parameters */ -+ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, -+ "Number of times to retry LAC Sym Session Deregistration. " -+ "Default 10, Max 100"); -+ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " -+ "(added to a schedule() function call) before a LAC Sym " -+ "Session Dereg is retried. Default 10"); -+ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, -+ "This sets the maximum number of sessions " -+ "between OCF and this driver. If this value is set to zero," -+ "max session count checking is disabled. Default is zero(0)"); -+ -+/* Module dependencies */ -+#define MODULE_MIN_VER 1 -+#define CRYPTO_MAX_VER 3 -+#define LAC_MAX_VER 2 -+ -+ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ LAC_MAX_VER); -diff --git a/crypto/ocf/ep80579/icp_ocf.h b/crypto/ocf/ep80579/icp_ocf.h -new file mode 100644 -index 0000000..854b306 ---- /dev/null -+++ b/crypto/ocf/ep80579/icp_ocf.h -@@ -0,0 +1,376 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * OCF driver header file for the Intel ICP processor. -+ */ -+ -+#ifndef ICP_OCF_H_ -+#define ICP_OCF_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icp_os.h" -+ -+#define NUM_BITS_IN_BYTE (8) -+#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) -+#define INVALID_DRIVER_ID (-1) -+#define RETURN_RAND_NUM_GEN_FAILED (-1) -+ -+/*This is the max block cipher initialisation vector*/ -+#define MAX_IV_LEN_IN_BYTES (20) -+/*This is used to check whether the OCF to this driver session limit has -+ been disabled*/ -+#define NO_OCF_TO_DRV_MAX_SESSIONS (0) -+ -+/*OCF values mapped here*/ -+#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) -+#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) -+#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) -+#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) -+#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) -+#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) -+ -+#define OCF_REGISTRATION_STATUS_SUCCESS (0) -+#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) -+#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) -+#define ICP_OCF_DRV_STATUS_SUCCESS (0) -+#define ICP_OCF_DRV_STATUS_FAIL (1) -+ -+/*Turn on/off debug options*/ -+#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) -+#define ICP_OCF_PRINT_KERN_ALERT (1) -+#define ICP_OCF_PRINT_KERN_ERRS (1) -+ -+#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+#define DPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#define DPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#if ICP_OCF_PRINT_KERN_ALERT == 1 -+#define APRINTK(args...) \ -+{ \ -+ ICP_APRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#define APRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#if ICP_OCF_PRINT_KERN_ERRS == 1 -+#define EPRINTK(args...) \ -+{ \ -+ ICP_EPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define EPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define IPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+/*DSA Prime Q size in bytes (as defined in the standard) */ -+#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) -+ -+#define BITS_TO_BYTES(bytes, bits) \ -+ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE -+ -+typedef enum { -+ ICP_OCF_DRV_ALG_CIPHER = 0, -+ ICP_OCF_DRV_ALG_HASH -+} icp_ocf_drv_alg_type_t; -+ -+typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, -+ icp_drvSessionData) icp_drvSessionListHead_t; -+ -+/*Values used to derisk chances of performs being called against -+deregistered sessions (for which the slab page has been reclaimed) -+This is not a fix - since page frames are reclaimed from a slab, one cannot -+rely on that memory not being re-used by another app.*/ -+typedef enum { -+ ICP_SESSION_INITIALISED = 0x5C5C5C, -+ ICP_SESSION_RUNNING = 0x005C00, -+ ICP_SESSION_DEREGISTERED = 0xC5C5C5 -+} usage_derisk; -+ -+/* This struct is required for deferred session -+ deregistration as a work queue function can -+ only have one argument*/ -+struct icp_ocfDrvFreeLacSession { -+ CpaCySymSessionCtx sessionToDeregister; -+ icp_workstruct work; -+}; -+ -+/* -+This is the OCF<->OCF_DRV session object: -+ -+1.listNode -+ The first member is a listNode. These session objects are added to a linked -+ list in order to make it easier to remove them all at session exit time. -+ -+2.inUse -+ The second member is used to give the session object state and derisk the -+ possibility of OCF batch calls executing against a deregistered session (as -+ described above). -+ -+3.sessHandle -+ The third member is a LAC<->OCF_DRV session handle (initialised with the first -+ perform request for that session). -+ -+4.lacSessCtx -+ The fourth is the LAC session context. All the parameters for this structure -+ are only known when the first perform request for this session occurs. That is -+ why the OCF EP80579 Driver only registers a new LAC session at perform time -+*/ -+struct icp_drvSessionData { -+ ICP_LIST_ENTRY(icp_drvSessionData) listNode; -+ usage_derisk inUse; -+ CpaCySymSessionCtx sessHandle; -+ CpaCySymSessionSetupData lacSessCtx; -+}; -+ -+/* These are all defined in icp_common.c */ -+extern icp_atomic_t lac_session_failed_dereg_count; -+extern icp_atomic_t icp_ocfDrvIsExiting; -+extern icp_atomic_t num_ocf_to_drv_registered_sessions; -+ -+extern int32_t icp_ocfDrvDriverId; -+ -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; -+extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Slab zones for symettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvSessionData_zone; -+extern icp_kmem_cache drvOpData_zone; -+ -+/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvDH_zone; -+extern icp_kmem_cache drvLnModExp_zone; -+extern icp_kmem_cache drvRSADecrypt_zone; -+extern icp_kmem_cache drvRSAPrivateKey_zone; -+extern icp_kmem_cache drvDSARSSign_zone; -+extern icp_kmem_cache drvDSARSSignKValue_zone; -+extern icp_kmem_cache drvDSAVerify_zone; -+ -+/* Module parameters defined in icp_cpmmon.c*/ -+ -+/* Module parameters - gives the number of times LAC deregistration shall be -+ re-tried */ -+extern int num_dereg_retries; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+extern int dereg_retry_delay_in_jiffies; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+extern int max_sessions; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+extern icp_kmem_cache drvFlatBuffer_zone; -+ -+#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) -+ -+struct icp_drvBuffListInfo { -+ Cpa16U numBuffers; -+ Cpa32U metaSize; -+ Cpa32U metaOffset; -+ Cpa32U buffListSize; -+}; -+ -+extern struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* This struct is used to keep a reference to the relevant node in the list -+ of sessionData structs, to the buffer type required by OCF and to the OCF -+ provided crp struct that needs to be returned. All this info is needed in -+ the callback function.*/ -+struct icp_drvOpData { -+ CpaCySymOpData lacOpData; -+ uint32_t digestSizeInBytes; -+ struct cryptop *crp; -+ uint8_t bufferType; -+ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; -+ uint16_t numBufferListArray; -+ CpaBufferList srcBuffer; -+ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; -+ CpaBoolean verifyResult; -+}; -+ -+/* Create a new session between OCF and this driver*/ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, -+ struct cryptoini *cri); -+ -+/* Free a session between this driver and the Quick Assist Framework*/ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); -+ -+/* Defer freeing a Quick Assist session*/ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); -+ -+/* Process OCF cryptographic request for a symmetric algorithm*/ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); -+ -+/* Process OCF cryptographic request for an asymmetric algorithm*/ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); -+ -+/* Populate a buffer with random data*/ -+int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); -+ -+/* Retry Quick Assist session deregistration*/ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); -+ -+/* Convert an OS scatter gather list to a CPA buffer list*/ -+int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, -+ CpaBufferList * bufferList); -+ -+/* Convert a CPA buffer list to an OS scatter gather list*/ -+int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, -+ icp_packet_buffer_t ** pPacketBuffer); -+ -+/* Get the number of buffers in an OS scatter gather list*/ -+uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); -+ -+/* Convert a single OS buffer to a CPA Flat Buffer*/ -+void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Add pointer and length to a CPA Flat Buffer structure*/ -+void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Convert pointer and length values to a CPA buffer list*/ -+void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList); -+ -+/* Convert a CPA buffer list to pointer and length values*/ -+void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength); -+ -+/* Set the number of flat buffers in bufferlist and the size of memory -+ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ -+int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo); -+ -+/* Find pointer position of the digest within an OS scatter gather list*/ -+uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData -+ *drvOpData, -+ int offsetInBytes, -+ uint32_t digestSizeInBytes); -+ -+/*This top level function is used to find a pointer to where a digest is -+ stored/needs to be inserted. */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/* Free a CPA flat buffer*/ -+void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); -+ -+/* This function will allocate memory for the pPrivateMetaData -+ member of CpaBufferList. */ -+int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData); -+ -+/* Free data allocated for the pPrivateMetaData -+ member of CpaBufferList.*/ -+void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); -+ -+#define ICP_CACHE_CREATE(cache_ID, cache_name) \ -+ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ -+ ICP_KERNEL_CACHE_NOINIT) -+ -+#define ICP_CACHE_FREE(args...) \ -+ icp_kmem_cache_free (args) -+ -+#define ICP_CACHE_DESTROY(slab_zone)\ -+{\ -+ if(NULL != slab_zone){\ -+ icp_kmem_cache_destroy(slab_zone);\ -+ slab_zone = NULL;\ -+ }\ -+} -+ -+#endif -+/* ICP_OCF_H_ */ -diff --git a/crypto/ocf/ep80579/icp_sym.c b/crypto/ocf/ep80579/icp_sym.c -new file mode 100644 -index 0000000..a3edc43 ---- /dev/null -+++ b/crypto/ocf/ep80579/icp_sym.c -@@ -0,0 +1,1153 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+/* -+ * An OCF module that uses the API for Intel® QuickAssist Technology to do the -+ * cryptography. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+/*This is the call back function for all symmetric cryptographic processes. -+ Its main functionality is to free driver crypto operation structure and to -+ call back to OCF*/ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); -+ -+/*This function is used to extract crypto processing information from the OCF -+ inputs, so as that it may be passed onto LAC*/ -+static int -+icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/*This function checks whether the crp_desc argument pertains to a digest or a -+ cipher operation*/ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); -+ -+/*This function copies all the passed in session context information and stores -+ it in a LAC context structure*/ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx); -+ -+/*This function is used to free an OCF->OCF_DRV session object*/ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); -+ -+/*max IOV buffs supported in a UIO structure*/ -+#define NUM_IOV_SUPPORTED (1) -+ -+/* Name : icp_ocfDrvSymCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the relevant symmetric operation. -+ * -+ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory -+ * object was passed to LAC for the cryptographic processing and contains all -+ * the relevant information for cleaning up buffer handles etc. so that the -+ * OCF EP80579 Driver portion of this crypto operation can be fully completed. -+ */ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) -+{ -+ struct cryptop *crp = NULL; -+ struct icp_drvOpData *temp_drvOpData = -+ (struct icp_drvOpData *)callbackTag; -+ uint64_t *tempBasePtr = NULL; -+ uint32_t tempLen = 0; -+ -+ if (NULL == temp_drvOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null userOpaque data" -+ "(status == %d).\n", __FUNCTION__, status); -+ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); -+ return; -+ } -+ -+ crp = temp_drvOpData->crp; -+ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Symmetric Op data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (NULL == pDstBuffer) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Dst Bufferlist data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ -+ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, -+ (icp_packet_buffer_t -+ **) -+ & (crp->crp_buf))) { -+ EPRINTK("%s(): BufferList to SkBuff " -+ "conversion error.\n", __FUNCTION__); -+ crp->crp_etype = EPERM; -+ } -+ } else { -+ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, -+ (void **)&tempBasePtr, -+ &tempLen); -+ crp->crp_olen = (int)tempLen; -+ } -+ -+ } else { -+ DPRINTK("%s(): The callback from the LAC component has failed" -+ "(status == %d).\n", __FUNCTION__, status); -+ -+ crp->crp_etype = ECANCELED; -+ } -+ -+ if (temp_drvOpData->numBufferListArray > -+ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(pDstBuffer->pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(pDstBuffer); -+ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); -+ -+ /* Invoke the OCF callback function */ -+ crypto_done(crp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvNewSession -+ * -+ * Description : This function will create a new Driver<->OCF session -+ * -+ * Notes : LAC session registration happens during the first perform call. -+ * That is the first time we know all information about a given session. -+ */ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, -+ struct cryptoini *cri) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ uint32_t delete_session = 0; -+ -+ /* The SID passed in should be our driver ID. We can return the */ -+ /* local ID (LID) which is a unique identifier which we can use */ -+ /* to differentiate between the encrypt/decrypt LAC session handles */ -+ if (NULL == sid) { -+ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == cri) { -+ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (icp_ocfDrvDriverId != *sid) { -+ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", -+ __FUNCTION__); -+ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); -+ return EINVAL; -+ } -+ -+ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); -+ if (NULL == sessionData) { -+ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ /*put this check in the spinlock so no new sessions can be added to the -+ linked list when we are exiting */ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ delete_session++; -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { -+ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= -+ (max_sessions - -+ icp_atomic_read(&lac_session_failed_dereg_count))) { -+ delete_session++; -+ } else { -+ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); -+ /* Add to session data linked list */ -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ sessionData->inUse = ICP_SESSION_INITIALISED; -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (delete_session) { -+ DPRINTK("%s():No Session handles available\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ if (cri->cri_next) { -+ if (cri->cri_next->cri_next != NULL) { -+ DPRINTK("%s():only two chained algorithms supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri->cri_next, -+ &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():second algorithm not supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ sessionData->lacSessCtx.symOperation = -+ CPA_CY_SYM_OP_ALGORITHM_CHAINING; -+ } -+ -+ *sid = (uint32_t) sessionData; -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvAlgorithmSetup -+ * -+ * Description : This function builds the session context data from the -+ * information supplied through OCF. Algorithm chain order and whether the -+ * session is Encrypt/Decrypt can only be found out at perform time however, so -+ * the session is registered with LAC at that time. -+ */ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx) -+{ -+ -+ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_NULL_CBC: -+ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_NULL; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_DES_CBC: -+ DPRINTK("%s(): DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_3DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_AES_CBC: -+ DPRINTK("%s(): AES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_AES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_ARC4: -+ DPRINTK("%s(): ARC4\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_ARC4; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_SHA1: -+ DPRINTK("%s(): SHA1\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA1_HMAC: -+ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_256: -+ DPRINTK("%s(): SHA256\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_256_HMAC: -+ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_384: -+ DPRINTK("%s(): SHA384\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_384_HMAC: -+ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_512: -+ DPRINTK("%s(): SHA512\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_512_HMAC: -+ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_MD5: -+ DPRINTK("%s(): MD5\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_MD5_HMAC: -+ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ default: -+ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeOCFSession -+ * -+ * Description : This function deletes all existing Session data representing -+ * the Cryptographic session established between OCF and this driver. This -+ * also includes freeing the memory allocated for the session context. The -+ * session object is also removed from the session linked list. -+ */ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) -+{ -+ -+ sessionData->inUse = ICP_SESSION_DEREGISTERED; -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ /*If the Driver is exiting, allow that process to -+ handle any deletions */ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ return; -+ } -+ -+ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); -+ -+ ICP_LIST_DEL(sessionData, listNode); -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (NULL != sessionData->sessHandle) { -+ icp_kfree(sessionData->sessHandle); -+ } -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+} -+ -+/* Name : icp_ocfDrvFreeLACSession -+ * -+ * Description : This attempts to deregister a LAC session. If it fails, the -+ * deregistation retry function is called. -+ */ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) -+{ -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ struct icp_drvSessionData *sessionData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ int retval = 0; -+ -+ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); -+ if (NULL == sessionData) { -+ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ sessionToDeregister = sessionData->sessHandle; -+ -+ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && -+ (ICP_SESSION_RUNNING != sessionData->inUse) && -+ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { -+ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (ICP_SESSION_RUNNING == sessionData->inUse) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvDeregRetry(&sessionToDeregister)) { -+ /* the retry function increments the -+ dereg failed count */ -+ DPRINTK("%s(): LAC failed to deregister the " -+ "session. (localSessionId= %p)\n", -+ __FUNCTION__, sessionToDeregister); -+ retval = EPERM; -+ } -+ -+ } else if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): LAC failed to deregister the session. " -+ "localSessionId= %p, lacStatus = %d\n", -+ __FUNCTION__, sessionToDeregister, lacStatus); -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ retval = EPERM; -+ } -+ } else { -+ DPRINTK("%s() Session not registered with LAC.\n", -+ __FUNCTION__); -+ } -+ -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return retval; -+ -+} -+ -+/* Name : icp_ocfDrvAlgCheck -+ * -+ * Description : This function checks whether the cryptodesc argument pertains -+ * to a sym or hash function -+ */ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) -+{ -+ -+ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || -+ crp_desc->crd_alg == CRYPTO_AES_CBC || -+ crp_desc->crd_alg == CRYPTO_DES_CBC || -+ crp_desc->crd_alg == CRYPTO_NULL_CBC || -+ crp_desc->crd_alg == CRYPTO_ARC4) { -+ return ICP_OCF_DRV_ALG_CIPHER; -+ } -+ -+ return ICP_OCF_DRV_ALG_HASH; -+} -+ -+/* Name : icp_ocfDrvSymProcess -+ * -+ * Description : This function will map symmetric functionality calls from OCF -+ * to the LAC API. It will also allocate memory to store the session context. -+ * -+ * Notes: If it is the first perform call for a given session, then a LAC -+ * session is registered. After the session is registered, no checks as -+ * to whether session paramaters have changed (e.g. alg chain order) are -+ * done. -+ */ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvOpData *drvOpData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ Cpa32U sessionCtxSizeInBytes = 0; -+ -+ if (NULL == crp) { -+ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_desc) { -+ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_buf) { -+ DPRINTK("%s(): Invalid input parameters, no buffer attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData = (struct icp_drvSessionData *) -+ (CRYPTO_SESID2LID(crp->crp_sid)); -+ if (NULL == sessionData) { -+ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", -+ __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+/*If we get a request against a deregisted session, cancel operation*/ -+ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { -+ DPRINTK("%s(): Session ID %d was deregistered \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+/*If none of the session states are set, then the session structure was either -+ not initialised properly or we are reading from a freed memory area (possible -+ due to OCF batch mode not removing queued requests against deregistered -+ sessions*/ -+ if (ICP_SESSION_INITIALISED != sessionData->inUse && -+ ICP_SESSION_RUNNING != sessionData->inUse) { -+ DPRINTK("%s(): Session - ID %d - not properly initialised or " -+ "memory freed back to the kernel \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ /*For the below checks, remember error checking is already done in LAC. -+ We're not validating inputs subsequent to registration */ -+ if (sessionData->inUse == ICP_SESSION_INITIALISED) { -+ DPRINTK("%s(): Initialising session\n", __FUNCTION__); -+ -+ if (NULL != crp->crp_desc->crd_next) { -+ if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; -+ -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ } else { -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; -+ -+ if (crp->crp_desc->crd_next->crd_flags & -+ CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ } else if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ /*No action required for standalone Auth here */ -+ -+ /* Allocate memory for SymSessionCtx before the Session Registration */ -+ lacStatus = -+ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, -+ &(sessionData->lacSessCtx), -+ &sessionCtxSizeInBytes); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ sessionData->sessHandle = -+ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); -+ if (NULL == sessionData->sessHandle) { -+ EPRINTK -+ ("%s(): Failed to get memory for SymSessionCtx\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvSymCallBack, -+ &(sessionData->lacSessCtx), -+ sessionData->sessHandle); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData->inUse = ICP_SESSION_RUNNING; -+ } -+ -+ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); -+ if (NULL == drvOpData) { -+ EPRINTK("%s():Failed to get memory for drvOpData\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; -+ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. -+ digestResultLenInBytes; -+ drvOpData->crp = crp; -+ -+ /* Set the default buffer list array memory allocation */ -+ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; -+ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ if (drvOpData->crp->crp_desc->crd_next != NULL) { -+ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> -+ crp_desc->crd_next)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } -+ -+ /* -+ * Allocate buffer list array memory if the data fragment is more than -+ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not -+ * calculated already -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ drvOpData->numBufferListArray = -+ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) -+ crp->crp_buf); -+ } -+ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < -+ drvOpData->numBufferListArray) { -+ DPRINTK("%s() numBufferListArray more than default\n", -+ __FUNCTION__); -+ drvOpData->srcBuffer.pBuffers = NULL; -+ drvOpData->srcBuffer.pBuffers = -+ icp_kmalloc(drvOpData->numBufferListArray * -+ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); -+ if (NULL == drvOpData->srcBuffer.pBuffers) { -+ EPRINTK("%s() Failed to get memory for " -+ "pBuffers\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ } -+ } -+ -+ /* -+ * Check the type of buffer structure we got and convert it into -+ * CpaBufferList format. -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) -+ crp->crp_buf, -+ &(drvOpData->srcBuffer))) { -+ EPRINTK("%s():Failed to translate from packet buffer " -+ "to bufferlist\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* OCF only supports IOV of one entry. */ -+ if (NUM_IOV_SUPPORTED == -+ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { -+ -+ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_base, -+ ((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_len, -+ &(drvOpData-> -+ srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_F_IOV; -+ -+ } else { -+ DPRINTK("%s():Unable to handle IOVs with lengths of " -+ "greater than one!\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } else { -+ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, -+ crp->crp_ilen, -+ &(drvOpData->srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_BUF_CONTIG; -+ } -+ -+ /* Allocate srcBuffer's private meta data */ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { -+ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ /* Perform "in-place" crypto operation */ -+ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, -+ (void *)drvOpData, -+ &(drvOpData->lacOpData), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->verifyResult)); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = ERESTART; -+ goto err; -+ } -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ return 0; //OCF success status value -+ -+ err: -+ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(drvOpData->srcBuffer.pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ -+ return crp->crp_etype; -+} -+ -+/* Name : icp_ocfDrvProcessDataSetup -+ * -+ * Description : This function will setup all the cryptographic operation data -+ * that is required by LAC to execute the operation. -+ */ -+static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc) -+{ -+ CpaCyRandGenOpData randGenOpData; -+ CpaFlatBuffer randData; -+ -+ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; -+ -+ /* Convert from the cryptop to the ICP LAC crypto parameters */ -+ switch (crp_desc->crd_alg) { -+ case CRYPTO_NULL_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; -+ break; -+ case CRYPTO_ARC4: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ case CRYPTO_SHA2_256: -+ case CRYPTO_SHA2_256_HMAC: -+ case CRYPTO_SHA2_384: -+ case CRYPTO_SHA2_384_HMAC: -+ case CRYPTO_SHA2_512: -+ case CRYPTO_SHA2_512_HMAC: -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ drvOpData->lacOpData. -+ hashStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToHashInBytes = crp_desc->crd_len; -+ drvOpData->lacOpData. -+ pDigestResult = -+ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); -+ -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ DPRINTK("%s(): ERROR - could not calculate " -+ "Digest Result memory address\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ drvOpData->lacOpData.digestVerify = CPA_FALSE; -+ break; -+ default: -+ DPRINTK("%s(): Crypto process error - algorithm not " -+ "found \n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ /* Figure out what the IV is supposed to be */ -+ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { -+ /*ARC4 doesn't use an IV */ -+ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { -+ /* Explicit IV provided to OCF */ -+ drvOpData->lacOpData.pIv = crp_desc->crd_iv; -+ } else { -+ /* IV is not explicitly provided to OCF */ -+ -+ /* Point the LAC OP Data IV pointer to our allocated -+ storage location for this session. */ -+ drvOpData->lacOpData.pIv = drvOpData->ivData; -+ -+ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && -+ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { -+ -+ /* Encrypting - need to create IV */ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) -+ drvOpData-> -+ ivData, -+ MAX_IV_LEN_IN_BYTES, -+ &randData); -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, -+ &randGenOpData, &randData)) { -+ DPRINTK("%s(): ERROR - Failed to" -+ " generate" -+ " Initialisation Vector\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ crypto_copyback(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } else { -+ /* Reading IV from buffer */ -+ crypto_copydata(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } -+ -+ } -+ -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvDigestPointerFind -+ * -+ * Description : This function is used to find the memory address of where the -+ * digest information shall be stored in. Input buffer types are an skbuff, iov -+ * or flat buffer. The address is found using the buffer data start address and -+ * an offset. -+ * -+ * Note: In the case of a linux skbuff, the digest address may exist within -+ * a memory space linked to from the start buffer. These linked memory spaces -+ * must be traversed by the data length offset in order to find the digest start -+ * address. Whether there is enough space for the digest must also be checked. -+ */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, -+ struct cryptodesc * crp_desc) -+{ -+ -+ int offsetInBytes = crp_desc->crd_inject; -+ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; -+ uint8_t *flat_buffer_base = NULL; -+ int flat_buffer_length = 0; -+ -+ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ -+ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, -+ offsetInBytes, -+ digestSizeInBytes); -+ -+ } else { -+ /* IOV or flat buffer */ -+ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { -+ /*single IOV check has already been done */ -+ flat_buffer_base = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_base; -+ flat_buffer_length = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_len; -+ } else { -+ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; -+ flat_buffer_length = drvOpData->crp->crp_ilen; -+ } -+ -+ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { -+ DPRINTK("%s() Not enough space for Digest " -+ "(IOV/Flat Buffer) \n", __FUNCTION__); -+ return NULL; -+ } else { -+ return (uint8_t *) (flat_buffer_base + offsetInBytes); -+ } -+ } -+ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); -+ return NULL; -+} -diff --git a/crypto/ocf/hifn/Makefile b/crypto/ocf/hifn/Makefile -new file mode 100644 -index 0000000..163fed0 ---- /dev/null -+++ b/crypto/ocf/hifn/Makefile -@@ -0,0 +1,13 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_HIFN) += hifn7751.o -+obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/hifn/hifn7751.c b/crypto/ocf/hifn/hifn7751.c -new file mode 100644 -index 0000000..e7a5958 ---- /dev/null -+++ b/crypto/ocf/hifn/hifn7751.c -@@ -0,0 +1,2976 @@ -+/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * Copyright (c) 2003 Hifn Inc. -+ * -+ * This driver is based on a previous driver by Invertex, for which they -+ * requested: Please send any comments, feedback, bug-fixes, or feature -+ * requests to software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ * -+__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a...) if (hifn_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+static struct hifn_stats hifnstats; -+ -+#define debug hifn_debug -+int hifn_debug = 0; -+module_param(hifn_debug, int, 0644); -+MODULE_PARM_DESC(hifn_debug, "Enable debug"); -+ -+int hifn_maxbatch = 1; -+module_param(hifn_maxbatch, int, 0644); -+MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); -+ -+int hifn_cache_linesize = 0x10; -+module_param(hifn_cache_linesize, int, 0444); -+MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); -+ -+#ifdef MODULE_PARM -+char *hifn_pllconfig = NULL; -+MODULE_PARM(hifn_pllconfig, "s"); -+#else -+char hifn_pllconfig[32]; /* This setting is RO after loading */ -+module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); -+#endif -+MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); -+ -+#ifdef HIFN_VULCANDEV -+#include -+#include -+ -+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ -+#endif -+ -+/* -+ * Prototypes and count for the pci_device structure -+ */ -+static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hifn_remove(struct pci_dev *dev); -+ -+static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hifn_freesession(device_t, u_int64_t); -+static int hifn_process(device_t, struct cryptop *, int); -+ -+static device_method_t hifn_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hifn_newsession), -+ DEVMETHOD(cryptodev_freesession,hifn_freesession), -+ DEVMETHOD(cryptodev_process, hifn_process), -+}; -+ -+static void hifn_reset_board(struct hifn_softc *, int); -+static void hifn_reset_puc(struct hifn_softc *); -+static void hifn_puc_wait(struct hifn_softc *); -+static int hifn_enable_crypto(struct hifn_softc *); -+static void hifn_set_retry(struct hifn_softc *sc); -+static void hifn_init_dma(struct hifn_softc *); -+static void hifn_init_pci_registers(struct hifn_softc *); -+static int hifn_sramsize(struct hifn_softc *); -+static int hifn_dramsize(struct hifn_softc *); -+static int hifn_ramtype(struct hifn_softc *); -+static void hifn_sessions(struct hifn_softc *); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hifn_intr(int irq, void *arg); -+#else -+static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+static u_int hifn_write_command(struct hifn_command *, u_int8_t *); -+static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); -+static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); -+static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); -+static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); -+static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); -+static int hifn_init_pubrng(struct hifn_softc *); -+static void hifn_tick(unsigned long arg); -+static void hifn_abort(struct hifn_softc *); -+static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); -+ -+static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); -+static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int hifn_read_random(void *arg, u_int32_t *buf, int len); -+#endif -+ -+#define HIFN_MAX_CHIPS 8 -+static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; -+ -+static __inline u_int32_t -+READ_REG_0(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar0 + reg); -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) -+ -+static __inline u_int32_t -+READ_REG_1(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar1 + reg); -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) -+ -+/* -+ * map in a given buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ iov->iov_base, iov->iov_len, -+ PCI_DMA_BIDIRECTIONAL); -+ buf->segs[buf->nsegs].ds_len = iov->iov_len; -+ buf->mapsize += iov->iov_len; -+ iov++; -+ buf->nsegs++; -+ } -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = skb_headlen(skb); -+ buf->mapsize += buf->segs[0].ds_len; -+ -+ buf->nsegs = 1; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { -+ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->mapsize += buf->segs[buf->nsegs].ds_len; -+ buf->nsegs++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given contiguous buffer -+ */ -+ -+static int -+pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ b, len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = len; -+ buf->mapsize += buf->segs[0].ds_len; -+ buf->nsegs = 1; -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) { -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+static const char* -+hifn_partname(struct hifn_softc *sc) -+{ -+ /* XXX sprintf numbers when not decoded */ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; -+ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; -+ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; -+ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; -+ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; -+ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; -+ } -+ return "Hifn unknown-part"; -+ case PCI_VENDOR_INVERTEX: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; -+ } -+ return "Invertex unknown-part"; -+ case PCI_VENDOR_NETSEC: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; -+ } -+ return "NetSec unknown-part"; -+ } -+ return "Unknown-vendor unknown-part"; -+} -+ -+static u_int -+checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ if (v > max) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using max %u\n", what, v, max); -+ v = max; -+ } else if (v < min) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using min %u\n", what, v, min); -+ v = min; -+ } -+ return v; -+} -+ -+/* -+ * Select PLL configuration for 795x parts. This is complicated in -+ * that we cannot determine the optimal parameters without user input. -+ * The reference clock is derived from an external clock through a -+ * multiplier. The external clock is either the host bus (i.e. PCI) -+ * or an external clock generator. When using the PCI bus we assume -+ * the clock is either 33 or 66 MHz; for an external source we cannot -+ * tell the speed. -+ * -+ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" -+ * for an external source, followed by the frequency. We calculate -+ * the appropriate multiplier and PLL register contents accordingly. -+ * When no configuration is given we default to "pci66" since that -+ * always will allow the card to work. If a card is using the PCI -+ * bus clock and in a 33MHz slot then it will be operating at half -+ * speed until the correct information is provided. -+ * -+ * We use a default setting of "ext66" because according to Mike Ham -+ * of HiFn, almost every board in existence has an external crystal -+ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, -+ * because PCI33 can have clocks from 0 to 33Mhz, and some have -+ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. -+ */ -+static void -+hifn_getpllconfig(struct pci_dev *dev, u_int *pll) -+{ -+ const char *pllspec = hifn_pllconfig; -+ u_int freq, mul, fl, fh; -+ u_int32_t pllconfig; -+ char *nxt; -+ -+ if (pllspec == NULL) -+ pllspec = "ext66"; -+ fl = 33, fh = 66; -+ pllconfig = 0; -+ if (strncmp(pllspec, "ext", 3) == 0) { -+ pllspec += 3; -+ pllconfig |= HIFN_PLL_REF_SEL; -+ switch (pci_get_device(dev)) { -+ case PCI_PRODUCT_HIFN_7955: -+ case PCI_PRODUCT_HIFN_7956: -+ fl = 20, fh = 100; -+ break; -+#ifdef notyet -+ case PCI_PRODUCT_HIFN_7954: -+ fl = 20, fh = 66; -+ break; -+#endif -+ } -+ } else if (strncmp(pllspec, "pci", 3) == 0) -+ pllspec += 3; -+ freq = strtoul(pllspec, &nxt, 10); -+ if (nxt == pllspec) -+ freq = 66; -+ else -+ freq = checkmaxmin(dev, "frequency", freq, fl, fh); -+ /* -+ * Calculate multiplier. We target a Fck of 266 MHz, -+ * allowing only even values, possibly rounded down. -+ * Multipliers > 8 must set the charge pump current. -+ */ -+ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); -+ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; -+ if (mul > 8) -+ pllconfig |= HIFN_PLL_IS; -+ *pll = pllconfig; -+} -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hifn_softc *sc = NULL; -+ char rbase; -+ u_int16_t ena, rev; -+ int rseg, rc; -+ unsigned long mem_start, mem_len; -+ static int num_chips = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn", num_chips, hifn_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = num_chips++; -+ if (sc->sc_num < HIFN_MAX_CHIPS) -+ hifn_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* XXX handle power management */ -+ -+ /* -+ * The 7951 and 795x have a random number generator and -+ * public key support; note this. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) -+ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; -+ /* -+ * The 7811 has a random number generator and -+ * we also note it's identity 'cuz of some quirks. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) -+ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; -+ -+ /* -+ * The 795x parts support AES. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { -+ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; -+ /* -+ * Select PLL configuration. This depends on the -+ * bus and board design and must be manually configured -+ * if the default setting is unacceptable. -+ */ -+ hifn_getpllconfig(dev, &sc->sc_pllconfig); -+ } -+ -+ /* -+ * Setup PCI resources. Note that we record the bus -+ * tag and handle for each register mapping, this is -+ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver. -+ */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar0) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); -+ goto fail; -+ } -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ -+ mem_start = pci_resource_start(sc->sc_pcidev, 1); -+ mem_len = pci_resource_len(sc->sc_pcidev, 1); -+ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar1) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); -+ goto fail; -+ } -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, -+ "No usable consistent DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ -+ hifn_set_retry(sc); -+ -+ /* -+ * Setup the area where the Hifn DMA's descriptors -+ * and associated data structures. -+ */ -+ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, -+ sizeof(*sc->sc_dma), -+ &sc->sc_dma_physaddr); -+ if (!sc->sc_dma) { -+ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); -+ goto fail; -+ } -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* -+ * Reset the board and do the ``secret handshake'' -+ * to enable the crypto support. Then complete the -+ * initialization procedure by setting up the interrupt -+ * and hooking in to the system crypto support so we'll -+ * get used for system services like the crypto device, -+ * IPsec, RNG device, etc. -+ */ -+ hifn_reset_board(sc, 0); -+ -+ if (hifn_enable_crypto(sc) != 0) { -+ device_printf(sc->sc_dev, "crypto enabling failed\n"); -+ goto fail; -+ } -+ hifn_reset_puc(sc); -+ -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ /* XXX can't dynamically determine ram type for 795x; force dram */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_drammodel = 1; -+ else if (hifn_ramtype(sc)) -+ goto fail; -+ -+ if (sc->sc_drammodel == 0) -+ hifn_sramsize(sc); -+ else -+ hifn_dramsize(sc); -+ -+ /* -+ * Workaround for NetSec 7751 rev A: half ram size because two -+ * of the address lines were left floating -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && -+ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && -+ pci_get_revid(dev) == 0x61) /*XXX???*/ -+ sc->sc_ramsize >>= 1; -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ hifn_sessions(sc); -+ -+ /* -+ * NB: Keep only the low 16 bits; this masks the chip id -+ * from the 7951. -+ */ -+ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; -+ -+ rseg = sc->sc_ramsize / 1024; -+ rbase = 'K'; -+ if (sc->sc_ramsize >= (1024 * 1024)) { -+ rbase = 'M'; -+ rseg /= 1024; -+ } -+ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", -+ hifn_partname(sc), rev, -+ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, -+ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); -+ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ switch (ena) { -+ case HIFN_PUSTAT_ENA_2: -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ if (sc->sc_flags & HIFN_HAS_AES) -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ /*FALLTHROUGH*/ -+ case HIFN_PUSTAT_ENA_1: -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ break; -+ } -+ -+ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) -+ hifn_init_pubrng(sc); -+ -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hifn_remove(struct pci_dev *dev) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); -+ -+ /* disable interrupts */ -+ HIFN_LOCK(sc); -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+} -+ -+ -+static int -+hifn_init_pubrng(struct hifn_softc *sc) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if ((sc->sc_flags & HIFN_IS_7811) == 0) { -+ /* Reset 7951 public key/rng engine */ -+ WRITE_REG_1(sc, HIFN_1_PUB_RESET, -+ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); -+ -+ for (i = 0; i < 100; i++) { -+ DELAY(1000); -+ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & -+ HIFN_PUBRST_RESET) == 0) -+ break; -+ } -+ -+ if (i == 100) { -+ device_printf(sc->sc_dev, "public key init failed\n"); -+ return (1); -+ } -+ } -+ -+ /* Enable the rng, if available */ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_flags & HIFN_HAS_RNG) { -+ if (sc->sc_flags & HIFN_IS_7811) { -+ u_int32_t r; -+ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); -+ if (r & HIFN_7811_RNGENA_ENA) { -+ r &= ~HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } -+ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, -+ HIFN_7811_RNGCFG_DEFL); -+ r |= HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } else -+ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, -+ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | -+ HIFN_RNGCFG_ENA); -+ -+ sc->sc_rngfirst = 1; -+ crypto_rregister(sc->sc_cid, hifn_read_random, sc); -+ } -+#endif -+ -+ /* Enable public key engine, if available */ -+ if (sc->sc_flags & HIFN_HAS_PUBLIC) { -+ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); -+ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+#ifdef HIFN_VULCANDEV -+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, -+ UID_ROOT, GID_WHEEL, 0666, -+ "vulcanpk"); -+ sc->sc_pkdev->si_drv1 = sc; -+#endif -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int -+hifn_read_random(void *arg, u_int32_t *buf, int len) -+{ -+ struct hifn_softc *sc = (struct hifn_softc *) arg; -+ u_int32_t sts; -+ int i, rc = 0; -+ -+ if (len <= 0) -+ return rc; -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ /* ONLY VALID ON 7811!!!! */ -+ for (i = 0; i < 5; i++) { -+ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); -+ if (sts & HIFN_7811_RNGSTS_UFL) { -+ device_printf(sc->sc_dev, -+ "RNG underflow: disabling\n"); -+ /* DAVIDM perhaps return -1 */ -+ break; -+ } -+ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) -+ break; -+ -+ /* -+ * There are at least two words in the RNG FIFO -+ * at this point. -+ */ -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ } -+ } else -+ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); -+ -+ /* NB: discard first data read */ -+ if (sc->sc_rngfirst) { -+ sc->sc_rngfirst = 0; -+ rc = 0; -+ } -+ -+ return(rc); -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+static void -+hifn_puc_wait(struct hifn_softc *sc) -+{ -+ int i; -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ -+ for (i = 5000; i > 0; i--) { -+ DELAY(1); -+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) -+ break; -+ } -+ if (!i) -+ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", -+ READ_REG_0(sc, HIFN_0_PUCTRL)); -+} -+ -+/* -+ * Reset the processing unit. -+ */ -+static void -+hifn_reset_puc(struct hifn_softc *sc) -+{ -+ /* Reset processing unit */ -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); -+ -+ hifn_puc_wait(sc); -+} -+ -+/* -+ * Set the Retry and TRDY registers; note that we set them to -+ * zero because the 7811 locks up when forced to retry (section -+ * 3.6 of "Specification Update SU-0014-04". Not clear if we -+ * should do this for all Hifn parts, but it doesn't seem to hurt. -+ */ -+static void -+hifn_set_retry(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* NB: RETRY only responds to 8-bit reads/writes */ -+ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); -+ pci_write_config_dword(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); -+ /* piggy back the cache line setting here */ -+ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+hifn_reset_board(struct hifn_softc *sc, int full) -+{ -+ u_int32_t reg; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* -+ * Set polling in the DMA configuration register to zero. 0x7 avoids -+ * resetting the board and zeros out the other fields. -+ */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ /* -+ * Now that polling has been disabled, we have to wait 1 ms -+ * before resetting the board. -+ */ -+ DELAY(1000); -+ -+ /* Reset the DMA unit */ -+ if (full) { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ } else { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, -+ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); -+ hifn_reset_puc(sc); -+ } -+ -+ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* Bring dma unit out of reset */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ hifn_puc_wait(sc); -+ hifn_set_retry(sc); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ for (reg = 0; reg < 1000; reg++) { -+ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & -+ HIFN_MIPSRST_CRAMINIT) -+ break; -+ DELAY(1000); -+ } -+ if (reg == 1000) -+ device_printf(sc->sc_dev, ": cram init timeout\n"); -+ } else { -+ /* set up DMA configuration register #2 */ -+ /* turn off all PK and BAR0 swaps */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, -+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| -+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); -+ } -+} -+ -+static u_int32_t -+hifn_next_signature(u_int32_t a, u_int cnt) -+{ -+ int i; -+ u_int32_t v; -+ -+ for (i = 0; i < cnt; i++) { -+ -+ /* get the parity */ -+ v = a & 0x80080125; -+ v ^= v >> 16; -+ v ^= v >> 8; -+ v ^= v >> 4; -+ v ^= v >> 2; -+ v ^= v >> 1; -+ -+ a = (v & 1) ^ (a << 1); -+ } -+ -+ return a; -+} -+ -+ -+/* -+ * Checks to see if crypto is already enabled. If crypto isn't enable, -+ * "hifn_enable_crypto" is called to enable it. The check is important, -+ * as enabling crypto twice will lock the board. -+ */ -+static int -+hifn_enable_crypto(struct hifn_softc *sc) -+{ -+ u_int32_t dmacfg, ramcfg, encl, addr, i; -+ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00 }; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); -+ -+ /* -+ * The RAM config register's encrypt level bit needs to be set before -+ * every read performed on the encryption level register. -+ */ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ /* -+ * Make sure we don't re-unlock. Two unlocks kills chip until the -+ * next reboot. -+ */ -+ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Strong crypto already enabled!\n"); -+#endif -+ goto report; -+ } -+ -+ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Unknown encryption level 0x%x\n", encl); -+#endif -+ return 1; -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | -+ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); -+ DELAY(1000); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); -+ DELAY(1000); -+ -+ for (i = 0; i <= 12; i++) { -+ addr = hifn_next_signature(addr, offtbl[i] + 0x101); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); -+ -+ DELAY(1000); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) -+ device_printf(sc->sc_dev, "Engine is permanently " -+ "locked until next system reset!\n"); -+ else -+ device_printf(sc->sc_dev, "Engine enabled " -+ "successfully!\n"); -+ } -+#endif -+ -+report: -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); -+ -+ switch (encl) { -+ case HIFN_PUSTAT_ENA_1: -+ case HIFN_PUSTAT_ENA_2: -+ break; -+ case HIFN_PUSTAT_ENA_0: -+ default: -+ device_printf(sc->sc_dev, "disabled\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Give initial values to the registers listed in the "Register Space" -+ * section of the HIFN Software Development reference manual. -+ */ -+static void -+hifn_init_pci_registers(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* write fixed values needed by the Initialization registers */ -+ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); -+ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); -+ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); -+ -+ /* write all 4 ring address registers */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, cmdr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, srcr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, dstr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, resr[0])); -+ -+ DELAY(2000); -+ -+ /* write status register */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | -+ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | -+ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | -+ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | -+ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | -+ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | -+ HIFN_DMACSR_S_WAIT | -+ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | -+ HIFN_DMACSR_C_WAIT | -+ HIFN_DMACSR_ENGINE | -+ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? -+ HIFN_DMACSR_PUBDONE : 0) | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); -+ -+ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; -+ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | -+ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | -+ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ u_int32_t pll; -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); -+ -+ /* turn off the clocks and insure bypass is set */ -+ pll = READ_REG_1(sc, HIFN_1_PLL); -+ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) -+ | HIFN_PLL_BP | HIFN_PLL_MBSET; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* change configuration */ -+ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* disable bypass */ -+ pll &= ~HIFN_PLL_BP; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ /* enable clocks with new configuration */ -+ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ } else { -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | -+ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | -+ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | -+ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); -+} -+ -+/* -+ * The maximum number of sessions supported by the card -+ * is dependent on the amount of context ram, which -+ * encryption algorithms are enabled, and how compression -+ * is configured. This should be configured before this -+ * routine is called. -+ */ -+static void -+hifn_sessions(struct hifn_softc *sc) -+{ -+ u_int32_t pucnfg; -+ int ctxsize; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ -+ if (pucnfg & HIFN_PUCNFG_COMPSING) { -+ if (pucnfg & HIFN_PUCNFG_ENCCNFG) -+ ctxsize = 128; -+ else -+ ctxsize = 512; -+ /* -+ * 7955/7956 has internal context memory of 32K -+ */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_maxses = 32768 / ctxsize; -+ else -+ sc->sc_maxses = 1 + -+ ((sc->sc_ramsize - 32768) / ctxsize); -+ } else -+ sc->sc_maxses = sc->sc_ramsize / 16384; -+ -+ if (sc->sc_maxses > 2048) -+ sc->sc_maxses = 2048; -+} -+ -+/* -+ * Determine ram type (sram or dram). Board should be just out of a reset -+ * state when this is called. -+ */ -+static int -+hifn_ramtype(struct hifn_softc *sc) -+{ -+ u_int8_t data[8], dataexpect[8]; -+ int i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0x55; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0xaa; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ return (0); -+} -+ -+#define HIFN_SRAM_MAX (32 << 20) -+#define HIFN_SRAM_STEP_SIZE 16384 -+#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) -+ -+static int -+hifn_sramsize(struct hifn_softc *sc) -+{ -+ u_int32_t a; -+ u_int8_t data[8]; -+ u_int8_t dataexpect[sizeof(data)]; -+ int32_t i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = i ^ 0x5a; -+ -+ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, data, sizeof(i)); -+ hifn_writeramaddr(sc, a, data); -+ } -+ -+ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, dataexpect, sizeof(i)); -+ if (hifn_readramaddr(sc, a, data) < 0) -+ return (0); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) -+ return (0); -+ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; -+ } -+ -+ return (0); -+} -+ -+/* -+ * XXX For dram boards, one should really try all of the -+ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG -+ * is already set up correctly. -+ */ -+static int -+hifn_dramsize(struct hifn_softc *sc) -+{ -+ u_int32_t cnfg; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ /* -+ * 7955/7956 have a fixed internal ram of only 32K. -+ */ -+ sc->sc_ramsize = 32768; -+ } else { -+ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & -+ HIFN_PUCNFG_DRAMMASK; -+ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); -+ } -+ return (0); -+} -+ -+static void -+hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *cmdp = dma->cmdi++; -+ dma->cmdk = dma->cmdi; -+ -+ if (dma->srci == HIFN_D_SRC_RSIZE) { -+ dma->srci = 0; -+ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *srcp = dma->srci++; -+ dma->srck = dma->srci; -+ -+ if (dma->dsti == HIFN_D_DST_RSIZE) { -+ dma->dsti = 0; -+ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *dstp = dma->dsti++; -+ dma->dstk = dma->dsti; -+ -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *resp = dma->resi++; -+ dma->resk = dma->resi; -+} -+ -+static int -+hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t wc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, resi, srci, dsti; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ wc.masks = htole16(3 << 13); -+ wc.session_num = htole16(addr >> 14); -+ wc.total_source_count = htole16(8); -+ wc.total_dest_count = htole16(addr & 0x3fff); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ /* build write command */ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; -+ bcopy(data, &dma->test_src, sizeof(dma->test_src)); -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_src)); -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_dst)); -+ -+ dma->cmdr[cmdi].l = htole32(16 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(4 | masks); -+ dma->resr[resi].l = htole32(4 | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "writeramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ return (-1); -+ } else -+ r = 0; -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+static int -+hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t rc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, srci, dsti, resi; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ rc.masks = htole16(2 << 13); -+ rc.session_num = htole16(addr >> 14); -+ rc.total_source_count = htole16(addr & 0x3fff); -+ rc.total_dest_count = htole16(8); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_src)); -+ dma->test_src = 0; -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_dst)); -+ dma->test_dst = 0; -+ dma->cmdr[cmdi].l = htole32(8 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(8 | masks); -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "readramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ } else { -+ r = 0; -+ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+/* -+ * Initialize the descriptor rings. -+ */ -+static void -+hifn_init_dma(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ hifn_set_retry(sc); -+ -+ /* initialize static pointer values */ -+ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) -+ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, command_bufs[i][0])); -+ for (i = 0; i < HIFN_D_RES_RSIZE; i++) -+ dma->resr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, result_bufs[i][0])); -+ -+ dma->cmdr[HIFN_D_CMD_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); -+ dma->srcr[HIFN_D_SRC_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); -+ dma->dstr[HIFN_D_DST_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); -+ dma->resr[HIFN_D_RES_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); -+ -+ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; -+ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; -+ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; -+} -+ -+/* -+ * Writes out the raw command buffer space. Returns the -+ * command buffer size. -+ */ -+static u_int -+hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) -+{ -+ struct hifn_softc *sc = NULL; -+ u_int8_t *buf_pos; -+ hifn_base_command_t *base_cmd; -+ hifn_mac_command_t *mac_cmd; -+ hifn_crypt_command_t *cry_cmd; -+ int using_mac, using_crypt, len, ivlen; -+ u_int32_t dlen, slen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf_pos = buf; -+ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; -+ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; -+ -+ base_cmd = (hifn_base_command_t *)buf_pos; -+ base_cmd->masks = htole16(cmd->base_masks); -+ slen = cmd->src_mapsize; -+ if (cmd->sloplen) -+ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); -+ else -+ dlen = cmd->dst_mapsize; -+ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); -+ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); -+ dlen >>= 16; -+ slen >>= 16; -+ base_cmd->session_num = htole16( -+ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | -+ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); -+ buf_pos += sizeof(hifn_base_command_t); -+ -+ if (using_mac) { -+ mac_cmd = (hifn_mac_command_t *)buf_pos; -+ dlen = cmd->maccrd->crd_len; -+ mac_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ mac_cmd->masks = htole16(cmd->mac_masks | -+ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); -+ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); -+ mac_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_mac_command_t); -+ } -+ -+ if (using_crypt) { -+ cry_cmd = (hifn_crypt_command_t *)buf_pos; -+ dlen = cmd->enccrd->crd_len; -+ cry_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ cry_cmd->masks = htole16(cmd->cry_masks | -+ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); -+ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); -+ cry_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_crypt_command_t); -+ } -+ -+ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { -+ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); -+ buf_pos += HIFN_MAC_KEY_LENGTH; -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_3DES: -+ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); -+ buf_pos += HIFN_3DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_DES: -+ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); -+ buf_pos += HIFN_DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_RC4: -+ len = 256; -+ do { -+ int clen; -+ -+ clen = MIN(cmd->cklen, len); -+ bcopy(cmd->ck, buf_pos, clen); -+ len -= clen; -+ buf_pos += clen; -+ } while (len > 0); -+ bzero(buf_pos, 4); -+ buf_pos += 4; -+ break; -+ case HIFN_CRYPT_CMD_ALG_AES: -+ /* -+ * AES keys are variable 128, 192 and -+ * 256 bits (16, 24 and 32 bytes). -+ */ -+ bcopy(cmd->ck, buf_pos, cmd->cklen); -+ buf_pos += cmd->cklen; -+ break; -+ } -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_AES: -+ ivlen = HIFN_AES_IV_LENGTH; -+ break; -+ default: -+ ivlen = HIFN_IV_LENGTH; -+ break; -+ } -+ bcopy(cmd->iv, buf_pos, ivlen); -+ buf_pos += ivlen; -+ } -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { -+ bzero(buf_pos, 8); -+ buf_pos += 8; -+ } -+ -+ return (buf_pos - buf); -+} -+ -+static int -+hifn_dmamap_aligned(struct hifn_operand *op) -+{ -+ struct hifn_softc *sc = NULL; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+static __inline int -+hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_DST_RSIZE) { -+ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | -+ HIFN_D_MASKDONEIRQ); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *dst = &cmd->dst; -+ u_int32_t p, l; -+ int idx, used = 0, i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->dsti; -+ for (i = 0; i < dst->nsegs - 1; i++) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ -+ if (cmd->sloplen == 0) { -+ p = dst->segs[i].ds_addr; -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ dst->segs[i].ds_len; -+ } else { -+ p = sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, slop[cmd->slopidx]); -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ sizeof(u_int32_t); -+ -+ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | -+ (dst->segs[i].ds_len - cmd->sloplen)); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ } -+ dma->dstr[idx].p = htole32(p); -+ dma->dstr[idx].l = htole32(l); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ -+ dma->dsti = idx; -+ dma->dstu += used; -+ return (idx); -+} -+ -+static __inline int -+hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_SRC_RSIZE) { -+ dma->srcr[idx].l = htole32(HIFN_D_VALID | -+ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *src = &cmd->src; -+ int idx, i; -+ u_int32_t last = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->srci; -+ for (i = 0; i < src->nsegs; i++) { -+ if (i == src->nsegs - 1) -+ last = HIFN_D_LAST; -+ -+ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); -+ dma->srcr[idx].l = htole32(src->segs[i].ds_len | -+ HIFN_D_MASKDONEIRQ | last); -+ wmb(); -+ dma->srcr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, idx, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ -+ idx = hifn_dmamap_srcwrap(sc, idx); -+ } -+ dma->srci = idx; -+ dma->srcu += src->nsegs; -+ return (idx); -+} -+ -+ -+static int -+hifn_crypto( -+ struct hifn_softc *sc, -+ struct hifn_command *cmd, -+ struct cryptop *crp, -+ int hint) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t cmdlen, csr; -+ int cmdi, resi, err = 0; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * need 1 cmd, and 1 res -+ * -+ * NB: check this first since it's easy. -+ */ -+ HIFN_LOCK(sc); -+ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || -+ (dma->resu + 1) > HIFN_D_RES_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "cmd/result exhaustion, cmdu %u resu %u\n", -+ dma->cmdu, dma->resu); -+ } -+#endif -+ hifnstats.hst_nomem_cr++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ HIFN_UNLOCK(sc); -+ return (ERESTART); -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } -+ -+ if (hifn_dmamap_aligned(&cmd->src)) { -+ cmd->sloplen = cmd->src_mapsize & 3; -+ cmd->dst = cmd->src; -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto err_srcmap; -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#ifdef NOTYET -+ int totlen, len; -+ struct mbuf *m, *m0, *mlast; -+ -+ KASSERT(cmd->dst_m == cmd->src_m, -+ ("hifn_crypto: dst_m initialized improperly")); -+ hifnstats.hst_unaligned++; -+ /* -+ * Source is not aligned on a longword boundary. -+ * Copy the data to insure alignment. If we fail -+ * to allocate mbufs or clusters while doing this -+ * we return ERESTART so the operation is requeued -+ * at the crypto later, but only if there are -+ * ops already posted to the hardware; otherwise we -+ * have no guarantee that we'll be re-entered. -+ */ -+ totlen = cmd->src_mapsize; -+ if (cmd->src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m0, M_DONTWAIT, MT_DATA); -+ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { -+ m_free(m0); -+ m0 = NULL; -+ } -+ } else { -+ len = MLEN; -+ MGET(m0, M_DONTWAIT, MT_DATA); -+ } -+ if (m0 == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ goto err_srcmap; -+ } -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m0, M_DONTWAIT); -+ if ((m0->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ totlen -= len; -+ m0->m_pkthdr.len = m0->m_len = len; -+ mlast = m0; -+ -+ while (totlen > 0) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MLEN; -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if ((m->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ mlast->m_next = m; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ -+ m->m_len = len; -+ m0->m_pkthdr.len += len; -+ totlen -= len; -+ -+ mlast->m_next = m; -+ mlast = m; -+ } -+ cmd->dst_m = m0; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+#endif -+ } else { -+ device_printf(sc->sc_dev, -+ "%s,%d: unaligned contig buffers not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+ } -+ } -+ -+ if (cmd->dst_map == NULL) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { -+ hifnstats.hst_nomem_map++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } -+ } -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER), -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu, -+ cmd->src_nsegs, cmd->dst_nsegs); -+ } -+#endif -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_PREREAD); -+ } -+#endif -+ -+ /* -+ * need N src, and N dst -+ */ -+ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || -+ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", -+ dma->srcu, cmd->src_nsegs, -+ dma->dstu, cmd->dst_nsegs); -+ } -+#endif -+ hifnstats.hst_nomem_sd++; -+ err = ERESTART; -+ goto err_dstmap; -+ } -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ cmdi = dma->cmdi++; -+ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); -+ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); -+ -+ /* .p for command/result already set */ -+ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | -+ HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, cmdi, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ dma->cmdu++; -+ -+ /* -+ * We don't worry about missing an interrupt (which a "command wait" -+ * interrupt salvages us from), unless there is more than one command -+ * in the queue. -+ */ -+ if (dma->cmdu > 1) { -+ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ hifnstats.hst_ipackets++; -+ hifnstats.hst_ibytes += cmd->src_mapsize; -+ -+ hifn_dmamap_load_src(sc, cmd); -+ -+ /* -+ * Unlike other descriptors, we don't mask done interrupt from -+ * result descriptor. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "load res\n"); -+#endif -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ } -+ resi = dma->resi++; -+ KASSERT(dma->hifn_commands[resi] == NULL, -+ ("hifn_crypto: command slot %u busy", resi)); -+ dma->hifn_commands[resi] = cmd; -+ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); -+ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | -+ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch++; -+ if (sc->sc_curbatch > hifnstats.hst_maxbatch) -+ hifnstats.hst_maxbatch = sc->sc_curbatch; -+ hifnstats.hst_totbatch++; -+ } else { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch = 0; -+ } -+ HIFN_RESR_SYNC(sc, resi, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ dma->resu++; -+ -+ if (cmd->sloplen) -+ cmd->slopidx = resi; -+ -+ hifn_dmamap_load_dst(sc, cmd); -+ -+ csr = 0; -+ if (sc->sc_c_busy == 0) { -+ csr |= HIFN_DMACSR_C_CTRL_ENA; -+ sc->sc_c_busy = 1; -+ } -+ if (sc->sc_s_busy == 0) { -+ csr |= HIFN_DMACSR_S_CTRL_ENA; -+ sc->sc_s_busy = 1; -+ } -+ if (sc->sc_r_busy == 0) { -+ csr |= HIFN_DMACSR_R_CTRL_ENA; -+ sc->sc_r_busy = 1; -+ } -+ if (sc->sc_d_busy == 0) { -+ csr |= HIFN_DMACSR_D_CTRL_ENA; -+ sc->sc_d_busy = 1; -+ } -+ if (csr) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER)); -+ } -+#endif -+ -+ sc->sc_active = 5; -+ HIFN_UNLOCK(sc); -+ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); -+ return (err); /* success */ -+ -+err_dstmap: -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+err_dstmap1: -+err_srcmap: -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) -+#ifdef NOTYET -+ m_freem(cmd->dst_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ pci_unmap_buf(sc, &cmd->src); -+err_srcmap1: -+ HIFN_UNLOCK(sc); -+ return (err); -+} -+ -+static void -+hifn_tick(unsigned long arg) -+{ -+ struct hifn_softc *sc; -+ unsigned long l_flags; -+ -+ if (arg >= HIFN_MAX_CHIPS) -+ return; -+ sc = hifn_chip_idx[arg]; -+ if (!sc) -+ return; -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_active == 0) { -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t r = 0; -+ -+ if (dma->cmdu == 0 && sc->sc_c_busy) { -+ sc->sc_c_busy = 0; -+ r |= HIFN_DMACSR_C_CTRL_DIS; -+ } -+ if (dma->srcu == 0 && sc->sc_s_busy) { -+ sc->sc_s_busy = 0; -+ r |= HIFN_DMACSR_S_CTRL_DIS; -+ } -+ if (dma->dstu == 0 && sc->sc_d_busy) { -+ sc->sc_d_busy = 0; -+ r |= HIFN_DMACSR_D_CTRL_DIS; -+ } -+ if (dma->resu == 0 && sc->sc_r_busy) { -+ sc->sc_r_busy = 0; -+ r |= HIFN_DMACSR_R_CTRL_DIS; -+ } -+ if (r) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); -+ } else -+ sc->sc_active--; -+ HIFN_UNLOCK(sc); -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+hifn_intr(int irq, void *arg) -+#else -+hifn_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hifn_softc *sc = arg; -+ struct hifn_dma *dma; -+ u_int32_t dmacsr, restart; -+ int i, u; -+ unsigned long l_flags; -+ -+ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); -+ -+ /* Nothing in the DMA unit interrupted */ -+ if ((dmacsr & sc->sc_dmaier) == 0) -+ return IRQ_NONE; -+ -+ HIFN_LOCK(sc); -+ -+ dma = sc->sc_dma; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", -+ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, -+ dma->cmdi, dma->srci, dma->dsti, dma->resi, -+ dma->cmdk, dma->srck, dma->dstk, dma->resk, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+ } -+#endif -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); -+ -+ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && -+ (dmacsr & HIFN_DMACSR_PUBDONE)) -+ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, -+ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); -+ -+ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); -+ if (restart) -+ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (dmacsr & HIFN_DMACSR_ILLR) -+ device_printf(sc->sc_dev, "illegal read\n"); -+ if (dmacsr & HIFN_DMACSR_ILLW) -+ device_printf(sc->sc_dev, "illegal write\n"); -+ } -+ -+ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); -+ if (restart) { -+ device_printf(sc->sc_dev, "abort, resetting.\n"); -+ hifnstats.hst_abort++; -+ hifn_abort(sc); -+ HIFN_UNLOCK(sc); -+ return IRQ_HANDLED; -+ } -+ -+ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { -+ /* -+ * If no slots to process and we receive a "waiting on -+ * command" interrupt, we disable the "waiting on command" -+ * (by clearing it). -+ */ -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ /* clear the rings */ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ -+ if (i != HIFN_D_RES_RSIZE) { -+ struct hifn_command *cmd; -+ u_int8_t *macbuf = NULL; -+ -+ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, -+ ("hifn_intr: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } -+ -+ hifn_callback(sc, cmd, macbuf); -+ hifnstats.hst_opackets++; -+ u--; -+ } -+ -+ if (++i == (HIFN_D_RES_RSIZE + 1)) -+ i = 0; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ i = dma->srck; u = dma->srcu; -+ while (u != 0) { -+ if (i == HIFN_D_SRC_RSIZE) -+ i = 0; -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ i++, u--; -+ } -+ dma->srck = i; dma->srcu = u; -+ -+ i = dma->cmdk; u = dma->cmdu; -+ while (u != 0) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ if (i != HIFN_D_CMD_RSIZE) { -+ u--; -+ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); -+ } -+ if (++i == (HIFN_D_CMD_RSIZE + 1)) -+ i = 0; -+ } -+ dma->cmdk = i; dma->cmdu = u; -+ -+ HIFN_UNLOCK(sc); -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "wakeup crypto (%x) u %d/%d/%d/%d\n", -+ sc->sc_needwakeup, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+#endif -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct cryptoini *c; -+ int mac = 0, cry = 0, sesn; -+ struct hifn_session *ses = NULL; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_newsession: null softc")); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (!sc->sc_sessions[sesn].hs_used) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); -+ bzero(sc->sc_sessions, sesn * sizeof(*ses)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ HIFN_UNLOCK(sc); -+ -+ bzero(ses, sizeof(*ses)); -+ ses->hs_used = 1; -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_SHA1: -+ case CRYPTO_MD5_HMAC: -+ case CRYPTO_SHA1_HMAC: -+ if (mac) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ mac = 1; -+ ses->hs_mlen = c->cri_mlen; -+ if (ses->hs_mlen == 0) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ses->hs_mlen = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ses->hs_mlen = 20; -+ break; -+ } -+ } -+ break; -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ case CRYPTO_AES_CBC: -+ /* XXX this may read fewer, does it matter? */ -+ read_random(ses->hs_iv, -+ c->cri_alg == CRYPTO_AES_CBC ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ /*FALLTHROUGH*/ -+ case CRYPTO_ARC4: -+ if (cry) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ cry = 1; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ } -+ if (mac == 0 && cry == 0) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); -+ -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ * XXX this routine should run a zero'd mac/encrypt key into context ram. -+ * XXX to blow away any keys already stored there. -+ */ -+static int -+hifn_freesession(device_t dev, u_int64_t tid) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ int session, error; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_freesession: null softc")); -+ if (sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ session = HIFN_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); -+ error = 0; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ error = EINVAL; -+ } -+ HIFN_UNLOCK(sc); -+ -+ return (error); -+} -+ -+static int -+hifn_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct hifn_command *cmd = NULL; -+ int session, err, ivlen; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL) { -+ hifnstats.hst_invalid++; -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ session = HIFN_SESSION(crp->crp_sid); -+ -+ if (sc == NULL || session >= sc->sc_nsessions) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); -+ if (cmd == NULL) { -+ hifnstats.hst_nomem++; -+ err = ENOMEM; -+ goto errout; -+ } -+ memset(cmd, 0, sizeof(*cmd)); -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ cmd->src_skb = (struct sk_buff *)crp->crp_buf; -+ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ cmd->src_io = (struct uio *)crp->crp_buf; -+ cmd->dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ cmd->src_buf = crp->crp_buf; -+ cmd->dst_buf = crp->crp_buf; -+ } -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) -+ cmd->base_masks |= HIFN_BASE_CMD_DECODE; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ cmd->base_masks = HIFN_BASE_CMD_DECODE; -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the 7751 as requested -+ */ -+ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd) { -+ cmd->enccrd = enccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; -+ switch (enccrd->crd_alg) { -+ case CRYPTO_ARC4: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; -+ break; -+ case CRYPTO_DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_3DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_AES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ if (enccrd->crd_alg != CRYPTO_ARC4) { -+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else -+ bcopy(sc->sc_sessions[session].hs_iv, -+ cmd->iv, ivlen); -+ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) -+ == 0) { -+ crypto_copyback(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else { -+ crypto_copydata(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ cmd->ck = enccrd->crd_key; -+ cmd->cklen = enccrd->crd_klen >> 3; -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ -+ /* -+ * Need to specify the size for the AES key in the masks. -+ */ -+ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == -+ HIFN_CRYPT_CMD_ALG_AES) { -+ switch (cmd->cklen) { -+ case 16: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; -+ break; -+ case 24: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; -+ break; -+ case 32: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ } -+ -+ if (maccrd) { -+ cmd->maccrd = maccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_MAC; -+ -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_MD5_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ case CRYPTO_SHA1: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || -+ maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; -+ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); -+ bzero(cmd->mac + (maccrd->crd_klen >> 3), -+ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); -+ } -+ } -+ -+ cmd->crp = crp; -+ cmd->session_num = session; -+ cmd->softc = sc; -+ -+ err = hifn_crypto(sc, cmd, crp, hint); -+ if (!err) { -+ return 0; -+ } else if (err == ERESTART) { -+ /* -+ * There weren't enough resources to dispatch the request -+ * to the part. Notify the caller so they'll requeue this -+ * request and resubmit it again soon. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "requeue request\n"); -+#endif -+ kfree(cmd); -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ return (err); -+ } -+ -+errout: -+ if (cmd != NULL) -+ kfree(cmd); -+ if (err == EINVAL) -+ hifnstats.hst_invalid++; -+ else -+ hifnstats.hst_nomem++; -+ crp->crp_etype = err; -+ crypto_done(crp); -+ return (err); -+} -+ -+static void -+hifn_abort(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_command *cmd; -+ struct cryptop *crp; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ crp = cmd->crp; -+ -+ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { -+ /* Salvage what we can. */ -+ u_int8_t *macbuf; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } else -+ macbuf = NULL; -+ hifnstats.hst_opackets++; -+ hifn_callback(sc, cmd, macbuf); -+ } else { -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ m_freem(cmd->src_m); -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ -+ /* non-shared buffers cannot be restarted */ -+ if (cmd->src_map != cmd->dst_map) { -+ /* -+ * XXX should be EAGAIN, delayed until -+ * after the reset. -+ */ -+ crp->crp_etype = ENOMEM; -+ pci_unmap_buf(sc, &cmd->dst); -+ } else -+ crp->crp_etype = ENOMEM; -+ -+ pci_unmap_buf(sc, &cmd->src); -+ -+ kfree(cmd); -+ if (crp->crp_etype != EAGAIN) -+ crypto_done(crp); -+ } -+ -+ if (++i == HIFN_D_RES_RSIZE) -+ i = 0; -+ u--; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ hifn_reset_board(sc, 1); -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+} -+ -+static void -+hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct cryptop *crp = cmd->crp; -+ struct cryptodesc *crd; -+ int i, u, ivlen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+ totlen = cmd->src_mapsize; -+ for (m = cmd->dst_m; m != NULL; m = m->m_next) { -+ if (totlen < m->m_len) { -+ m->m_len = totlen; -+ totlen = 0; -+ } else -+ totlen -= m->m_len; -+ } -+ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; -+ m_freem(cmd->src_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ } -+ -+ if (cmd->sloplen != 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, -+ (caddr_t)&dma->slop[cmd->slopidx]); -+ } -+ -+ i = dma->dstk; u = dma->dstu; -+ while (u != 0) { -+ if (i == HIFN_D_DST_RSIZE) -+ i = 0; -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+#endif -+ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ break; -+ } -+ i++, u--; -+ } -+ dma->dstk = i; dma->dstu = u; -+ -+ hifnstats.hst_obytes += cmd->dst_mapsize; -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == -+ HIFN_BASE_CMD_CRYPT) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_DES_CBC && -+ crd->crd_alg != CRYPTO_3DES_CBC && -+ crd->crd_alg != CRYPTO_AES_CBC) -+ continue; -+ ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivlen, ivlen, -+ cmd->softc->sc_sessions[cmd->session_num].hs_iv); -+ break; -+ } -+ } -+ -+ if (macbuf != NULL) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int len; -+ -+ if (crd->crd_alg != CRYPTO_MD5 && -+ crd->crd_alg != CRYPTO_SHA1 && -+ crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) { -+ continue; -+ } -+ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, len, macbuf); -+ break; -+ } -+ } -+ -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+ pci_unmap_buf(sc, &cmd->src); -+ kfree(cmd); -+ crypto_done(crp); -+} -+ -+/* -+ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 -+ * and Group 1 registers; avoid conditions that could create -+ * burst writes by doing a read in between the writes. -+ * -+ * NB: The read we interpose is always to the same register; -+ * we do this because reading from an arbitrary (e.g. last) -+ * register may not always work. -+ */ -+static void -+hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar0_lastreg == reg - 4) -+ readl(sc->sc_bar0 + HIFN_0_PUCNFG); -+ sc->sc_bar0_lastreg = reg; -+ } -+ writel(val, sc->sc_bar0 + reg); -+} -+ -+static void -+hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar1_lastreg == reg - 4) -+ readl(sc->sc_bar1 + HIFN_1_REVID); -+ sc->sc_bar1_lastreg = reg; -+ } -+ writel(val, sc->sc_bar1 + reg); -+} -+ -+ -+static struct pci_device_id hifn_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ /* -+ * Other vendors share this PCI ID as well, such as -+ * http://www.powercrypt.com, and obviously they also -+ * use the same key. -+ */ -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { 0, 0, 0, 0, 0, 0, } -+}; -+MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); -+ -+static struct pci_driver hifn_driver = { -+ .name = "hifn", -+ .id_table = hifn_pci_tbl, -+ .probe = hifn_probe, -+ .remove = hifn_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hifn_init (void) -+{ -+ struct hifn_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); -+ -+ rc = pci_register_driver(&hifn_driver); -+ pci_register_driver_compat(&hifn_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hifn_exit (void) -+{ -+ pci_unregister_driver(&hifn_driver); -+} -+ -+module_init(hifn_init); -+module_exit(hifn_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); -diff --git a/crypto/ocf/hifn/hifn7751reg.h b/crypto/ocf/hifn/hifn7751reg.h -new file mode 100644 -index 0000000..23d70c5 ---- /dev/null -+++ b/crypto/ocf/hifn/hifn7751reg.h -@@ -0,0 +1,540 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#ifndef __HIFN_H__ -+#define __HIFN_H__ -+ -+/* -+ * Some PCI configuration space offset defines. The names were made -+ * identical to the names used by the Linux kernel. -+ */ -+#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ -+#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ -+#define HIFN_TRDY_TIMEOUT 0x40 -+#define HIFN_RETRY_TIMEOUT 0x41 -+ -+/* -+ * PCI vendor and device identifiers -+ * (the names are preserved from their OpenBSD source). -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ -+#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ -+#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ -+ -+#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ -+#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ -+ -+#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ -+#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ -+ -+/* -+ * The values below should multiple of 4 -- and be large enough to handle -+ * any command the driver implements. -+ * -+ * MAX_COMMAND = base command + mac command + encrypt command + -+ * mac-key + rc4-key -+ * MAX_RESULT = base result + mac result + mac + encrypt result -+ * -+ * -+ */ -+#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) -+#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) -+ -+/* -+ * hifn_desc_t -+ * -+ * Holds an individual descriptor for any of the rings. -+ */ -+typedef struct hifn_desc { -+ volatile u_int32_t l; /* length and status bits */ -+ volatile u_int32_t p; -+} hifn_desc_t; -+ -+/* -+ * Masks for the "length" field of struct hifn_desc. -+ */ -+#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ -+#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ -+#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ -+#define HIFN_D_OVER 0x08000000 /* overflow */ -+#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ -+#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ -+#define HIFN_D_VALID 0x80000000 /* valid bit */ -+ -+ -+/* -+ * Processing Unit Registers (offset from BASEREG0) -+ */ -+#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ -+#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ -+#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ -+#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ -+#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ -+#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ -+#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ -+#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ -+#define HIFN_0_MUTE1 0x80 -+#define HIFN_0_MUTE2 0x90 -+#define HIFN_0_SPACESIZE 0x100 /* Register space size */ -+ -+/* Processing Unit Control Register (HIFN_0_PUCTRL) */ -+#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ -+#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ -+#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ -+#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ -+#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ -+ -+/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ -+#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ -+#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ -+#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ -+#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ -+#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ -+#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ -+#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ -+#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ -+#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ -+#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ -+#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ -+#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ -+#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ -+#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ -+#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ -+#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ -+#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ -+#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ -+#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ -+#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ -+ -+/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ -+#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ -+#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ -+#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ -+#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ -+#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ -+#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ -+#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ -+#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ -+#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ -+ -+/* FIFO Status Register (HIFN_0_FIFOSTAT) */ -+#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ -+#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ -+ -+/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ -+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ -+ -+/* -+ * DMA Interface Registers (offset from BASEREG1) -+ */ -+#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ -+#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ -+#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ -+#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ -+#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ -+#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ -+#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ -+#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ -+#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ -+#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ -+#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ -+#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ -+#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ -+#define HIFN_1_REVID 0x98 /* Revision ID */ -+ -+#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ -+#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ -+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ -+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ -+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ -+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ -+#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ -+#define HIFN_1_RNG_DATA 0x318 /* RNG data */ -+#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ -+#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ -+#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ -+ -+/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ -+#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ -+#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ -+#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ -+#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ -+#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ -+#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ -+#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ -+#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ -+#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ -+#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ -+#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ -+#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ -+#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ -+#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ -+#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ -+#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ -+#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ -+#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ -+#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ -+#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ -+#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ -+#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ -+#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ -+ -+/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ -+#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ -+#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ -+#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ -+#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ -+#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ -+#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ -+#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ -+#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ -+#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ -+#define HIFN_DMACNFG_UNLOCK 0x00000800 -+#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ -+#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ -+#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ -+#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ -+#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 -+ -+/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ -+#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ -+ -+/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ -+#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ -+#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ -+#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ -+ -+/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ -+#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ -+#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ -+ -+/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ -+#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ -+#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ -+#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ -+#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ -+#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ -+#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ -+#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ -+#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ -+#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ -+ -+/* Public key reset register (HIFN_1_PUB_RESET) */ -+#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ -+ -+/* Public operation register (HIFN_1_PUB_OP) */ -+#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ -+#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ -+#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ -+#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ -+#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ -+#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ -+#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ -+#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ -+#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ -+#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ -+#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ -+#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ -+#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ -+#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ -+#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ -+#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ -+#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ -+ -+/* Public operand length register (HIFN_1_PUB_OPLEN) */ -+#define HIFN_PUBOPLEN_MODLEN 0x0000007f -+#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 -+#define HIFN_PUBOPLEN_REDLEN 0x003c0000 -+ -+/* Public status register (HIFN_1_PUB_STATUS) */ -+#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ -+#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ -+ -+/* Public interrupt enable register (HIFN_1_PUB_IEN) */ -+#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ -+ -+/* Random number generator config register (HIFN_1_RNG_CONFIG) */ -+#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ -+ -+/* -+ * Register offsets in register set 1 -+ */ -+ -+#define HIFN_UNLOCK_SECRET1 0xf4 -+#define HIFN_UNLOCK_SECRET2 0xfc -+ -+/* -+ * PLL config register -+ * -+ * This register is present only on 7954/7955/7956 parts. It must be -+ * programmed according to the bus interface method used by the h/w. -+ * Note that the parts require a stable clock. Since the PCI clock -+ * may vary the reference clock must usually be used. To avoid -+ * overclocking the core logic, setup must be done carefully, refer -+ * to the driver for details. The exact multiplier required varies -+ * by part and system configuration; refer to the Hifn documentation. -+ */ -+#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ -+#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ -+/* bit 2 reserved */ -+#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ -+#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ -+/* bits 5-9 reserved */ -+#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ -+#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ -+#define HIFN_PLL_ND_SHIFT 11 -+#define HIFN_PLL_ND_2 0x00000000 /* 2x */ -+#define HIFN_PLL_ND_4 0x00000800 /* 4x */ -+#define HIFN_PLL_ND_6 0x00001000 /* 6x */ -+#define HIFN_PLL_ND_8 0x00001800 /* 8x */ -+#define HIFN_PLL_ND_10 0x00002000 /* 10x */ -+#define HIFN_PLL_ND_12 0x00002800 /* 12x */ -+/* bits 14-15 reserved */ -+#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ -+/* bits 17-31 reserved */ -+ -+/* -+ * Board configuration specifies only these bits. -+ */ -+#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) -+ -+/* -+ * Public Key Engine Mode Register -+ */ -+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ -+ -+ -+/********************************************************************* -+ * Structs for board commands -+ * -+ *********************************************************************/ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_base_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t session_num; -+ volatile u_int16_t total_source_count; -+ volatile u_int16_t total_dest_count; -+} hifn_base_command_t; -+ -+#define HIFN_BASE_CMD_MAC 0x0400 -+#define HIFN_BASE_CMD_CRYPT 0x0800 -+#define HIFN_BASE_CMD_DECODE 0x2000 -+#define HIFN_BASE_CMD_SRCLEN_M 0xc000 -+#define HIFN_BASE_CMD_SRCLEN_S 14 -+#define HIFN_BASE_CMD_DSTLEN_M 0x3000 -+#define HIFN_BASE_CMD_DSTLEN_S 12 -+#define HIFN_BASE_CMD_LENMASK_HI 0x30000 -+#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_crypt_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_crypt_command_t; -+ -+#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ -+#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ -+#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ -+#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ -+#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ -+#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ -+#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ -+#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ -+#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ -+#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ -+#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ -+#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ -+#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ -+ -+#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 -+#define HIFN_CRYPT_CMD_SRCLEN_S 14 -+ -+#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ -+#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ -+#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ -+#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_mac_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_mac_command_t; -+ -+#define HIFN_MAC_CMD_ALG_MASK 0x0001 -+#define HIFN_MAC_CMD_ALG_SHA1 0x0000 -+#define HIFN_MAC_CMD_ALG_MD5 0x0001 -+#define HIFN_MAC_CMD_MODE_MASK 0x000c -+#define HIFN_MAC_CMD_MODE_HMAC 0x0000 -+#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 -+#define HIFN_MAC_CMD_MODE_HASH 0x0008 -+#define HIFN_MAC_CMD_MODE_FULL 0x0004 -+#define HIFN_MAC_CMD_TRUNC 0x0010 -+#define HIFN_MAC_CMD_RESULT 0x0020 -+#define HIFN_MAC_CMD_APPEND 0x0040 -+#define HIFN_MAC_CMD_SRCLEN_M 0xc000 -+#define HIFN_MAC_CMD_SRCLEN_S 14 -+ -+/* -+ * MAC POS IPsec initiates authentication after encryption on encodes -+ * and before decryption on decodes. -+ */ -+#define HIFN_MAC_CMD_POS_IPSEC 0x0200 -+#define HIFN_MAC_CMD_NEW_KEY 0x0800 -+ -+/* -+ * The poll frequency and poll scalar defines are unshifted values used -+ * to set fields in the DMA Configuration Register. -+ */ -+#ifndef HIFN_POLL_FREQUENCY -+#define HIFN_POLL_FREQUENCY 0x1 -+#endif -+ -+#ifndef HIFN_POLL_SCALAR -+#define HIFN_POLL_SCALAR 0x0 -+#endif -+ -+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ -+#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ -+#endif /* __HIFN_H__ */ -diff --git a/crypto/ocf/hifn/hifn7751var.h b/crypto/ocf/hifn/hifn7751var.h -new file mode 100644 -index 0000000..6146bfb ---- /dev/null -+++ b/crypto/ocf/hifn/hifn7751var.h -@@ -0,0 +1,369 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __HIFN7751VAR_H__ -+#define __HIFN7751VAR_H__ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Some configurable values for the driver. By default command+result -+ * descriptor rings are the same size. The src+dst descriptor rings -+ * are sized at 3.5x the number of potential commands. Slower parts -+ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) -+ * src+cmd/result descriptors. It's not clear that increasing the size -+ * of the descriptor rings helps performance significantly as other -+ * factors tend to come into play (e.g. copying misaligned packets). -+ */ -+#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ -+#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ -+#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ -+#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ -+ -+/* -+ * Length values for cryptography -+ */ -+#define HIFN_DES_KEY_LENGTH 8 -+#define HIFN_3DES_KEY_LENGTH 24 -+#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH -+#define HIFN_IV_LENGTH 8 -+#define HIFN_AES_IV_LENGTH 16 -+#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH -+ -+/* -+ * Length values for authentication -+ */ -+#define HIFN_MAC_KEY_LENGTH 64 -+#define HIFN_MD5_LENGTH 16 -+#define HIFN_SHA1_LENGTH 20 -+#define HIFN_MAC_TRUNC_LENGTH 12 -+ -+#define MAX_SCATTER 64 -+ -+/* -+ * Data structure to hold all 4 rings and any other ring related data. -+ */ -+struct hifn_dma { -+ /* -+ * Descriptor rings. We add +1 to the size to accomidate the -+ * jump descriptor. -+ */ -+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; -+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; -+ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; -+ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; -+ -+ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; -+ -+ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; -+ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; -+ u_int32_t slop[HIFN_D_CMD_RSIZE]; -+ -+ u_int64_t test_src, test_dst; -+ -+ /* -+ * Our current positions for insertion and removal from the desriptor -+ * rings. -+ */ -+ int cmdi, srci, dsti, resi; -+ volatile int cmdu, srcu, dstu, resu; -+ int cmdk, srck, dstk, resk; -+}; -+ -+struct hifn_session { -+ int hs_used; -+ int hs_mlen; -+ u_int8_t hs_iv[HIFN_MAX_IV_LENGTH]; -+}; -+ -+#define HIFN_RING_SYNC(sc, r, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) -+#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) -+#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) -+#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) -+ -+#define HIFN_CMD_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_RES_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+typedef int bus_size_t; -+ -+/* -+ * Holds data specific to a single HIFN board. -+ */ -+struct hifn_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* PCI device pointer */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ -+ int sc_num; /* for multiple devs */ -+ -+ ocf_iomem_t sc_bar0; -+ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ -+ ocf_iomem_t sc_bar1; -+ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ -+ -+ int sc_irq; -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int32_t sc_cid; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+#ifdef HIFN_VULCANDEV -+ struct cdev *sc_pkdev; -+#endif -+}; -+ -+#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+/* -+ * hifn_command_t -+ * -+ * This is the control structure used to pass commands to hifn_encrypt(). -+ * -+ * flags -+ * ----- -+ * Flags is the bitwise "or" values for command configuration. A single -+ * encrypt direction needs to be set: -+ * -+ * HIFN_ENCODE or HIFN_DECODE -+ * -+ * To use cryptography, a single crypto algorithm must be included: -+ * -+ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES -+ * -+ * To use authentication is used, a single MAC algorithm must be included: -+ * -+ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 -+ * -+ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. -+ * If the value below is set, hash values are truncated or assumed -+ * truncated to 12 bytes: -+ * -+ * HIFN_MAC_TRUNC -+ * -+ * Keys for encryption and authentication can be sent as part of a command, -+ * or the last key value used with a particular session can be retrieved -+ * and used again if either of these flags are not specified. -+ * -+ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY -+ * -+ * session_num -+ * ----------- -+ * A number between 0 and 2048 (for DRAM models) or a number between -+ * 0 and 768 (for SRAM models). Those who don't want to use session -+ * numbers should leave value at zero and send a new crypt key and/or -+ * new MAC key on every command. If you use session numbers and -+ * don't send a key with a command, the last key sent for that same -+ * session number will be used. -+ * -+ * Warning: Using session numbers and multiboard at the same time -+ * is currently broken. -+ * -+ * mbuf -+ * ---- -+ * Either fill in the mbuf pointer and npa=0 or -+ * fill packp[] and packl[] and set npa to > 0 -+ * -+ * mac_header_skip -+ * --------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * authentication begins. This must be a number between 0 and 2^16-1 -+ * and can be used by IPsec implementers to skip over IP headers. -+ * *** Value ignored if authentication not used *** -+ * -+ * crypt_header_skip -+ * ----------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * the cryptographic operation begins. This must be a number between 0 -+ * and 2^16-1. For IPsec, this number will always be 8 bytes larger -+ * than the auth_header_skip (to skip over the ESP header). -+ * *** Value ignored if cryptography not used *** -+ * -+ */ -+struct hifn_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ unsigned char *buf; -+ } u; -+ void *map; -+ bus_size_t mapsize; -+ int nsegs; -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ } segs[MAX_SCATTER]; -+}; -+ -+struct hifn_command { -+ u_int16_t session_num; -+ u_int16_t base_masks, cry_masks, mac_masks; -+ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; -+ int cklen; -+ int sloplen, slopidx; -+ -+ struct hifn_operand src; -+ struct hifn_operand dst; -+ -+ struct hifn_softc *softc; -+ struct cryptop *crp; -+ struct cryptodesc *enccrd, *maccrd; -+}; -+ -+#define src_skb src.u.skb -+#define src_io src.u.io -+#define src_map src.map -+#define src_mapsize src.mapsize -+#define src_segs src.segs -+#define src_nsegs src.nsegs -+#define src_buf src.u.buf -+ -+#define dst_skb dst.u.skb -+#define dst_io dst.u.io -+#define dst_map dst.map -+#define dst_mapsize dst.mapsize -+#define dst_segs dst.segs -+#define dst_nsegs dst.nsegs -+#define dst_buf dst.u.buf -+ -+/* -+ * Return values for hifn_crypto() -+ */ -+#define HIFN_CRYPTO_SUCCESS 0 -+#define HIFN_CRYPTO_BAD_INPUT (-1) -+#define HIFN_CRYPTO_RINGS_FULL (-2) -+ -+/************************************************************************** -+ * -+ * Function: hifn_crypto -+ * -+ * Purpose: Called by external drivers to begin an encryption on the -+ * HIFN board. -+ * -+ * Blocking/Non-blocking Issues -+ * ============================ -+ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. -+ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough -+ * room in any of the rings for the request to proceed. -+ * -+ * Return Values -+ * ============= -+ * 0 for success, negative values on error -+ * -+ * Defines for negative error codes are: -+ * -+ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. -+ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking -+ * behaviour was requested. -+ * -+ *************************************************************************/ -+ -+/* -+ * Convert back and forth from 'sid' to 'card' and 'session' -+ */ -+#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define HIFN_SESSION(sid) ((sid) & 0x000007ff) -+#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) -+ -+#endif /* _KERNEL */ -+ -+struct hifn_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ -+ u_int32_t hst_abort; -+ u_int32_t hst_noirq; /* IRQ for no reason */ -+ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ -+ u_int32_t hst_maxbatch; /* max ops submitted together */ -+ u_int32_t hst_unaligned; /* unaligned src caused copy */ -+ /* -+ * The following divides hst_nomem into more specific buckets. -+ */ -+ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ -+ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ -+ u_int32_t hst_nomem_mbuf; /* MGET* failed */ -+ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ -+ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ -+ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ -+}; -+ -+#endif /* __HIFN7751VAR_H__ */ -diff --git a/crypto/ocf/hifn/hifnHIPP.c b/crypto/ocf/hifn/hifnHIPP.c -new file mode 100644 -index 0000000..1785147 ---- /dev/null -+++ b/crypto/ocf/hifn/hifnHIPP.c -@@ -0,0 +1,420 @@ -+/*- -+ * Driver for Hifn HIPP-I/II chipset -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn Inc. -+ * -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "hifnHIPPreg.h" -+#include "hifnHIPPvar.h" -+ -+#if 1 -+#define DPRINTF(a...) if (hipp_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+typedef int bus_size_t; -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+#define debug hipp_debug -+int hipp_debug = 0; -+module_param(hipp_debug, int, 0644); -+MODULE_PARM_DESC(hipp_debug, "Enable debug"); -+ -+int hipp_maxbatch = 1; -+module_param(hipp_maxbatch, int, 0644); -+MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); -+ -+static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hipp_remove(struct pci_dev *dev); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg); -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+ -+static int hipp_num_chips = 0; -+static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; -+ -+static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hipp_freesession(device_t, u_int64_t); -+static int hipp_process(device_t, struct cryptop *, int); -+ -+static device_method_t hipp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hipp_newsession), -+ DEVMETHOD(cryptodev_freesession,hipp_freesession), -+ DEVMETHOD(cryptodev_process, hipp_process), -+}; -+ -+static __inline u_int32_t -+READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar[barno] + reg); -+ //sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+static __inline void -+WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) -+{ -+ writel(val, sc->sc_bar[barno] + reg); -+} -+ -+#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) -+#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) -+#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) -+#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) -+ -+static int -+hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_freesession(device_t dev, u_int64_t tid) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ return EINVAL; -+} -+ -+static const char* -+hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) -+{ -+ char *n = NULL; -+ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; -+ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; -+ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; -+ } -+ } -+ -+ if(n==NULL) { -+ snprintf(buf, blen, "VID=%02x,PID=%02x", -+ pci_get_vendor(sc->sc_pcidev), -+ pci_get_device(sc->sc_pcidev)); -+ } else { -+ buf[0]='\0'; -+ strncat(buf, n, blen); -+ } -+ return buf; -+} -+ -+struct hipp_fs_entry { -+ struct attribute attr; -+ /* other stuff */ -+}; -+ -+ -+static ssize_t -+cryptoid_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct hipp_softc *sc; -+ -+ sc = pci_get_drvdata(to_pci_dev (dev)); -+ return sprintf (buf, "%d\n", sc->sc_cid); -+} -+ -+struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hipp_softc *sc = NULL; -+ int i; -+ //char rbase; -+ //u_int16_t ena; -+ int rev; -+ //int rseg; -+ int rc; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = hipp_num_chips++; -+ -+ if (sc->sc_num < HIPP_MAX_CHIPS) -+ hipp_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* -+ * Setup PCI resources. -+ * The READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver are used -+ * to permit better debugging. -+ */ -+ for(i=0; i<4; i++) { -+ unsigned long mem_start, mem_len; -+ mem_start = pci_resource_start(sc->sc_pcidev, i); -+ mem_len = pci_resource_len(sc->sc_pcidev, i); -+ sc->sc_barphy[i] = (caddr_t)mem_start; -+ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar[i]) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); -+ goto fail; -+ } -+ } -+ -+ //hipp_reset_board(sc, 0); -+ pci_set_master(sc->sc_pcidev); -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; -+ -+ { -+ char b[32]; -+ device_printf(sc->sc_dev, "%s, rev %u", -+ hipp_partname(sc, b, sizeof(b)), rev); -+ } -+ -+#if 0 -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+#endif -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+#if 0 /* cannot work with a non-GPL module */ -+ /* make a sysfs entry to let the world know what entry we got */ -+ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); -+#endif -+ -+#if 0 -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+#endif -+ -+#if 0 /* no code here yet ?? */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+#endif -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+#endif -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hipp_remove(struct pci_dev *dev) -+{ -+ struct hipp_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* disable interrupts */ -+ HIPP_LOCK(sc); -+ -+#if 0 -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+#endif -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+#endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg) -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hipp_softc *sc = arg; -+ -+ sc = sc; /* shut up compiler */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct pci_device_id hipp_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+}; -+MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); -+ -+static struct pci_driver hipp_driver = { -+ .name = "hipp", -+ .id_table = hipp_pci_tbl, -+ .probe = hipp_probe, -+ .remove = hipp_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hipp_init (void) -+{ -+ struct hipp_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); -+ -+ rc = pci_register_driver(&hipp_driver); -+ pci_register_driver_compat(&hipp_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hipp_exit (void) -+{ -+ pci_unregister_driver(&hipp_driver); -+} -+ -+module_init(hipp_init); -+module_exit(hipp_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("Michael Richardson "); -+MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); -diff --git a/crypto/ocf/hifn/hifnHIPPreg.h b/crypto/ocf/hifn/hifnHIPPreg.h -new file mode 100644 -index 0000000..8c0e720 ---- /dev/null -+++ b/crypto/ocf/hifn/hifnHIPPreg.h -@@ -0,0 +1,46 @@ -+/*- -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPP_H__ -+#define __HIFNHIPP_H__ -+ -+/* -+ * PCI vendor and device identifiers -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ -+ -+#define HIPP_1_REVID 0x01 /* BOGUS */ -+ -+#endif /* __HIPP_H__ */ -diff --git a/crypto/ocf/hifn/hifnHIPPvar.h b/crypto/ocf/hifn/hifnHIPPvar.h -new file mode 100644 -index 0000000..dde47f7 ---- /dev/null -+++ b/crypto/ocf/hifn/hifnHIPPvar.h -@@ -0,0 +1,93 @@ -+/* -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson * -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPPVAR_H__ -+#define __HIFNHIPPVAR_H__ -+ -+#define HIPP_MAX_CHIPS 8 -+ -+/* -+ * Holds data specific to a single Hifn HIPP-I board. -+ */ -+struct hipp_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* device backpointer */ -+ ocf_iomem_t sc_bar[5]; -+ caddr_t sc_barphy[5]; /* physical address */ -+ int sc_num; /* for multiple devs */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ int32_t sc_cid; -+ int sc_irq; -+ -+#if 0 -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+ struct miscdevice sc_miscdev; -+#endif -+}; -+ -+#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+#endif /* __HIFNHIPPVAR_H__ */ -diff --git a/crypto/ocf/ixp4xx/Makefile b/crypto/ocf/ixp4xx/Makefile -new file mode 100644 -index 0000000..d94a3b7 ---- /dev/null -+++ b/crypto/ocf/ixp4xx/Makefile -@@ -0,0 +1,104 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+# -+# You will need to point this at your Intel ixp425 includes, this portion -+# of the Makefile only really works under SGLinux with the appropriate libs -+# installed. They can be downloaded from http://www.snapgear.org/ -+# -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXPLATFORM = ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXPLATFORM = ixp43X -+else -+IXPLATFORM = ixp42X -+endif -+endif -+ -+ifdef CONFIG_IXP400_LIB_2_4 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_1 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_0 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal -+endif -+ifdef IX_XSCALE_SW -+ifdef CONFIG_IXP400_LIB_2_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/common/include/ \ -+ -I$(OSAL_DIR)/common/include/modules/ \ -+ -I$(OSAL_DIR)/common/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ -+ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ -+ -DUSE_IXP4XX_CRYPTO -+else -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/ \ -+ -I$(OSAL_DIR)/os/linux/include/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/include/ \ -+ -I$(OSAL_DIR)/include/modules/ \ -+ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/include/platforms/ \ -+ -I$(OSAL_DIR)/include/platforms/ixp400/ \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+endif -+ifdef CONFIG_IXP400_LIB_1_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+ifndef IXPDIR -+IXPDIR = ixp-version-is-not-supported -+endif -+ -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXP_CFLAGS += -D__ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXP_CFLAGS += -D__ixp43X -+else -+IXP_CFLAGS += -D__ixp42X -+endif -+endif -+ -+obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o -+ -+obj ?= . -+EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/ixp4xx/ixp4xx.c b/crypto/ocf/ixp4xx/ixp4xx.c -new file mode 100644 -index 0000000..7af7b0a ---- /dev/null -+++ b/crypto/ocf/ixp4xx/ixp4xx.c -@@ -0,0 +1,1324 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *qcache; -+#else -+static struct kmem_cache *qcache; -+#endif -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff --git a/crypto/ocf/kirkwood/Makefile b/crypto/ocf/kirkwood/Makefile -new file mode 100644 -index 0000000..6dafd00 ---- /dev/null -+++ b/crypto/ocf/kirkwood/Makefile -@@ -0,0 +1,19 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o -+ -+mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o -+ -+# Extra objects required by the CESA driver -+mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o -+ -+ifdef src -+EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) -+endif -+ -+EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/kirkwood/cesa/AES/mvAes.h b/crypto/ocf/kirkwood/cesa/AES/mvAes.h -new file mode 100644 -index 0000000..969727f ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/AES/mvAes.h -@@ -0,0 +1,62 @@ -+/* mvAes.h v2.0 August '99 -+ * Reference ANSI C code -+ */ -+ -+/* AES Cipher header file for ANSI C Submissions -+ Lawrence E. Bassham III -+ Computer Security Division -+ National Institute of Standards and Technology -+ -+ April 15, 1998 -+ -+ This sample is to assist implementers developing to the Cryptographic -+API Profile for AES Candidate Algorithm Submissions. Please consult this -+document as a cross-reference. -+ -+ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE -+MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH -+THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT -+BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE -+IMPLEMENTATION SPECIFIC INFORMATION. -+*/ -+ -+/* Includes: -+ Standard include files -+*/ -+ -+#include "mvOs.h" -+ -+ -+/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ -+ -+/* Key direction is invalid, e.g., unknown value */ -+#define AES_BAD_KEY_DIR -1 -+ -+/* Key material not of correct length */ -+#define AES_BAD_KEY_MAT -2 -+ -+/* Key passed is not valid */ -+#define AES_BAD_KEY_INSTANCE -3 -+ -+/* Params struct passed to cipherInit invalid */ -+#define AES_BAD_CIPHER_MODE -4 -+ -+/* Cipher in wrong state (e.g., not initialized) */ -+#define AES_BAD_CIPHER_STATE -5 -+ -+#define AES_BAD_CIPHER_INSTANCE -7 -+ -+ -+/* Function protoypes */ -+/* CHANGED: makeKey(): parameter blockLen added -+ this parameter is absolutely necessary if you want to -+ setup the round keys in a variable block length setting -+ cipherInit(): parameter blockLen added (for obvious reasons) -+ */ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); -+int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+ -+ -diff --git a/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c b/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c -new file mode 100644 -index 0000000..2f57e4f ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c -@@ -0,0 +1,317 @@ -+/* rijndael-alg-ref.c v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+ -+#include "mvOs.h" -+ -+#include "mvAesAlg.h" -+ -+#include "mvAesBoxes.dat" -+ -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb); -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]); -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]); -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); -+void InvMixColumn(MV_U8 a[4][MAXBC]); -+ -+ -+#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb) -+{ -+ return mask[bb] & Alogtable[aa + Logtable[bb]]; -+} -+ -+ -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) -+{ -+ /* Exor corresponding text input and round key input bytes -+ */ -+ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; -+ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; -+ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; -+ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; -+ -+} -+ -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][1]; -+ tmp[1] = a[1][2]; -+ tmp[2] = a[1][3]; -+ tmp[3] = a[1][0]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ tmp[0] = a[3][3]; -+ tmp[1] = a[3][0]; -+ tmp[2] = a[3][1]; -+ tmp[3] = a[3][2]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][3]; -+ tmp[1] = a[1][0]; -+ tmp[2] = a[1][1]; -+ tmp[3] = a[1][2]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[3][1]; -+ tmp[1] = a[3][2]; -+ tmp[2] = a[3][3]; -+ tmp[3] = a[3][0]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { -+ /* Replace every byte of the input by the byte at that place -+ * in the nonlinear S-box -+ */ -+ int i, j; -+ -+ for(i = 0; i < 4; i++) -+ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; -+} -+ -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; -+ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; -+ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; -+ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; -+} -+ -+void InvMixColumn(MV_U8 a[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ * This is the opposite operation of Mixcolumn -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); -+ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); -+ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); -+ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; -+} -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) -+{ -+ /* Calculate the necessary round keys -+ * The number of calculations depends on keyBits and blockBits -+ */ -+ int KC, BC, ROUNDS; -+ int i, j, t, rconpointer = 0; -+ MV_U8 tk[4][MAXKC]; -+ -+ switch (keyBits) { -+ case 128: KC = 4; break; -+ case 192: KC = 6; break; -+ case 256: KC = 8; break; -+ default : return (-1); -+ } -+ -+ switch (blockBits) { -+ case 128: BC = 4; break; -+ case 192: BC = 6; break; -+ case 256: BC = 8; break; -+ default : return (-2); -+ } -+ -+ switch (keyBits >= blockBits ? keyBits : blockBits) { -+ case 128: ROUNDS = 10; break; -+ case 192: ROUNDS = 12; break; -+ case 256: ROUNDS = 14; break; -+ default : return (-3); /* this cannot happen */ -+ } -+ -+ -+ for(j = 0; j < KC; j++) -+ for(i = 0; i < 4; i++) -+ tk[i][j] = k[i][j]; -+ t = 0; -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ -+ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ -+ /* calculate new values */ -+ for(i = 0; i < 4; i++) -+ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; -+ tk[0][0] ^= rcon[rconpointer++]; -+ -+ if (KC != 8) -+ for(j = 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ else { -+ for(j = 1; j < KC/2; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; -+ for(j = KC/2 + 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ } -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ } -+ -+ return 0; -+} -+ -+ -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ /* Encryption of one block. -+ */ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* begin with a key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = 1; r < ROUNDS; r++) { -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ MixColumn(a, rk[r]); -+ /*KeyAddition(a,rk[r],BC);*/ -+ } -+ -+ /* Last round is special: there is no MixColumn -+ */ -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ KeyAddition(a,rk[ROUNDS],BC); -+ -+ return 0; -+} -+ -+ -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* To decrypt: apply the inverse operations of the encrypt routine, -+ * in opposite order -+ * -+ * (KeyAddition is an involution: it 's equal to its inverse) -+ * (the inverse of Substitution with table S is Substitution with the inverse table of S) -+ * (the inverse of Shiftrow is Shiftrow over a suitable distance) -+ */ -+ -+ /* First the special round: -+ * without InvMixColumn -+ * with extra KeyAddition -+ */ -+ KeyAddition(a,rk[ROUNDS],BC); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = ROUNDS-1; r > 0; r--) { -+ KeyAddition(a,rk[r],BC); -+ InvMixColumn(a); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ } -+ -+ /* End with the extra key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ return 0; -+} -+ -diff --git a/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h b/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h -new file mode 100644 -index 0000000..ec81e40 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h -@@ -0,0 +1,19 @@ -+/* rijndael-alg-ref.h v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ */ -+#ifndef __RIJNDAEL_ALG_H -+#define __RIJNDAEL_ALG_H -+ -+#define MAXBC (128/32) -+#define MAXKC (256/32) -+#define MAXROUNDS 14 -+ -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+ -+#endif /* __RIJNDAEL_ALG_H */ -diff --git a/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c b/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c -new file mode 100644 -index 0000000..70ae60d ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c -@@ -0,0 +1,312 @@ -+/* rijndael-api-ref.c v2.1 April 2000 -+ * Reference ANSI C code -+ * authors: v2.0 Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * v2.1 Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+#include "mvOs.h" -+ -+#include "mvAes.h" -+#include "mvAesAlg.h" -+ -+ -+/* Defines: -+ Add any additional defines you need -+*/ -+ -+#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ -+#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ -+#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ -+ -+ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) -+{ -+ MV_U8 W[MAXROUNDS+1][4][MAXBC]; -+ MV_U8 k[4][MAXKC]; -+ MV_U8 j; -+ int i, rounds, KC; -+ -+ if (expandedKey == NULL) -+ { -+ return AES_BAD_KEY_INSTANCE; -+ } -+ -+ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ if (keyMaterial == NULL) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ /* initialize key schedule: */ -+ for(i=0; i= 3) -+MV_U32 cesaChainLength = 0; -+int chainReqNum = 0; -+MV_U32 chainIndex = 0; -+MV_CESA_REQ* pNextActiveChain = 0; -+MV_CESA_REQ* pEndCurrChain = 0; -+MV_BOOL isFirstReq = MV_TRUE; -+#endif -+ -+static INLINE MV_U8* mvCesaSramAddrGet(void) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_U8*)cesaSramVirtPtr; -+#else -+ return (MV_U8*)cesaCryptEngBase; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); -+#else -+ return (MV_ULONG)pSramVirt; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+/* Internal Function prototypes */ -+ -+static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, int macTotalLen, -+ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); -+ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); -+ -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush); -+ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]); -+ -+static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, -+ int macDataSize); -+ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void); -+ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); -+ -+static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); -+ -+static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); -+static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); -+ -+static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); -+ -+ -+/* Go to the next request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqLast) -+ return pCesaReqFirst; -+ -+ return pReq+1; -+} -+ -+#if (MV_CESA_VERSION >= 3) -+/* Go to the previous request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqFirst) -+ return pCesaReqLast; -+ -+ return pReq-1; -+} -+ -+#endif -+ -+ -+static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) -+{ -+ int frag; -+ -+#if (MV_CESA_VERSION >= 3) -+ pReq->state = MV_CESA_CHAIN; -+#else -+ pReq->state = MV_CESA_PROCESS; -+#endif -+ cesaStats.startCount++; -+ -+ if(pReq->fragMode == MV_CESA_FRAG_NONE) -+ { -+ frag = 0; -+ } -+ else -+ { -+ frag = pReq->frags.nextFrag; -+ pReq->frags.nextFrag++; -+ } -+#if (MV_CESA_VERSION >= 2) -+ /* Enable TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#else -+ /* Enable IDMA engine */ -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+ mvOsBridgeReorderWA(); -+#endif -+ -+ /* Start Accelerator */ -+ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); -+} -+ -+ -+/******************************************************************************* -+* mvCesaHalInit - Initialize the CESA driver -+* -+* DESCRIPTION: -+* This function initialize the CESA driver. -+* 1) Session database -+* 2) Request queue -+* 4) DMA descriptor lists - one list per request. Each list -+* has MV_CESA_MAX_DMA_DESC descriptors. -+* -+* INPUT: -+* numOfSession - maximum number of supported sessions -+* queueDepth - number of elements in the request queue. -+* pSramBase - virtual address of Sram -+* osHandle - A handle used by the OS to allocate memory for the -+* module (Passed to the OS Services layer) -+* -+* RETURN: -+* MV_OK - Success -+* MV_NO_RESOURCE - Fail, can't allocate resources: -+* Session database, request queue, -+* DMA descriptors list, LRU cache database. -+* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, -+ void *osHandle) -+{ -+ int i, req; -+ MV_U32 descOffsetReg, configReg; -+ MV_CESA_SRAM_SA *pSramSA; -+ -+ -+ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", -+ numOfSession, queueDepth, pSramBase); -+ -+ cesaOsHandle = osHandle; -+ /* Create Session database */ -+ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); -+ if(pCesaSAD == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", -+ sizeof(MV_CESA_SA)*numOfSession, numOfSession); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); -+ cesaMaxSA = numOfSession; -+ -+ /* Allocate imag of sramSA in the DRAM */ -+ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, -+ &cesaSramSaBuf.bufPhysAddr, -+ &cesaSramSaBuf.memHandle); -+ -+ if(cesaSramSaBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", -+ cesaSramSaBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); -+ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ for(i=0; i= 3) -+ cesaChainLength = MAX_CESA_CHAIN_LENGTH; -+#endif -+ /* pSramBase must be 8 byte aligned */ -+ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) -+ { -+ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", -+ pSramBase); -+ mvCesaFinish(); -+ return MV_NOT_ALIGNED; -+ } -+ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; -+ -+ cesaCryptEngBase = cryptEngBase; -+ -+ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ -+ -+ /* Clear registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ /* Initialize DMA descriptor lists for all requests in Request queue */ -+ descOffsetReg = configReg = 0; -+ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->cesaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, -+ &pReq->cesaDescBuf.bufPhysAddr, -+ &pReq->cesaDescBuf.memHandle); -+ -+ if(pReq->cesaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", -+ req, pReq->cesaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); -+ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->dmaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, -+ &pReq->dmaDescBuf.bufPhysAddr, -+ &pReq->dmaDescBuf.memHandle); -+ -+ if(pReq->dmaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", -+ req, pReq->dmaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); -+ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ for(frag=0; fragdma[frag]; -+ -+ pDma->pDmaFirst = pDmaDesc; -+ pDma->pDmaLast = NULL; -+ -+ for(i=0; ipDmaFirst[i].phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); -+ } -+ pDma->pDmaFirst[i].phyNextDescPtr = 0; -+ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); -+ -+ pDmaDesc += MV_CESA_MAX_DMA_DESC; -+ } -+ } -+ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ -+ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); -+ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); -+ -+ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); -+#if (MV_CESA_VERSION >= 3) -+ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; -+#endif -+ -+#if (MV_CESA_VERSION >= 2) -+ /* Initialize TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); -+ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+#else -+ /* Initialize IDMA #0 engine */ -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE -+#ifdef MV_CPU_LE -+ | ICCHR_DESC_BYTE_SWAP_EN -+#endif -+ ); -+ /* Clear Cause Byte of IDMA channel to be used */ -+ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); -+#endif /* (MV_CESA_VERSION >= 2) */ -+ -+ /* Set CESA configuration registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); -+ mvCesaDebugStatsClear(); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFinish - Shutdown the CESA driver -+* -+* DESCRIPTION: -+* This function shutdown the CESA driver and free all allocted resources. -+* -+* INPUT: None -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaFinish (void) -+{ -+ int req; -+ MV_CESA_REQ* pReq; -+ -+ mvOsPrintf("mvCesaFinish: \n"); -+ -+ cesaSramVirtPtr = NULL; -+ -+ /* Free all resources: DMA list, etc. */ -+ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, -+ pReq->dmaDescBuf.bufPhysAddr, -+ pReq->dmaDescBuf.bufVirtPtr, -+ pReq->dmaDescBuf.memHandle); -+ } -+ if(pReq->cesaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, -+ pReq->cesaDescBuf.bufPhysAddr, -+ pReq->cesaDescBuf.bufVirtPtr, -+ pReq->cesaDescBuf.memHandle); -+ } -+ } -+#if (MV_CESA_VERSION < 2) -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+#endif /* (MV_CESA_VERSION < 2) */ -+ -+ /* Free request queue */ -+ if(pCesaReqFirst != NULL) -+ { -+ mvOsFree(pCesaReqFirst); -+ pCesaReqFirst = pCesaReqLast = NULL; -+ pCesaReqEmpty = pCesaReqProcess = NULL; -+ cesaQueueDepth = cesaReqResources = 0; -+ } -+ /* Free SA database */ -+ if(pCesaSAD != NULL) -+ { -+ mvOsFree(pCesaSAD); -+ pCesaSAD = NULL; -+ cesaMaxSA = 0; -+ } -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode -+* -+* DESCRIPTION: -+* This function set IV value using by Crypto algorithms in CBC mode. -+* Each channel has its own IV value. -+* This function gets IV value from the caller. If no IV value passed from -+* the caller or only part of IV passed, the function will init the rest part -+* of IV value (or the whole IV) by random value. -+* -+* INPUT: -+* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL -+* the function will generate random IV value. -+* int ivSize - size (in bytes) of IV provided by user. If ivSize is -+* smaller than maximum IV size, the function will complete -+* IV by random value. -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) -+{ -+ MV_U8* pSramIV; -+#if defined(MV646xx) -+ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); -+#endif -+ pSramIV = cesaSramVirtPtr->cryptoIV; -+ if(ivSize > MV_CESA_MAX_IV_LENGTH) -+ { -+ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH; -+ } -+ if(pIV != NULL) -+ { -+ memcpy(pSramIV, pIV, ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; -+ pSramIV += ivSize; -+ } -+ -+ while(ivSize > 0) -+ { -+ int size, mv_random = mvOsRand(); -+ -+ size = MV_MIN(ivSize, sizeof(mv_random)); -+ memcpy(pSramIV, (void*)&mv_random, size); -+ -+ pSramIV += size; -+ ivSize -= size; -+ } -+/* -+ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+*/ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionOpen - Open new uni-directional crypto session -+* -+* DESCRIPTION: -+* This function open new session. -+* -+* INPUT: -+* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters -+* -+* OUTPUT: -+* short *pSid - session ID, should be used for all future -+* requests over this session. -+* -+* RETURN: -+* MV_OK - Session opend successfully. -+* MV_FULL - All sessions are in use, no free place in -+* SA database. -+* MV_BAD_PARAM - One of session input parameters is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) -+{ -+ short sid; -+ MV_U32 config = 0; -+ int digestSize; -+ -+ cesaStats.openedCount++; -+ -+ /* Find free entry in SAD */ -+ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", -+ pSession->operation); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); -+ -+ if( (pSession->direction != MV_CESA_DIR_ENCODE) && -+ (pSession->direction != MV_CESA_DIR_DECODE) ) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", -+ pSession->direction); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); -+ /* Clear SA entry */ -+ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ -+ -+ /* Check AUTH parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ -+ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || -+ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) -+ { -+ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) -+ { -+ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", -+ pSession->macKeyLength); -+ return MV_BAD_PARAM; -+ } -+ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, -+ pCesaSAD[sid].pSramSA->macInnerIV, -+ pCesaSAD[sid].pSramSA->macOuterIV); -+ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; -+ } -+ switch(pSession->macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", -+ pSession->macMode); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); -+ -+ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ -+ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ -+ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", -+ pSession->digestSize); -+ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].digestSize = pSession->digestSize; -+ -+ if(pCesaSAD[sid].digestSize == 12) -+ { -+ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ -+ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); -+ } -+ } -+ -+ /* Check CRYPTO parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_MAC_ONLY) -+ { -+ switch(pSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_3DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ /* Only EDE mode is supported */ -+ config |= (MV_CESA_CRYPTO_3DES_EDE << -+ MV_CESA_CRYPTO_3DES_MODE_BIT); -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ switch(pSession->cryptoKeyLength) -+ { -+ case 16: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_128 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 24: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_192 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 32: -+ default: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_256 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ } -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", -+ pSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); -+ -+ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) -+ { -+ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", -+ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Copy Crypto key */ -+ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && -+ (pSession->direction == MV_CESA_DIR_DECODE)) -+ { -+ /* Crypto Key for AES decode is computed from original key material */ -+ /* and depend on cryptoKeyLength (128/192/256 bits) */ -+ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); -+ } -+ else -+ { -+ /*panic("mvCesaSessionOpen2");*/ -+ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pCesaSAD[sid].cryptoKeyLength); -+ -+ } -+ -+ switch(pSession->cryptoMode) -+ { -+ case MV_CESA_CRYPTO_ECB: -+ pCesaSAD[sid].cryptoIvSize = 0; -+ break; -+ -+ case MV_CESA_CRYPTO_CBC: -+ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; -+ break; -+ -+ case MV_CESA_CRYPTO_CTR: -+ /* Supported only for AES algorithm */ -+ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) -+ { -+ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].cryptoIvSize = 0; -+ pCesaSAD[sid].ctrMode = 1; -+ /* Replace to ECB mode for HW */ -+ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", -+ pSession->cryptoMode); -+ return MV_BAD_PARAM; -+ } -+ -+ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); -+ } -+ pCesaSAD[sid].config = config; -+ -+ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ if(pSid != NULL) -+ *pSid = sid; -+ -+ pCesaSAD[sid].valid = 1; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionClose - Close active crypto session -+* -+* DESCRIPTION: -+* This function closes existing session -+* -+* INPUT: -+* short sid - Unique identifier of the session to be closed -+* -+* RETURN: -+* MV_OK - Session closed successfully. -+* MV_BAD_PARAM - Session identifier is out of valid range. -+* MV_NOT_FOUND - There is no active session with such ID. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionClose(short sid) -+{ -+ cesaStats.closedCount++; -+ -+ if(sid >= cesaMaxSA) -+ { -+ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); -+ return MV_BAD_PARAM; -+ } -+ if(pCesaSAD[sid].valid == 0) -+ { -+ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); -+ return MV_NOT_FOUND; -+ } -+ if(cesaLastSid == sid) -+ cesaLastSid = -1; -+ -+ pCesaSAD[sid].valid = 0; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaAction - Perform crypto operation -+* -+* DESCRIPTION: -+* This function set new CESA request FIFO queue for further HW processing. -+* The function checks request parameters before set new request to the queue. -+* If one of the CESA channels is ready for processing the request will be -+* passed to HW. When request processing is finished the CESA interrupt will -+* be generated by HW. The caller should call mvCesaReadyGet() function to -+* complete request processing and get result. -+* -+* INPUT: -+* MV_CESA_COMMAND *pCmd - pointer to new CESA request. -+* It includes pointers to Source and Destination -+* buffers, session identifier get from -+* mvCesaSessionOpen() function, pointer to caller -+* private data and all needed crypto parameters. -+* -+* RETURN: -+* MV_OK - request successfully added to request queue -+* and will be processed. -+* MV_NO_MORE - request successfully added to request queue and will -+* be processed, but request queue became Full and next -+* request will not be accepted. -+* MV_NO_RESOURCE - request queue is FULL and the request can not -+* be processed. -+* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is -+* failed. Request can not be processed. -+* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed -+* as one request and should be splitted for two requests: -+* CRYPTO_ONLY and MAC_ONLY. -+* MV_BAD_PARAM - One of the request parameters is out of valid range. -+* The request can not be processed. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) -+{ -+ MV_STATUS status; -+ MV_CESA_REQ* pReq = pCesaReqEmpty; -+ int sid = pCmd->sessionId; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_REQ* pFromReq; -+ MV_CESA_REQ* pToReq; -+#endif -+ cesaStats.reqCount++; -+ -+ /* Check that the request queue is not FULL */ -+ if(cesaReqResources == 0) -+ return MV_NO_RESOURCE; -+ -+ if( (sid >= cesaMaxSA) || (!pSA->valid) ) -+ { -+ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); -+ return MV_BAD_PARAM; -+ } -+ pSA->count++; -+ -+ if(pSA->ctrMode) -+ { -+ /* AES in CTR mode can't be mixed with Authentication */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); -+ return MV_NOT_ALLOWED; -+ } -+ /* All other request parameters should not be checked because key stream */ -+ /* (not user data) processed by AES HW engine */ -+ pReq->pOrgCmd = pCmd; -+ /* Allocate temporary pCmd structure for Key stream */ -+ pCmd = mvCesaCtrModeInit(); -+ if(pCmd == NULL) -+ return MV_OUT_OF_CPU_MEM; -+ -+ /* Prepare Key stream */ -+ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); -+ pReq->fixOffset = 0; -+ } -+ else -+ { -+ /* Check request parameters and calculae fixOffset */ -+ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); -+ if(status != MV_OK) -+ { -+ return status; -+ } -+ } -+ pReq->pCmd = pCmd; -+ -+ /* Check if the packet need fragmentation */ -+ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) -+ { -+ /* request size is smaller than single buffer size */ -+ pReq->fragMode = MV_CESA_FRAG_NONE; -+ -+ /* Prepare NOT fragmented packets */ -+ status = mvCesaReqProcess(pReq); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", -+ pReq, status); -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.numFrag = 1; -+#endif -+ } -+ else -+ { -+ MV_U8 frag = 0; -+ -+ /* request size is larger than buffer size - needs fragmentation */ -+ -+ /* Check restrictions for processing fragmented packets */ -+ status = mvCesaFragParamCheck(pSA, pCmd); -+ if(status != MV_OK) -+ return status; -+ -+ pReq->fragMode = MV_CESA_FRAG_FIRST; -+ pReq->frags.nextFrag = 0; -+ -+ /* Prepare Process Fragmented packets */ -+ while(pReq->fragMode != MV_CESA_FRAG_LAST) -+ { -+ if(frag >= MV_CESA_MAX_REQ_FRAGS) -+ { -+ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ status = mvCesaFragReqProcess(pReq, frag); -+ if(status == MV_OK) { -+#if (MV_CESA_VERSION >= 3) -+ if(frag) { -+ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ } -+#endif -+ frag++; -+ } -+ } -+ pReq->frags.numFrag = frag; -+#if (MV_CESA_VERSION >= 3) -+ if(chainReqNum) { -+ chainReqNum += pReq->frags.numFrag; -+ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) -+ chainReqNum = MAX_CESA_CHAIN_LENGTH; -+ } -+#endif -+ } -+ -+ pReq->state = MV_CESA_PENDING; -+ -+ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources -= 1; -+ -+/* #ifdef CESA_DEBUG */ -+ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) -+ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); -+/* #endif CESA_DEBUG */ -+ -+ cesaLastSid = sid; -+ -+#if (MV_CESA_VERSION >= 3) -+ /* Are we within chain bounderies and follows the first request ? */ -+ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { -+ if(chainIndex) { -+ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); -+ pToReq = pReq; -+ pReq->state = MV_CESA_CHAIN; -+ /* assume concatenating is possible */ -+ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); -+ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ } -+ else { /* we have only one chain, start new one */ -+ chainReqNum = 0; -+ chainIndex++; -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ } -+ } -+ else { -+ /* In case we concatenate full chain */ -+ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { -+ chainIndex++; -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ chainReqNum = 0; -+ } -+ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) { -+ pNextActiveChain = pReq; -+ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+ } -+ -+ chainReqNum++; -+ -+ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) -+ cesaStats.maxChainUsage = chainReqNum; -+ -+#else -+ -+ /* Check status of CESA channels and process requests if possible */ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) -+ { -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+#endif -+ /* If request queue became FULL - return MV_NO_MORE */ -+ if(cesaReqResources == 0) -+ return MV_NO_MORE; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCesaReadyGet - Get crypto request that processing is finished -+* -+* DESCRIPTION: -+* This function complete request processing and return ready request to -+* caller. To don't miss interrupts the caller must call this function -+* while MV_OK or MV_TERMINATE values returned. -+* -+* INPUT: -+* MV_U32 chanMap - map of CESA channels finished thier job -+* accordingly with CESA Cause register. -+* MV_CESA_RESULT* pResult - pointer to structure contains information -+* about ready request. It includes pointer to -+* user private structure "pReqPrv", session identifier -+* for this request "sessionId" and return code. -+* Return code set to MV_FAIL if calculated digest value -+* on decode direction is different than digest value -+* in the packet. -+* -+* RETURN: -+* MV_OK - Success, ready request is returned. -+* MV_NOT_READY - Next request is not ready yet. New interrupt will -+* be generated for futher request processing. -+* MV_EMPTY - There is no more request for processing. -+* MV_BUSY - Fragmented request is not ready yet. -+* MV_TERMINATE - Call this function once more to complete processing -+* of fragmented request. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) -+{ -+ MV_STATUS status, readyStatus = MV_NOT_READY; -+ MV_U32 statusReg; -+ MV_CESA_REQ* pReq; -+ MV_CESA_SA* pSA; -+ -+#if (MV_CESA_VERSION >= 3) -+ if(isFirstReq == MV_TRUE) { -+ if(chainIndex == 0) -+ chainReqNum = 0; -+ -+ isFirstReq = MV_FALSE; -+ -+ if(pNextActiveChain->state == MV_CESA_PENDING) { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pNextActiveChain); -+ pEndCurrChain = pNextActiveChain; -+ if(chainIndex > 0) -+ chainIndex--; -+ /* Update pNextActiveChain to next chain head */ -+ while(pNextActiveChain->state == MV_CESA_CHAIN) -+ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); -+ } -+ } -+ -+ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ -+ if(pCesaReqProcess == pEndCurrChain) { -+ isFirstReq = MV_TRUE; -+ pEndCurrChain = pNextActiveChain; -+#else -+ if(pCesaReqProcess->state != MV_CESA_PROCESS) { -+#endif -+ return MV_EMPTY; -+ } -+ -+#ifdef CESA_DEBUG -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) -+ { -+ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); -+ cesaStats.notReadyCount++; -+ return MV_NOT_READY; -+ } -+#endif /* CESA_DEBUG */ -+ -+ cesaStats.readyCount++; -+ -+ pReq = pCesaReqProcess; -+ pSA = &pCesaSAD[pReq->pCmd->sessionId]; -+ -+ pResult->retCode = MV_OK; -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ MV_U8* pNewDigest; -+ int frag; -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag = 1; -+ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { -+#endif -+ frag = (pReq->frags.nextFrag - 1); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[frag].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); -+ pReq->dma[frag].pDmaLast = NULL; -+ -+ /* Special processing for finished fragmented request */ -+ if(pReq->frags.nextFrag >= pReq->frags.numFrag) -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Fragmented packet is ready */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; -+ -+ if(macDataSize != 0) -+ { -+ /* Calculate all other blocks by SW */ -+ mvCesaFragAuthComplete(pReq, pSA, macDataSize); -+ } -+ -+ /* Copy new digest from SRAM to the Destination buffer */ -+ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; -+ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, -+ pReq->pCmd->digestOffset, pSA->digestSize); -+ -+ /* For decryption: Compare new digest value with original one */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", -+ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ } -+ readyStatus = MV_OK; -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag++; -+ } -+#endif -+ } -+ else -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[0].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); -+ pReq->dma[0].pDmaLast = NULL; -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ /* For AUTH on decode : Check Digest result in Status register */ -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", -+ chan, statusReg); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ readyStatus = MV_OK; -+ } -+ -+ if(readyStatus == MV_OK) -+ { -+ /* If Request is ready - Prepare pResult structure */ -+ pResult->pReqPrv = pReq->pCmd->pReqPrv; -+ pResult->sessionId = pReq->pCmd->sessionId; -+ -+ pReq->state = MV_CESA_IDLE; -+ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources++; -+ -+ if(pSA->ctrMode) -+ { -+ /* For AES CTR mode - complete processing and free allocated resources */ -+ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); -+ mvCesaCtrModeFinish(pReq->pCmd); -+ pReq->pOrgCmd = NULL; -+ } -+ } -+ -+#if (MV_CESA_VERSION < 3) -+ if(pCesaReqProcess->state == MV_CESA_PROCESS) -+ { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ if(readyStatus == MV_NOT_READY) -+ readyStatus = MV_BUSY; -+ } -+ else if(pCesaReqProcess != pCesaReqEmpty) -+ { -+ /* Start process new request from the queue */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ } -+#endif -+ return readyStatus; -+} -+ -+/***************** Functions to work with CESA_MBUF structure ******************/ -+ -+/******************************************************************************* -+* mvCesaMbufOffset - Locate offset in the Mbuf structure -+* -+* DESCRIPTION: -+* This function locates offset inside Multi-Bufeer structure. -+* It get fragment number and place in the fragment where the offset -+* is located. -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure -+* int offset - Offset from the beginning of the data presented by -+* the Mbuf structure. -+* -+* OUTPUT: -+* int* pBufOffset - Offset from the beginning of the fragment where -+* the offset is located. -+* -+* RETURN: -+* int - Number of fragment, where the offset is located\ -+* -+*******************************************************************************/ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) -+{ -+ int frag = 0; -+ -+ while(offset > 0) -+ { -+ if(frag >= pMbuf->numFrags) -+ { -+ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", -+ frag, pMbuf->numFrags); -+ return MV_INVALID; -+ } -+ if(offset < pMbuf->pFrags[frag].bufSize) -+ { -+ break; -+ } -+ offset -= pMbuf->pFrags[frag].bufSize; -+ frag++; -+ } -+ if(pBufOffset != NULL) -+ *pBufOffset = offset; -+ -+ return frag; -+} -+ -+/******************************************************************************* -+* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pDstBuf - Pointer to continuous buffer, where data is -+* copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_EMPTY - Multi-buffer structure has not enough data to copy -+* Data from the offset to end of Mbuf data is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pDstBuf, pBuf, size); -+ return MV_OK; -+ } -+ memcpy(pDstBuf, pBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pDstBuf += bufSize; -+ if(frag >= pSrcMbuf->numFrags) -+ break; -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", -+ size); -+ return MV_EMPTY; -+} -+ -+/******************************************************************************* -+* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is -+* copied from. -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_FULL - Multi-buffer structure has not enough place to copy -+* all data. Data from the offset to end of Mbuf data -+* is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pBuf, pSrcBuf, size); -+ return MV_OK; -+ } -+ memcpy(pBuf, pSrcBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pSrcBuf += bufSize; -+ if(frag >= pDstMbuf->numFrags) -+ break; -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", -+ size); -+ return MV_FULL; -+} -+ -+/******************************************************************************* -+* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int dstMbufOffset - Offset in the dstMbuf structure where first byte -+* of data should be copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int srcMbufOffset - Offset in the srcMbuf structure where first byte -+* of data should be copied from. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of -+* srcMbuf or dstMbuf structure correspondently. -+* No data is copied. -+* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy -+* all data. Partial data is copied -+* -+*******************************************************************************/ -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) -+{ -+ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; -+ int copySize; -+ MV_U8 *pSrc, *pDst; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); -+ if(srcFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; -+ -+ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); -+ if(dstFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; -+ -+ while(size > 0) -+ { -+ copySize = MV_MIN(srcSize, dstSize); -+ if(size <= copySize) -+ { -+ memcpy(pDst, pSrc, size); -+ return MV_OK; -+ } -+ memcpy(pDst, pSrc, copySize); -+ size -= copySize; -+ srcSize -= copySize; -+ dstSize -= copySize; -+ -+ if(srcSize == 0) -+ { -+ srcFrag++; -+ if(srcFrag >= pMbufSrc->numFrags) -+ break; -+ -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstSize == 0) -+ { -+ dstFrag++; -+ if(dstFrag >= pMbufDst->numFrags) -+ break; -+ -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", -+ size); -+ -+ return MV_BAD_SIZE; -+} -+ -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); -+ return MV_OK; -+ } -+ -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); -+ size -= bufSize; -+ frag++; -+ if(frag >= pMbuf->numFrags) -+ break; -+ -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", -+ __FUNCTION__, size); -+ return MV_FULL; -+} -+ -+ -+/*************************************** Local Functions ******************************/ -+ -+/******************************************************************************* -+* mvCesaFragReqProcess - Process fragmented request -+* -+* DESCRIPTION: -+* This function processes a fragment of fragmented request (First, Middle or Last) -+* -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The fragment is successfully passed to HW for processing. -+* MV_TERMINATE - Means, that HW finished its work on this packet and no more -+* interrupts will be generated for this request. -+* Function mvCesaReadyGet() must be called to complete request -+* processing and get request result. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) -+{ -+ int i, copySize, cryptoDataSize, macDataSize, sid; -+ int cryptoIvOffset, digestOffset; -+ MV_U32 config; -+ MV_CESA_COMMAND* pCmd = pReq->pCmd; -+ MV_CESA_SA* pSA; -+ MV_CESA_MBUF* pMbuf; -+ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; -+ MV_U8* pSramBuf = cesaSramVirtPtr->buf; -+ int macTotalLen = 0; -+ int fixOffset, cryptoOffset, macOffset; -+ -+ cesaStats.fragCount++; -+ -+ sid = pReq->pCmd->sessionId; -+ -+ pSA = &pCesaSAD[sid]; -+ -+ cryptoIvOffset = digestOffset = 0; -+ i = macDataSize = 0; -+ cryptoDataSize = 0; -+ -+ /* First fragment processing */ -+ if(pReq->fragMode == MV_CESA_FRAG_FIRST) -+ { -+ /* pReq->frags monitors processing of fragmented request between fragments */ -+ pReq->frags.bufOffset = 0; -+ pReq->frags.cryptoSize = 0; -+ pReq->frags.macSize = 0; -+ -+ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); -+ -+ /* fixOffset can be not equal to zero only for FIRST fragment */ -+ fixOffset = pReq->fixOffset; -+ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ -+ cryptoOffset = pCmd->cryptoOffset; -+ macOffset = pCmd->macOffset; -+ -+ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; -+ -+ /* Find fragment size: Must meet all requirements for CRYPTO and MAC -+ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment -+ * macDataSize - size of data will be signed/verified in this fragment -+ * copySize - size of data will be copied from srcMbuf to SRAM and -+ * back to dstMbuf for this fragment -+ */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) -+ { -+ /* CryptoIV special processing */ -+ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == -+ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) -+ { -+ /* In CBC mode for encode direction when IV from user */ -+ if( (pCmd->ivFromUser) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Special processing when IV is not located in the first fragment */ -+ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) -+ { -+ /* Prepare dummy place for cryptoIV in SRAM */ -+ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); -+ -+ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ else -+ { -+ /* For Encryption when IV is NOT from User: */ -+ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ -+ if(pCmd->ivFromUser == 0) -+ { -+ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ } -+ } -+ else -+ { -+ cryptoIvOffset = pCmd->ivOffset; -+ } -+ } -+ } -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* MAC digest special processing on Decode direction */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ /* Save digest from pCmd->digestOffset */ -+ mvCesaCopyFromMbuf(pReq->frags.orgDigest, -+ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* If pCmd->digestOffset is not located on the first */ -+ if(pCmd->digestOffset > (copySize - pSA->digestSize)) -+ { -+ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ /* Set zeros to pCmd->digestOffset (DRAM) */ -+ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); -+ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset; -+ } -+ } -+ } -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ pReq->fragMode = MV_CESA_FRAG_MIDDLE; -+ } -+ else -+ { -+ /* Continue fragment */ -+ fixOffset = 0; -+ cryptoOffset = 0; -+ macOffset = 0; -+ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) -+ { -+ /* Last fragment */ -+ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = pCmd->macLength - pReq->frags.macSize; -+ -+ /* If pCmd->digestOffset is not located on last fragment */ -+ if(pCmd->digestOffset < pReq->frags.bufOffset) -+ { -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; -+ } -+ pReq->frags.newDigestOffset = digestOffset; -+ macTotalLen = pCmd->macLength; -+ -+ /* HW can't calculate the Digest correctly for fragmented packets -+ * in the following cases: -+ * - MV88F5182 || -+ * - MV88F5181L when total macLength more that 16 Kbytes || -+ * - total macLength more that 64 Kbytes -+ */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_TERMINATE; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; -+ } -+ -+ /* cryptoIvOffset - don't care */ -+ } -+ else -+ { -+ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && -+ (((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || -+ ((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) -+ { -+ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ -+ return MV_TERMINATE; -+ } -+ /* Middle fragment */ -+ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); -+ copySize = sizeof(cesaSramVirtPtr->buf); -+ /* digestOffset and cryptoIvOffset - don't care */ -+ -+ /* Find fragment size */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ } -+ } -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ -+ mvCesaSramDescrBuild(config, frag, -+ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, -+ cryptoDataSize, macOffset + fixOffset, -+ digestOffset + fixOffset, macDataSize, macTotalLen, -+ pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, -+ i*sizeof(MV_DMA_DESC)); -+ -+ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ -+ -+ pReq->frags.bufOffset += copySize; -+ pReq->frags.cryptoSize += cryptoDataSize; -+ pReq->frags.macSize += macDataSize; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaReqProcess - Process regular (Non-fragmented) request -+* -+* DESCRIPTION: -+* This function processes the whole (not fragmented) request -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The request is successfully passed to HW for processing. -+* Other - Failure. The request will not be processed -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_DMA_DESC *pDmaDesc; -+ MV_U8 *pSramBuf; -+ int sid, i, fixOffset; -+ MV_CESA_SA *pSA; -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ -+ cesaStats.procCount++; -+ -+ sid = pCmd->sessionId; -+ pSA = &pCesaSAD[sid]; -+ pDmaDesc = pReq->dma[0].pDmaFirst; -+ pSramBuf = cesaSramVirtPtr->buf; -+ fixOffset = pReq->fixOffset; -+ -+/* -+ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", -+ sid, pSA, pDmaDesc, pSramBuf); -+*/ -+ i = 0; -+ -+ /* Crypto IV Special processing in CBC mode for Encryption direction */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && -+ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && -+ (pCmd->ivFromUser) ) -+ { -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ -+ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, -+ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, -+ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, -+ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaSramDescrBuild - Set CESA descriptor in SRAM -+* -+* DESCRIPTION: -+* This function builds CESA descriptor in SRAM from all Command parameters -+* -+* -+* INPUT: -+* int chan - CESA channel uses the descriptor -+* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure -+* int cryptoOffset - Offset from the beginning of SRAM buffer where -+* data for encryption/decription is started. -+* int ivOffset - Offset of crypto IV from the SRAM base. Valid only -+* for first fragment. -+* int cryptoLength - Size (in bytes) of data for encryption/descryption -+* operation on this fragment. -+* int macOffset - Offset from the beginning of SRAM buffer where -+* data for Authentication is started -+* int digestOffset - Offset from the beginning of SRAM buffer where -+* digest is located. Valid for first and last fragments. -+* int macLength - Size (in bytes) of data for Authentication -+* operation on this fragment. -+* int macTotalLen - Toatl size (in bytes) of data for Authentication -+* operation on the whole request (packet). Valid for -+* last fragment only. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, -+ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) -+{ -+ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; -+ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; -+ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); -+ -+ pCesaDesc->config = MV_32BIT_LE(config); -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 1 */ -+ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ /* word 2 */ -+ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); -+ /* word 3 */ -+ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - -+ mvCesaSramAddrGet())); -+ /* word 4 */ -+ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); -+ } -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 5 */ -+ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); -+ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); -+ -+ /* word 6 */ -+ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); -+ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); -+ -+ /* word 7 */ -+ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - -+ mvCesaSramAddrGet())); -+ } -+ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); -+ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); -+ -+ /* flush Source buffer */ -+ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); -+} -+ -+/******************************************************************************* -+* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. -+* -+* DESCRIPTION: -+* Copy to SRAM values of the required SA. -+* -+* -+* INPUT: -+* short sid - Session ID needs SRAM Cache update -+* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to -+* copy SA values from DRAM to SRAM. -+* -+* RETURN: -+* MV_OK - Cache entry for this SA copied to SRAM. -+* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM -+* -+*******************************************************************************/ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) -+{ -+ MV_CESA_SA *pSA = &pCesaSAD[sid]; -+ -+ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); -+ pDmaDesc->phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); -+ -+ /* Source buffer is already flushed during OpenSession*/ -+ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ -+} -+ -+/******************************************************************************* -+* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by -+* Mbuf structure from DRAM to SRAM -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request -+* data in DRAM -+* MV_U8* pSramBuf - pointer to buffer in SRAM where data should -+* be copied to. -+* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. -+* The function set number of DMA descriptors needed -+* to copy the copySize bytes from Mbuf. -+* MV_BOOL isToMbuf - Copy direction. -+* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. -+* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. -+* int offset - Offset in the Mbuf structure that copy should be -+* started from. -+* int copySize - Size of data should be copied. -+* -+* RETURN: -+* int - number of DMA descriptors used for the copy. -+* -+*******************************************************************************/ -+#ifndef MV_NETBSD -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, size, frag, i; -+ MV_U8* pBuf; -+ -+ i = 0; -+ -+ /* Calculate start place for copy: fragment number and offset in the fragment */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ -+ /* Size accumulate total copy size */ -+ size = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while(size < copySize) -+ { -+ /* Find copy size for each DMA descriptor */ -+ bufSize = MV_MIN(bufSize, (copySize - size)); -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); -+ if(isToMbuf) -+ { -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phySrcAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, bufSize); -+ } -+ else -+ { -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, bufSize); -+ } -+ -+ /* Count number of used DMA descriptors */ -+ i++; -+ size += bufSize; -+ -+ /* go to next fragment in the Mbuf */ -+ frag++; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ } -+ return i; -+} -+#else /* MV_NETBSD */ -+static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, thisSize, size, frag, i; -+ MV_ULONG bufPhys, sramPhys; -+ MV_U8* pBuf; -+ -+ /* -+ * Calculate start place for copy: fragment number and offset in -+ * the fragment -+ */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ -+ /* -+ * Get SRAM physical address only once. We can update it in-place -+ * as we build the descriptor chain. -+ */ -+ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); -+ -+ /* -+ * 'size' accumulates total copy size, 'i' counts desccriptors. -+ */ -+ size = i = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while (size < copySize) { -+ /* -+ * Calculate # of bytes to copy from the current fragment, -+ * and the pointer to the start of data -+ */ -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ bufOffset = 0; /* First frag may be non-zero */ -+ frag++; -+ -+ /* -+ * As long as there is data in the current fragment... -+ */ -+ while (bufSize > 0) { -+ /* -+ * Ensure we don't cross an MMU page boundary. -+ * XXX: This is NetBSD-specific, but it is a -+ * quick and dirty way to fix the problem. -+ * A true HAL would rely on the OS-specific -+ * driver to do this... -+ */ -+ thisSize = PAGE_SIZE - -+ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); -+ thisSize = MV_MIN(bufSize, thisSize); -+ /* -+ * Make sure we don't copy more than requested -+ */ -+ if (thisSize > (copySize - size)) { -+ thisSize = copySize - size; -+ bufSize = 0; -+ } -+ -+ /* -+ * Physicall address of this fragment -+ */ -+ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ -+ /* -+ * Set up the descriptor -+ */ -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); -+ if(isToMbuf) { -+ pDmaDesc[i].phyDestAdd = bufPhys; -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, thisSize); -+ } else { -+ pDmaDesc[i].phySrcAdd = bufPhys; -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, thisSize); -+ } -+ -+ pDmaDesc[i].phyNextDescPtr = -+ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); -+ -+ /* flush the DMA desc */ -+ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); -+ -+ /* Update state */ -+ bufSize -= thisSize; -+ sramPhys += thisSize; -+ pBuf += thisSize; -+ size += thisSize; -+ i++; -+ } -+ } -+ -+ return i; -+} -+#endif /* MV_NETBSD */ -+/******************************************************************************* -+* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key -+* -+* DESCRIPTION: -+* This function calculate Inner and Outer values used for HMAC algorithm. -+* This operation allows improve performance fro the whole HMAC processing. -+* -+* INPUT: -+* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. -+* unsigned char key[] - Pointer to HMAC key. -+* int keyLength - Size of HMAC key (maximum 64 bytes) -+* -+* OUTPUT: -+* unsigned char innerIV[] - HASH(key^inner) -+* unsigned char outerIV[] - HASH(key^outter) -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]) -+{ -+ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ int i, digestSize = 0; -+#if defined(MV_CPU_LE) || defined(MV_PPC) -+ MV_U32 swapped32, val32, *pVal32; -+#endif -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvSHA1Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvSHA1Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvSHA1Final(pDigest, &ctx); -+/* -+ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+*/ -+ -+ if(pOuterIV != NULL) -+ { -+ /* If HMAC - Complete Outer part */ -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvMD5Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvMD5Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvMD5Final(pDigest, &ctx); -+ -+/* -+ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+*/ -+ if(pOuterIV != NULL) -+ { -+ /* Complete Outer part */ -+ for(i=0; ipCmd; -+ MV_U8* pDigest; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8* pOuterIV = NULL; -+ -+ /* Copy data from Source fragment to Destination */ -+ if(pCmd->pSrc != pCmd->pDst) -+ { -+ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, -+ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ } -+ -+/* -+ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); -+*/ -+ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); -+ -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+/* -+ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", -+ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); -+*/ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_HMAC_MD5: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_MD5: -+ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_SHA1: -+ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); -+ return MV_BAD_PARAM; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeInit - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: NONE -+* -+* -+* RETURN: -+* MV_CESA_COMMAND* -+* -+*******************************************************************************/ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf; -+ MV_CESA_COMMAND *pCmd; -+ -+ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + -+ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", -+ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); -+ return NULL; -+ } -+ pCmd = (MV_CESA_COMMAND*)pBuf; -+ pBuf += sizeof(MV_CESA_COMMAND); -+ -+ pMbuf = (MV_CESA_MBUF*)pBuf; -+ pBuf += sizeof(MV_CESA_MBUF); -+ -+ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; -+ -+ pMbuf->numFrags = 1; -+ pCmd->pSrc = pMbuf; -+ pCmd->pDst = pMbuf; -+/* -+ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pMbuf->pFrags); -+*/ -+ return pCmd; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModePrepare - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf, *pIV; -+ MV_U32 counter, *pCounter; -+ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); -+/* -+ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); -+*/ -+ pMbuf = pCtrModeCmd->pSrc; -+ -+ /* Allocate buffer for Key stream */ -+ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, -+ &pMbuf->pFrags[0].bufPhysAddr, -+ &pMbuf->pFrags[0].memHandle); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ memset(pBuf, 0, cryptoSize); -+ mvOsCacheFlush(NULL, pBuf, cryptoSize); -+ -+ pMbuf->pFrags[0].bufVirtPtr = pBuf; -+ pMbuf->mbufSize = cryptoSize; -+ pMbuf->pFrags[0].bufSize = cryptoSize; -+ -+ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; -+ pCtrModeCmd->sessionId = pCmd->sessionId; -+ -+ /* ivFromUser and ivOffset are don't care */ -+ pCtrModeCmd->cryptoOffset = 0; -+ pCtrModeCmd->cryptoLength = cryptoSize; -+ -+ /* digestOffset, macOffset and macLength are don't care */ -+ -+ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter = *pCounter; -+ counter = MV_32BIT_BE(counter); -+ pIV = pBuf; -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ -+ /* fill key stream */ -+ while(cryptoSize > 0) -+ { -+ pBuf += MV_CESA_AES_BLOCK_SIZE; -+ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter++; -+ *pCounter = MV_32BIT_BE(counter); -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeComplete - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) -+{ -+ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; -+ int cryptoSize = pCmd->cryptoLength; -+ MV_U8 *pSrc, *pDst, *pKey; -+ MV_STATUS status = MV_OK; -+/* -+ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); -+*/ -+ /* XOR source data with key stream to destination data */ -+ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; -+ keyOffset = 0; -+ -+ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && -+ (pOrgCmd->cryptoOffset > 0) ) -+ { -+ /* Copy Prefix from source buffer to destination buffer */ -+ -+ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, -+ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ 0, pOrgCmd->cryptoOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ 0, pOrgCmd->cryptoOffset); -+*/ -+ } -+ -+ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ -+ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ -+ while(cryptoSize > 0) -+ { -+ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); -+ -+ cryptoSize--; -+ dstOffset++; -+ srcOffset++; -+ keyOffset++; -+ -+ if(srcOffset >= srcSize) -+ { -+ srcFrag++; -+ srcOffset = 0; -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstOffset >= dstSize) -+ { -+ dstFrag++; -+ dstOffset = 0; -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ -+ if(pOrgCmd->pSrc != pOrgCmd->pDst) -+ { -+ /* Copy Suffix from source buffer to destination buffer */ -+ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; -+ -+ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) -+ { -+ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, -+ pOrgCmd->pSrc, srcOffset, -+ pOrgCmd->pDst->mbufSize - srcOffset); -+ } -+ -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); -+*/ -+ } -+ -+ /* Free buffer used for Key stream */ -+ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, -+ pCmd->pDst->pFrags[0].bufPhysAddr, -+ pCmd->pDst->pFrags[0].bufVirtPtr, -+ pCmd->pDst->pFrags[0].memHandle); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeFinish - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND* pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) -+{ -+ mvOsFree(pCmd); -+} -+ -+/******************************************************************************* -+* mvCesaParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+ MV_U8* pFixOffset) -+{ -+ MV_U8 fixOffset = 0xFF; -+ -+ /* Check AUTH operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* MAC offset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* Digest offset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", -+ pCmd->digestOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->macOffset % 8); -+ } -+ else -+ { -+ if( (pCmd->macOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", -+ pCmd->macOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ if( (pCmd->digestOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", -+ pCmd->digestOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ /* Check CRYPTO operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* CryptoOffset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ /* cryptoLength should be the whole number of blocks */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) -+ { -+ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", -+ pCmd->cryptoLength, pSA->cryptoBlockSize); -+ return MV_BAD_PARAM; -+ } -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->cryptoOffset % 8); -+ } -+ else -+ { -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->cryptoOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", -+ pCmd->cryptoOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* check for CBC mode */ -+ if(pSA->cryptoIvSize > 0) -+ { -+ /* cryptoIV must not be part of CryptoLength */ -+ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && -+ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* ivOffset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", -+ pCmd->ivOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->ivOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", -+ pCmd->ivOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) -+{ -+ int offset; -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* macOffset must be less that SRAM buffer size */ -+ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= -+ sizeof(cesaSramVirtPtr->buf)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", -+ pCmd->macLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* cryptoOffset must be less that SRAM buffer size */ -+ /* 4 for possible fixOffset */ -+ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ -+ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= -+ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", -+ pCmd->cryptoLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || -+ ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_NOT_ALLOWED; -+ } -+ -+ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ -+ if(pCmd->cryptoOffset > pCmd->macOffset) -+ { -+ offset = pCmd->cryptoOffset - pCmd->macOffset; -+ } -+ else -+ { -+ offset = pCmd->macOffset - pCmd->cryptoOffset; -+ } -+ -+ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", -+ pSA->cryptoBlockSize); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ /* Digest must not be part of CryptoLength */ -+ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && -+ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragSizeFind - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+* int cryptoOffset, int macOffset, -+* -+* OUTPUT: -+* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) -+{ -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ int cryptoDataSize, macDataSize, copySize; -+ -+ cryptoDataSize = macDataSize = 0; -+ copySize = *pCopySize; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), -+ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); -+ -+ /* cryptoSize for each fragment must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) -+ { -+ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); -+ copySize = cryptoOffset + cryptoDataSize; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = MV_MIN( (copySize - macOffset), -+ (pCmd->macLength - (pReq->frags.macSize + 1))); -+ -+ /* macSize for each fragment (except last) must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) -+ { -+ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); -+ copySize = macOffset + macDataSize; -+ } -+ cryptoDataSize = copySize - cryptoOffset; -+ } -+ *pCopySize = copySize; -+ -+ if(pCryptoDataSize != NULL) -+ *pCryptoDataSize = cryptoDataSize; -+ -+ if(pMacDataSize != NULL) -+ *pMacDataSize = macDataSize; -+} -diff --git a/crypto/ocf/kirkwood/cesa/mvCesa.h b/crypto/ocf/kirkwood/cesa/mvCesa.h -new file mode 100644 -index 0000000..6898699 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvCesa.h -@@ -0,0 +1,412 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Marvell Cryptographic Engines and Security Accelerator. -+* -+*******************************************************************************/ -+ -+#ifndef __mvCesa_h__ -+#define __mvCesa_h__ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/AES/mvAes.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef MV_INCLUDE_IDMA -+#include "idma/mvIdma.h" -+#include "idma/mvIdmaRegs.h" -+#else -+/* Redefine MV_DMA_DESC structure */ -+typedef struct _mvDmaDesc -+{ -+ MV_U32 byteCnt; /* The total number of bytes to transfer */ -+ MV_U32 phySrcAdd; /* The physical source address */ -+ MV_U32 phyDestAdd; /* The physical destination address */ -+ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ -+ /* then this pointer should point to the */ -+ /* physical address of the next descriptor, */ -+ /* otherwise it should be NULL. */ -+}MV_DMA_DESC; -+#endif /* MV_INCLUDE_IDMA */ -+ -+#include "cesa/mvCesaRegs.h" -+ -+#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ -+ -+#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ -+#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ -+ -+#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE -+ -+#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ -+#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ -+ -+#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH -+ -+#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+ -+#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ -+ -+#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE -+ -+#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ -+ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ MV_CESA_OPERATION operation; -+ MV_CESA_DIRECTION direction; -+ MV_CESA_CRYPTO_ALG cryptoAlgorithm; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_U8 cryptoKeyLength; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8 macKeyLength; -+ MV_U8 digestSize; -+ -+} MV_CESA_OPEN_SESSION; -+ -+typedef struct -+{ -+ MV_BUF_INFO *pFrags; -+ MV_U16 numFrags; -+ MV_U16 mbufSize; -+ -+} MV_CESA_MBUF; -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_U32 retCode; -+ MV_16 sessionId; -+ -+} MV_CESA_RESULT; -+ -+typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); -+ -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_CESA_MBUF* pSrc; -+ MV_CESA_MBUF* pDst; -+ MV_CESA_CALLBACK* pFuncCB; -+ MV_16 sessionId; -+ MV_U16 ivFromUser; -+ MV_U16 ivOffset; -+ MV_U16 cryptoOffset; -+ MV_U16 cryptoLength; -+ MV_U16 digestOffset; -+ MV_U16 macOffset; -+ MV_U16 macLength; -+ MV_BOOL skipFlush; -+} MV_CESA_COMMAND; -+ -+ -+ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); -+MV_STATUS mvCesaFinish (void); -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); -+MV_STATUS mvCesaSessionClose(short sid); -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); -+ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); -+ -+MV_U32 mvCesaInProcessGet(void); -+MV_STATUS mvCesaReadyDispatch(void); -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); -+MV_BOOL mvCesaIsReady(void); -+ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size); -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size); -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); -+ -+/********** Debug functions ********/ -+ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); -+void mvCesaDebugSA(short sid, int mode); -+void mvCesaDebugStats(void); -+void mvCesaDebugStatsClear(void); -+void mvCesaDebugRegs(void); -+void mvCesaDebugStatus(void); -+void mvCesaDebugQueue(int mode); -+void mvCesaDebugSram(int mode); -+void mvCesaDebugSAD(int mode); -+ -+ -+/******** CESA Private definitions ********/ -+#if (MV_CESA_VERSION >= 2) -+#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ -+ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ -+ | MV_CESA_TDMA_ENABLE_MASK -+#else -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ -+ | MV_CESA_TDMA_ENABLE_MASK -+ -+#endif -+#else -+#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ -+ | ICCLR_SRC_BURST_LIM_128BYTE \ -+ | ICCLR_INT_MODE_MASK \ -+ | ICCLR_BLOCK_MODE \ -+ | ICCLR_CHAN_ENABLE \ -+ | ICCLR_DESC_MODE_16M -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#define MV_CESA_MAX_PKT_SIZE (64 * 1024) -+#define MV_CESA_MAX_MBUF_FRAGS 20 -+ -+#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) -+ -+#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) -+ -+#define MAX_CESA_CHAIN_LENGTH 20 -+ -+typedef enum -+{ -+ MV_CESA_IDLE = 0, -+ MV_CESA_PENDING, -+ MV_CESA_PROCESS, -+ MV_CESA_READY, -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_CHAIN, -+#endif -+} MV_CESA_STATE; -+ -+ -+/* Session database */ -+ -+/* Map of Key materials of the session in SRAM. -+ * Each field must be 8 byte aligned -+ * Total size: 32 + 24 + 24 = 80 bytes -+ */ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedInner[4]; -+ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedOuter[4]; -+ -+} MV_CESA_SRAM_SA; -+ -+typedef struct -+{ -+ MV_CESA_SRAM_SA* pSramSA; -+ MV_U32 config; -+ MV_U8 cryptoKeyLength; -+ MV_U8 cryptoIvSize; -+ MV_U8 cryptoBlockSize; -+ MV_U8 digestSize; -+ MV_U8 macKeyLength; -+ MV_U8 valid; -+ MV_U8 ctrMode; -+ MV_U32 count; -+ -+} MV_CESA_SA; -+ -+/* DMA list management */ -+typedef struct -+{ -+ MV_DMA_DESC* pDmaFirst; -+ MV_DMA_DESC* pDmaLast; -+ -+} MV_CESA_DMA; -+ -+ -+typedef struct -+{ -+ MV_U8 numFrag; -+ MV_U8 nextFrag; -+ int bufOffset; -+ int cryptoSize; -+ int macSize; -+ int newDigestOffset; -+ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+} MV_CESA_FRAGS; -+ -+/* Request queue */ -+typedef struct -+{ -+ MV_U8 state; -+ MV_U8 fragMode; -+ MV_U8 fixOffset; -+ MV_CESA_COMMAND* pCmd; -+ MV_CESA_COMMAND* pOrgCmd; -+ MV_BUF_INFO dmaDescBuf; -+ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; -+ MV_BUF_INFO cesaDescBuf; -+ MV_CESA_DESC* pCesaDesc; -+ MV_CESA_FRAGS frags; -+ -+ -+} MV_CESA_REQ; -+ -+ -+/* SRAM map */ -+/* Total SRAM size calculation */ -+/* SRAM size = -+ * MV_CESA_MAX_BUF_SIZE + -+ * sizeof(MV_CESA_DESC) + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_DIGEST_SIZE + -+ * sizeof(MV_CESA_SRAM_SA) -+ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes -+ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes -+ */ -+typedef struct -+{ -+ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; -+ MV_CESA_DESC desc; -+ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; -+ MV_CESA_SRAM_SA sramSA; -+ -+} MV_CESA_SRAM_MAP; -+ -+ -+typedef struct -+{ -+ MV_U32 openedCount; -+ MV_U32 closedCount; -+ MV_U32 fragCount; -+ MV_U32 reqCount; -+ MV_U32 maxReqCount; -+ MV_U32 procCount; -+ MV_U32 readyCount; -+ MV_U32 notReadyCount; -+ MV_U32 startCount; -+#if (MV_CESA_VERSION >= 3) -+ MV_U32 maxChainUsage; -+#endif -+ -+} MV_CESA_STATS; -+ -+ -+/* External variables */ -+ -+extern MV_CESA_STATS cesaStats; -+extern MV_CESA_FRAGS cesaFrags; -+ -+extern MV_BUF_INFO cesaSramSaBuf; -+ -+extern MV_CESA_SA* pCesaSAD; -+extern MV_U16 cesaMaxSA; -+ -+extern MV_CESA_REQ* pCesaReqFirst; -+extern MV_CESA_REQ* pCesaReqLast; -+extern MV_CESA_REQ* pCesaReqEmpty; -+extern MV_CESA_REQ* pCesaReqProcess; -+extern int cesaQueueDepth; -+extern int cesaReqResources; -+#if (MV_CESA_VERSION>= 3) -+extern MV_U32 cesaChainLength; -+#endif -+ -+extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; -+extern MV_U32 cesaSramPhysAddr; -+ -+static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) -+{ -+ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); -+} -+ -+/* Additional DEBUG functions */ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); -+ -+ -+ -+#endif /* __mvCesa_h__ */ -diff --git a/crypto/ocf/kirkwood/cesa/mvCesaDebug.c b/crypto/ocf/kirkwood/cesa/mvCesaDebug.c -new file mode 100644 -index 0000000..0b7cb48 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvCesaDebug.c -@@ -0,0 +1,484 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+ -+static const char* mvCesaDebugStateStr(MV_CESA_STATE state) -+{ -+ switch(state) -+ { -+ case MV_CESA_IDLE: -+ return "Idle"; -+ -+ case MV_CESA_PENDING: -+ return "Pend"; -+ -+ case MV_CESA_PROCESS: -+ return "Proc"; -+ -+ case MV_CESA_READY: -+ return "Ready"; -+ -+ default: -+ break; -+ } -+ return "Unknown"; -+} -+ -+static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) -+{ -+ switch(oper) -+ { -+ case MV_CESA_MAC_ONLY: -+ return "MacOnly"; -+ -+ case MV_CESA_CRYPTO_ONLY: -+ return "CryptoOnly"; -+ -+ case MV_CESA_MAC_THEN_CRYPTO: -+ return "MacCrypto"; -+ -+ case MV_CESA_CRYPTO_THEN_MAC: -+ return "CryptoMac"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) -+{ -+ switch(cryptoAlg) -+ { -+ case MV_CESA_CRYPTO_DES: -+ return "DES"; -+ -+ case MV_CESA_CRYPTO_3DES: -+ return "3DES"; -+ -+ case MV_CESA_CRYPTO_AES: -+ return "AES"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) -+{ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ return "MD5"; -+ -+ case MV_CESA_MAC_SHA1: -+ return "SHA1"; -+ -+ case MV_CESA_MAC_HMAC_MD5: -+ return "HMAC-MD5"; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ return "HMAC_SHA1"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) -+{ -+ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", -+ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, -+ pCmd->pFuncCB, pCmd->sessionId); -+ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", -+ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, -+ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); -+} -+ -+/* no need to use in tool */ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) -+{ -+ int frag, len, fragOffset; -+ -+ if(str != NULL) -+ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", -+ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return; -+ } -+ -+ for(; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pMbuf->pFrags[frag].bufVirtPtr, -+ pMbuf->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); -+ size -= len; -+ fragOffset = 0; -+ } -+ } -+} -+ -+void mvCesaDebugRegs(void) -+{ -+ mvOsPrintf("\t CESA Registers:\n"); -+ -+ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CMD_REG, -+ MV_REG_READ( MV_CESA_CMD_REG ) ); -+ -+ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CHAN_DESC_OFFSET_REG, -+ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); -+ -+ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CFG_REG, -+ MV_REG_READ( MV_CESA_CFG_REG ) ); -+ -+ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", -+ MV_CESA_STATUS_REG, -+ MV_REG_READ( MV_CESA_STATUS_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_MASK_REG, -+ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); -+#if (MV_CESA_VERSION >= 2) -+ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CTRL_REG, -+ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_BYTE_COUNT_REG, -+ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_SRC_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_DST_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CURR_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_MASK_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+#endif -+} -+ -+void mvCesaDebugStatus(void) -+{ -+ mvOsPrintf("\n\t CESA Status\n\n"); -+ -+ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", -+ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), -+ cesaReqResources); -+#if (MV_CESA_VERSION >= 3) -+ mvOsPrintf("chainLength=%u\n",cesaChainLength); -+#else -+ mvOsPrintf("\n"); -+#endif -+ -+ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", -+ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); -+ -+ mvOsPrintf("\n"); -+ -+ mvCesaDebugRegs(); -+ mvCesaDebugStats(); -+ mvCesaDebugStatsClear(); -+} -+ -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) -+{ -+ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", -+ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); -+ -+ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", -+ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, -+ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); -+ -+ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", -+ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, -+ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); -+} -+ -+void mvCesaDebugQueue(int mode) -+{ -+ mvOsPrintf("\n\t CESA Request Queue:\n\n"); -+ -+ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", -+ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); -+ -+ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", -+ pCesaReqEmpty, pCesaReqProcess, -+ cesaReqResources); -+ -+ if(mode != 0) -+ { -+ int count = 0; -+ MV_CESA_REQ* pReq = pCesaReqFirst; -+ -+ for(count=0; countstate), -+ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ int frag; -+ -+ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", -+ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, -+ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); -+ for(frag=0; fragfrags.numFrag; frag++) -+ { -+ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, -+ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); -+ } -+ } -+ if(mode > 1) -+ { -+ /* Print out Command */ -+ mvCesaDebugCmd(pReq->pCmd, mode); -+ -+ /* Print out Descriptor */ -+ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); -+ } -+ pReq++; -+ } -+ } -+} -+ -+ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) -+{ -+ if(pSramSA == NULL) -+ { -+ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); -+ return; -+ } -+ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", -+ pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ -+ if(mode != 0) -+ { -+ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", -+ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); -+ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); -+ -+ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", -+ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ -+ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", -+ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ } -+} -+ -+void mvCesaDebugSA(short sid, int mode) -+{ -+ MV_CESA_OPERATION oper; -+ MV_CESA_DIRECTION dir; -+ MV_CESA_CRYPTO_ALG cryptoAlg; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_CESA_MAC_MODE macMode; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+ -+ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) -+ { -+ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", -+ sid, pSA, -+ pSA->valid ? "Valid" : "Invalid", pSA->count); -+ -+ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; -+ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; -+ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), -+ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); -+ if(oper != MV_CESA_MAC_ONLY) -+ { -+ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; -+ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; -+ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), -+ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); -+ } -+ if(oper != MV_CESA_CRYPTO_ONLY) -+ { -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); -+ } -+ mvOsPrintf("\n"); -+ -+ if(mode > 0) -+ { -+ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", -+ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, -+ pCesaSAD[sid].digestSize); -+ -+ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); -+ } -+ } -+} -+ -+ -+/**/ -+void mvCesaDebugSram(int mode) -+{ -+ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", -+ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); -+ -+ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); -+ if(mode != 0) -+ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); -+ -+ mvOsPrintf("\n"); -+ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", -+ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); -+ } -+ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); -+ } -+ mvOsPrintf("\n"); -+ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); -+} -+ -+void mvCesaDebugSAD(int mode) -+{ -+ int sid; -+ -+ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", -+ pCesaSAD, cesaMaxSA); -+ -+ for(sid=0; sid= 3) -+ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); -+#endif -+ mvOsPrintf("\n"); -+ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", -+ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); -+} -+ -+void mvCesaDebugStatsClear(void) -+{ -+ memset(&cesaStats, 0, sizeof(cesaStats)); -+} -diff --git a/crypto/ocf/kirkwood/cesa/mvCesaRegs.h b/crypto/ocf/kirkwood/cesa/mvCesaRegs.h -new file mode 100644 -index 0000000..c6eecae ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvCesaRegs.h -@@ -0,0 +1,357 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvCesaRegs_h__ -+#define __mvCesaRegs_h__ -+ -+#include "mvTypes.h" -+ -+typedef struct -+{ -+ /* word 0 */ -+ MV_U32 config; -+ /* word 1 */ -+ MV_U16 cryptoSrcOffset; -+ MV_U16 cryptoDstOffset; -+ /* word 2 */ -+ MV_U16 cryptoDataLen; -+ MV_U16 reserved1; -+ /* word 3 */ -+ MV_U16 cryptoKeyOffset; -+ MV_U16 reserved2; -+ /* word 4 */ -+ MV_U16 cryptoIvOffset; -+ MV_U16 cryptoIvBufOffset; -+ /* word 5 */ -+ MV_U16 macSrcOffset; -+ MV_U16 macTotalLen; -+ /* word 6 */ -+ MV_U16 macDigestOffset; -+ MV_U16 macDataLen; -+ /* word 7 */ -+ MV_U16 macInnerIvOffset; -+ MV_U16 macOuterIvOffset; -+ -+} MV_CESA_DESC; -+ -+/* operation */ -+typedef enum -+{ -+ MV_CESA_MAC_ONLY = 0, -+ MV_CESA_CRYPTO_ONLY = 1, -+ MV_CESA_MAC_THEN_CRYPTO = 2, -+ MV_CESA_CRYPTO_THEN_MAC = 3, -+ -+ MV_CESA_MAX_OPERATION -+ -+} MV_CESA_OPERATION; -+ -+#define MV_CESA_OPERATION_OFFSET 0 -+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) -+ -+/* mac algorithm */ -+typedef enum -+{ -+ MV_CESA_MAC_NULL = 0, -+ MV_CESA_MAC_MD5 = 4, -+ MV_CESA_MAC_SHA1 = 5, -+ MV_CESA_MAC_HMAC_MD5 = 6, -+ MV_CESA_MAC_HMAC_SHA1 = 7, -+ -+} MV_CESA_MAC_MODE; -+ -+#define MV_CESA_MAC_MODE_OFFSET 4 -+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) -+ -+typedef enum -+{ -+ MV_CESA_MAC_DIGEST_FULL = 0, -+ MV_CESA_MAC_DIGEST_96B = 1, -+ -+} MV_CESA_MAC_DIGEST_SIZE; -+ -+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 -+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) -+ -+ -+typedef enum -+{ -+ MV_CESA_CRYPTO_NULL = 0, -+ MV_CESA_CRYPTO_DES = 1, -+ MV_CESA_CRYPTO_3DES = 2, -+ MV_CESA_CRYPTO_AES = 3, -+ -+} MV_CESA_CRYPTO_ALG; -+ -+#define MV_CESA_CRYPTO_ALG_OFFSET 8 -+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) -+ -+ -+/* direction */ -+typedef enum -+{ -+ MV_CESA_DIR_ENCODE = 0, -+ MV_CESA_DIR_DECODE = 1, -+ -+} MV_CESA_DIRECTION; -+ -+#define MV_CESA_DIRECTION_BIT 12 -+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) -+ -+/* crypto IV mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_ECB = 0, -+ MV_CESA_CRYPTO_CBC = 1, -+ -+ /* NO HW Support */ -+ MV_CESA_CRYPTO_CTR = 10, -+ -+} MV_CESA_CRYPTO_MODE; -+ -+#define MV_CESA_CRYPTO_MODE_BIT 16 -+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) -+ -+/* 3DES mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_3DES_EEE = 0, -+ MV_CESA_CRYPTO_3DES_EDE = 1, -+ -+} MV_CESA_CRYPTO_3DES_MODE; -+ -+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 -+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) -+ -+ -+/* AES Key Length */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_AES_KEY_128 = 0, -+ MV_CESA_CRYPTO_AES_KEY_192 = 1, -+ MV_CESA_CRYPTO_AES_KEY_256 = 2, -+ -+} MV_CESA_CRYPTO_AES_KEY_LEN; -+ -+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 -+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) -+ -+/* Fragmentation mode */ -+typedef enum -+{ -+ MV_CESA_FRAG_NONE = 0, -+ MV_CESA_FRAG_FIRST = 1, -+ MV_CESA_FRAG_LAST = 2, -+ MV_CESA_FRAG_MIDDLE = 3, -+ -+} MV_CESA_FRAG_MODE; -+ -+#define MV_CESA_FRAG_MODE_OFFSET 30 -+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) -+/*---------------------------------------------------------------------------*/ -+ -+/********** Security Accelerator Command Register **************/ -+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) -+ -+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 -+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) -+ -+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 -+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) -+ -+/********** Security Accelerator Descriptor Pointers Register **********/ -+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) -+ -+/********** Security Accelerator Configuration Register **********/ -+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) -+ -+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 -+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) -+ -+#define MV_CESA_CFG_WAIT_DMA_BIT 7 -+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) -+ -+#define MV_CESA_CFG_ACT_DMA_BIT 9 -+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) -+ -+#define MV_CESA_CFG_CHAIN_MODE_BIT 11 -+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) -+ -+/********** Security Accelerator Status Register ***********/ -+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) -+ -+#define MV_CESA_STATUS_ACTIVE_BIT 0 -+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) -+ -+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 -+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) -+ -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ -+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ -+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) -+ -+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) -+#define MV_CESA_CAUSE_DES_MASK (1 << 1) -+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) -+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) -+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) -+ -+#define MV_CESA_CAUSE_ACC_BIT 5 -+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) -+ -+#define MV_CESA_CAUSE_ACC_DMA_BIT 7 -+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) -+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) -+ -+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 -+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) -+ -+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 -+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) -+ -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) -+ -+ -+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) -+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) -+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) -+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) -+ -+#define MV_CESA_AUTH_ALGORITHM_BIT 0 -+#define MV_CESA_AUTH_ALGORITHM_MD5 (0< -+wait_queue_head_t cesaTest_waitq; -+spinlock_t cesaLock; -+ -+#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) -+#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); -+ -+#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) -+#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) -+#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) -+ -+#define CESA_TEST_TICK_GET() jiffies -+#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) -+ -+#elif defined(MV_NETBSD) -+ -+#include -+#include -+static int cesaLock; -+ -+#define CESA_TEST_LOCK(flags) flags = splnet() -+#define CESA_TEST_UNLOCK(flags) splx(flags) -+ -+#define CESA_TEST_WAIT_INIT() /* nothing */ -+#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) -+#define CESA_TEST_WAIT(cond, ms) \ -+do { \ -+ while (!(cond)) \ -+ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ -+} while (/*CONSTCOND*/0) -+ -+#define CESA_TEST_TICK_GET() hardclock_ticks -+#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) -+ -+#define request_irq(i,h,t,n,a) \ -+ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) -+ -+#else -+#error "Only Linux, VxWorks, or NetBSD OS are supported" -+#endif -+ -+#include "mvDebug.h" -+ -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cntmr/mvCntmr.h" -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#if defined(CONFIG_MV646xx) -+#include "marvell_pic.h" -+#endif -+ -+#define MV_CESA_USE_TIMER_ID 0 -+#define CESA_DEF_BUF_SIZE 1500 -+#define CESA_DEF_BUF_NUM 1 -+#define CESA_DEF_SESSION_NUM 32 -+ -+#define CESA_DEF_ITER_NUM 100 -+ -+#define CESA_DEF_REQ_SIZE 256 -+ -+ -+/* CESA Tests Debug */ -+#undef CESA_TEST_DEBUG -+ -+#ifdef CESA_TEST_DEBUG -+ -+# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg -+# define CESA_TEST_DEBUG_CODE(code) code -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 25 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type, MV_U32 cause) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].cause = cause; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else -+ -+# define CESA_TEST_DEBUG_PRINT(msg) -+# define CESA_TEST_DEBUG_CODE(code) -+ -+#endif /* CESA_TEST_DEBUG */ -+ -+int cesaExpReqId=0; -+int cesaCbIter=0; -+ -+int cesaIdx; -+int cesaIteration; -+int cesaRateSize; -+int cesaReqSize; -+unsigned long cesaTaskId; -+int cesaBufNum; -+int cesaBufSize; -+int cesaCheckOffset; -+int cesaCheckSize; -+int cesaCheckMode; -+int cesaTestIdx; -+int cesaCaseIdx; -+ -+ -+MV_U32 cesaTestIsrCount = 0; -+MV_U32 cesaTestIsrMissCount = 0; -+ -+MV_U32 cesaCryptoError = 0; -+MV_U32 cesaReqIdError = 0; -+MV_U32 cesaError = 0; -+ -+char* cesaHexBuffer = NULL; -+ -+char* cesaBinBuffer = NULL; -+char* cesaExpBinBuffer = NULL; -+ -+char* cesaInputHexStr = NULL; -+char* cesaOutputHexStr = NULL; -+ -+MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; -+ -+MV_CESA_COMMAND* cesaCmdRing; -+MV_CESA_RESULT cesaResult; -+ -+int cesaTestFull = 0; -+ -+MV_BOOL cesaIsReady = MV_FALSE; -+MV_U32 cesaCycles = 0; -+MV_U32 cesaBeginTicks = 0; -+MV_U32 cesaEndTicks = 0; -+MV_U32 cesaRate = 0; -+MV_U32 cesaRateAfterDot = 0; -+ -+void *cesaTestOSHandle = NULL; -+ -+enum -+{ -+ CESA_FAST_CHECK_MODE = 0, -+ CESA_FULL_CHECK_MODE, -+ CESA_NULL_CHECK_MODE, -+ CESA_SHOW_CHECK_MODE, -+ CESA_SW_SHOW_CHECK_MODE, -+ CESA_SW_NULL_CHECK_MODE, -+ -+ CESA_MAX_CHECK_MODE -+}; -+ -+enum -+{ -+ DES_TEST_TYPE = 0, -+ TRIPLE_DES_TEST_TYPE = 1, -+ AES_TEST_TYPE = 2, -+ MD5_TEST_TYPE = 3, -+ SHA_TEST_TYPE = 4, -+ COMBINED_TEST_TYPE = 5, -+ -+ MAX_TEST_TYPE -+}; -+ -+/* Tests data base */ -+typedef struct -+{ -+ short sid; -+ char cryptoAlgorithm; /* DES/3DES/AES */ -+ char cryptoMode; /* ECB or CBC */ -+ char macAlgorithm; /* MD5 / SHA1 */ -+ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ -+ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ -+ unsigned char* pCryptoKey; -+ int cryptoKeySize; -+ unsigned char* pMacKey; -+ int macKeySize; -+ const char* name; -+ -+} MV_CESA_TEST_SESSION; -+ -+typedef struct -+{ -+ MV_CESA_TEST_SESSION* pSessions; -+ int numSessions; -+ -+} MV_CESA_TEST_DB_ENTRY; -+ -+typedef struct -+{ -+ char* plainHexStr; -+ char* cipherHexStr; -+ unsigned char* pCryptoIV; -+ int cryptoLength; -+ int macLength; -+ int digestOffset; -+ -+} MV_CESA_TEST_CASE; -+ -+typedef struct -+{ -+ int size; -+ const char* outputHexStr; -+ -+} MV_CESA_SIZE_TEST; -+ -+static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+ -+static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; -+ -+ -+static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; -+ -+static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; -+ -+static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; -+ -+static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, -+ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; -+ -+ -+static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, -+ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, -+ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; -+ -+/* Input ASCII string: The quick brown fox jump */ -+static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; -+static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; -+ -+static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, -+ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, -+ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; -+ -+static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; -+ -+static char plain3des2[] = "326a494cd33fe756"; -+ -+static char cipher3desCbc2[] = "8e29f75ea77e5475" -+ "b22b8d66de970692"; -+ -+static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, -+ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, -+ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; -+ -+static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; -+ -+static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; -+ -+static char cipher3desCbc3[] = "3d1de3cc132e3b65" -+ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; -+ -+static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, -+ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; -+ -+static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, -+ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; -+ -+static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; -+ -+static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, -+ 0x11, 0x12, 0x13, 0x14}; -+ -+ -+static MV_CESA_TEST_SESSION desTestSessions[] = -+{ -+/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB encode", -+ }, -+/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB decode", -+ }, -+/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC encode" -+ }, -+/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC decode" -+ }, -+/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, NULL, 0, -+ "NULL Crypto Algorithm encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION tripleDesTestSessions[] = -+{ -+/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB encode", -+ }, -+/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB decode", -+ }, -+/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC encode" -+ }, -+/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC decode" -+ }, -+/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des1, sizeof(key3des1), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des2, sizeof(key3des2), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des3, sizeof(key3des3), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION aesTestSessions[] = -+{ -+/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB encode" -+ }, -+/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB decode" -+ }, -+/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC encode" -+ }, -+/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC decode" -+ }, -+/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB encode" -+ }, -+/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB decode" -+ }, -+/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB encode" -+ }, -+/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB decode" -+ }, -+/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), -+ NULL, 0, -+ "AES-128 CTR encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION md5TestSessions[] = -+{ -+/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-MD5 Generate Signature" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION shaTestSessions[] = -+{ -+/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey4, sizeof(shaKey4), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-SHA1 Generate Signature" -+ }, -+}; -+ -+static MV_CESA_TEST_SESSION combinedTestSessions[] = -+{ -+/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ mdKey4, sizeof(mdKey4), -+ "DES + MD5 encode" -+ }, -+/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ shaKey4, sizeof(shaKey4), -+ "DES + SHA1 encode" -+ }, -+/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES + MD5 encode" -+ }, -+/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES + SHA1 encode" -+ }, -+/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES CBC + MD5 encode" -+ }, -+/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES CBC + SHA1 encode" -+ }, -+/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ mdKey4, sizeof(mdKey4), -+ "AES-128 CBC + MD5 encode" -+ }, -+/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ shaKey4, sizeof(shaKey4), -+ "AES-128 CBC + SHA1 encode" -+ }, -+/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 + 3DES decode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = -+{ -+ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, -+ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, -+ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, -+ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, -+ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, -+ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, -+ { NULL, 0 } -+}; -+ -+ -+char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; -+ -+char cesaPlainAsciiText[] = "Now is the time for all "; -+char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; -+char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; -+ -+char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; -+char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; -+char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; -+char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; -+ -+char cesaAsciiStr1[] = "Hi There"; -+char cesaDataHexStr1[] = "4869205468657265"; -+char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; -+char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; -+char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; -+char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; -+ -+char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" -+ "000102030405060708090A0B0C0D0E0F" -+ "101112131415161718191A1B1C1D1E1F" -+ "20212223"; -+ -+char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" -+ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" -+ "4540A42BDE6D7836D59A5CEAAEF31053" -+ "25B2072F"; -+ -+ -+ -+/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ -+char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; -+char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; -+char cesaDataHexStr3[50*2+1] = ""; -+char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; -+char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; -+ -+/* Ascii string is "abc" */ -+char hashHexStr3[] = "616263"; -+char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; -+char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; -+ -+char hashHexStr80[] = "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930"; -+ -+char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; -+ -+char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; -+char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; -+ -+char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; -+char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; -+ -+char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; -+char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; -+ -+ -+static MV_CESA_TEST_CASE cesaTestCases[] = -+{ -+ /* plainHexStr cipherHexStr IV crypto mac digest */ -+ /* Length Length Offset */ -+ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, -+ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, -+ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, -+ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, -+ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, -+ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, -+ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, -+ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, -+ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, -+ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, -+/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, -+/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, -+/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, -+/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, -+/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, -+/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, -+/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, -+/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, -+/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, -+/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, -+/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, -+/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, -+/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, -+/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, -+/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, -+/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, -+/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, -+/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * Input 0xdd repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = -+{ -+ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, -+ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, -+ { 1000, "d00814f586a8b78a05724239d2531821" }, -+ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, -+ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, -+ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, -+ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, -+ { 1005, "e082790b4857fcfc266e92e59e608814" }, -+ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, -+ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, -+ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, -+ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, -+ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, -+ { 1401, "e913858b484cbe2b384099ea88d8855b" }, -+ { 1402, "d9848a164af53620e0540c1d7d87629e" }, -+ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, -+ { 1404, "12edd4f609416e3c936170360561b064" }, -+ { 1405, "7fc912718a05446395345009132bf562" }, -+ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, -+ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, -+ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, -+ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, -+ { 2048, "67caf64475650732def374ebb8bde3fd" }, -+ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, -+ { 2050, "8999586754a73a99efbe4dbad2816d41" }, -+ { 2051, "ba6946b610e098d286bc81091659dfff" }, -+ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, -+ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, -+ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, -+ { 3075, "ea4a6929be67e33e61ff475369248b73" }, -+ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, -+ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, -+ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, -+ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, -+ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, -+ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, -+ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, -+ { 8192, "c600ea4429ac47f9941f09182166e51a" }, -+ {16384, "16e8754bfbeb4c649218422792267a37" }, -+ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = -+{ -+ { 80, "a456c4723fee6068530af5a2afa71627" }, -+ { 512, "f85c2a2344f5de68b432208ad13e5794" }, -+ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, -+ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, -+ { 1002, "5664f71800c011cc311cb6943339c1b8" }, -+ { 1003, "779c723b044c585dc7802b13e8501bdc" }, -+ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, -+ { 1005, "d5f978954f5c38529d1679d2b714f068" }, -+ { 1006, "cd3efc827ce628b7281b72172693abf9" }, -+ { 1336, "6f04479910785878ae6335b8d1e87edf" }, -+ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, -+ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, -+ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, -+ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, -+ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, -+ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, -+ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, -+ { 1405, "d1487bd42f6edd9b4dab316631159221" }, -+ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, -+ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, -+ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, -+ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, -+ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, -+ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, -+ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, -+ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, -+ { 2052, "32f76610a14310309eb748fe025081bf" }, -+ { 3072, "45edc1a42bf9d708a621076b63b774da" }, -+ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, -+ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, -+ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, -+ { 4052, "81976bcaeb274223983996c137875cb8" }, -+ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, -+ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, -+ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, -+ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, -+ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, -+ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, -+ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, -+ {16384, "c6c722087653b62007aea668277175e5" }, -+ {18432, "f1faca8e907872c809e14ffbd85792d6" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-MD5 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = -+{ -+ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, -+ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, -+ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, -+ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, -+ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, -+ { 1003, "961753017feee04c9b93a8e51658a829" }, -+ { 1004, "dd68c4338608dcc87807a711636bf2af" }, -+ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, -+ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, -+ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, -+ { 1344, "335a919805f370b9e402a62c6fe01739" }, -+ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, -+ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, -+ { 1401, "49590f61298a76719bc93a57a30136f5" }, -+ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, -+ { 1403, "37073a02ab00ecba2645c57c228860db" }, -+ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, -+ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, -+ { 1406, "4b6695772a4c66313fa4871017d05f36" }, -+ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, -+ { 1408, "b801b9b69920907cd018e8063092ede9" }, -+ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, -+ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, -+ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, -+ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, -+ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, -+ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, -+ { 3072, "37d158e33b21390822739d13db7b87fe" }, -+ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, -+ { 3075, "335ffb428eabf210bada96d74d5a4012" }, -+ { 4048, "2434c2b43d798d2819487a886261fc64" }, -+ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, -+ { 4058, "856781f85616c341c3533d090c1e1e84" }, -+ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, -+ { 6150, "a09a353be7795fac2401dac5601872e6" }, -+ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, -+ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, -+ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, -+ { 8320, "b727589d9183ff4e8491dd24466974a3" }, -+ {16384, "3f54d970793d2274d5b20d10a69938ac" }, -+ {18432, "f558511dcf81985b7a1bb57fad970531" }, -+ { 0, NULL }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * 0xaa, 0xaa, 0xaa, 0xaa -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = -+{ -+ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, -+ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, -+ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, -+ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, -+ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, -+ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, -+ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, -+ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, -+ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, -+ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, -+ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, -+ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, -+ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, -+ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, -+ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, -+ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, -+ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, -+ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, -+ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, -+ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, -+ { 1408, "3987511182b18473a564436003139b808fa46343" }, -+ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, -+ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, -+ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, -+ { 2050, "8831939904009338de10e7fa670847041387807d" }, -+ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, -+ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, -+ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, -+ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, -+ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, -+ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, -+ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, -+ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, -+ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, -+ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, -+ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, -+ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, -+ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, -+ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, -+ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, -+ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = -+{ -+ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, -+ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, -+ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, -+ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, -+ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, -+ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, -+ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, -+ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, -+ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, -+ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, -+ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, -+ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, -+ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, -+ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, -+ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, -+ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, -+ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, -+ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, -+ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, -+ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, -+ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, -+ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, -+ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, -+ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, -+ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, -+ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, -+ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, -+ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, -+ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, -+ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, -+ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, -+ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, -+ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, -+ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, -+ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, -+ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, -+ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, -+ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, -+ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, -+ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, -+ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-SHA1 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = -+{ -+ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, -+ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, -+ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, -+ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, -+ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, -+ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, -+ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, -+ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, -+ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, -+ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, -+ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, -+ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, -+ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, -+ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, -+ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, -+ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, -+ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, -+ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, -+ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, -+ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, -+ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, -+ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, -+ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, -+ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, -+ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, -+ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, -+ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, -+ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, -+ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, -+ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, -+ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, -+ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, -+ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, -+ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, -+ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, -+ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, -+ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, -+ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, -+ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, -+ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, -+ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = -+{ -+ { 64, "9586962a2aaaef28803dec2e17807a7f" }, -+ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, -+ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, -+ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, -+ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, -+ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, -+ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, -+ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, -+ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, -+ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, -+ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, -+ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, -+ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, -+ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, -+ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, -+ { 8192, "d581780b7163138a0f412be681457d82" }, -+ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, -+ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = -+{ -+ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, -+ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, -+ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, -+ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, -+ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, -+ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, -+ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, -+ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, -+ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, -+ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, -+ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, -+ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, -+ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, -+ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, -+ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, -+ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, -+ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, -+ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = -+{ -+ { 64, "8d10e00802460ede0058c139ba48bd2d" }, -+ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, -+ { 352, "4938d48bdf86aece2c6851e7c6079788" }, -+ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, -+ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, -+ { 1336, "44af60087b74ed07950088efbe3b126a" }, -+ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, -+ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, -+ { 1408, "4fb436624b02516fc9d1535466574bf9" }, -+ { 2048, "c909b0985c423d8d86719f701e9e83db" }, -+ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, -+ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, -+ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, -+ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, -+ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, -+ { 8192, "afe101fbe745bb449ae4f50d10801456" }, -+ {16384, "9741706d0b1c923340c4660ff97cacdf" }, -+ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = -+{ -+ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, -+ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, -+ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, -+ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, -+ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, -+ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, -+ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, -+ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, -+ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, -+ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, -+ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, -+ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, -+ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, -+ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, -+ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, -+ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, -+ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, -+ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = -+{ -+ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, -+ { 64, "7dba7fb988e80da609b1fea7254bced8" }, -+ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, -+ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, -+ { 512, "596c055c1c55db748379223164075641" }, -+ { 1008, "f920989c02f3b3603f53c99d89492377" }, -+ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, -+ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, -+ { 2048, "a917f0099c69eb94079a8421714b6aad" }, -+ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, -+ { 4048, "139dca91bcff65b3c40771749052906b" }, -+ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, -+ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, -+ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, -+ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, -+ {16384, "60fda559c74f91df538100c9842f2f15" }, -+ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = -+{ -+ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, -+ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, -+ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, -+ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, -+ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, -+ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, -+ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, -+ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, -+ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, -+ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, -+ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, -+ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, -+ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, -+ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, -+ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, -+ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, -+ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, -+ { 0, NULL }, -+}; -+ -+ -+void cesaTestPrintStatus(void); -+ -+ -+/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); -+MV_STATUS testClose(int idx); -+MV_STATUS testOpen(int idx); -+void close_session(int sid); -+void cesaTestCheckReady(const MV_CESA_RESULT *r); -+void cesaCheckReady(MV_CESA_RESULT* r); -+void printTestResults(int idx, MV_STATUS status, int checkMode); -+void cesaLastResult(void); -+void cesaTestPrintReq(int req, int offset, int size); -+ -+void cesaTestPrintStatus(void); -+void cesaTestPrintSession(int idx); -+void sizeTest(int testIdx, int iter, int checkMode); -+void multiTest(int iter, int reqSize, int checkMode); -+void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void multiSizeTest(int idx, int iter, int checkMode, char* inputData); -+void cesaTest(int iter, int reqSize, int checkMode); -+void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void combiTest(int iter, int reqSize, int checkMode); -+void shaTest(int iter, int reqSize, int checkMode); -+void mdTest(int iter, int reqSize, int checkMode); -+void aesTest(int iter, int reqSize, int checkMode); -+void tripleDesTest(int iter, int reqSize, int checkMode); -+void desTest(int iter, int reqSize, int checkMode); -+void cesaTestStop(void); -+MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); -+void cesaTestStart(int bufNum, int bufSize); -+ -+ -+static MV_U32 getRate(MV_U32* remainder) -+{ -+ MV_U32 kBits, milliSec, rate; -+ -+ milliSec = 0; -+ if( (cesaEndTicks - cesaBeginTicks) > 0) -+ { -+ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); -+ } -+ if(milliSec == 0) -+ { -+ if(remainder != NULL) -+ *remainder = 0; -+ return 0; -+ } -+ -+ kBits = (cesaIteration*cesaRateSize*8)/1000; -+ rate = kBits/milliSec; -+ if(remainder != NULL) -+ *remainder = ((kBits % milliSec)*10)/milliSec; -+ -+ return rate; -+} -+ -+static char* extractMbuf(MV_CESA_MBUF *pMbuf, -+ int offset, int size, char* hexStr) -+{ -+ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); -+ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); -+ -+ return hexStr; -+} -+ -+static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, int offset, -+ int checkSize) -+{ -+ MV_BOOL isFailed = MV_FALSE; -+ MV_STATUS status; -+ int size = strlen(hexString)/2; -+ int checkedSize = 0; -+/* -+ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", -+ pMbuf, offset, checkSize, pMbuf->mbufSize); -+*/ -+ if(pMbuf->mbufSize < (checkSize + offset)) -+ { -+ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", -+ checkSize, offset, pMbuf->mbufSize); -+ return MV_TRUE; -+ } -+ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", -+ checkSize, pMbuf, cesaBinBuffer); -+ return MV_TRUE; -+ } -+/* -+ mvDebugMemDump(cesaBinBuffer, size, 1); -+*/ -+ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); -+ -+ /* Compare buffers */ -+ while(checkSize > checkedSize) -+ { -+ size = MV_MIN(size, (checkSize - checkedSize)); -+ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) -+ { -+ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", -+ checkSize, size, checkedSize); -+ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); -+ mvDebugMemDump(cesaExpBinBuffer, size, 1); -+ -+ isFailed = MV_TRUE; -+ break; -+ } -+ checkedSize += size; -+ } -+ -+ return isFailed; -+} -+ -+static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, -+ int offset, int reqSize) -+{ -+ MV_STATUS status = MV_OK; -+ int copySize, size = strlen(hexString)/2; -+ -+ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); -+ -+ copySize = 0; -+ while(reqSize > copySize) -+ { -+ size = MV_MIN(size, (reqSize - copySize)); -+ -+ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", -+ copySize, reqSize); -+ break; -+ } -+ copySize += size; -+ } -+ pMbuf->mbufSize = offset+copySize; -+ return status; -+} -+ -+static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) -+{ -+ int testIdx, dbIdx = idx/100; -+ -+ if(dbIdx > MAX_TEST_TYPE) -+ { -+ mvOsPrintf("Wrong index %d - No such test type\n", idx); -+ return NULL; -+ } -+ testIdx = idx % 100; -+ -+ if(testIdx >= cesaTestsDB[dbIdx].numSessions) -+ { -+ mvOsPrintf("Wrong index %d - No such test\n", idx); -+ return NULL; -+ } -+ if(pTestIdx != NULL) -+ *pTestIdx = testIdx; -+ -+ return cesaTestsDB[dbIdx].pSessions; -+} -+ -+/* Debug */ -+void cesaTestPrintReq(int req, int offset, int size) -+{ -+ MV_CESA_MBUF* pMbuf; -+ -+ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", -+ req, offset, size); -+ mvDebugMemDump(cesaCmdRing, 128, 4); -+ -+ pMbuf = cesaCmdRing[req].pSrc; -+ mvCesaDebugMbuf("src", pMbuf, offset,size); -+ pMbuf = cesaCmdRing[req].pDst; -+ mvCesaDebugMbuf("dst", pMbuf, offset, size); -+ -+ cesaTestPrintStatus(); -+} -+ -+void cesaLastResult(void) -+{ -+ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", -+ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, -+ cesaResult.retCode); -+} -+ -+void printTestResults(int idx, MV_STATUS status, int checkMode) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); -+ -+ if(pTestSessions == NULL) -+ return; -+ -+ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, -+ cesaIteration, cesaReqSize); -+ if( (status == MV_OK) && -+ (cesaCryptoError == 0) && -+ (cesaError == 0) && -+ (cesaReqIdError == 0) ) -+ { -+ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", -+ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); -+ } -+ else -+ { -+ mvOsPrintf("Failed, Status = 0x%x\n", status); -+ if(cesaCryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); -+ if(cesaReqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); -+ if(cesaError > 0) -+ mvOsPrintf("cesaError : %d\n", cesaError); -+ } -+ if(cesaTestIsrMissCount > 0) -+ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); -+} -+ -+void cesaCheckReady(MV_CESA_RESULT* r) -+{ -+ int reqId; -+ MV_CESA_MBUF *pMbuf; -+ MV_BOOL isFailed; -+ -+ cesaResult = *r; -+ reqId = (int)cesaResult.pReqPrv; -+ pMbuf = cesaCmdRing[reqId].pDst; -+ -+/* -+ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaCheckOffset, cesaCheckSize); -+*/ -+ /* Check expected reqId */ -+ if(reqId != cesaExpReqId) -+ { -+ cesaReqIdError++; -+/* -+ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaExpReqId); -+*/ -+ } -+ else -+ { -+ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || -+ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) -+ { -+ if(cesaResult.retCode != MV_OK) -+ { -+ cesaError++; -+ -+ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); -+ } -+ else -+ { -+ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) -+ { -+ /* Check expected output */ -+ -+ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); -+ if(isFailed) -+ { -+ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", -+ cesaCbIter, cesaIteration, reqId); -+ -+ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); -+ -+ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); -+ -+ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); -+ -+ cesaCryptoError++; -+ } -+ } -+ } -+ } -+ } -+ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) -+ { -+ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); -+ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); -+ } -+ -+ cesaCbIter++; -+ if(cesaCbIter >= cesaIteration) -+ { -+ cesaCbIter = 0; -+ cesaExpReqId = 0; -+ cesaIsReady = MV_TRUE; -+ -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ } -+ else -+ { -+ cesaExpReqId = reqId + 1; -+ if(cesaExpReqId == CESA_DEF_REQ_SIZE) -+ cesaExpReqId = 0; -+ } -+} -+ -+ -+#ifdef MV_NETBSD -+static int cesaTestReadyIsr(void *arg) -+#else -+#ifdef __KERNEL__ -+static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) -+#endif -+#ifdef MV_VXWORKS -+void cesaTestReadyIsr(void) -+#endif -+#endif -+{ -+ MV_U32 cause; -+ MV_STATUS status; -+ MV_CESA_RESULT result; -+ -+ cesaTestIsrCount++; -+ /* Clear cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); -+#ifdef MV_NETBSD -+ return 0; -+#else -+#ifdef __KERNEL__ -+ return 1; -+#else -+ return; -+#endif -+#endif -+ } -+ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ while(MV_TRUE) -+ { -+ /* Get Ready requests */ -+ status = mvCesaReadyGet(&result); -+ if(status == MV_OK) -+ cesaCheckReady(&result); -+ -+ break; -+ } -+ if( (cesaTestFull == 1) && (status != MV_BUSY) ) -+ { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+ -+#ifdef __KERNEL__ -+ return 1; -+#endif -+} -+ -+void -+cesaTestCheckReady(const MV_CESA_RESULT *r) -+{ -+ MV_CESA_RESULT result = *r; -+ -+ cesaCheckReady(&result); -+ -+ if (cesaTestFull == 1) { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+} -+ -+static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) -+{ -+ MV_U16 sid; -+ MV_STATUS status; -+ -+ status = mvCesaSessionOpen(pOs, (short*)&sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", -+ status); -+ return -1; -+ } -+ -+ return (int)sid; -+} -+ -+void close_session(int sid) -+{ -+ MV_STATUS status; -+ -+ status = mvCesaSessionClose(sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", -+ sid, status); -+ } -+} -+ -+MV_STATUS testOpen(int idx) -+{ -+ MV_CESA_OPEN_SESSION os; -+ int sid, i, testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_U16 digestSize = 0; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid != -1) -+ { -+ mvOsPrintf("Session for test %d already created: sid=%d\n", -+ idx, pTestSession->sid); -+ return MV_OK; -+ } -+ -+ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; -+ os.macMode = pTestSession->macAlgorithm; -+ switch(os.macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_NULL: -+ digestSize = 0; -+ } -+ os.cryptoMode = pTestSession->cryptoMode; -+ os.direction = pTestSession->direction; -+ os.operation = pTestSession->operation; -+ -+ for(i=0; icryptoKeySize; i++) -+ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; -+ -+ os.cryptoKeyLength = pTestSession->cryptoKeySize; -+ -+ for(i=0; imacKeySize; i++) -+ os.macKey[i] = pTestSession->pMacKey[i]; -+ -+ os.macKeyLength = pTestSession->macKeySize; -+ os.digestSize = digestSize; -+ -+ sid = open_session(&os); -+ if(sid == -1) -+ { -+ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", -+ idx, cesaResult.retCode); -+ return cesaResult.retCode; -+ } -+ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); -+ pTestSession->sid = sid; -+ return MV_OK; -+} -+ -+MV_STATUS testClose(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return MV_NO_SUCH; -+ } -+ -+ close_session(pTestSession->sid); -+ pTestSession->sid = -1; -+ -+ return MV_OK; -+} -+ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) -+{ -+ int cmdReqId = 0; -+ int i; -+ MV_STATUS rc = MV_OK; -+ char ivZeroHex[] = "0000"; -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pCmd == NULL) -+ { -+ mvOsPrintf("testCmd failed: pCmd=NULL\n"); -+ return MV_BAD_PARAM; -+ } -+ pCmd->sessionId = sid; -+ -+ cesaCryptoError = 0; -+ cesaReqIdError = 0; -+ cesaError = 0; -+ cesaTestIsrMissCount = 0; -+ cesaIsReady = MV_FALSE; -+ cesaIteration = iter; -+ -+ if(cesaInputHexStr == NULL) -+ cesaInputHexStr = cesaPlainHexEbc; -+ -+ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); -+ if(pIV != NULL) -+ { -+ /* If IV from SA - set IV in Source buffer to zeros */ -+ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, -+ (cesaReqSize - pCmd->cryptoOffset)); -+ } -+ else -+ { -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); -+ } -+ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); -+ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); -+ -+ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); -+ } -+ -+ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) -+ { -+ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ } -+ -+ cesaBeginTicks = CESA_TEST_TICK_GET(); -+ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); -+ cesaTestTraceIdx = 0; -+ ); -+ -+ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) -+ { -+ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); -+ } -+ } -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ cesaIsReady = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ /*cesaTestIsrCount = 0;*/ -+ /*mvCesaDebugStatsClear();*/ -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+#endif -+ -+ for(i=0; ipReqPrv = (void*)cmdReqId; -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ if(rc == MV_NO_RESOURCE) -+ cesaTestFull = 1; -+ -+ CESA_TEST_UNLOCK(flags); -+ -+ if(rc == MV_NO_RESOURCE) -+ { -+ CESA_TEST_LOCK(flags); -+ CESA_TEST_WAIT( (cesaTestFull == 0), 100); -+ CESA_TEST_UNLOCK(flags); -+ if(cesaTestFull == 1) -+ { -+ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", -+ i, iter, cesaTestFull); -+ cesaTestFull = 0; -+ return MV_TIMEOUT; -+ } -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ -+ CESA_TEST_UNLOCK(flags); -+ } -+ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) -+ { -+ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); -+ return rc; -+ } -+ -+ cmdReqId++; -+ if(cmdReqId >= CESA_DEF_REQ_SIZE) -+ cmdReqId = 0; -+ -+#ifdef MV_LINUX -+ /* Reschedule each 16 requests */ -+ if( (i & 0xF) == 0) -+ schedule(); -+#endif -+ } -+ return MV_OK; -+} -+ -+void cesaTestStart(int bufNum, int bufSize) -+{ -+ int i, j, idx; -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ char *pBuf; -+#ifndef MV_NETBSD -+ int numOfSessions, queueDepth; -+ char *pSram; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN addrDecWin; -+#endif -+ -+ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ if(cesaCmdRing == NULL) -+ { -+ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", -+ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ return; -+ } -+ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ -+ if(bufNum == 0) -+ bufNum = CESA_DEF_BUF_NUM; -+ -+ if(bufSize == 0) -+ bufSize = CESA_DEF_BUF_SIZE; -+ -+ cesaBufNum = bufNum; -+ cesaBufSize = bufSize; -+ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", -+ bufNum, bufSize); -+ -+ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); -+ if(cesaHexBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", -+ 2*bufNum*bufSize); -+ return; -+ } -+ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); -+ -+ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaBinBuffer, 0, (bufNum*bufSize)); -+ -+ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaExpBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); -+ -+ CESA_TEST_WAIT_INIT(); -+ -+ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || -+ (pMbufDst == NULL) || (pFragsDst == NULL) ) -+ { -+ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ -+ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", -+ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); -+ -+ idx = 0; -+ for(i=0; ipFrags = &pFragsSrc[idx]; -+ cesaCmdRing[i].pSrc->numFrags = bufNum; -+ cesaCmdRing[i].pSrc->mbufSize = 0; -+ -+ cesaCmdRing[i].pDst = &pMbufDst[i]; -+ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; -+ cesaCmdRing[i].pDst->numFrags = bufNum; -+ cesaCmdRing[i].pDst->mbufSize = 0; -+ -+ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ } -+ idx += bufNum; -+ } -+ -+#ifndef MV_NETBSD -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ pSram = (char*)addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return; -+ } -+ -+#ifdef MV_CESA_NO_SRAM -+ pSram = mvOsMalloc(4*1024+8); -+ if(pSram == NULL) -+ { -+ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", -+ 4*1024+8); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); -+#endif /* MV_CESA_NO_SRAM */ -+ -+ numOfSessions = CESA_DEF_SESSION_NUM; -+ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; -+ -+ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+#endif /* !MV_NETBSD */ -+ -+ /* Prepare data for tests */ -+ for(i=0; i<50; i++) -+ strcat((char*)cesaDataHexStr3, "dd"); -+ -+ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); -+ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); -+ -+ /* Digest must be 8 byte aligned */ -+ for(; i<56; i++) -+ { -+ strcat((char*)cesaDataAndMd5digest3, "00"); -+ strcat((char*)cesaDataAndSha1digest3, "00"); -+ } -+ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); -+ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+ -+#ifdef MV_VXWORKS -+ { -+ MV_STATUS status; -+ -+ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); -+ if (status != OK) -+ { -+ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", -+ INT_LVL_CESA, status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); -+ if(cesaSemId == NULL) -+ { -+ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); -+ return; -+ } -+ intEnable(INT_LVL_CESA); -+ } -+#endif /* MV_VXWORKS */ -+ -+#if !defined(MV_NETBSD) && defined(__KERNEL__) -+ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) -+ { -+ mvOsPrintf( "cannot assign irq\n" ); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ spin_lock_init( &cesaLock ); -+#endif -+} -+ -+MV_STATUS testRun(int idx, int caseIdx, int iter, -+ int reqSize, int checkMode) -+{ -+ int testIdx, count, sid, digestSize; -+ int blockSize; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_CESA_COMMAND cmd; -+ MV_STATUS status; -+ -+ memset(&cmd, 0, sizeof(cmd)); -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ sid = pTestSession->sid; -+ if(sid == -1) -+ { -+ mvOsPrintf("Test %d is not opened\n", idx); -+ return MV_BAD_STATE; -+ } -+ switch(pTestSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ case MV_CESA_CRYPTO_3DES: -+ blockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ blockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_NULL: -+ blockSize = 0; -+ break; -+ -+ default: -+ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", -+ pTestSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ switch(pTestSession->macAlgorithm) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ default: -+ digestSize = 0; -+ } -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pTestSession->direction == MV_CESA_DIR_ENCODE) -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ } -+ else -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ } -+ -+ cmd.sessionId = sid; -+ if(checkMode == CESA_FAST_CHECK_MODE) -+ { -+ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; -+ cmd.macLength = cesaTestCases[caseIdx].macLength; -+ } -+ else -+ { -+ cmd.cryptoLength = reqSize; -+ cmd.macLength = reqSize; -+ } -+ cesaRateSize = cmd.cryptoLength; -+ cesaReqSize = cmd.cryptoLength; -+ cmd.cryptoOffset = 0; -+ if(pTestSession->operation != MV_CESA_MAC_ONLY) -+ { -+ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || -+ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) -+ { -+ cmd.ivOffset = 0; -+ cmd.cryptoOffset = blockSize; -+ if(cesaTestCases[caseIdx].pCryptoIV == NULL) -+ { -+ cmd.ivFromUser = 1; -+ } -+ else -+ { -+ cmd.ivFromUser = 0; -+ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ } -+ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; -+ } -+ } -+ -+/* -+ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", -+ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); -+*/ -+ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ cmd.macOffset = cmd.cryptoOffset; -+ -+ if(cesaTestCases[caseIdx].digestOffset == -1) -+ { -+ cmd.digestOffset = cmd.macOffset + cmd.macLength; -+ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); -+ } -+ else -+ { -+ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; -+ } -+ if( (cmd.digestOffset + digestSize) > cesaReqSize) -+ cesaReqSize = cmd.digestOffset + digestSize; -+ } -+ -+ cesaCheckMode = checkMode; -+ -+ if(checkMode == CESA_NULL_CHECK_MODE) -+ { -+ cesaCheckSize = 0; -+ cesaCheckOffset = 0; -+ } -+ else -+ { -+ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) -+ { -+ cesaCheckOffset = 0; -+ cesaCheckSize = cmd.cryptoLength; -+ } -+ else -+ { -+ cesaCheckSize = digestSize; -+ cesaCheckOffset = cmd.digestOffset; -+ } -+ } -+/* -+ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", -+ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); -+ -+ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", -+ blockSize, cmd.ivOffset, cmd.ivFromUser, -+ cmd.cryptoOffset, cmd.cryptoLength); -+ -+ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", -+ cmd.macOffset, cmd.digestOffset, cmd.macLength); -+*/ -+ status = testCmd(sid, iter, &cmd, pTestSession, -+ cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ -+ if(status != MV_OK) -+ return status; -+ -+ /* Wait when all callbacks is received */ -+ count = 0; -+ while(cesaIsReady == MV_FALSE) -+ { -+ mvOsSleep(10); -+ count++; -+ if(count > 100) -+ { -+ mvOsPrintf("testRun: Timeout occured\n"); -+ return MV_TIMEOUT; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+void cesaTestStop(void) -+{ -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ int i; -+ -+ /* Release all allocated memories */ -+ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); -+ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; -+ -+ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); -+ pFragsDst = cesaCmdRing[0].pDst->pFrags; -+ -+ mvOsFree(pMbufSrc); -+ mvOsFree(pMbufDst); -+ mvOsFree(pFragsSrc); -+ mvOsFree(pFragsDst); -+ -+ for(i=0; i 0) -+ cryptoError++; -+ if(cesaReqIdError > 0) -+ reqIdError++; -+ -+ testClose(idx); -+ } -+ } -+ if(cryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cryptoError); -+ if(reqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", reqIdError); -+ -+ if(openErrors > 0) -+ { -+ mvOsPrintf("Open Errors = %d\n", openErrors); -+ for(i=0; i<100; i++) -+ { -+ if(openErrDisp[i] != 0) -+ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); -+ } -+ } -+} -+ -+ -+void loopback_test(int idx, int iter, int size, char* pPlainData) -+{ -+} -+ -+ -+#if defined(MV_VXWORKS) -+int testMode = 0; -+unsigned __TASKCONV cesaTask(void* args) -+{ -+ int reqSize = cesaReqSize; -+ -+ if(testMode == 0) -+ { -+ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, -+ reqSize, cesaCheckMode); -+ } -+ else -+ { -+ if(testMode == 1) -+ { -+ cesaTest(cesaIteration, reqSize, cesaCheckMode); -+ combiTest(cesaIteration, reqSize, cesaCheckMode); -+ } -+ else -+ { -+ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); -+ } -+ } -+ return 0; -+} -+ -+void oneTest(int testIdx, int caseIdx, -+ int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaReqSize = cesaRateSize = reqSize; -+ cesaCheckMode = checkMode; -+ testMode = 0; -+ cesaTestIdx = testIdx; -+ cesaCaseIdx = caseIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void multiTest(int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ cesaReqSize = reqSize; -+ testMode = 1; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void sizeTest(int testIdx, int iter, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ testMode = 2; -+ cesaIdx = testIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); -+ } -+} -+ -+#endif /* MV_VXWORKS */ -+ -+extern void mvCesaDebugSA(short sid, int mode); -+void cesaTestPrintSession(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return; -+ } -+ -+ mvCesaDebugSA(pTestSession->sid, 1); -+} -+ -+void cesaTestPrintStatus(void) -+{ -+ mvOsPrintf("\n\t Cesa Test Status\n\n"); -+ -+ mvOsPrintf("isrCount=%d\n", -+ cesaTestIsrCount); -+ -+#ifdef CESA_TEST_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); -+ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); -+ if(pLruCache->table == NULL) -+ { -+ mvOsFree(pLruCache); -+ return NULL; -+ } -+ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); -+ pLruCache->tableSize = numOfEntries; -+ -+ for(i=0; itable[i].next = i+1; -+ pLruCache->table[i].prev = i-1; -+ } -+ pLruCache->least = 0; -+ pLruCache->most = numOfEntries-1; -+ -+ return pLruCache; -+} -+ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) -+{ -+ mvOsFree(pLruCache->table); -+ mvOsFree(pLruCache); -+} -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->most) -+ return; -+ -+ next = pLruHndl->table[cacheIdx].next; -+ if(cacheIdx == pLruHndl->least) -+ { -+ pLruHndl->least = next; -+ } -+ else -+ { -+ prev = pLruHndl->table[cacheIdx].prev; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ -+ pLruHndl->table[pLruHndl->most].next = cacheIdx; -+ pLruHndl->table[cacheIdx].prev = pLruHndl->most; -+ pLruHndl->most = cacheIdx; -+} -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->least) -+ return; -+ -+ prev = pLruHndl->table[cacheIdx].prev; -+ if(cacheIdx == pLruHndl->most) -+ { -+ pLruHndl->most = prev; -+ } -+ else -+ { -+ next = pLruHndl->table[cacheIdx].next; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ pLruHndl->table[pLruHndl->least].prev = cacheIdx; -+ pLruHndl->table[cacheIdx].next = pLruHndl->least; -+ pLruHndl->least = cacheIdx; -+} -diff --git a/crypto/ocf/kirkwood/cesa/mvLru.h b/crypto/ocf/kirkwood/cesa/mvLru.h -new file mode 100644 -index 0000000..39d2f89 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvLru.h -@@ -0,0 +1,112 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvLru.h - Header File for Least Recently Used Cache algorithm -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Least Recently Used Cache algorithm. -+* -+*******************************************************************************/ -+ -+#ifndef __mvLru_h__ -+#define __mvLru_h__ -+ -+ -+typedef struct -+{ -+ int next; -+ int prev; -+} MV_LRU_ENTRY; -+ -+typedef struct -+{ -+ int least; -+ int most; -+ MV_LRU_ENTRY* table; -+ int tableSize; -+ -+}MV_LRU_CACHE; -+ -+ -+/* Find Cache index for replacement LRU */ -+static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) -+{ -+ return pLruHndl->least; -+} -+ -+/* Init LRU cache module */ -+MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); -+ -+/* Finish LRU cache module */ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+ -+#endif /* __mvLru_h__ */ -diff --git a/crypto/ocf/kirkwood/cesa/mvMD5.c b/crypto/ocf/kirkwood/cesa/mvMD5.c -new file mode 100644 -index 0000000..b012976 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvMD5.c -@@ -0,0 +1,349 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvMD5.h" -+ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); -+ -+#ifdef MV_CPU_LE -+#define mvByteReverse(buf, len) /* Nothing */ -+#else -+static void mvByteReverse(unsigned char *buf, unsigned longs); -+ -+/* -+ * Note: this code is harmless on little-endian machines. -+ */ -+static void mvByteReverse(unsigned char *buf, unsigned longs) -+{ -+ MV_U32 t; -+ -+ do -+ { -+ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | -+ ((unsigned) buf[1] << 8 | buf[0]); -+ *(MV_U32 *) buf = t; -+ buf += 4; -+ } while (--longs); -+} -+#endif -+ -+/* -+ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious -+ * initialization constants. -+ */ -+void mvMD5Init(MV_MD5_CONTEXT *ctx) -+{ -+ ctx->buf[0] = 0x67452301; -+ ctx->buf[1] = 0xefcdab89; -+ ctx->buf[2] = 0x98badcfe; -+ ctx->buf[3] = 0x10325476; -+ -+ ctx->bits[0] = 0; -+ ctx->bits[1] = 0; -+} -+ -+/* -+ * Update context to reflect the concatenation of another buffer full -+ * of bytes. -+ */ -+void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) -+{ -+ MV_U32 t; -+ -+ /* Update bitcount */ -+ -+ t = ctx->bits[0]; -+ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) -+ ctx->bits[1]++; /* Carry from low to high */ -+ ctx->bits[1] += len >> 29; -+ -+ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ -+ -+ /* Handle any leading odd-sized chunks */ -+ -+ if (t) -+ { -+ unsigned char *p = (unsigned char *) ctx->in + t; -+ -+ t = 64 - t; -+ if (len < t) -+ { -+ memcpy(p, buf, len); -+ return; -+ } -+ memcpy(p, buf, t); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += t; -+ len -= t; -+ } -+ /* Process data in 64-byte chunks */ -+ -+ while (len >= 64) -+ { -+ memcpy(ctx->in, buf, 64); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += 64; -+ len -= 64; -+ } -+ -+ /* Handle any remaining bytes of data. */ -+ -+ memcpy(ctx->in, buf, len); -+} -+ -+/* -+ * Final wrapup - pad to 64-byte boundary with the bit pattern -+ * 1 0* (64-bit count of bits processed, MSB-first) -+ */ -+void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) -+{ -+ unsigned count; -+ unsigned char *p; -+ -+ /* Compute number of bytes mod 64 */ -+ count = (ctx->bits[0] >> 3) & 0x3F; -+ -+ /* Set the first char of padding to 0x80. This is safe since there is -+ always at least one byte free */ -+ p = ctx->in + count; -+ *p++ = 0x80; -+ -+ /* Bytes of padding needed to make 64 bytes */ -+ count = 64 - 1 - count; -+ -+ /* Pad out to 56 mod 64 */ -+ if (count < 8) -+ { -+ /* Two lots of padding: Pad the first block to 64 bytes */ -+ memset(p, 0, count); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ -+ /* Now fill the next block with 56 bytes */ -+ memset(ctx->in, 0, 56); -+ } -+ else -+ { -+ /* Pad block to 56 bytes */ -+ memset(p, 0, count - 8); -+ } -+ mvByteReverse(ctx->in, 14); -+ -+ /* Append length in bits and transform */ -+ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; -+ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; -+ -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ mvByteReverse((unsigned char *) ctx->buf, 4); -+ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); -+ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ -+} -+ -+/* The four core functions - F1 is optimized somewhat */ -+ -+/* #define F1(x, y, z) (x & y | ~x & z) */ -+#define F1(x, y, z) (z ^ (x & (y ^ z))) -+#define F2(x, y, z) F1(z, x, y) -+#define F3(x, y, z) (x ^ y ^ z) -+#define F4(x, y, z) (y ^ (x | ~z)) -+ -+/* This is the central step in the MD5 algorithm. */ -+#define MD5STEP(f, w, x, y, z, data, s) \ -+ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) -+ -+/* -+ * The core of the MD5 algorithm, this alters an existing MD5 hash to -+ * reflect the addition of 16 longwords of new data. MD5Update blocks -+ * the data and converts bytes into longwords for this routine. -+ */ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) -+{ -+ register MV_U32 a, b, c, d; -+ -+ a = buf[0]; -+ b = buf[1]; -+ c = buf[2]; -+ d = buf[3]; -+ -+ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); -+ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); -+ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); -+ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); -+ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); -+ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); -+ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); -+ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); -+ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); -+ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); -+ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); -+ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); -+ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); -+ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); -+ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); -+ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); -+ -+ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); -+ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); -+ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); -+ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); -+ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); -+ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); -+ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); -+ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); -+ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); -+ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); -+ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); -+ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); -+ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); -+ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); -+ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); -+ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); -+ -+ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); -+ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); -+ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); -+ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); -+ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); -+ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); -+ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); -+ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); -+ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); -+ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); -+ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); -+ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); -+ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); -+ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); -+ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); -+ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); -+ -+ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); -+ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); -+ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); -+ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); -+ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); -+ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); -+ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); -+ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); -+ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); -+ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); -+ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); -+ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); -+ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); -+ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); -+ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); -+ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); -+ -+ buf[0] += a; -+ buf[1] += b; -+ buf[2] += c; -+ buf[3] += d; -+} -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) -+{ -+ MV_MD5_CONTEXT ctx; -+ -+ mvMD5Init(&ctx); -+ mvMD5Update(&ctx, buf, len); -+ mvMD5Final(digest, &ctx); -+} -+ -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest) -+{ -+ int i; -+ MV_MD5_CONTEXT ctx; -+ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ -+ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ -+ -+ /* start out by storing key in pads */ -+ memset(k_ipad, 0, 64); -+ memcpy(k_ipad, key, key_len); -+ memset(k_opad, 0, 64); -+ memcpy(k_opad, key, key_len); -+ -+ /* XOR key with ipad and opad values */ -+ for (i=0; i<64; i++) -+ { -+ k_ipad[i] ^= 0x36; -+ k_opad[i] ^= 0x5c; -+ } -+ -+ /* perform inner MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 1st pass */ -+ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ -+ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ -+ mvMD5Final(digest, &ctx); /* finish up 1st pass */ -+ -+ /* perform outer MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 2nd pass */ -+ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ -+ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ -+ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ -+} -diff --git a/crypto/ocf/kirkwood/cesa/mvMD5.h b/crypto/ocf/kirkwood/cesa/mvMD5.h -new file mode 100644 -index 0000000..d20281e ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvMD5.h -@@ -0,0 +1,93 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvMD5_h__ -+#define __mvMD5_h__ -+ -+#include "mvMD5.h" -+ -+#define MV_MD5_MAC_LEN 16 -+ -+ -+typedef struct -+{ -+ MV_U32 buf[4]; -+ MV_U32 bits[2]; -+ MV_U8 in[64]; -+ -+} MV_MD5_CONTEXT; -+ -+void mvMD5Init(MV_MD5_CONTEXT *context); -+void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, -+ unsigned len); -+void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest); -+ -+ -+#endif /* __mvMD5_h__ */ -diff --git a/crypto/ocf/kirkwood/cesa/mvSHA1.c b/crypto/ocf/kirkwood/cesa/mvSHA1.c -new file mode 100644 -index 0000000..6342985 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvSHA1.c -@@ -0,0 +1,239 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvSHA1.h" -+ -+#define SHA1HANDSOFF -+ -+typedef union -+{ -+ MV_U8 c[64]; -+ MV_U32 l[16]; -+ -+} CHAR64LONG16; -+ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); -+ -+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) -+ -+ -+#ifdef MV_CPU_LE -+#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ -+ (rol(block->l[i], 8) & 0x00FF00FF)) -+#else -+#define blk0(i) block->l[i] -+#endif -+#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ -+ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) -+ -+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ -+#define R0(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R1(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R2(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); -+#define R3(v,w,x,y,z,i) \ -+ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ -+ w = rol(w, 30); -+#define R4(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ -+ w=rol(w, 30); -+ -+/* Hash a single 512-bit block. This is the core of the algorithm. */ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) -+{ -+ MV_U32 a, b, c, d, e; -+ CHAR64LONG16* block; -+ -+#ifdef SHA1HANDSOFF -+ static MV_U32 workspace[16]; -+ -+ block = (CHAR64LONG16 *) workspace; -+ memcpy(block, buffer, 64); -+#else -+ block = (CHAR64LONG16 *) buffer; -+#endif -+ /* Copy context->state[] to working vars */ -+ a = state[0]; -+ b = state[1]; -+ c = state[2]; -+ d = state[3]; -+ e = state[4]; -+ /* 4 rounds of 20 operations each. Loop unrolled. */ -+ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); -+ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); -+ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); -+ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); -+ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); -+ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); -+ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); -+ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); -+ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); -+ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); -+ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); -+ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); -+ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); -+ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); -+ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); -+ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); -+ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); -+ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); -+ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); -+ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); -+ /* Add the working vars back into context.state[] */ -+ state[0] += a; -+ state[1] += b; -+ state[2] += c; -+ state[3] += d; -+ state[4] += e; -+ /* Wipe variables */ -+ a = b = c = d = e = 0; -+} -+ -+void mvSHA1Init(MV_SHA1_CTX* context) -+{ -+ /* SHA1 initialization constants */ -+ context->state[0] = 0x67452301; -+ context->state[1] = 0xEFCDAB89; -+ context->state[2] = 0x98BADCFE; -+ context->state[3] = 0x10325476; -+ context->state[4] = 0xC3D2E1F0; -+ context->count[0] = context->count[1] = 0; -+} -+ -+ -+/* Run your data through this. */ -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, -+ unsigned int len) -+{ -+ MV_U32 i, j; -+ -+ j = (context->count[0] >> 3) & 63; -+ if ((context->count[0] += len << 3) < (len << 3)) -+ context->count[1]++; -+ context->count[1] += (len >> 29); -+ if ((j + len) > 63) -+ { -+ memcpy(&context->buffer[j], data, (i = 64-j)); -+ mvSHA1Transform(context->state, context->buffer); -+ for ( ; i + 63 < len; i += 64) -+ { -+ mvSHA1Transform(context->state, &data[i]); -+ } -+ j = 0; -+ } -+ else -+ { -+ i = 0; -+ } -+ memcpy(&context->buffer[j], &data[i], len - i); -+} -+ -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) -+{ -+ MV_U32 i; -+ MV_U8 finalcount[8]; -+ -+ for (i = 0; i < 8; i++) -+ { -+ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> -+ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ -+ } -+ mvSHA1Update(context, (const unsigned char *) "\200", 1); -+ while ((context->count[0] & 504) != 448) -+ { -+ mvSHA1Update(context, (const unsigned char *) "\0", 1); -+ } -+ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() -+ */ -+ for (i = 0; i < 20; i++) -+ { -+ digest[i] = (unsigned char) -+ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); -+ } -+ /* Wipe variables */ -+ i = 0; -+ memset(context->buffer, 0, 64); -+ memset(context->state, 0, 20); -+ memset(context->count, 0, 8); -+ memset(finalcount, 0, 8); -+ -+#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ -+ mvSHA1Transform(context->state, context->buffer); -+#endif -+} -+ -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) -+{ -+ MV_SHA1_CTX ctx; -+ -+ mvSHA1Init(&ctx); -+ mvSHA1Update(&ctx, buf, len); -+ mvSHA1Final(digest, &ctx); -+} -diff --git a/crypto/ocf/kirkwood/cesa/mvSHA1.h b/crypto/ocf/kirkwood/cesa/mvSHA1.h -new file mode 100644 -index 0000000..1914f47 ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa/mvSHA1.h -@@ -0,0 +1,88 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSHA1_h__ -+#define __mvSHA1_h__ -+ -+#include "mvSHA1.h" -+ -+#define MV_SHA1_MAC_LEN 20 -+ -+ -+typedef struct -+{ -+ MV_U32 state[5]; -+ MV_U32 count[2]; -+ MV_U8 buffer[64]; -+ -+} MV_SHA1_CTX; -+ -+void mvSHA1Init(MV_SHA1_CTX *context); -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); -+ -+ -+#endif /* __mvSHA1_h__ */ -diff --git a/crypto/ocf/kirkwood/cesa_ocf_drv.c b/crypto/ocf/kirkwood/cesa_ocf_drv.c -new file mode 100644 -index 0000000..c056b1f ---- /dev/null -+++ b/crypto/ocf/kirkwood/cesa_ocf_drv.c -@@ -0,0 +1,1296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ctrlEnv/sys/mvSysCesa.h" -+#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ -+#include -+#include -+#include -+#include -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+#include "cesa/mvLru.h" -+ -+#undef RT_DEBUG -+#ifdef RT_DEBUG -+static int debug = 1; -+module_param(debug, int, 1); -+MODULE_PARM_DESC(debug, "Enable debug"); -+#undef dprintk -+#define dprintk(a...) if (debug) { printk(a); } else -+#else -+static int debug = 0; -+#undef dprintk -+#define dprintk(a...) -+#endif -+ -+ -+/* TDMA Regs */ -+#define WINDOW_BASE(i) 0xA00 + (i << 3) -+#define WINDOW_CTRL(i) 0xA04 + (i << 3) -+ -+/* interrupt handling */ -+#undef CESA_OCF_POLLING -+#undef CESA_OCF_TASKLET -+ -+#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) -+#error "don't use both tasklet and polling mode" -+#endif -+ -+extern int cesaReqResources; -+/* support for spliting action into 2 actions */ -+#define CESA_OCF_SPLIT -+ -+/* general defines */ -+#define CESA_OCF_MAX_SES 128 -+#define CESA_Q_SIZE 64 -+ -+ -+/* data structures */ -+struct cesa_ocf_data { -+ int cipher_alg; -+ int auth_alg; -+ int encrypt_tn_auth; -+#define auth_tn_decrypt encrypt_tn_auth -+ int ivlen; -+ int digestlen; -+ short sid_encrypt; -+ short sid_decrypt; -+ /* fragment workaround sessions */ -+ short frag_wa_encrypt; -+ short frag_wa_decrypt; -+ short frag_wa_auth; -+}; -+ -+/* CESA device data */ -+struct cesa_dev { -+ void __iomem *sram; -+ void __iomem *reg; -+ struct mv_cesa_platform_data *plat_data; -+ int irq; -+}; -+ -+#define DIGEST_BUF_SIZE 32 -+struct cesa_ocf_process { -+ MV_CESA_COMMAND cesa_cmd; -+ MV_CESA_MBUF cesa_mbuf; -+ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; -+ char digest[DIGEST_BUF_SIZE]; -+ int digest_len; -+ struct cryptop *crp; -+ int need_cb; -+}; -+ -+/* global variables */ -+static int32_t cesa_ocf_id = -1; -+static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; -+static spinlock_t cesa_lock; -+static struct cesa_dev cesa_device; -+ -+/* static APIs */ -+static int cesa_ocf_process (device_t, struct cryptop *, int); -+static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); -+static int cesa_ocf_freesession (device_t, u_int64_t); -+static void cesa_callback (unsigned long); -+static irqreturn_t cesa_interrupt_handler (int, void *); -+#ifdef CESA_OCF_POLLING -+static void cesa_interrupt_polling(void); -+#endif -+#ifdef CESA_OCF_TASKLET -+static struct tasklet_struct cesa_ocf_tasklet; -+#endif -+ -+static struct timeval tt_start; -+static struct timeval tt_end; -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} mv_cesa_dev; -+ -+static device_method_t mv_cesa_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), -+ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), -+ DEVMETHOD(cryptodev_process, cesa_ocf_process), -+ DEVMETHOD(cryptodev_kprocess, NULL), -+}; -+ -+ -+ -+/* Add debug Trace */ -+#undef CESA_OCF_TRACE_DEBUG -+#ifdef CESA_OCF_TRACE_DEBUG -+ -+#define MV_CESA_USE_TIMER_ID 0 -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 50 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else /* CESA_OCF_TRACE_DEBUG */ -+ -+#define cesaTestTraceAdd(x) -+ -+#endif /* CESA_OCF_TRACE_DEBUG */ -+ -+unsigned int -+get_usec(unsigned int start) -+{ -+ if(start) { -+ do_gettimeofday (&tt_start); -+ return 0; -+ } -+ else { -+ do_gettimeofday (&tt_end); -+ tt_end.tv_sec -= tt_start.tv_sec; -+ tt_end.tv_usec -= tt_start.tv_usec; -+ if (tt_end.tv_usec < 0) { -+ tt_end.tv_usec += 1000 * 1000; -+ tt_end.tv_sec -= 1; -+ } -+ } -+ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); -+ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); -+} -+ -+#ifdef RT_DEBUG -+/* -+ * check that the crp action match the current session -+ */ -+static int -+ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { -+ int count = 0; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ struct cryptodesc *crd; -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { -+ if(count > 2) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ /* check that the action is compatible with session */ -+ if(encrypt || decrypt) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ encrypt++; -+ } -+ else { /* decrypt */ -+ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ decrypt++; -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ /* check that the action is compatible with session */ -+ if(auth) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ auth++; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ } -+ return 0; -+ -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; -+ MV_CESA_COMMAND *cesa_cmd; -+ struct cryptodesc *crd; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ int sid = 0, temp_len = 0, i; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ int status; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ unsigned char *ivp; -+ MV_BUF_INFO *p_buf_info; -+ MV_CESA_MBUF *p_mbuf_info; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if( cesaReqResources <= 1 ) { -+ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); -+ return ERESTART; -+ } -+ -+#ifdef RT_DEBUG -+ /* Sanity check */ -+ if (crp == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ sid = crp->crp_sid & 0xffffffff; -+ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { -+ crp->crp_etype = ENOENT; -+ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); -+ return EINVAL; -+ } -+#endif -+ -+ sid = crp->crp_sid & 0xffffffff; -+ crp->crp_etype = 0; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ -+#ifdef RT_DEBUG -+ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ -+ goto p_error; -+ } -+#endif -+ -+ /* malloc a new cesa process */ -+ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); -+ -+ /* init cesa_process */ -+ cesa_ocf_cmd->crp = crp; -+ /* always call callback */ -+ cesa_ocf_cmd->need_cb = 1; -+ -+ /* init cesa_cmd for usage of the HALs */ -+ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; -+ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ -+ -+ /* prepare src buffer */ -+ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ -+ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ -+ /* from skip to crd_len. */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; -+ -+ p_buf_info += 2; /* save 2 first buffers for IV and digest - -+ we won't append them to the end since, they -+ might be places in an unaligned addresses. */ -+ -+ p_mbuf_info->pFrags = p_buf_info; -+ temp_len = 0; -+ -+ /* handle SKB */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ -+ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); -+ skb = (struct sk_buff *) crp->crp_buf; -+ -+ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = skb->len; -+ temp_len = skb->len; -+ /* first skb fragment */ -+ p_buf_info->bufSize = skb_headlen(skb); -+ p_buf_info->bufVirtPtr = skb->data; -+ p_buf_info++; -+ -+ /* now handle all other skb fragments */ -+ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ p_buf_info->bufSize = frag->size; -+ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; -+ p_buf_info++; -+ } -+ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; -+ } -+ /* handle UIO */ -+ else if(crp->crp_flags & CRYPTO_F_IOV) { -+ -+ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); -+ uiop = (struct uio *) crp->crp_buf; -+ -+ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_mbuf_info->numFrags = uiop->uio_iovcnt; -+ for(i = 0; i < uiop->uio_iovcnt; i++) { -+ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; -+ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; -+ temp_len += p_buf_info->bufSize; -+ dprintk("%s,%d: buf %x-> addr %x, size %x \n" -+ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); -+ p_buf_info++; -+ } -+ -+ } -+ /* handle CONTIG */ -+ else { -+ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags = 1; -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_buf_info->bufVirtPtr = crp->crp_buf; -+ p_buf_info->bufSize = crp->crp_ilen; -+ temp_len = crp->crp_ilen; -+ p_buf_info++; -+ } -+ -+ /* Support up to 64K why? cause! */ -+ if(crp->crp_ilen > 64*1024) { -+ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); -+ goto p_error; -+ } -+ -+ if( temp_len != crp->crp_ilen ) { -+ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); -+ } -+ -+ cesa_cmd->pSrc = p_mbuf_info; -+ cesa_cmd->pDst = p_mbuf_info; -+ -+ /* restore p_buf_info to point to first available buf */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_buf_info += 1; -+ -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ -+ dprintk("%s,%d: cipher", __FILE__, __LINE__); -+ -+ cesa_cmd->cryptoOffset = crd->crd_skip; -+ cesa_cmd->cryptoLength = crd->crd_len; -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ dprintk(" encrypt \n"); -+ encrypt++; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ -+ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); -+ cesa_cmd->ivFromUser = 1; -+ ivp = crd->crd_iv; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); -+ cesa_cmd->ivOffset = crd->crd_inject; -+ crypto_copy_bits_back(crp->crp_buf, crd->crd_inject, ivp, cesa_ocf_cur_ses->ivlen); -+ } -+ else { -+ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = ivp; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ } -+ else { /* random IV */ -+ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ /* in this mode the HAL will always copy the IV */ -+ /* given by the session to the ivOffset */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ else { -+ /* if IV isn't copy, then how will the user know which IV did we use??? */ -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ } -+ else { /* decrypt */ -+ dprintk(" decrypt \n"); -+ decrypt++; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); -+ /* append the IV buf to the mbuf */ -+ cesa_cmd->ivFromUser = 1; -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = crd->crd_iv; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ else { -+ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); -+ auth++; -+ cesa_cmd->macOffset = crd->crd_skip; -+ cesa_cmd->macLength = crd->crd_len; -+ -+ /* digest + mac */ -+ cesa_cmd->digestOffset = crd->crd_inject; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ -+ dprintk("\n"); -+ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); -+ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); -+ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); -+ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); -+ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); -+ if(debug) { -+ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); -+ } -+ -+ -+ /* send action to HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ /* action not allowed */ -+ if(status == MV_NOT_ALLOWED) { -+#ifdef CESA_OCF_SPLIT -+ /* if both encrypt and auth try to split */ -+ if(auth && (encrypt || decrypt)) { -+ MV_CESA_COMMAND *cesa_cmd_wa; -+ -+ /* malloc a new cesa process and init it */ -+ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd_wa == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); -+ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; -+ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; -+ cesa_ocf_cmd_wa->need_cb = 0; -+ -+ /* break requests to two operation, first operation completion won't call callback */ -+ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ } -+ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ } -+ else { -+ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ -+ /* send the 2 actions to the HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd_wa); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ } -+ /* action not allowed and can't split */ -+ else -+#endif -+ { -+ goto p_error; -+ } -+ } -+ -+ /* Hal Q is full, send again. This should never happen */ -+ if(status == MV_NO_RESOURCE) { -+ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return ERESTART; -+ } -+ else if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ -+ -+#ifdef CESA_OCF_POLLING -+ cesa_interrupt_polling(); -+#endif -+ cesaTestTraceAdd(5); -+ -+ return 0; -+p_error: -+ crp->crp_etype = EINVAL; -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return EINVAL; -+} -+ -+/* -+ * cesa callback. -+ */ -+static void -+cesa_callback(unsigned long dummy) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cryptop *crp = NULL; -+ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; -+ int res_idx = 0,i; -+ MV_STATUS status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CESA_OCF_TASKLET -+ disable_irq(cesa_device.irq); -+#endif -+ while(MV_TRUE) { -+ -+ /* Get Ready requests */ -+ spin_lock(&cesa_lock); -+ status = mvCesaReadyGet(&result[res_idx]); -+ spin_unlock(&cesa_lock); -+ -+ cesaTestTraceAdd(2); -+ -+ if(status != MV_OK) { -+#ifdef CESA_OCF_POLLING -+ if(status == MV_BUSY) { /* Fragment */ -+ cesa_interrupt_polling(); -+ return; -+ } -+#endif -+ break; -+ } -+ res_idx++; -+ break; -+ } -+ -+ for(i = 0; i < res_idx; i++) { -+ -+ if(!result[i].pReqPrv) { -+ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); -+ break; -+ } -+ -+ cesa_ocf_cmd = result[i].pReqPrv; -+ crp = cesa_ocf_cmd->crp; -+ -+ // ignore HMAC error. -+ //if(result->retCode) -+ // crp->crp_etype = EIO; -+ -+#if defined(CESA_OCF_POLLING) -+ if(!cesa_ocf_cmd->need_cb){ -+ cesa_interrupt_polling(); -+ } -+#endif -+ if(cesa_ocf_cmd->need_cb) { -+ if(debug) { -+ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); -+ } -+ crypto_done(crp); -+ } -+ kfree(cesa_ocf_cmd); -+ } -+#ifdef CESA_OCF_TASKLET -+ enable_irq(cesa_device.irq); -+#endif -+ -+ cesaTestTraceAdd(3); -+ -+ return; -+} -+ -+#ifdef CESA_OCF_POLLING -+static void -+cesa_interrupt_polling(void) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Read cause register */ -+ do { -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; -+ -+ } while (cause == 0); -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesa_callback(0); -+ -+ return; -+} -+ -+#endif -+ -+/* -+ * cesa Interrupt polling routine. -+ */ -+static irqreturn_t -+cesa_interrupt_handler(int irq, void *arg) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cesaTestTraceAdd(0); -+ -+ /* Read cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ /* Empty interrupt */ -+ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); -+ return IRQ_HANDLED; -+ } -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesaTestTraceAdd(1); -+#ifdef CESA_OCF_TASKLET -+ tasklet_hi_schedule(&cesa_ocf_tasklet); -+#else -+ cesa_callback(0); -+#endif -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Open a session. -+ */ -+static int -+/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ -+cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ u32 status = 0, i; -+ u32 count = 0, auth = 0, encrypt =0; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ MV_CESA_OPEN_SESSION cesa_session; -+ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; -+ -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* leave first empty like in other implementations */ -+ for (i = 1; i < CESA_OCF_MAX_SES; i++) { -+ if (cesa_ocf_sessions[i] == NULL) -+ break; -+ } -+ -+ if(i >= CESA_OCF_MAX_SES) { -+ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); -+ if (cesa_ocf_sessions[i] == NULL) { -+ cesa_ocf_freesession(NULL, i); -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); -+ -+ *sid = i; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; -+ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); -+ cesa_ocf_cur_ses->sid_encrypt = -1; -+ cesa_ocf_cur_ses->sid_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_encrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_auth = -1; -+ -+ /* init the session */ -+ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); -+ count = 1; -+ while (cri) { -+ if(count > 2) { -+ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); -+ goto error; -+ } -+ switch (cri->cri_alg) { -+ case CRYPTO_AES_CBC: -+ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_3DES_CBC: -+ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_DES_CBC: -+ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ default: -+ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); -+ goto error; -+ } -+ cri = cri->cri_next; -+ count++; -+ } -+ -+ if((encrypt > 2) || (auth > 2)) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ /* create new sessions in HAL */ -+ if(encrypt) { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ /* encrypt session */ -+ if(auth == 1) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ else if(auth == 2) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ cesa_ocf_cur_ses->encrypt_tn_auth = 1; -+ } -+ else { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ } -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* decrypt session */ -+ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ } -+ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ /* preapre one action sessions for case we will need to split an action */ -+#ifdef CESA_OCF_SPLIT -+ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || -+ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { -+ /* open one session for encode and one for decode */ -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* open one session for auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+#endif -+ } -+ else { /* only auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ cesa_ocf_freesession(NULL, *sid); -+ return EINVAL; -+ -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+cesa_ocf_freesession(device_t dev, u_int64_t tid) -+{ -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ //unsigned long flags; -+ -+ dprintk("%s() %d \n", __FUNCTION__, sid); -+ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { -+ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ /* release session from HAL */ -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ if (cesa_ocf_cur_ses->sid_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); -+ } -+ if (cesa_ocf_cur_ses->sid_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); -+ } -+ -+ kfree(cesa_ocf_cur_ses); -+ cesa_ocf_sessions[sid] = NULL; -+ -+ return 0; -+} -+ -+ -+/* TDMA Window setup */ -+ -+static void __init -+setup_tdma_mbus_windows(struct cesa_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ writel(0, dev->reg + WINDOW_BASE(i)); -+ writel(0, dev->reg + WINDOW_CTRL(i)); -+ } -+ -+ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; -+ writel( -+ ((cs->size - 1) & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, -+ dev->reg + WINDOW_CTRL(i) -+ ); -+ writel(cs->base, dev->reg + WINDOW_BASE(i)); -+ } -+} -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+static int -+mv_cesa_ocf_init(struct platform_device *pdev) -+{ -+#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) -+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) -+ { -+ dprintk("CESA is not mapped to this CPU\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ dprintk("%s\n", __FUNCTION__); -+ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); -+ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); -+ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); -+ -+ if (cesa_ocf_id < 0) -+ panic("MV CESA crypto device cannot initialize!"); -+ -+ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); -+ -+ /* CESA unit is auto power on off */ -+#if 0 -+ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) -+ { -+ printk("\nWarning CESA %d is Powered Off\n",0); -+ return EINVAL; -+ } -+#endif -+ -+ memset(&cesa_device, 0, sizeof(struct cesa_dev)); -+ /* Get the IRQ, and crypto memory regions */ -+ { -+ struct resource *res; -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); -+ -+ if (!res) -+ return -ENXIO; -+ -+ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ -+ if (!res) { -+ iounmap(cesa_device.sram); -+ return -ENXIO; -+ } -+ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); -+ cesa_device.irq = platform_get_irq(pdev, 0); -+ cesa_device.plat_data = pdev->dev.platform_data; -+ setup_tdma_mbus_windows(&cesa_device); -+ -+ } -+ -+ -+ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, -+ NULL) ) { -+ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* clear and unmask Int */ -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+#ifndef CESA_OCF_POLLING -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+#ifdef CESA_OCF_TASKLET -+ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); -+#endif -+ /* register interrupt */ -+ if( request_irq( cesa_device.irq, cesa_interrupt_handler, -+ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { -+ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); -+ return EINVAL; -+ } -+ -+ -+ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); -+ -+#define REGISTER(alg) \ -+ crypto_register(cesa_ocf_id, alg, 0,0) -+ REGISTER(CRYPTO_AES_CBC); -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+mv_cesa_ocf_exit(struct platform_device *pdev) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ crypto_unregister_all(cesa_ocf_id); -+ cesa_ocf_id = -1; -+ iounmap(cesa_device.reg); -+ iounmap(cesa_device.sram); -+ free_irq(cesa_device.irq, NULL); -+ -+ /* mask and clear Int */ -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ -+ -+ if( MV_OK != mvCesaFinish() ) { -+ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); -+ return; -+ } -+} -+ -+ -+void cesa_ocf_debug(void) -+{ -+ -+#ifdef CESA_OCF_TRACE_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); -+ for(i=0; i= _1G) -+ { -+ mvOsOutput("%3dGB ", size / _1G); -+ size %= _1G; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1M ) -+ { -+ mvOsOutput("%3dMB ", size / _1M); -+ size %= _1M; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1K) -+ { -+ mvOsOutput("%3dKB ", size / _1K); -+ size %= _1K; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size > 0) -+ { -+ mvOsOutput("%3dB ", size); -+ } -+} -+ -+/******************************************************************************* -+* mvHexToBin - Convert hex to binary -+* -+* DESCRIPTION: -+* This function Convert hex to binary. -+* -+* INPUT: -+* pHexStr - hex buffer pointer. -+* size - Size to convert. -+* -+* OUTPUT: -+* pBin - Binary buffer pointer. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) -+{ -+ int j, i; -+ char tmp[3]; -+ MV_U8 byte; -+ -+ for(j=0, i=0; j> 1; -+ result++; -+ } -+ return result; -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvCommon.h b/crypto/ocf/kirkwood/mvHal/common/mvCommon.h -new file mode 100644 -index 0000000..5caf47c ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvCommon.h -@@ -0,0 +1,308 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvCommonh -+#define __INCmvCommonh -+ -+#include "mvTypes.h" -+ -+/* Swap tool */ -+ -+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ -+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4)) -+ -+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ -+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4) | \ -+ ((X&0xf0000) << 4) | \ -+ ((X&0xf00000) >> 4) | \ -+ ((X&0xf000000) << 4) | \ -+ ((X&0xf0000000) >> 4)) -+ -+/* 16bit byte swap. For example 0x1122 -> 0x2211 */ -+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) -+ -+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ -+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ -+ (((X)&0xff00)<<8) | \ -+ (((X)&0xff0000)>>8) | \ -+ (((X)&0xff000000)>>24)) -+ -+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ -+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ -+ (((X)&0xff00ULL)<<40) | \ -+ (((X)&0xff0000ULL)<<24) | \ -+ (((X)&0xff000000ULL)<<8) | \ -+ (((X)&0xff00000000ULL)>>8) | \ -+ (((X)&0xff0000000000ULL)>>24) | \ -+ (((X)&0xff000000000000ULL)>>40) | \ -+ (((X)&0xff00000000000000ULL)>>56))) -+ -+/* Endianess macros. */ -+#if defined(MV_CPU_LE) -+ #define MV_16BIT_LE(X) (X) -+ #define MV_32BIT_LE(X) (X) -+ #define MV_64BIT_LE(X) (X) -+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) -+#elif defined(MV_CPU_BE) -+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) -+ #define MV_16BIT_BE(X) (X) -+ #define MV_32BIT_BE(X) (X) -+ #define MV_64BIT_BE(X) (X) -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ -+/* Bit field definitions */ -+#define NO_BIT 0x00000000 -+#define BIT0 0x00000001 -+#define BIT1 0x00000002 -+#define BIT2 0x00000004 -+#define BIT3 0x00000008 -+#define BIT4 0x00000010 -+#define BIT5 0x00000020 -+#define BIT6 0x00000040 -+#define BIT7 0x00000080 -+#define BIT8 0x00000100 -+#define BIT9 0x00000200 -+#define BIT10 0x00000400 -+#define BIT11 0x00000800 -+#define BIT12 0x00001000 -+#define BIT13 0x00002000 -+#define BIT14 0x00004000 -+#define BIT15 0x00008000 -+#define BIT16 0x00010000 -+#define BIT17 0x00020000 -+#define BIT18 0x00040000 -+#define BIT19 0x00080000 -+#define BIT20 0x00100000 -+#define BIT21 0x00200000 -+#define BIT22 0x00400000 -+#define BIT23 0x00800000 -+#define BIT24 0x01000000 -+#define BIT25 0x02000000 -+#define BIT26 0x04000000 -+#define BIT27 0x08000000 -+#define BIT28 0x10000000 -+#define BIT29 0x20000000 -+#define BIT30 0x40000000 -+#define BIT31 0x80000000 -+ -+/* Handy sizes */ -+#define _1K 0x00000400 -+#define _2K 0x00000800 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/* Tclock and Sys clock define */ -+#define _100MHz 100000000 -+#define _125MHz 125000000 -+#define _133MHz 133333334 -+#define _150MHz 150000000 -+#define _160MHz 160000000 -+#define _166MHz 166666667 -+#define _175MHz 175000000 -+#define _178MHz 178000000 -+#define _183MHz 183333334 -+#define _187MHz 187000000 -+#define _192MHz 192000000 -+#define _194MHz 194000000 -+#define _200MHz 200000000 -+#define _233MHz 233333334 -+#define _250MHz 250000000 -+#define _266MHz 266666667 -+#define _300MHz 300000000 -+ -+/* For better address window table readability */ -+#define EN MV_TRUE -+#define DIS MV_FALSE -+#define N_A -1 /* Not applicable */ -+ -+/* Cache configuration options for memory (DRAM, SRAM, ... ) */ -+ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+ -+/* Macro for testing aligment. Positive if number is NOT aligned */ -+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) -+ -+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ -+#define MV_ALIGN_UP(number, align) \ -+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) -+ -+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ -+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) -+ -+/* This macro returns absolute value */ -+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) -+ -+ -+/* Bit fields manipulation macros */ -+ -+/* An integer word which its 'x' bit is set */ -+#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) -+ -+/* Checks wheter bit 'x' in integer word is set */ -+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) -+ -+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ -+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) -+ -+/* Set bit 'x' in integer word (RMW) */ -+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) -+ -+/* Invert bit 'x' in integer word (RMW) */ -+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) -+ -+/* Get the min between 'a' or 'b' */ -+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) -+ -+/* Get the max between 'a' or 'b' */ -+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) -+ -+/* Temporary */ -+#define mvOsDivide(num, div) \ -+({ \ -+ int i=0, rem=(num); \ -+ \ -+ while(rem >= (div)) \ -+ { \ -+ rem -= (div); \ -+ i++; \ -+ } \ -+ (i); \ -+}) -+ -+/* Temporary */ -+#define mvOsReminder(num, div) \ -+({ \ -+ int rem = (num); \ -+ \ -+ while(rem >= (div)) \ -+ rem -= (div); \ -+ (rem); \ -+}) -+ -+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) -+ -+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) -+ -+#ifndef MV_ASMLANGUAGE -+/* mvCommon API list */ -+ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); -+void mvAsciiToHex(const char* asciiStr, char* hexStr); -+void mvBinToHex(const MV_U8* bin, char* hexStr, int size); -+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); -+ -+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); -+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); -+void mvSizePrint(MV_U32); -+ -+MV_U32 mvLog2(MV_U32 num); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCommonh */ -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvDebug.c b/crypto/ocf/kirkwood/mvHal/common/mvDebug.c -new file mode 100644 -index 0000000..d98a9e4 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvDebug.c -@@ -0,0 +1,326 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mv802_3.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros -+ * mvDebug - map of bits (one for each module) bit=1 means enable -+ * debug code and messages for this module -+ * mvModuleDebug - array of 32 bits varables one for each module -+ */ -+MV_U32 mvDebug = 0; -+MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+/* Init mvModuleDebug array to default values */ -+void mvDebugInit(void) -+{ -+ int bit; -+ -+ mvDebug = 0; -+ for(bit=0; bit 0) -+ { -+ mvOsPrintf("%08x: ", memAddr); -+ i = 0; -+ /* 32 bytes in the line */ -+ while(i < 32) -+ { -+ if(memAddr >= (MV_U32)addr) -+ { -+ switch(access) -+ { -+ case 1: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); -+ } -+ break; -+ -+ case 2: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); -+ } -+ break; -+ -+ case 4: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); -+ } -+ break; -+ } -+ } -+ else -+ { -+ for(j=0; j<(access*2+1); j++) -+ mvOsPrintf(" "); -+ } -+ i += access; -+ memAddr += access; -+ size -= access; -+ if(size <= 0) -+ break; -+ } -+ mvOsPrintf("\n"); -+ } -+} -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) -+{ -+ if(pBufInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pBufInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", -+ (unsigned int)pBufInfo, -+ (unsigned int)pBufInfo->cmdSts, -+ (unsigned int)pBufInfo->pBuff, -+ (unsigned int)pBufInfo->bufSize); -+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", -+ (unsigned int)pBufInfo->pData, -+ (unsigned int)pBufInfo->byteCnt, -+ (unsigned int)pBufInfo->pNextBufInfo, -+ (unsigned int)pBufInfo->userInfo1, -+ (unsigned int)pBufInfo->userInfo2); -+ if(pBufInfo->pData != NULL) -+ { -+ if(size > pBufInfo->byteCnt) -+ size = pBufInfo->byteCnt; -+ mvDebugMemDump(pBufInfo->pData, size, access); -+ } -+} -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) -+{ -+ int frag, len; -+ -+ if(pPktInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pPktInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", -+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, -+ pPktInfo->pFrags, pPktInfo->osInfo); -+ -+ for(frag=0; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pPktInfo->pFrags[frag].bufVirtPtr, -+ pPktInfo->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); -+ size -= len; -+ } -+ } -+ -+} -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr) -+{ -+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); -+} -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr) -+{ -+ int i; -+ -+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); -+ for(i=1; ibegin = 0; -+ pTimeEntry->count = count; -+ pTimeEntry->end = 0; -+ pTimeEntry->left = pTimeEntry->count; -+ pTimeEntry->total = 0; -+ pTimeEntry->min = 0xFFFFFFFF; -+ pTimeEntry->max = 0x0; -+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); -+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; -+} -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) -+{ -+ int num; -+ -+ if(isTitle == MV_TRUE) -+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); -+ -+ num = pTimeEntry->count-pTimeEntry->left; -+ if(num > 0) -+ { -+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", -+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, -+ pTimeEntry->min, pTimeEntry->max); -+ } -+} -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) -+{ -+ MV_U32 delta; -+ -+ if(pTimeEntry->left > 0) -+ { -+ if(pTimeEntry->end <= pTimeEntry->begin) -+ { -+ delta = pTimeEntry->begin - pTimeEntry->end; -+ } -+ else -+ { -+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; -+ } -+ pTimeEntry->total += delta; -+ -+ if(delta < pTimeEntry->min) -+ pTimeEntry->min = delta; -+ -+ if(delta > pTimeEntry->max) -+ pTimeEntry->max = delta; -+ -+ pTimeEntry->left--; -+ } -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvDebug.h b/crypto/ocf/kirkwood/mvHal/common/mvDebug.h -new file mode 100644 -index 0000000..ed07a1f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvDebug.h -@@ -0,0 +1,178 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvDebugh -+#define __INCmvDebugh -+ -+/* includes */ -+#include "mvTypes.h" -+ -+typedef enum -+{ -+ MV_MODULE_INVALID = -1, -+ MV_MODULE_ETH = 0, -+ MV_MODULE_IDMA, -+ MV_MODULE_XOR, -+ MV_MODULE_TWASI, -+ MV_MODULE_MGI, -+ MV_MODULE_USB, -+ MV_MODULE_CESA, -+ -+ MV_MODULE_MAX -+}MV_MODULE_ID; -+ -+/* Define generic flags useful for most of modules */ -+#define MV_DEBUG_FLAG_ALL (0) -+#define MV_DEBUG_FLAG_INIT (1 << 0) -+#define MV_DEBUG_FLAG_RX (1 << 1) -+#define MV_DEBUG_FLAG_TX (1 << 2) -+#define MV_DEBUG_FLAG_ERR (1 << 3) -+#define MV_DEBUG_FLAG_TRACE (1 << 4) -+#define MV_DEBUG_FLAG_DUMP (1 << 5) -+#define MV_DEBUG_FLAG_CACHE (1 << 6) -+#define MV_DEBUG_FLAG_IOCTL (1 << 7) -+#define MV_DEBUG_FLAG_STATS (1 << 8) -+ -+extern MV_U32 mvDebug; -+extern MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+#ifdef MV_DEBUG -+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) code -+#elif defined(MV_RT_DEBUG) -+# define MV_DEBUG_PRINT(module, flags, msg) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ code -+#else -+# define MV_DEBUG_PRINT(module, flags, msg) -+# define MV_DEBUG_CODE(module, flags, code) -+#endif -+ -+ -+ -+/* typedefs */ -+ -+/* time measurement structure used to check how much time pass between -+ * two points -+ */ -+typedef struct { -+ char name[20]; /* name of the entry */ -+ unsigned long begin; /* time measured on begin point */ -+ unsigned long end; /* time measured on end point */ -+ unsigned long total; /* Accumulated time */ -+ unsigned long left; /* The rest measurement actions */ -+ unsigned long count; /* Maximum measurement actions */ -+ unsigned long min; /* Minimum time from begin to end */ -+ unsigned long max; /* Maximum time from begin to end */ -+} MV_DEBUG_TIMES; -+ -+ -+/* mvDebug.h API list */ -+ -+/****** Error Recording ******/ -+ -+/* Dump memory in specific format: -+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 -+ */ -+void mvDebugMemDump(void* addr, int size, int access); -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr); -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr); -+ -+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ -+ -+/* Reset MV_DEBUG_TIMES entry */ -+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); -+ -+ -+/******** General ***********/ -+ -+/* Change value of mvDebugPrint global variable */ -+ -+void mvDebugInit(void); -+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); -+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); -+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); -+ -+ -+#endif /* __INCmvDebug.h */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h b/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h -new file mode 100644 -index 0000000..2e0c04f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h -@@ -0,0 +1,225 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceIdh -+#define __INCmvDeviceIdh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MARVELL_VEN_ID 0x11ab -+ -+/* Disco-3 */ -+#define MV64460_DEV_ID 0x6480 -+#define MV64460B_DEV_ID 0x6485 -+#define MV64430_DEV_ID 0x6420 -+ -+/* Disco-5 */ -+#define MV64560_DEV_ID 0x6450 -+ -+/* Disco-6 */ -+#define MV64660_DEV_ID 0x6460 -+ -+/* Orion */ -+#define MV_1181_DEV_ID 0x1181 -+#define MV_5181_DEV_ID 0x5181 -+#define MV_5281_DEV_ID 0x5281 -+#define MV_5182_DEV_ID 0x5182 -+#define MV_8660_DEV_ID 0x8660 -+#define MV_5180_DEV_ID 0x5180 -+#define MV_5082_DEV_ID 0x5082 -+#define MV_1281_DEV_ID 0x1281 -+#define MV_6082_DEV_ID 0x6082 -+#define MV_6183_DEV_ID 0x6183 -+#define MV_6183L_DEV_ID 0x6083 -+ -+#define MV_5281_D0_REV 0x4 -+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) -+#define MV_5281_D0_NAME "88F5281 D0" -+ -+#define MV_5281_D1_REV 0x5 -+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) -+#define MV_5281_D1_NAME "88F5281 D1" -+ -+#define MV_5281_D2_REV 0x6 -+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) -+#define MV_5281_D2_NAME "88F5281 D2" -+ -+ -+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ -+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ -+#define MV_5181_B0_REV 0x2 -+#define MV_5181_B1_REV 0x3 -+#define MV_5182_A1_REV 0x1 -+#define MV_5180N_B1_REV 0x3 -+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) -+ -+ -+ -+/* kw */ -+#define MV_6281_DEV_ID 0x6281 -+#define MV_6192_DEV_ID 0x6192 -+#define MV_6190_DEV_ID 0x6190 -+#define MV_6180_DEV_ID 0x6180 -+ -+#define MV_6281_A0_REV 0x2 -+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) -+#define MV_6281_A0_NAME "88F6281 A0" -+ -+#define MV_6192_A0_REV 0x2 -+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) -+#define MV_6192_A0_NAME "88F6192 A0" -+ -+#define MV_6190_A0_REV 0x2 -+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) -+#define MV_6190_A0_NAME "88F6190 A0" -+ -+#define MV_6180_A0_REV 0x2 -+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) -+#define MV_6180_A0_NAME "88F6180 A0" -+ -+#define MV_6281_A1_REV 0x3 -+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) -+#define MV_6281_A1_NAME "88F6281 A1" -+ -+#define MV_6192_A1_REV 0x3 -+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) -+#define MV_6192_A1_NAME "88F6192 A1" -+ -+#define MV_6190_A1_REV 0x3 -+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) -+#define MV_6190_A1_NAME "88F6190 A1" -+ -+#define MV_6180_A1_REV 0x3 -+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) -+#define MV_6180_A1_NAME "88F6180 A1" -+ -+#define MV_88F6XXX_A0_REV 0x2 -+#define MV_88F6XXX_A1_REV 0x3 -+/* Disco-Duo */ -+#define MV_78XX0_ZY_DEV_ID 0x6381 -+#define MV_78XX0_ZY_NAME "MV78X00" -+ -+#define MV_78XX0_Z0_REV 0x1 -+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) -+#define MV_78XX0_Z0_NAME "78X00 Z0" -+ -+#define MV_78XX0_Y0_REV 0x2 -+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) -+#define MV_78XX0_Y0_NAME "78X00 Y0" -+ -+#define MV_78XX0_DEV_ID 0x7800 -+#define MV_78XX0_NAME "MV78X00" -+ -+#define MV_76100_DEV_ID 0x7610 -+#define MV_78200_DEV_ID 0x7820 -+#define MV_78100_DEV_ID 0x7810 -+#define MV_78XX0_A0_REV 0x1 -+#define MV_78XX0_A1_REV 0x2 -+ -+#define MV_76100_NAME "MV76100" -+#define MV_78100_NAME "MV78100" -+#define MV_78200_NAME "MV78200" -+ -+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) -+ -+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) -+ -+#define MV_76100_A0_NAME "MV76100 A0" -+#define MV_78100_A0_NAME "MV78100 A0" -+#define MV_78200_A0_NAME "MV78200 A0" -+#define MV_78XX0_A0_NAME "MV78XX0 A0" -+ -+#define MV_76100_A1_NAME "MV76100 A1" -+#define MV_78100_A1_NAME "MV78100 A1" -+#define MV_78200_A1_NAME "MV78200 A1" -+#define MV_78XX0_A1_NAME "MV78XX0 A1" -+ -+/*MV88F632X family*/ -+#define MV_6321_DEV_ID 0x6321 -+#define MV_6322_DEV_ID 0x6322 -+#define MV_6323_DEV_ID 0x6323 -+ -+#define MV_6321_NAME "88F6321" -+#define MV_6322_NAME "88F6322" -+#define MV_6323_NAME "88F6323" -+ -+#define MV_632X_A1_REV 0x2 -+ -+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) -+ -+#define MV_6321_A1_NAME "88F6321 A1" -+#define MV_6322_A1_NAME "88F6322 A1" -+#define MV_6323_A1_NAME "88F6323 A1" -+ -+ -+#endif /* __INCmvDeviceIdh */ -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h b/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h -new file mode 100644 -index 0000000..1849198 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h -@@ -0,0 +1,73 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvHalVerh -+#define __INCmvHalVerh -+ -+/* Defines */ -+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" -+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" -+ -+#endif /* __INCmvHalVerh */ -\ No newline at end of file -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvStack.c b/crypto/ocf/kirkwood/mvHal/common/mvStack.c -new file mode 100644 -index 0000000..7ba48ea ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvStack.c -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvQueue.c -+* -+* FILENAME: $Workfile: mvStack.c $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file implements simple Stack LIFO functionality. -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mvTypes.h" -+#include "mvDebug.h" -+#include "mvStack.h" -+ -+/* defines */ -+ -+ -+/* Public functions */ -+ -+ -+/* Purpose: Create new stack -+ * Inputs: -+ * - MV_U32 noOfElements - maximum number of elements in the stack. -+ * Each element 4 bytes size -+ * Return: void* - pointer to created stack. -+ */ -+void* mvStackCreate(int numOfElements) -+{ -+ MV_STACK* pStack; -+ MV_U32* pStackElements; -+ -+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); -+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); -+ if( (pStack == NULL) || (pStackElements == NULL) ) -+ { -+ mvOsPrintf("mvStack: Can't create new stack\n"); -+ return NULL; -+ } -+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); -+ pStack->numOfElements = numOfElements; -+ pStack->stackIdx = 0; -+ pStack->stackElements = pStackElements; -+ -+ return pStack; -+} -+ -+/* Purpose: Delete existing stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function -+ * -+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. -+ * MV_OK - Success. -+ */ -+MV_STATUS mvStackDelete(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if( (pStack == NULL) || (pStack->stackElements == NULL) ) -+ return MV_NOT_FOUND; -+ -+ mvOsFree(pStack->stackElements); -+ mvOsFree(pStack); -+ -+ return MV_OK; -+} -+ -+ -+/* PrintOut status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) -+{ -+ int i; -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", -+ stackHndl, pStack->stackElements, pStack->numOfElements, -+ pStack->stackIdx); -+ if(isPrintElements == MV_TRUE) -+ { -+ for(i=0; istackIdx; i++) -+ { -+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); -+ } -+ } -+} -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvStack.h b/crypto/ocf/kirkwood/mvHal/common/mvStack.h -new file mode 100644 -index 0000000..7e33d91 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvStack.h -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvStack.h - Header File for : -+* -+* FILENAME: $Workfile: mvStack.h $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file defines simple Stack (LIFO) functionality. -+* -+*******************************************************************************/ -+ -+#ifndef __mvStack_h__ -+#define __mvStack_h__ -+ -+ -+/* includes */ -+#include "mvTypes.h" -+ -+ -+/* defines */ -+ -+ -+/* typedefs */ -+/* Data structure describes general purpose Stack */ -+typedef struct -+{ -+ int stackIdx; -+ int numOfElements; -+ MV_U32* stackElements; -+} MV_STACK; -+ -+static INLINE MV_BOOL mvStackIsFull(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == pStack->numOfElements) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/* Purpose: Push new element to stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - New element. -+ * -+ * Return: MV_STATUS MV_FULL - Failure. Stack is full. -+ * MV_OK - Success. Element is put to stack. -+ */ -+static INLINE void mvStackPush(void* stackHndl, MV_U32 value) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == pStack->numOfElements) -+ { -+ mvOsPrintf("mvStackPush: Stack is FULL\n"); -+ return; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackElements[pStack->stackIdx] = value; -+ pStack->stackIdx++; -+} -+ -+/* Purpose: Pop element from the top of stack and copy it to "pValue" -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - Element in the top of stack. -+ * -+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. -+ * MV_OK - Success. Element is removed from the stack and -+ * copied to pValue argument -+ */ -+static INLINE MV_U32 mvStackPop(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == 0) -+ { -+ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); -+ return 0; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackIdx--; -+ return pStack->stackElements[pStack->stackIdx]; -+} -+ -+static INLINE int mvStackIndex(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return pStack->stackIdx; -+} -+ -+static INLINE int mvStackFreeElements(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return (pStack->numOfElements - pStack->stackIdx); -+} -+ -+/* mvStack.h API list */ -+ -+/* Create new Stack */ -+void* mvStackCreate(int numOfElements); -+ -+/* Delete existing stack */ -+MV_STATUS mvStackDelete(void* stackHndl); -+ -+/* Print status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); -+ -+#endif /* __mvStack_h__ */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/common/mvTypes.h b/crypto/ocf/kirkwood/mvHal/common/mvTypes.h -new file mode 100644 -index 0000000..1538a24 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/common/mvTypes.h -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvTypesh -+#define __INCmvTypesh -+ -+/* Defines */ -+ -+/* The following is a list of Marvell status */ -+#define MV_ERROR (-1) -+#define MV_OK (0x00) /* Operation succeeded */ -+#define MV_FAIL (0x01) /* Operation failed */ -+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ -+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ -+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ -+#define MV_BAD_PTR (0x05) /* Illegal pointer value */ -+#define MV_BAD_SIZE (0x06) /* Illegal size */ -+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ -+#define MV_SET_ERROR (0x08) /* Set operation failed */ -+#define MV_GET_ERROR (0x09) /* Get operation failed */ -+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ -+#define MV_NOT_FOUND (0x0B) /* Item not found */ -+#define MV_NO_MORE (0x0C) /* No more items found */ -+#define MV_NO_SUCH (0x0D) /* No such item */ -+#define MV_TIMEOUT (0x0E) /* Time Out */ -+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ -+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ -+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ -+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ -+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ -+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ -+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ -+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ -+#define MV_HW_ERROR (0x17) /* Hardware error */ -+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ -+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ -+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ -+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ -+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ -+#define MV_NOT_STARTED (0x1D) /* Not started yet */ -+#define MV_BUSY (0x1E) /* Item is busy. */ -+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ -+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ -+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ -+#define MV_WRITE_PROTECT (0x22) /* Write protected */ -+ -+ -+#define MV_INVALID (int)(-1) -+ -+#define MV_FALSE 0 -+#define MV_TRUE (!(MV_FALSE)) -+ -+ -+#ifndef NULL -+#define NULL ((void*)0) -+#endif -+ -+ -+#ifndef MV_ASMLANGUAGE -+/* typedefs */ -+ -+typedef char MV_8; -+typedef unsigned char MV_U8; -+ -+typedef int MV_32; -+typedef unsigned int MV_U32; -+ -+typedef short MV_16; -+typedef unsigned short MV_U16; -+ -+#ifdef MV_PPC64 -+typedef long MV_64; -+typedef unsigned long MV_U64; -+#else -+typedef long long MV_64; -+typedef unsigned long long MV_U64; -+#endif -+ -+typedef long MV_LONG; /* 32/64 */ -+typedef unsigned long MV_ULONG; /* 32/64 */ -+ -+typedef int MV_STATUS; -+typedef int MV_BOOL; -+typedef void MV_VOID; -+typedef float MV_FLOAT; -+ -+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ -+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ -+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ -+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ -+ -+typedef MV_U32 MV_KHZ; -+typedef MV_U32 MV_MHZ; -+typedef MV_U32 MV_HZ; -+ -+ -+/* This enumerator describes the set of commands that can be applied on */ -+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ -+/* status (see MV_STATE enumerator) */ -+/* Start can be applied only when status is IDLE */ -+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ -+/* Pause can be applied only when status is ACTIVE */ -+/* Restart can be applied only when status is PAUSED */ -+typedef enum _mvCommand -+{ -+ MV_START, /* Start */ -+ MV_STOP, /* Stop */ -+ MV_PAUSE, /* Pause */ -+ MV_RESTART /* Restart */ -+} MV_COMMAND; -+ -+/* This enumerator describes the set of state conditions. */ -+/* Moving from one state to other is stricted. */ -+typedef enum _mvState -+{ -+ MV_IDLE, -+ MV_ACTIVE, -+ MV_PAUSED, -+ MV_UNDEFINED_STATE -+} MV_STATE; -+ -+ -+/* This structure describes address space window. Window base can be */ -+/* 64 bit, window size up to 4GB */ -+typedef struct _mvAddrWin -+{ -+ MV_U32 baseLow; /* 32bit base low */ -+ MV_U32 baseHigh; /* 32bit base high */ -+ MV_U32 size; /* 32bit size */ -+}MV_ADDR_WIN; -+ -+/* This binary enumerator describes protection attribute status */ -+typedef enum _mvProtRight -+{ -+ ALLOWED, /* Protection attribute allowed */ -+ FORBIDDEN /* Protection attribute forbidden */ -+}MV_PROT_RIGHT; -+ -+/* Unified struct for Rx and Tx packet operations. The user is required to */ -+/* be familier only with Tx/Rx descriptor command status. */ -+typedef struct _bufInfo -+{ -+ MV_U32 cmdSts; /* Tx/Rx command status */ -+ MV_U16 byteCnt; /* Size of valid data in the buffer */ -+ MV_U16 bufSize; /* Total size of the buffer */ -+ MV_U8 *pBuff; /* Pointer to Buffer */ -+ MV_U8 *pData; /* Pointer to data in the Buffer */ -+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ -+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ -+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ -+} BUF_INFO; -+ -+/* This structure contains information describing one of buffers -+ * (fragments) they are built Ethernet packet. -+ */ -+typedef struct -+{ -+ MV_U8* bufVirtPtr; -+ MV_ULONG bufPhysAddr; -+ MV_U32 bufSize; -+ MV_U32 dataSize; -+ MV_U32 memHandle; -+ MV_32 bufAddrShift; -+} MV_BUF_INFO; -+ -+/* This structure contains information describing Ethernet packet. -+ * The packet can be divided for few buffers (fragments) -+ */ -+typedef struct -+{ -+ MV_ULONG osInfo; -+ MV_BUF_INFO *pFrags; -+ MV_U32 status; -+ MV_U16 pktSize; -+ MV_U16 numFrags; -+ MV_U32 ownerId; -+ MV_U32 fragIP; -+} MV_PKT_INFO; -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+#endif /* __INCmvTypesh */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/dbg-trace.c b/crypto/ocf/kirkwood/mvHal/dbg-trace.c -new file mode 100644 -index 0000000..6576d35 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/dbg-trace.c -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include "dbg-trace.h" -+ -+#define TRACE_ARR_LEN 800 -+#define STR_LEN 128 -+struct trace { -+ struct timeval tv; -+ char str[STR_LEN]; -+ unsigned int callback_val1; -+ unsigned int callback_val2; -+ char valid; -+}; -+static unsigned int (*trc_callback1) (unsigned char) = NULL; -+static unsigned int (*trc_callback2) (unsigned char) = NULL; -+static unsigned char trc_param1 = 0; -+static unsigned char trc_param2 = 0; -+struct trace *trc_arr; -+static int trc_index; -+static int trc_active = 0; -+ -+void TRC_START() -+{ -+ trc_active = 1; -+} -+ -+void TRC_STOP() -+{ -+ trc_active = 0; -+} -+ -+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) -+{ -+ printk("Marvell debug tracing is on\n"); -+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); -+ if(trc_arr == NULL) -+ { -+ printk("Can't allocate Debug Trace buffer\n"); -+ return; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+ trc_callback1 = callback1; -+ trc_callback2 = callback2; -+ trc_param1 = callback1_param; -+ trc_param2 = callback2_param; -+} -+void TRC_REC(char *fmt,...) -+{ -+ va_list args; -+ struct trace *trc = &trc_arr[trc_index]; -+ -+ if(trc_active == 0) -+ return; -+ -+ do_gettimeofday(&trc->tv); -+ if(trc_callback1) -+ trc->callback_val1 = trc_callback1(trc_param1); -+ if(trc_callback2) -+ trc->callback_val2 = trc_callback2(trc_param2); -+ va_start(args, fmt); -+ vsprintf(trc->str,fmt,args); -+ va_end(args); -+ trc->valid = 1; -+ if((++trc_index) == TRACE_ARR_LEN) { -+ trc_index = 0; -+ } -+} -+void TRC_OUTPUT(void) -+{ -+ int i,j; -+ struct trace *p; -+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); -+ for(i=0,j=trc_index; ivalid) { -+ unsigned long uoffs; -+ struct trace *plast; -+ if(p == &trc_arr[0]) -+ plast = &trc_arr[TRACE_ARR_LEN-1]; -+ else -+ plast = p-1; -+ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) -+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); -+ else -+ uoffs = (1000000 - ((plast)->tv.tv_usec)) + -+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + -+ p->tv.tv_usec; -+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); -+ if(trc_callback1) -+ printk("[%u]",p->callback_val1); -+ if(trc_callback2) -+ printk("[%u]",p->callback_val2); -+ printk(": %s",p->str); -+ } -+ p->valid = 0; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+} -+void TRC_RELEASE(void) -+{ -+ kfree(trc_arr); -+ trc_index = 0; -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/dbg-trace.h b/crypto/ocf/kirkwood/mvHal/dbg-trace.h -new file mode 100644 -index 0000000..e3dd480 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/dbg-trace.h -@@ -0,0 +1,24 @@ -+ -+#ifndef _MV_DBG_TRCE_H_ -+#define _MV_DBG_TRCE_H_ -+ -+#ifdef CONFIG_MV_DBG_TRACE -+void TRC_INIT(void *callback1, void *callback2, -+ unsigned char callback1_param, unsigned char callback2_param); -+void TRC_REC(char *fmt,...); -+void TRC_OUTPUT(void); -+void TRC_RELEASE(void); -+void TRC_START(void); -+void TRC_STOP(void); -+ -+#else -+#define TRC_INIT(x1,x2,x3,x4) -+#define TRC_REC(X...) -+#define TRC_OUTPUT() -+#define TRC_RELEASE() -+#define TRC_START() -+#define TRC_STOP() -+#endif -+ -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c -new file mode 100644 -index 0000000..8a6ba2c ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c -@@ -0,0 +1,2513 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cpu/mvCpu.h" -+#include "cntmr/mvCntmr.h" -+#include "gpp/mvGpp.h" -+#include "twsi/mvTwsi.h" -+#include "pex/mvPex.h" -+#include "device/mvDevice.h" -+#include "eth/gbe/mvEthRegs.h" -+ -+/* defines */ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; -+ -+#define CODE_IN_ROM MV_FALSE -+#define CODE_IN_RAM MV_TRUE -+ -+extern MV_BOARD_INFO* boardInfoTbl[]; -+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] -+ -+/* Locals */ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+MV_U32 tClkRate = -1; -+ -+ -+/******************************************************************************* -+* mvBoardEnvInit - Init board -+* -+* DESCRIPTION: -+* In this function the board environment take care of device bank -+* initialization. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardEnvInit(MV_VOID) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); -+ return; -+ -+ } -+ -+ /* Set GPP Out value */ -+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); -+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); -+ -+ /* set GPP polarity */ -+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); -+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) -+ { -+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; -+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; -+ } /*End of WA*/ -+ -+ /* Set GPP Out Enable*/ -+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); -+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); -+ -+ /* Nand CE */ -+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); -+} -+ -+/******************************************************************************* -+* mvBoardModelGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns 16bit describing board model. -+* Board model is constructed of one byte major and minor numbers in the -+* following manner: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardModelGet(MV_VOID) -+{ -+ return (mvBoardIdGet() >> 16); -+} -+ -+/******************************************************************************* -+* mbBoardRevlGet - Get Board revision -+* -+* DESCRIPTION: -+* This function returns a 32bit describing the board revision. -+* Board revision is constructed of 4bytes. 2bytes describes major number -+* and the other 2bytes describes minor munber. -+* For example for board revision 3.4 the function will return -+* 0x00030004. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardRevGet(MV_VOID) -+{ -+ return (mvBoardIdGet() & 0xFFFF); -+} -+ -+/******************************************************************************* -+* mvBoardNameGet - Get Board name -+* -+* DESCRIPTION: -+* This function returns a string describing the board model and revision. -+* String is extracted from board I2C EEPROM. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvBoardNameGet(char *pNameBuff) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsSPrintf (pNameBuff, "Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInSgmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in SGMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) -+{ -+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; -+ -+ if(ethPortNum >= BOARD_ETH_PORT_NUM) -+ { -+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); -+ return MV_FALSE; -+ } -+ return ethPortSgmiiSupport[ethPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInGmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in GMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInGmii(MV_VOID) -+{ -+ MV_U32 devClassId, devClass = 0; -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_BOARD_MODULE_GMII_ID == devClassId) -+ return MV_TRUE; -+ } -+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* mvBoardPhyAddrGet - Get the phy address -+* -+* DESCRIPTION: -+* This routine returns the Phy address of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing Phy address, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; -+} -+ -+/******************************************************************************* -+* mvBoardMacSpeedGet - Get the Mac speed -+* -+* DESCRIPTION: -+* This routine returns the Mac speed if pre define of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; -+} -+ -+/******************************************************************************* -+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication -+* -+* DESCRIPTION: -+* This routine returns the IRQ number for the link status indication. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the number of the IRQ for the link status indication, -1 if the port -+* number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchPortGet - Get the mapping between the board connector and the -+* Ethernet Switch port -+* -+* DESCRIPTION: -+* This routine returns the matching Switch port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* boardPortNum - logical number of the connector on the board -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the matching Switch port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port -+* -+* DESCRIPTION: -+* This routine returns the Switch CPU port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the Switch CPU port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; -+} -+ -+/******************************************************************************* -+* mvBoardIsSwitchConnected - Get switch connection status -+* DESCRIPTION: -+* This routine returns port's connection status -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 - if ethPortNum is connected to switch, 0 otherwise -+* -+*******************************************************************************/ -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); -+ return MV_ERROR; -+ } -+ -+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) -+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); -+ else -+ return 0; -+} -+/******************************************************************************* -+* mvBoardSmiScanModeGet - Get Switch SMI scan mode -+* -+* DESCRIPTION: -+* This routine returns Switch SMI scan mode. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; -+} -+/******************************************************************************* -+* mvBoardSpecInitGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, -+* otherwise return MV_FALSE. -+* -+* -+*******************************************************************************/ -+ -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) -+{ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvBoardTclkGet - Get the board Tclk (Controller clock) -+* -+* DESCRIPTION: -+* This routine extract the controller core clock. -+* This function uses the controller counters to make identification. -+* Note: In order to avoid interference, make sure task context switch -+* and interrupts will not occure during this function operation -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+MV_U32 mvBoardTclkGet(MV_VOID) -+{ -+ if(mvCtrlModelGet()==MV_6281_DEV_ID) -+ { -+#if defined(TCLK_AUTO_DETECT) -+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; -+ -+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpTClkRate &= MSAR_TCLCK_MASK; -+ -+ switch (tmpTClkRate) -+ { -+ case MSAR_TCLCK_166: -+ return MV_BOARD_TCLK_166MHZ; -+ break; -+ case MSAR_TCLCK_200: -+ return MV_BOARD_TCLK_200MHZ; -+ break; -+ } -+#else -+ return MV_BOARD_TCLK_200MHZ; -+#endif -+ } -+ -+ return MV_BOARD_TCLK_166MHZ; -+ -+} -+/******************************************************************************* -+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU bus clock. -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvBoard6180SysClkGet(MV_VOID) -+{ -+ MV_U32 sysClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; -+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; -+ -+ return sysClkRate; -+ -+} -+ -+MV_U32 mvBoardSysClkGet(MV_VOID) -+{ -+#ifdef SYSCLK_AUTO_DETECT -+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvBoard6180SysClkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); -+ pClkRate = cpuCLK[pClkRate]; -+ -+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; -+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; -+ if(ddrRtio[indexDdrRtio][0] != 0) -+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); -+ else -+ sysClkRate = 0; -+ return sysClkRate; -+#else -+ return MV_BOARD_DEFAULT_SYSCLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number -+* -+* DESCRIPTION: -+* Multi-ported PCI Express bridges that is implemented on the board -+* collapse interrupts across multiple conventional PCI/PCI-X buses. -+* A dual-headed PCI Express bridge would map (or "swizzle") the -+* interrupts per the following table (in accordance with the respective -+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# -+* signals from its two logical PCI/PCI-X bridges, collapse the -+* INTA#-INTD# signals from any internal sources, and convert the -+* signals to in-band PCI Express messages. 10 -+* This function returns the upstream interrupt as it was converted by -+* the bridge, according to board configuration and the following table: -+* PCI dev num -+* Interrupt pin 7, 8, 9 -+* A -> A D C -+* B -> B A D -+* C -> C B A -+* D -> D C B -+* -+* -+* INPUT: -+* devNum - PCI/PCIX device number. -+* intPin - PCI Int pin -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Int pin connected to the Interrupt controller -+* -+*******************************************************************************/ -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) -+{ -+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); -+ -+ if (realIntPin == 0) return 4; -+ else return realIntPin; -+ -+} -+ -+/******************************************************************************* -+* mvBoardDebugLedNumGet - Get number of debug Leds -+* -+* DESCRIPTION: -+* INPUT: -+* boardId -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) -+{ -+ return BOARD_INFO(boardId)->activeLedsNumber; -+} -+ -+/******************************************************************************* -+* mvBoardDebugLeg - Set the board debug Leds -+* -+* DESCRIPTION: turn on/off status leds. -+* Note: assume MPP leds are part of group 0 only. -+* -+* INPUT: -+* hexNum - Number to be displied in hex by Leds. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardDebugLed(MV_U32 hexNum) -+{ -+ MV_U32 val = 0,totalMask, currentBitMask = 1,i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (BOARD_INFO(boardId)->pLedGppPin == NULL) -+ return; -+ -+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; -+ hexNum &= totalMask; -+ totalMask = 0; -+ -+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) -+ { -+ if (hexNum & currentBitMask) -+ { -+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ } -+ -+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ -+ currentBitMask = (currentBitMask << 1); -+ } -+ -+ if (BOARD_INFO(boardId)->ledsPolarity) -+ { -+ mvGppValueSet(0, totalMask, val); -+ } -+ else -+ { -+ mvGppValueSet(0, totalMask, ~val); -+ } -+} -+ -+ -+/******************************************************************************* -+* mvBoarGpioPinGet - mvBoarGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* class - MV_BOARD_GPP_CLASS enum. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) -+{ -+ MV_U32 boardId, i; -+ MV_U32 indexFound = 0; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) -+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { -+ if (indexFound == index) -+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; -+ else -+ indexFound++; -+ -+ } -+ -+ return MV_ERROR; -+} -+ -+ -+/******************************************************************************* -+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardRTCGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); -+} -+ -+ -+/******************************************************************************* -+* mvBoardReset - mvBoardReset -+* -+* DESCRIPTION: -+* Reset the board -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+MV_VOID mvBoardReset(MV_VOID) -+{ -+ MV_32 resetPin; -+ -+ /* Get gpp reset pin if define */ -+ resetPin = mvBoardResetGpioPinGet(); -+ if (resetPin != MV_ERROR) -+ { -+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); -+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); -+ -+ } -+ else -+ { -+ /* No gpp reset pin was found, try to reset ussing -+ system reset out */ -+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); -+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); -+ } -+} -+ -+/******************************************************************************* -+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardResetGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); -+} -+/******************************************************************************* -+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet -+* -+* DESCRIPTION: -+* used for hotswap detection -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); -+} -+ -+ -+/******************************************************************************* -+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins -+* -+* DESCRIPTION: -+* This function returns a 32-bit mask of GPP pins that connected to -+* interrupt generating sources on board. -+* For example if UART channel A is hardwired to GPP pin 8 and -+* UART channel B is hardwired to GPP pin 4 the fuinction will return -+* the value 0x000000110 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* See description. The function return -1 if board is not identified. -+* -+*******************************************************************************/ -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskLow; -+} -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskHigh; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGet - Get board dependent MPP register value -+* -+* DESCRIPTION: -+* MPP settings are derived from board design. -+* MPP group consist of 8 MPPs. An MPP group represent MPP -+* control register. -+* This function retrieves board dependend MPP register value. -+* -+* INPUT: -+* mppGroupNum - MPP group number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit value describing MPP control register value. -+* -+*******************************************************************************/ -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MODULE_ID_CLASS devClassId; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ /* If MPP group can be defined by the module connected to it */ -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_ERROR != devClassId) -+ { -+ switch(devClassId) -+ { -+ case MV_BOARD_MODULE_TDM_ID: -+ case MV_BOARD_MODULE_TDM_5CHAN_ID: -+ mppGroupType = MV_BOARD_TDM; -+ break; -+ case MV_BOARD_MODULE_AUDIO_ID: -+ mppGroupType = MV_BOARD_AUDIO; -+ break; -+ case MV_BOARD_MODULE_RGMII_ID: -+ mppGroupType = MV_BOARD_RGMII; -+ break; -+ case MV_BOARD_MODULE_GMII_ID: -+ mppGroupType = MV_BOARD_GMII; -+ break; -+ case MV_BOARD_MODULE_TS_ID: -+ mppGroupType = MV_BOARD_TS; -+ break; -+ case MV_BOARD_MODULE_MII_ID: -+ mppGroupType = MV_BOARD_MII; -+ break; -+ default: -+ mppGroupType = MV_BOARD_OTHER; -+ break; -+ } -+ } -+ else -+ /* The module bay is empty */ -+ mppGroupType = MV_BOARD_OTHER; -+ -+ /* Update MPP group type */ -+ mvBoardMppGroupTypeSet(devClass, mppGroupType); -+ } -+ -+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) -+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); -+ else -+ { -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) -+ { -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) -+ { -+ /* Assumption that the MDC & MDIO should be 3.3V */ -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ /* Assumption that only ETH1 can be MII when using modules on DB */ -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; -+ else -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeSet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; -+ else -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppMuxSet - Update MPP mux -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppMuxSet(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 0xf; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ case MV_BOARD_AUDIO: -+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ -+ break; -+ case MV_BOARD_TS: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ default: -+ muxVal |= (devClass ? 0xf : 0); -+ break; -+ } -+ } -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 2; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 6; -+ muxVal = 0; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ -+} -+ -+/******************************************************************************* -+* mvBoardTdmMppSet - set MPPs in TDM module -+* -+* DESCRIPTION: -+* -+* INPUT: type of second telephony device -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardTdmMppSet(MV_32 chType) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 1; -+ MV_U8 muxValMask = 1; -+ MV_U8 twsiVal; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ if(mppGroupType == MV_BOARD_TDM) -+ break; -+ } -+ -+ if(devClass == maxMppGrp) -+ return; /* TDM module not found */ -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ muxVal = 0xfe; -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ muxVal = 0xf3; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxVal); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ /* reset the line to 0 */ -+ twsiSlave.offset = 3; -+ muxVal = 0; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) { -+ muxVal = 0x0; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ mvOsDelay(20); -+ -+ /* set the line to 1 */ -+ twsiSlave.offset = 3; -+ muxVal = 1; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ if(chType) /* FXS - issue reset properly */ -+ { -+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ mvOsDelay(50); -+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ } -+ else /* FXO - issue reset via TDM_CODEC_RST*/ -+ { -+ /* change MPP44 type to TDM_CODEC_RST(0x2) */ -+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); -+ } -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ -+ /* TBD - 5 channels */ -+#if defined(MV_TDM_5CHANNELS) -+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ -+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); -+ mvGppPolaritySet(1, MV_GPP6, 0); -+ -+ twsiSlave.offset = 6; -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ -+ -+ twsiSlave.offset = 2; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+#endif -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ -+} -+/******************************************************************************* -+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) -+{ -+ switch(mvBoardIdGet()) -+ { -+ case RD_88F6281A_ID: -+ *connMode = DAISY_CHAIN_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6281A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case RD_88F6192A_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6192A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ default: -+ *connMode = *irqMode = -1; -+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); -+ } -+ return; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppModuleTypePrint - print module detect -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TDM\n", devClass); -+ break; -+ case MV_BOARD_AUDIO: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is AUDIO\n", devClass); -+ break; -+ case MV_BOARD_RGMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is RGMII\n", devClass); -+ break; -+ case MV_BOARD_GMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is GMII\n", devClass); -+ break; -+ case MV_BOARD_TS: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TS\n", devClass); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+/* Board devices API managments */ -+ -+/******************************************************************************* -+* mvBoardGetDeviceNumber - Get number of device of some type on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* number of those devices else the function returns 0 -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devNum; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) -+ { -+ foundIndex++; -+ } -+ } -+ -+ return foundIndex; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Base address else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Bus width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return 8; -+ } -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->devWidth; -+ -+ return MV_ERROR; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* window size else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* boardGetDevEntry - returns the entry pointer of a device on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev number else the function returns 0x0 -+* -+* -+*******************************************************************************/ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devIndex; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); -+ return NULL; -+ -+ } -+ -+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) -+ { -+ /* TBR */ -+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) -+ continue;*/ -+ -+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) -+ { -+ if (foundIndex == devNum) -+ { -+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); -+ } -+ foundIndex++; -+ } -+ } -+ -+ /* device not found */ -+ return NULL; -+} -+ -+/* Get device CS number */ -+ -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->deviceCS; -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardNandWidthGet - -+* -+* DESCRIPTION: Get the width of the first NAND device in byte. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: 1, 2, 4 or MV_ERROR -+* -+* -+*******************************************************************************/ -+/* */ -+MV_32 mvBoardNandWidthGet(void) -+{ -+ MV_U32 devNum; -+ MV_U32 devWidth; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); -+ if (devWidth != MV_ERROR) -+ return (devWidth / 8); -+ } -+ -+ /* NAND wasn't found */ -+ return MV_ERROR; -+} -+ -+MV_U32 gBoardId = -1; -+ -+/******************************************************************************* -+* mvBoardIdGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns board ID. -+* Board ID is 32bit word constructed of board model (16bit) and -+* board revision (16bit) in the following way: 0xMMMMRRRR. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit board ID number, '-1' if board is undefined. -+* -+*******************************************************************************/ -+MV_U32 mvBoardIdGet(MV_VOID) -+{ -+ MV_U32 tmpBoardId = -1; -+ -+ if(gBoardId == -1) -+ { -+ #if defined(DB_88F6281A) -+ tmpBoardId = DB_88F6281A_BP_ID; -+ #elif defined(RD_88F6281A) -+ tmpBoardId = RD_88F6281A_ID; -+ #elif defined(DB_88F6192A) -+ tmpBoardId = DB_88F6192A_BP_ID; -+ #elif defined(DB_88F6190A) -+ tmpBoardId = DB_88F6190A_BP_ID; -+ #elif defined(RD_88F6192A) -+ tmpBoardId = RD_88F6192A_ID; -+ #elif defined(RD_88F6190A) -+ tmpBoardId = RD_88F6190A_ID; -+ #elif defined(DB_88F6180A) -+ tmpBoardId = DB_88F6180A_BP_ID; -+ #elif defined(RD_88F6281A_PCAC) -+ tmpBoardId = RD_88F6281A_PCAC_ID; -+ #elif defined(RD_88F6281A_SHEEVA_PLUG) -+ tmpBoardId = SHEEVA_PLUG_ID; -+ #elif defined(DB_CUSTOMER) -+ tmpBoardId = DB_CUSTOMER_ID; -+ #endif -+ gBoardId = tmpBoardId; -+ } -+ -+ return gBoardId; -+} -+ -+ -+/******************************************************************************* -+* mvBoarModuleTypeGet - mvBoarModuleTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group num - MV_BOARD_MPP_GROUP_CLASS enum -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* module num - MV_BOARD_MODULE_CLASS enum -+* -+*******************************************************************************/ -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read MPP module ID\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* device num - one of three devices -+* reg num - 0 or 1 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read S@R device read\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read S@R succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRSet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devNum - one of three devices -+* regNum - 0 or 1 -+* regVal - value -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ -+ twsiSlave.slaveAddr.type, regVal)); -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) -+ { -+ DB(mvOsPrintf("Board: Write S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Write S@R succeded\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSlicGpioPinGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) -+{ -+ MV_U32 boardId; -+ boardId = mvBoardIdGet(); -+ -+ switch (boardId) -+ { -+ case DB_88F6281A_BP_ID: -+ case RD_88F6281A_ID: -+ default: -+ return MV_ERROR; -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x1; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe) | val; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x2; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x10; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h -new file mode 100644 -index 0000000..522493d ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvBoardEnvLibh -+#define __INCmvBoardEnvLibh -+ -+/* defines */ -+/* The below constant macros defines the board I2C EEPROM data offsets */ -+ -+ -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+ -+ -+/* DUART stuff for Tclk detection only */ -+#define DUART_BAUD_RATE 115200 -+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ -+ -+/* Voice devices assembly modes */ -+#define DAISY_CHAIN_MODE 1 -+#define DUAL_CHIP_SELECT_MODE 0 -+#define INTERRUPT_TO_MPP 1 -+#define INTERRUPT_TO_TDM 0 -+ -+ -+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS -+#define BOARD_ETH_SWITCH_PORT_NUM 5 -+ -+#define MV_BOARD_MAX_USB_IF 1 -+#define MV_BOARD_MAX_MPP 7 -+#define MV_BOARD_NAME_LEN 0x20 -+ -+typedef struct _boardData -+{ -+ MV_U32 magic; -+ MV_U16 boardId; -+ MV_U8 boardVer; -+ MV_U8 boardRev; -+ MV_U32 reserved1; -+ MV_U32 reserved2; -+ -+}BOARD_DATA; -+ -+typedef enum _devBoardMppGroupClass -+{ -+ MV_BOARD_MPP_GROUP_1, -+ MV_BOARD_MPP_GROUP_2, -+ MV_BOARD_MAX_MPP_GROUP -+}MV_BOARD_MPP_GROUP_CLASS; -+ -+typedef enum _devBoardMppTypeClass -+{ -+ MV_BOARD_AUTO, -+ MV_BOARD_TDM, -+ MV_BOARD_AUDIO, -+ MV_BOARD_RGMII, -+ MV_BOARD_GMII, -+ MV_BOARD_TS, -+ MV_BOARD_MII, -+ MV_BOARD_OTHER -+}MV_BOARD_MPP_TYPE_CLASS; -+ -+typedef enum _devBoardModuleIdClass -+{ -+ MV_BOARD_MODULE_TDM_ID = 1, -+ MV_BOARD_MODULE_AUDIO_ID, -+ MV_BOARD_MODULE_RGMII_ID, -+ MV_BOARD_MODULE_GMII_ID, -+ MV_BOARD_MODULE_TS_ID, -+ MV_BOARD_MODULE_MII_ID, -+ MV_BOARD_MODULE_TDM_5CHAN_ID, -+ MV_BOARD_MODULE_OTHER_ID -+}MV_BOARD_MODULE_ID_CLASS; -+ -+typedef struct _boardMppTypeInfo -+{ -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; -+ -+}MV_BOARD_MPP_TYPE_INFO; -+ -+ -+typedef enum _devBoardClass -+{ -+ BOARD_DEV_NOR_FLASH, -+ BOARD_DEV_NAND_FLASH, -+ BOARD_DEV_SEVEN_SEG, -+ BOARD_DEV_FPGA, -+ BOARD_DEV_SRAM, -+ BOARD_DEV_SPI_FLASH, -+ BOARD_DEV_OTHER, -+}MV_BOARD_DEV_CLASS; -+ -+typedef enum _devTwsiBoardClass -+{ -+ BOARD_TWSI_RTC, -+ BOARD_DEV_TWSI_EXP, -+ BOARD_DEV_TWSI_SATR, -+ BOARD_TWSI_AUDIO_DEC, -+ BOARD_TWSI_OTHER -+}MV_BOARD_TWSI_CLASS; -+ -+typedef enum _devGppBoardClass -+{ -+ BOARD_GPP_RTC, -+ BOARD_GPP_MV_SWITCH, -+ BOARD_GPP_USB_VBUS, -+ BOARD_GPP_USB_VBUS_EN, -+ BOARD_GPP_USB_OC, -+ BOARD_GPP_USB_HOST_DEVICE, -+ BOARD_GPP_REF_CLCK, -+ BOARD_GPP_VOIP_SLIC, -+ BOARD_GPP_LIFELINE, -+ BOARD_GPP_BUTTON, -+ BOARD_GPP_TS_BUTTON_C, -+ BOARD_GPP_TS_BUTTON_U, -+ BOARD_GPP_TS_BUTTON_D, -+ BOARD_GPP_TS_BUTTON_L, -+ BOARD_GPP_TS_BUTTON_R, -+ BOARD_GPP_POWER_BUTTON, -+ BOARD_GPP_RESTOR_BUTTON, -+ BOARD_GPP_WPS_BUTTON, -+ BOARD_GPP_HDD0_POWER, -+ BOARD_GPP_HDD1_POWER, -+ BOARD_GPP_FAN_POWER, -+ BOARD_GPP_RESET, -+ BOARD_GPP_POWER_ON_LED, -+ BOARD_GPP_HDD_POWER, -+ BOARD_GPP_SDIO_POWER, -+ BOARD_GPP_SDIO_DETECT, -+ BOARD_GPP_SDIO_WP, -+ BOARD_GPP_SWITCH_PHY_INT, -+ BOARD_GPP_TSU_DIRCTION, -+ BOARD_GPP_OTHER -+}MV_BOARD_GPP_CLASS; -+ -+ -+typedef struct _devCsInfo -+{ -+ MV_U8 deviceCS; -+ MV_U32 params; -+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ -+ MV_U8 devWidth; -+ -+}MV_DEV_CS_INFO; -+ -+ -+#define MV_BOARD_PHY_FORCE_10MB 0x0 -+#define MV_BOARD_PHY_FORCE_100MB 0x1 -+#define MV_BOARD_PHY_FORCE_1000MB 0x2 -+#define MV_BOARD_PHY_SPEED_AUTO 0x3 -+ -+typedef struct _boardSwitchInfo -+{ -+ MV_32 linkStatusIrq; -+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; -+ MV_32 qdCpuPort; -+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ -+ MV_32 switchOnPort; -+ -+}MV_BOARD_SWITCH_INFO; -+ -+typedef struct _boardLedInfo -+{ -+ MV_U8 activeLedsNumber; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ MV_U8* gppPinNum; /* Pointer to GPP values */ -+ -+}MV_BOARD_LED_INFO; -+ -+typedef struct _boardGppInfo -+{ -+ MV_BOARD_GPP_CLASS devClass; -+ MV_U8 gppPinNum; -+ -+}MV_BOARD_GPP_INFO; -+ -+ -+typedef struct _boardTwsiInfo -+{ -+ MV_BOARD_TWSI_CLASS devClass; -+ MV_U8 twsiDevAddr; -+ MV_U8 twsiDevAddrType; -+ -+}MV_BOARD_TWSI_INFO; -+ -+ -+typedef enum _boardMacSpeed -+{ -+ BOARD_MAC_SPEED_10M, -+ BOARD_MAC_SPEED_100M, -+ BOARD_MAC_SPEED_1000M, -+ BOARD_MAC_SPEED_AUTO, -+ -+}MV_BOARD_MAC_SPEED; -+ -+typedef struct _boardMacInfo -+{ -+ MV_BOARD_MAC_SPEED boardMacSpeed; -+ MV_U8 boardEthSmiAddr; -+ -+}MV_BOARD_MAC_INFO; -+ -+typedef struct _boardMppInfo -+{ -+ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; -+ -+}MV_BOARD_MPP_INFO; -+ -+typedef struct _boardInfo -+{ -+ char boardName[MV_BOARD_NAME_LEN]; -+ MV_U8 numBoardMppTypeValue; -+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; -+ MV_U8 numBoardMppConfigValue; -+ MV_BOARD_MPP_INFO* pBoardMppConfigValue; -+ MV_U32 intsGppMaskLow; -+ MV_U32 intsGppMaskHigh; -+ MV_U8 numBoardDeviceIf; -+ MV_DEV_CS_INFO* pDevCsInfo; -+ MV_U8 numBoardTwsiDev; -+ MV_BOARD_TWSI_INFO* pBoardTwsiDev; -+ MV_U8 numBoardMacInfo; -+ MV_BOARD_MAC_INFO* pBoardMacInfo; -+ MV_U8 numBoardGppInfo; -+ MV_BOARD_GPP_INFO* pBoardGppInfo; -+ MV_U8 activeLedsNumber; -+ MV_U8* pLedGppPin; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ /* GPP values */ -+ MV_U32 gppOutEnValLow; -+ MV_U32 gppOutEnValHigh; -+ MV_U32 gppOutValLow; -+ MV_U32 gppOutValHigh; -+ MV_U32 gppPolarityValLow; -+ MV_U32 gppPolarityValHigh; -+ -+ /* Switch Configuration */ -+ MV_BOARD_SWITCH_INFO* pSwitchInfo; -+}MV_BOARD_INFO; -+ -+ -+ -+MV_VOID mvBoardEnvInit(MV_VOID); -+MV_U32 mvBoardIdGet(MV_VOID); -+MV_U16 mvBoardModelGet(MV_VOID); -+MV_U16 mvBoardRevGet(MV_VOID); -+MV_STATUS mvBoardNameGet(char *pNameBuff); -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInGmii(MV_VOID); -+MV_U32 mvBoardTclkGet(MV_VOID); -+MV_U32 mvBoardSysClkGet(MV_VOID); -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); -+MV_VOID mvBoardDebugLed(MV_U32 hexNum); -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum); -+ -+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType); -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); -+MV_VOID mvBoardMppMuxSet(MV_VOID); -+MV_VOID mvBoardTdmMppSet(MV_32 chType); -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); -+ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID); -+MV_VOID mvBoardReset(MV_VOID); -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); -+/* Board devices API managments */ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+/* Gpio Pin Connections API */ -+MV_32 mvBoardUSBVbusGpioPinGet(int devId); -+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); -+ -+MV_32 mvBoardResetGpioPinGet(MV_VOID); -+MV_32 mvBoardRTCGpioPinGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); -+ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID); -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); -+ -+MV_32 mvBoardNandWidthGet(void); -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); -+#endif /* __INCmvBoardEnvLibh */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c -new file mode 100644 -index 0000000..54508c0 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c -@@ -0,0 +1,848 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvCommon.h" -+#include "mvBoardEnvLib.h" -+#include "mvBoardEnvSpec.h" -+#include "twsi/mvTwsi.h" -+ -+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+ -+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_AUTO} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_TSU_DIRCTION, 33} -+ /*muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_SDIO_DETECT, 38}, -+ {BOARD_GPP_USB_VBUS, 49}*/ -+ }; -+ -+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6281A_MPP0_7, -+ DB_88F6281A_MPP8_15, -+ DB_88F6281A_MPP16_23, -+ DB_88F6281A_MPP24_31, -+ DB_88F6281A_MPP32_39, -+ DB_88F6281A_MPP40_47, -+ DB_88F6281A_MPP48_55 -+ }}}; -+ -+ -+MV_BOARD_INFO db88f6281AInfo = { -+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6281AInfoBoardMppTypeInfo, -+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6281AInfoBoardDeCsInfo, -+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6281AInfoBoardTwsiDev, -+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6281AInfoBoardMacInfo, -+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6281AInfoBoardGppInfo, -+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6281A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 -+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 -+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_1000M, 0xa}, -+ {BOARD_MAC_SPEED_AUTO, 0xb} -+ }; -+ -+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = -+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, -+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ -+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, -+ {-1, {-1}, -1, -1, -1}}; -+ -+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_RGMII, MV_BOARD_TDM} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ {{BOARD_GPP_SDIO_DETECT, 28}, -+ {BOARD_GPP_USB_OC, 29}, -+ {BOARD_GPP_WPS_BUTTON, 35}, -+ {BOARD_GPP_MV_SWITCH, 38}, -+ {BOARD_GPP_USB_VBUS, 49} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_MPP0_7, -+ RD_88F6281A_MPP8_15, -+ RD_88F6281A_MPP16_23, -+ RD_88F6281A_MPP24_31, -+ RD_88F6281A_MPP32_39, -+ RD_88F6281A_MPP40_47, -+ RD_88F6281A_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281AInfo = { -+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281AInfoBoardMppTypeInfo, -+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281AInfoBoardDeCsInfo, -+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281AInfoBoardTwsiDev, -+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281AInfoBoardMacInfo, -+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6281AInfoBoardGppInfo, -+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ -+}; -+ -+ -+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_SDIO_WP, 20}, -+ {BOARD_GPP_USB_VBUS, 22}, -+ {BOARD_GPP_SDIO_DETECT, 23}, -+ }; -+ -+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6192A_MPP0_7, -+ DB_88F6192A_MPP8_15, -+ DB_88F6192A_MPP16_23, -+ DB_88F6192A_MPP24_31, -+ DB_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO db88f6192AInfo = { -+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 -+ -+MV_BOARD_INFO db88f6190AInfo = { -+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 -+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE -+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 -+ -+MV_U8 rd88f6192AInfoBoardDebugLedIf[] = -+ {17, 28, 29}; -+ -+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+ -+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_USB_VBUS_EN, 10}, -+ {BOARD_GPP_USB_HOST_DEVICE, 11}, -+ {BOARD_GPP_RESET, 14}, -+ {BOARD_GPP_POWER_ON_LED, 15}, -+ {BOARD_GPP_HDD_POWER, 16}, -+ {BOARD_GPP_WPS_BUTTON, 24}, -+ {BOARD_GPP_TS_BUTTON_C, 25}, -+ {BOARD_GPP_USB_VBUS, 26}, -+ {BOARD_GPP_USB_OC, 27}, -+ {BOARD_GPP_TS_BUTTON_U, 30}, -+ {BOARD_GPP_TS_BUTTON_R, 31}, -+ {BOARD_GPP_TS_BUTTON_L, 32}, -+ {BOARD_GPP_TS_BUTTON_D, 34}, -+ {BOARD_GPP_FAN_POWER, 35} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6192A_MPP0_7, -+ RD_88F6192A_MPP8_15, -+ RD_88F6192A_MPP16_23, -+ RD_88F6192A_MPP24_31, -+ RD_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO rd88f6192AInfo = { -+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO rd88f6190AInfo = { -+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 -+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 -+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 -+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 -+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ /* Muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_USB_VBUS, 6} */ -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_AUTO} -+ }; -+ -+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6180A_MPP0_7, -+ DB_88F6180A_MPP8_15, -+ DB_88F6180A_MPP16_23, -+ DB_88F6180A_MPP24_31, -+ DB_88F6180A_MPP32_39, -+ DB_88F6180A_MPP40_44 -+ }}}; -+ -+MV_BOARD_INFO db88f6180AInfo = { -+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6180AInfoBoardMppTypeInfo, -+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6180AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6180AInfoBoardDeCsInfo, -+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6180AInfoBoardTwsiDev, -+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6180AInfoBoardMacInfo, -+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ NULL, -+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6180A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 -+ -+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = -+ {38, 39, 40, 41}; -+ -+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_PCAC_MPP0_7, -+ RD_88F6281A_PCAC_MPP8_15, -+ RD_88F6281A_PCAC_MPP16_23, -+ RD_88F6281A_PCAC_MPP24_31, -+ RD_88F6281A_PCAC_MPP32_39, -+ RD_88F6281A_PCAC_MPP40_47, -+ RD_88F6281A_PCAC_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281APcacInfo = { -+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281APcacInfoBoardMppTypeInfo, -+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281APcacInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281APcacInfoBoardDeCsInfo, -+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281APcacInfoBoardTwsiDev, -+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281APcacInfoBoardMacInfo, -+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+/* 6281 Sheeva Plug*/ -+ -+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 -+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 -+ -+MV_U8 sheevaPlugInfoBoardDebugLedIf[] = -+ {49}; -+ -+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+ -+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = -+ {{{ -+ RD_SHEEVA_PLUG_MPP0_7, -+ RD_SHEEVA_PLUG_MPP8_15, -+ RD_SHEEVA_PLUG_MPP16_23, -+ RD_SHEEVA_PLUG_MPP24_31, -+ RD_SHEEVA_PLUG_MPP32_39, -+ RD_SHEEVA_PLUG_MPP40_47, -+ RD_SHEEVA_PLUG_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO sheevaPlugInfo = { -+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ -+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ sheevaPlugInfoBoardMppTypeInfo, -+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ sheevaPlugInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ sheevaPlugInfoBoardDeCsInfo, -+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ sheevaPlugInfoBoardTwsiDev, -+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ sheevaPlugInfoBoardMacInfo, -+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ sheevaPlugInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ -+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ -+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ -+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+/* Customer specific board place holder*/ -+ -+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 -+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#else -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#endif -+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_U8 dbCustomerInfoBoardDebugLedIf[] = -+ {0}; -+ -+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = -+ {{{ -+ DB_CUSTOMER_MPP0_7, -+ DB_CUSTOMER_MPP8_15, -+ DB_CUSTOMER_MPP16_23, -+ DB_CUSTOMER_MPP24_31, -+ DB_CUSTOMER_MPP32_39, -+ DB_CUSTOMER_MPP40_47, -+ DB_CUSTOMER_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO dbCustomerInfo = { -+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ dbCustomerInfoBoardMppTypeInfo, -+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ dbCustomerInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ dbCustomerInfoBoardDeCsInfo, -+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ dbCustomerInfoBoardTwsiDev, -+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ dbCustomerInfoBoardMacInfo, -+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ -+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ -+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ -+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO* boardInfoTbl[] = { -+ &db88f6281AInfo, -+ &rd88f6281AInfo, -+ &db88f6192AInfo, -+ &rd88f6192AInfo, -+ &db88f6180AInfo, -+ &db88f6190AInfo, -+ &rd88f6190AInfo, -+ &rd88f6281APcacInfo, -+ &dbCustomerInfo, -+ &sheevaPlugInfo -+ }; -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h -new file mode 100644 -index 0000000..b11dafb ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h -@@ -0,0 +1,262 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvBoardEnvSpech -+#define __INCmvBoardEnvSpech -+ -+#include "mvSysHwConfig.h" -+ -+ -+/* For future use */ -+#define BD_ID_DATA_START_OFFS 0x0 -+#define BD_DETECT_SEQ_OFFS 0x0 -+#define BD_SYS_NUM_OFFS 0x4 -+#define BD_NAME_OFFS 0x8 -+ -+/* I2C bus addresses */ -+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ -+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM0_I2C_ADDR 0x56 -+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM1_I2C_ADDR 0x54 -+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_EEPROM_I2C_ADDR 0x51 -+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 -+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 -+ -+#define BOOT_FLASH_INDEX 0 -+#define MAIN_FLASH_INDEX 1 -+ -+#define BOARD_ETH_START_PORT_NUM 0 -+ -+/* Supported clocks */ -+#define MV_BOARD_TCLK_100MHZ 100000000 -+#define MV_BOARD_TCLK_125MHZ 125000000 -+#define MV_BOARD_TCLK_133MHZ 133333333 -+#define MV_BOARD_TCLK_150MHZ 150000000 -+#define MV_BOARD_TCLK_166MHZ 166666667 -+#define MV_BOARD_TCLK_200MHZ 200000000 -+ -+#define MV_BOARD_SYSCLK_100MHZ 100000000 -+#define MV_BOARD_SYSCLK_125MHZ 125000000 -+#define MV_BOARD_SYSCLK_133MHZ 133333333 -+#define MV_BOARD_SYSCLK_150MHZ 150000000 -+#define MV_BOARD_SYSCLK_166MHZ 166666667 -+#define MV_BOARD_SYSCLK_200MHZ 200000000 -+#define MV_BOARD_SYSCLK_233MHZ 233333333 -+#define MV_BOARD_SYSCLK_250MHZ 250000000 -+#define MV_BOARD_SYSCLK_267MHZ 266666667 -+#define MV_BOARD_SYSCLK_300MHZ 300000000 -+#define MV_BOARD_SYSCLK_333MHZ 333333334 -+#define MV_BOARD_SYSCLK_400MHZ 400000000 -+ -+#define MV_BOARD_REFCLK_25MHZ 25000000 -+ -+/* Board specific */ -+/* =============================== */ -+ -+/* boards ID numbers */ -+ -+#define BOARD_ID_BASE 0x0 -+ -+/* New board ID numbers */ -+#define DB_88F6281A_BP_ID (BOARD_ID_BASE) -+#define DB_88F6281_BP_MLL_ID 1680 -+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) -+#define RD_88F6281_MLL_ID 1682 -+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) -+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) -+#define RD_88F6192_MLL_ID 1681 -+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) -+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) -+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) -+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) -+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) -+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) -+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) -+ -+/* DB-88F6281A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6281A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6281A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6281A_MPP8_15 0x11113311 -+#define DB_88F6281A_MPP16_23 0x00551111 -+#define DB_88F6281A_MPP24_31 0x00000000 -+#define DB_88F6281A_MPP32_39 0x00000000 -+#define DB_88F6281A_MPP40_47 0x00000000 -+#define DB_88F6281A_MPP48_55 0x00000000 -+#define DB_88F6281A_OE_LOW 0x0 -+#if defined(MV_TDM_5CHANNELS) -+ #define DB_88F6281A_OE_HIGH (BIT6) -+#else -+#define DB_88F6281A_OE_HIGH 0x0 -+#endif -+#define DB_88F6281A_OE_VAL_LOW 0x0 -+#define DB_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A */ -+#if defined(MV_NAND) -+ #define RD_88F6281A_MPP0_7 0x21111111 -+#else -+ #define RD_88F6281A_MPP0_7 0x21112220 -+#endif -+#define RD_88F6281A_MPP8_15 0x11113311 -+#define RD_88F6281A_MPP16_23 0x33331111 -+#define RD_88F6281A_MPP24_31 0x33003333 -+#define RD_88F6281A_MPP32_39 0x20440533 -+#define RD_88F6281A_MPP40_47 0x22202222 -+#define RD_88F6281A_MPP48_55 0x00000002 -+#define RD_88F6281A_OE_LOW (BIT28 | BIT29) -+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) -+#define RD_88F6281A_OE_VAL_LOW 0x0 -+#define RD_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* DB-88F6192A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6192A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6192A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6192A_MPP8_15 0x11113311 -+#define DB_88F6192A_MPP16_23 0x00501111 -+#define DB_88F6192A_MPP24_31 0x00000000 -+#define DB_88F6192A_MPP32_35 0x00000000 -+#define DB_88F6192A_OE_LOW (BIT22 | BIT23) -+#define DB_88F6192A_OE_HIGH 0x0 -+#define DB_88F6192A_OE_VAL_LOW 0x0 -+#define DB_88F6192A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6192A */ -+#define RD_88F6192A_MPP0_7 0x01222222 -+#define RD_88F6192A_MPP8_15 0x00000011 -+#define RD_88F6192A_MPP16_23 0x05550000 -+#define RD_88F6192A_MPP24_31 0x0 -+#define RD_88F6192A_MPP32_35 0x0 -+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) -+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) -+#define RD_88F6192A_OE_VAL_LOW 0x18400 -+#define RD_88F6192A_OE_VAL_HIGH 0x8 -+ -+/* DB-88F6180A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6180A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6180A_MPP0_7 0x01112222 -+#endif -+#define DB_88F6180A_MPP8_15 0x11113311 -+#define DB_88F6180A_MPP16_23 0x00001111 -+#define DB_88F6180A_MPP24_31 0x0 -+#define DB_88F6180A_MPP32_39 0x4444c000 -+#define DB_88F6180A_MPP40_44 0x00044444 -+#define DB_88F6180A_OE_LOW 0x0 -+#define DB_88F6180A_OE_HIGH 0x0 -+#define DB_88F6180A_OE_VAL_LOW 0x0 -+#define DB_88F6180A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A_PCAC */ -+#define RD_88F6281A_PCAC_MPP0_7 0x21111111 -+#define RD_88F6281A_PCAC_MPP8_15 0x00003311 -+#define RD_88F6281A_PCAC_MPP16_23 0x00001100 -+#define RD_88F6281A_PCAC_MPP24_31 0x00000000 -+#define RD_88F6281A_PCAC_MPP32_39 0x00000000 -+#define RD_88F6281A_PCAC_MPP40_47 0x00000000 -+#define RD_88F6281A_PCAC_MPP48_55 0x00000000 -+#define RD_88F6281A_PCAC_OE_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_HIGH 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 -+ -+/* SHEEVA PLUG */ -+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 -+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 -+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 -+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 -+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 -+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 -+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 -+#define RD_SHEEVA_PLUG_OE_LOW 0x0 -+#define RD_SHEEVA_PLUG_OE_HIGH 0x0 -+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) -+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) -+ -+/* DB-CUSTOMER */ -+#define DB_CUSTOMER_MPP0_7 0x21111111 -+#define DB_CUSTOMER_MPP8_15 0x00003311 -+#define DB_CUSTOMER_MPP16_23 0x00001100 -+#define DB_CUSTOMER_MPP24_31 0x00000000 -+#define DB_CUSTOMER_MPP32_39 0x00000000 -+#define DB_CUSTOMER_MPP40_47 0x00000000 -+#define DB_CUSTOMER_MPP48_55 0x00000000 -+#define DB_CUSTOMER_OE_LOW 0x0 -+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) -+#define DB_CUSTOMER_OE_VAL_LOW 0x0 -+#define DB_CUSTOMER_OE_VAL_HIGH 0x0 -+ -+#endif /* __INCmvBoardEnvSpech */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c b/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c -new file mode 100644 -index 0000000..9e39354 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c -@@ -0,0 +1,320 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+ -+/******************************************************************************* -+* mvCpuPclkGet - Get the CPU pClk (pipe clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU core clock. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in MHertz. -+* -+*******************************************************************************/ -+/* 6180 have different clk reset sampling */ -+ -+static MV_U32 mvCpu6180PclkGet(MV_VOID) -+{ -+ MV_U32 tmpPClkRate=0; -+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; -+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; -+ -+ return tmpPClkRate; -+} -+ -+ -+MV_U32 mvCpuPclkGet(MV_VOID) -+{ -+#if defined(PCLCK_AUTO_DETECT) -+ MV_U32 tmpPClkRate=0; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180PclkGet(); -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); -+ tmpPClkRate = cpuCLK[tmpPClkRate]; -+ -+ return tmpPClkRate; -+#else -+ return MV_DEFAULT_PCLK -+#endif -+} -+ -+/******************************************************************************* -+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU L2 clock. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvCpu6180L2ClkGet(MV_VOID) -+{ -+ MV_U32 L2ClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; -+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; -+ -+ return L2ClkRate; -+ -+} -+ -+MV_U32 mvCpuL2ClkGet(MV_VOID) -+{ -+#ifdef L2CLK_AUTO_DETECT -+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; -+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180L2ClkGet(); -+ -+ pClkRate = mvCpuPclkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); -+ -+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); -+ -+ return L2ClkRate; -+#else -+ return MV_BOARD_DEFAULT_L2CLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvCpuNameGet - Get CPU name -+* -+* DESCRIPTION: -+* This function returns a string describing the CPU model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* None. -+*******************************************************************************/ -+MV_VOID mvCpuNameGet(char *pNameBuff) -+{ -+ MV_U32 cpuModel; -+ -+ cpuModel = mvOsCpuPartGet(); -+ -+ /* The CPU module is indicated in the Processor Version Register (PVR) */ -+ switch(cpuModel) -+ { -+ case CPU_PART_MRVL131: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM926: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM946: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); -+ break; -+ default: -+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); -+ break; -+ } /* switch */ -+ -+ return; -+} -+ -+ -+#define MV_PROC_STR_SIZE 50 -+ -+static void mvCpuIfGetL2EccMode(MV_8 *buf) -+{ -+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); -+ if (regVal & BIT2) -+ mvOsSPrintf(buf, "L2 ECC Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 ECC Disabled"); -+} -+ -+static void mvCpuIfGetL2Mode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT22) -+ mvOsSPrintf(buf, "L2 Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 Disabled"); -+} -+ -+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT24) -+ mvOsSPrintf(buf, "L2 Prefetch Disabled"); -+ else -+ mvOsSPrintf(buf, "L2 Prefetch Enabled"); -+} -+ -+static void mvCpuIfGetWriteAllocMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT28) -+ mvOsSPrintf(buf, "Write Allocate Enabled"); -+ else -+ mvOsSPrintf(buf, "Write Allocate Disabled"); -+} -+ -+static void mvCpuIfGetCpuStreamMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT29) -+ mvOsSPrintf(buf, "CPU Streaming Enabled"); -+ else -+ mvOsSPrintf(buf, "CPU Streaming Disabled"); -+} -+ -+static void mvCpuIfPrintCpuRegs(void) -+{ -+ MV_U32 regVal = 0; -+ -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ -+ mvOsPrintf("Control Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ -+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ -+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); -+ -+} -+ -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) -+{ -+ MV_U32 count = 0; -+ -+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_En_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; -+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; -+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; -+ -+ mvCpuIfGetL2Mode(L2_En_str); -+ mvCpuIfGetL2EccMode(L2_ECC_str); -+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); -+ mvCpuIfGetWriteAllocMode(Write_Alloc_str); -+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); -+ mvCpuIfPrintCpuRegs(); -+ -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); -+ return count; -+} -+ -+MV_U32 whoAmI(MV_VOID) -+{ -+ return 0; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h b/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h -new file mode 100644 -index 0000000..dd3a70e ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h -@@ -0,0 +1,99 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuh -+#define __INCmvCpuh -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* defines */ -+#define CPU_PART_MRVL131 0x131 -+#define CPU_PART_ARM926 0x926 -+#define CPU_PART_ARM946 0x946 -+#define MV_CPU_ARM_CLK_ELM_SIZE 12 -+#define MV_CPU_ARM_CLK_RATIO_OFF 8 -+#define MV_CPU_ARM_CLK_DDR_OFF 4 -+ -+#ifndef MV_ASMLANGUAGE -+typedef struct _mvCpuArmClk -+{ -+ MV_U32 cpuClk; /* CPU clock in MHz */ -+ MV_U32 ddrClk; /* DDR clock in MHz */ -+ MV_U32 l2Clk; /* CPU DDR clock ratio */ -+ -+}MV_CPU_ARM_CLK; -+ -+MV_U32 mvCpuPclkGet(MV_VOID); -+MV_VOID mvCpuNameGet(char *pNameBuff); -+MV_U32 mvCpuL2ClkGet(MV_VOID); -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); -+MV_U32 whoAmI(MV_VOID); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCpuh */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c -new file mode 100644 -index 0000000..2e6226b ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c -@@ -0,0 +1,296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCtrlEnvAddrDec.h - Marvell controller address decode library -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ddr2/mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+ -+#define MV_DEBUG -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* Default Attributes array */ -+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; -+extern MV_TARGET *sampleAtResetTargetArray; -+/* Dram\AHBToMbus\PEX share regsiter */ -+ -+#define CTRL_DEC_BASE_OFFS 16 -+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) -+#define CTRL_DEC_BASE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_SIZE_OFFS 16 -+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) -+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_WIN_EN BIT0 -+ -+ -+ -+/******************************************************************************* -+* mvCtrlAddrDecToReg - Get address decode register format values -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) -+{ -+ -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; -+ pAddrDecRegs->baseReg |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; -+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlRegToAddrDec - Extract address decode struct from registers. -+* -+* DESCRIPTION: -+* This function extract address decode struct from address decode -+* registers given as parameters. -+* -+* INPUT: -+* pAddrDecRegs - Address decode register struct. -+* -+* OUTPUT: -+* pAddrDecWin - Target window data structure. -+* -+* RETURN: -+* MV_BAD_PARAM if address decode registers data is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 sizeRegVal; -+ -+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> -+ CTRL_DEC_SIZE_OFFS; -+ -+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; -+ -+ pAddrDecWin->baseHigh = 0; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlAttribGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib) -+{ -+ -+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; -+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlGetAttrib - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) -+{ -+ MV_TARGET target; -+ MV_TARGET x; -+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) -+ { -+ x = MV_CHANGE_BOOT_CS(target); -+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && -+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) -+ { -+ /* found it */ -+ break; -+ } -+ } -+ -+ return target; -+} -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam) -+{ -+ MV_U32 baseToReg=0, sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; -+ pWinParam->baseAddr |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); -+ return MV_BAD_PARAM; -+ } -+ pWinParam->size = sizeToReg; -+ -+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; -+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; -+ -+ return MV_OK; -+} -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; -+ -+ /* Upper 32bit address base is supported under PCI High Address remap */ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ /* Prepare sizeReg to ctrlRegToSize function */ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); -+ return MV_BAD_PARAM; -+ } -+ targetAttrib.targetId = pWinParam->targetId; -+ targetAttrib.attrib = pWinParam->attrib; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h -new file mode 100644 -index 0000000..fcb5a31 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h -@@ -0,0 +1,203 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAddrDech -+#define __INCmvCtrlEnvAddrDech -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+ -+ -+/* defines */ -+/* DUnit attributes */ -+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 -+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 -+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 -+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 -+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 -+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 -+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 -+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 -+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) -+ -+/* RUnit (Device) attributes */ -+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) -+ -+/* LMaster (PCI) attributes */ -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+ -+ -+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 -+ -+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 -+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 -+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 -+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 -+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 -+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 -+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+/* PEX Attributes */ -+#define ATMWCR_WIN_PEX_TYPE_OFFS 3 -+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 -+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) -+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) -+ -+/* typedefs */ -+ -+/* Unsupported attributes for address decode: */ -+/* 2) PCI0/1_REQ64n control */ -+ -+typedef struct _mvDecRegs -+{ -+ MV_U32 baseReg; -+ MV_U32 baseRegHigh; -+ MV_U32 sizeReg; -+ -+}MV_DEC_REGS; -+ -+typedef struct _mvTargetAttrib -+{ -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ -+}MV_TARGET_ATTRIB; -+ -+ -+/* This structure describes address decode window */ -+typedef struct _mvDecWin -+{ -+ MV_TARGET target; /* Target for addr decode window */ -+ MV_ADDR_WIN addrWin; /* Address window of target */ -+ MV_BOOL enable; /* Window enable/disable */ -+}MV_DEC_WIN; -+ -+typedef struct _mvDecWinParams -+{ -+ MV_TARGET_ID targetId; /* Target ID field */ -+ MV_U8 attrib; /* Attribute field */ -+ MV_U32 baseAddr; /* Base address in register format */ -+ MV_U32 size; /* Size in register format */ -+}MV_DEC_WIN_PARAMS; -+ -+ -+/* mvCtrlEnvAddrDec API list */ -+ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, -+ MV_DEC_REGS *pAddrDecRegs); -+ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, -+ MV_ADDR_WIN *pAddrDecWin); -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib); -+ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); -+ -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam); -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin); -+ -+ -+ -+ -+#endif /* __INCmvCtrlEnvAddrDech */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h -new file mode 100644 -index 0000000..14a5ac4 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAsmh -+#define __INCmvCtrlEnvAsmh -+#include "pex/mvPexRegs.h" -+ -+#define CHIP_BOND_REG 0x10034 -+#define PCKG_OPT_MASK_AS #3 -+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK -+ -+/* Read device ID into toReg bits 15:0 from 0xd0000000 */ -+/* defines */ -+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read device ID into toReg bits 15:0 from 0xf1000000*/ -+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read Revision into toReg bits 7:0 0xd0000000*/ -+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+/* Read Revision into toReg bits 7:0 0xf1000000*/ -+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+ -+#endif /* __INCmvCtrlEnvAsmh */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c -new file mode 100644 -index 0000000..fa097a2 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c -@@ -0,0 +1,1825 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+#include "ctrlEnv/sys/mvSysGbe.h" -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+#include "ctrlEnv/sys/mvSysXor.h" -+#endif -+ -+#if defined(MV_INCLUDE_SATA) -+#include "ctrlEnv/sys/mvSysSata.h" -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+#include "ctrlEnv/sys/mvSysUsb.h" -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+#include "ctrlEnv/sys/mvSysAudio.h" -+#endif -+ -+#if defined(MV_INCLUDE_CESA) -+#include "ctrlEnv/sys/mvSysCesa.h" -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+#include "ctrlEnv/sys/mvSysTs.h" -+#endif -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/******************************************************************************* -+* mvCtrlEnvInit - Initialize Marvell controller environment. -+* -+* DESCRIPTION: -+* This function get environment information and initialize controller -+* internal/external environment. For example -+* 1) MPP settings according to board MPP macros. -+* NOTE: It is the user responsibility to shut down all DMA channels -+* in device and disable controller sub units interrupts during -+* boot process. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlEnvInit(MV_VOID) -+{ -+ MV_U32 mppGroup; -+ MV_U32 devId; -+ MV_U32 boardId; -+ MV_U32 i; -+ MV_U32 maxMppGrp = 1; -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ MV_U32 mppGroupType = 0; -+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; -+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; -+ -+ devId = mvCtrlModelGet(); -+ boardId= mvBoardIdGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_GROUP; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_GROUP; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_GROUP; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_GROUP; -+ break; -+ } -+ -+ /* MPP Init */ -+ /* We split mpp init to 3 phases: -+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write -+ * in phase 2. -+ * 2. We detect the mpp group type and according the mpp values [35:20]. -+ * 3. We detect the mpp group type and according the mpp values [49:36]. -+ */ -+ /* Mpp phase 1 mpp[19:0] */ -+ /* Read MPP group from board level and assign to MPP register */ -+ for (mppGroup = 0; mppGroup < 3; mppGroup++) -+ { -+ mppVal = mvBoardMppGet(mppGroup); -+ if (mppGroup == 0) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromSPI()) -+ { -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromSPIUseNAND()) -+ { -+ mppVal &= ~0xf0000000; -+ bootVal &= 0xf0000000; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xffffff; -+ bootVal &= 0xffffff; -+ mppVal |= bootVal; -+ } -+ } -+ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xff00; -+ bootVal &= 0xff00; -+ mppVal |= bootVal; -+ } -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ -+ /* Identify MPPs group */ -+ mvBoardMppGroupIdUpdate(); -+ -+ /* Update MPPs mux relevent only on Marvell DB */ -+ if ((boardId == DB_88F6281A_BP_ID) || -+ (boardId == DB_88F6180A_BP_ID)) -+ mvBoardMppMuxSet(); -+ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); -+ -+ /* Mpp phase 2 */ -+ /* Read MPP group from board level and assign to MPP register */ -+ if (devId != MV_6180_DEV_ID) -+ { -+ i = 0; -+ for (mppGroup = 2; mppGroup < 5; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6192A_ID) || -+ (boardId == RD_88F6190A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup1[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 2 is shared mpp[23:16] */ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ } -+ -+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) -+ return MV_OK; -+ -+ /* Mpp phase 3 */ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); -+ /* Read MPP group from board level and assign to MPP register */ -+ i = 0; -+ for (mppGroup = 4; mppGroup < 7; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup2[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 4 is shared mpp[35:32] */ -+ if (mppGroup == 4) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ /* Update SSCG configuration register*/ -+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || -+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) -+ MV_REG_WRITE(0x100d8, 0x53); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlMppRegGet - return reg address of mpp group -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroup - MPP group. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - Register address. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) -+{ -+ MV_U32 ret; -+ -+ switch(mppGroup){ -+ case (0): ret = MPP_CONTROL_REG0; -+ break; -+ case (1): ret = MPP_CONTROL_REG1; -+ break; -+ case (2): ret = MPP_CONTROL_REG2; -+ break; -+ case (3): ret = MPP_CONTROL_REG3; -+ break; -+ case (4): ret = MPP_CONTROL_REG4; -+ break; -+ case (5): ret = MPP_CONTROL_REG5; -+ break; -+ case (6): ret = MPP_CONTROL_REG6; -+ break; -+ default: ret = MPP_CONTROL_REG0; -+ break; -+ } -+ return ret; -+} -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of PEX interfaces. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of PEX interfaces. If controller -+* ID is undefined the function returns '0'. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID) -+{ -+ -+ return MV_PEX_MAX_IF; -+} -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+/******************************************************************************* -+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of etherent port. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of etherent port. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_ETH_MAX_PORTS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_ETH_MAX_PORTS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_ETH_MAX_PORTS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_ETH_MAX_PORTS; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+/******************************************************************************* -+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of XOR channels. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of XOR channels. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID) -+{ -+ return MV_XOR_MAX_CHAN; -+} -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+/******************************************************************************* -+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* returns number of Marvell USB controllers. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlUsbMaxGet(void) -+{ -+ return MV_USB_MAX_PORTS; -+} -+#endif -+ -+ -+#if defined(MV_INCLUDE_NAND) -+/******************************************************************************* -+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if NAND is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlNandSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_NAND; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_NAND; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_NAND; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_NAND; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_SDIO) -+/******************************************************************************* -+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if SDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlSdioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_SDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_SDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_SDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_SDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+/******************************************************************************* -+* mvCtrlTsSupport - Return if this controller has integrated TS flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TS is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTsSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TS; -+ break; -+ } -+ return 0; -+} -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+/******************************************************************************* -+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlAudioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_AUDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_AUDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_AUDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_AUDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TDM) -+/******************************************************************************* -+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TDM is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTdmSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TDM; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TDM; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TDM; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TDM; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+/******************************************************************************* -+* mvCtrlModelGet - Get Marvell controller device model (Id) -+* -+* DESCRIPTION: -+* This function returns 16bit describing the device model (ID) as defined -+* in PCI Device and Vendor ID configuration register offset 0x0. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 16bit desscribing Marvell controller ID -+* -+*******************************************************************************/ -+MV_U16 mvCtrlModelGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = MV_REG_READ(CHIP_BOND_REG); -+ devId &= PCKG_OPT_MASK; -+ -+ switch(devId){ -+ case 2: -+ return MV_6281_DEV_ID; -+ break; -+ case 1: -+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) -+ == MV_6190_DEV_ID) -+ return MV_6190_DEV_ID; -+ else -+ return MV_6192_DEV_ID; -+ break; -+ case 0: -+ return MV_6180_DEV_ID; -+ break; -+ } -+ -+ return 0; -+} -+/******************************************************************************* -+* mvCtrlRevGet - Get Marvell controller device revision number -+* -+* DESCRIPTION: -+* This function returns 8bit describing the device revision as defined -+* in PCI Express Class Code and Revision ID Register. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 8bit desscribing Marvell controller revision number -+* -+*******************************************************************************/ -+MV_U8 mvCtrlRevGet(MV_VOID) -+{ -+ MV_U8 revNum; -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Check pex power state */ -+ MV_U32 pexPower; -+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); -+#endif -+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Return to power off state */ -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); -+#endif -+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); -+} -+ -+/******************************************************************************* -+* mvCtrlNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvCtrlNameGet(char *pNameBuff) -+{ -+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, -+ mvCtrlModelGet(), mvCtrlRevGet()); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision -+* -+* DESCRIPTION: -+* This function returns 32bit value describing both Device ID and Revision -+* as defined in PCI Express Device and Vendor ID Register and device revision -+* as defined in PCI Express Class Code and Revision ID Register. -+ -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing both controller device ID and revision number -+* -+*******************************************************************************/ -+MV_U32 mvCtrlModelRevGet(MV_VOID) -+{ -+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) -+{ -+ -+ switch (mvCtrlModelRevGet()) -+ { -+ case MV_6281_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); -+ break; -+ case MV_6192_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); -+ break; -+ case MV_6180_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); -+ break; -+ case MV_6190_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); -+ break; -+ case MV_6281_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); -+ break; -+ case MV_6192_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); -+ break; -+ case MV_6180_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); -+ break; -+ case MV_6190_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); -+ break; -+ default: -+ mvCtrlNameGet(pNameBuff); -+ break; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ctrlWinOverlapTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given two address windows for overlaping. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if address window overlaps, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ /* check if we have overflow than 4G*/ -+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| -+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) -+ { -+ return MV_TRUE; -+ } -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size-1; -+ winTop2 = winBase2 + pAddrWin2->size-1; -+ -+ -+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || -+ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+/******************************************************************************* -+* ctrlWinWithinWinTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given win1 boundries is within -+* win2 boundries. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size -1; -+ winTop2 = winBase2 + pAddrWin2->size -1; -+ -+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || -+ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+static const char* cntrlName[] = TARGETS_NAME_ARRAY; -+ -+/******************************************************************************* -+* mvCtrlTargetNameGet - Get Marvell controller target name -+* -+* DESCRIPTION: -+* This function convert the trget enumeration to string. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Target name (const MV_8 *) -+*******************************************************************************/ -+const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) -+{ -+ -+ if (target >= MAX_TARGETS) -+ { -+ return "target unknown"; -+ } -+ -+ return cntrlName[target]; -+} -+ -+/******************************************************************************* -+* mvCtrlAddrDecShow - Print the Controller units address decode map. -+* -+* DESCRIPTION: -+* This function the Controller units address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCtrlAddrDecShow(MV_VOID) -+{ -+ mvCpuIfAddDecShow(); -+ mvAhbToMbusAddDecShow(); -+#if defined(MV_INCLUDE_PEX) -+ mvPexAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_USB) -+ mvUsbAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ mvEthAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_XOR) -+ mvXorAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_SATA) -+ mvSataAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ mvAudioAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_TS) -+ mvTsuAddrDecShow(); -+#endif -+} -+ -+/******************************************************************************* -+* ctrlSizeToReg - Extract size value for register assignment. -+* -+* DESCRIPTION: -+* Address decode size parameter must be programed from LSB to MSB as -+* sequence of 1's followed by sequence of 0's. The number of 1's -+* specifies the size of the window in 64 KB granularity (e.g. a -+* value of 0x00ff specifies 256x64k = 16 MB). -+* This function extract the size value from the size parameter according -+* to given aligment paramter. For example for size 0x1000000 (16MB) and -+* aligment 0x10000 (64KB) the function will return 0x00FF. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size register value correspond to size parameter. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 retVal; -+ -+ /* Check size parameter alignment */ -+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); -+ return -1; -+ } -+ -+ /* Take out the "alignment" portion out of the size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ /* and size is 0x1000000 (16MB) for example */ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ -+ alignment = (alignment >> 1); -+ } -+ -+ /* If after the alignment first '0' was met we still have '1' in */ -+ /* it then aligment is invalid (not power of 2) */ -+ if (alignment) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ (MV_U32)alignment)); -+ return -1; -+ } -+ -+ /* Now the size is shifted right according to aligment: 0x0100 */ -+ size--; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ retVal = size ; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ while(size & 1) /* Check that LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", -+ size)); -+ return -1; -+ } -+ -+ return retVal; -+ -+} -+ -+/******************************************************************************* -+* ctrlRegToSize - Extract size value from register value. -+* -+* DESCRIPTION: -+* This function extract a size value from the register size parameter -+* according to given aligment paramter. For example for register size -+* value 0xff and aligment 0x10000 the function will return 0x01000000. -+* -+* INPUT: -+* regSize - Size as in register format. See ctrlSizeToReg. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) -+{ -+ MV_U32 temp; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ while(temp & 1) /* Check that LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", -+ regSize)); -+ return -1; -+ } -+ -+ -+ /* Check that aligment is a power of two */ -+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ -+ -+ while(temp & 1) /* Check that alignmet LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ -+ } -+ -+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ -+ /* then 'temp' is invalid (not power of 2) */ -+ if (temp) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ alignment)); -+ return -1; -+ } -+ -+ regSize++; /* Now the size is 0x0100 */ -+ -+ /* Add in the "alignment" portion to the register size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ -+ alignment = (alignment >> 1); -+ } -+ -+ return regSize; -+} -+ -+ -+/******************************************************************************* -+* ctrlSizeRegRoundUp - Round up given size -+* -+* DESCRIPTION: -+* This function round up a given size to a size that fits the -+* restrictions of size format given an aligment parameter. -+* to given aligment paramter. For example for size parameter 0xa1000 and -+* aligment 0x1000 the function will return 0xFF000. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size value correspond to size in register. -+*******************************************************************************/ -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 msbBit = 0; -+ MV_U32 retSize; -+ -+ /* Check if size parameter is already comply with restriction */ -+ if (!(-1 == ctrlSizeToReg(size, alignment))) -+ { -+ return size; -+ } -+ -+ while(size) -+ { -+ size = (size >> 1); -+ msbBit++; -+ } -+ -+ retSize = (1 << msbBit); -+ -+ if (retSize < alignment) -+ { -+ return alignment; -+ } -+ else -+ { -+ return retSize; -+ } -+} -+/******************************************************************************* -+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button -+* was pressed and clear counter -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: number of milliseconds the reset button was pressed -+*******************************************************************************/ -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) -+{ -+ static volatile MV_U32 Count = 0; -+ -+ if(!Count) { -+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); -+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); -+ /* clear counter for next boot */ -+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); -+ } -+ -+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); -+ -+ return Count; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return MV_FALSE; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ -+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+/******************************************************************************* -+* mvCtrlPwrSaveOn - Set Power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOn(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+ -+ -+/******************************************************************************* -+* mvCtrlPwrSaveOff - Go out of power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOff(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckSet - Set Power State for specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+ -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckGet - Get Power State of specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+/******************************************************************************* -+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+#else -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} -+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ -+ -+ -+/******************************************************************************* -+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToSPI(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -+/******************************************************************************* -+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToDefault(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = mvBoardMppGet(0); -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ mppVal &= ~0xffff000f; -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h -new file mode 100644 -index 0000000..0f8d2b4 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvLibh -+#define __INCmvCtrlEnvLibh -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mvOs.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+ -+/* typedefs */ -+ -+/* This enumerator describes the possible HW cache coherency policies the */ -+/* controllers supports. */ -+typedef enum _mvCachePolicy -+{ -+ NO_COHERENCY, /* No HW cache coherency support */ -+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ -+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ -+}MV_CACHE_POLICY; -+ -+ -+/* The swapping is referred to a 64-bit words (as this is the controller */ -+/* internal data path width). This enumerator describes the possible */ -+/* data swap types. Below is an example of the data 0x0011223344556677 */ -+typedef enum _mvSwapType -+{ -+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ -+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ -+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ -+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ -+ SWAP_TYPE_MAX /* Delimiter for this enumerator */ -+}MV_SWAP_TYPE; -+ -+/* This structure describes access rights for Access protection windows */ -+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ -+/* Note that the permission enumerator coresponds to its register format. */ -+/* For example, Read only premission is presented as "1" in register field. */ -+typedef enum _mvAccessRights -+{ -+ NO_ACCESS_ALLOWED = 0, /* No access allowed */ -+ READ_ONLY = 1, /* Read only permission */ -+ ACC_RESERVED = 2, /* Reserved access right */ -+ FULL_ACCESS = 3, /* Read and Write permission */ -+ MAX_ACC_RIGHTS -+}MV_ACCESS_RIGHTS; -+ -+ -+/* mcspLib.h API list */ -+ -+MV_STATUS mvCtrlEnvInit(MV_VOID); -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); -+ -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID); -+#else -+#define mvCtrlPexMaxIfGet() (0) -+#endif -+ -+#define mvCtrlPciIfMaxIfGet() (0) -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_XOR) -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_USB) -+MV_U32 mvCtrlUsbMaxGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_NAND) -+MV_U32 mvCtrlNandSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_SDIO) -+MV_U32 mvCtrlSdioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TS) -+MV_U32 mvCtrlTsSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+MV_U32 mvCtrlAudioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TDM) -+MV_U32 mvCtrlTdmSupport(MV_VOID); -+#endif -+ -+MV_U16 mvCtrlModelGet(MV_VOID); -+MV_U8 mvCtrlRevGet(MV_VOID); -+MV_STATUS mvCtrlNameGet(char *pNameBuff); -+MV_U32 mvCtrlModelRevGet(MV_VOID); -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); -+MV_VOID mvCtrlAddrDecShow(MV_VOID); -+const MV_8* mvCtrlTargetNameGet(MV_TARGET target); -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+MV_VOID mvCtrlPwrSaveOn(MV_VOID); -+MV_VOID mvCtrlPwrSaveOff(MV_VOID); -+#endif -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvMPPConfigToSPI(MV_VOID); -+MV_VOID mvMPPConfigToDefault(MV_VOID); -+ -+ -+#endif /* __INCmvCtrlEnvLibh */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h -new file mode 100644 -index 0000000..b889e24 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h -@@ -0,0 +1,419 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvRegsh -+#define __INCmvCtrlEnvRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* CV Support */ -+#define PEX0_MEM0 PEX0_MEM -+#define PCI0_MEM0 PEX0_MEM -+ -+/* Controller revision info */ -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+/* Controler environment registers offsets */ -+ -+/* Power Managment Control */ -+#define POWER_MNG_MEM_CTRL_REG 0x20118 -+ -+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) -+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+ -+#define PMC_PEXSTOPMEM_OFFS 1 -+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) -+ -+#define PMC_USBSTOPMEM_OFFS 2 -+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) -+ -+#define PMC_DUNITSTOPMEM_OFFS 3 -+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) -+ -+#define PMC_RUNITSTOPMEM_OFFS 4 -+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) -+ -+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) -+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+ -+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) -+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+ -+#define PMC_SESTOPMEM_OFFS 8 -+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) -+ -+#define PMC_AUDIOSTOPMEM_OFFS 9 -+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) -+ -+#define POWER_MNG_CTRL_REG 0x2011C -+ -+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) -+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) -+ -+#define PMC_PEXPHYSTOPCLOCK_OFFS 1 -+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) -+ -+#define PMC_PEXSTOPCLOCK_OFFS 2 -+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) -+ -+#define PMC_USBSTOPCLOCK_OFFS 3 -+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) -+ -+#define PMC_SDIOSTOPCLOCK_OFFS 4 -+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) -+ -+#define PMC_TSSTOPCLOCK_OFFS 5 -+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) -+ -+#define PMC_AUDIOSTOPCLOCK_OFFS 9 -+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) -+ -+#define PMC_POWERSAVE_OFFS 11 -+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) -+ -+ -+ -+ -+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) -+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) -+ -+#define PMC_SESTOPCLOCK_OFFS 17 -+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) -+ -+#define PMC_TDMSTOPCLOCK_OFFS 20 -+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) -+ -+ -+/* Controler environment registers offsets */ -+#define MPP_CONTROL_REG0 0x10000 -+#define MPP_CONTROL_REG1 0x10004 -+#define MPP_CONTROL_REG2 0x10008 -+#define MPP_CONTROL_REG3 0x1000C -+#define MPP_CONTROL_REG4 0x10010 -+#define MPP_CONTROL_REG5 0x10014 -+#define MPP_CONTROL_REG6 0x10018 -+#define MPP_SAMPLE_AT_RESET 0x10030 -+#define CHIP_BOND_REG 0x10034 -+#define SYSRST_LENGTH_COUNTER_REG 0x10050 -+#define SLCR_COUNT_OFFS 0 -+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) -+#define SLCR_CLR_OFFS 31 -+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) -+#define PCKG_OPT_MASK 0x3 -+#define MPP_OUTPUT_DRIVE_REG 0x100E0 -+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 -+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 -+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+ -+#define MSAR_BOOT_MODE_OFFS 12 -+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) -+ -+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ -+ ((X & 0x2) << 1)) -+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 -+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 -+ -+#define MSAR_TCLCK_OFFS 21 -+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) -+ -+ -+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ -+ ((X & 0x18) >> 1)) -+ -+#define MSAR_CPUCLCK_OFFS_6180 2 -+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) -+ -+#define MSAR_DDRCLCK_RTIO_OFFS 5 -+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) -+ -+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) -+ -+#ifndef MV_ASMLANGUAGE -+/* CPU clock for 6281,6192 0->Resereved */ -+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ -+ 600000000, 0, 800000000, 1000000000, \ -+ 0, 1200000000, 0, 0, \ -+ 1500000000, 0, 0, 0} -+ -+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ -+#define MV_DDR_CLCK_RTIO_TBL {\ -+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ -+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ -+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ -+#define MV_L2_CLCK_RTIO_TBL {\ -+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* 6180 have different clk reset sampling */ -+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ -+#define MV_CPU6180_DDR_L2_CLCK_TBL { \ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {600000000, 200000000, 300000000 },\ -+ {800000000, 200000000, 400000000 },\ -+ {0, 0, 0 }\ -+} -+ -+ -+ -+/* These macros help units to identify a target Mbus Arbiter group */ -+#define MV_TARGET_IS_DRAM(target) \ -+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) -+ -+#define MV_TARGET_IS_PEX0(target) \ -+ ((target >= PEX0_MEM) && (target <= PEX0_IO)) -+ -+#define MV_TARGET_IS_PEX1(target) 0 -+ -+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) -+ -+#define MV_TARGET_IS_DEVICE(target) \ -+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) -+ -+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 -+ -+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ -+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ -+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ -+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) -+ -+ -+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ -+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ -+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ -+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ -+ >> MSAR_BOOT_MODE_OFFS)]:(target)) -+ -+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ -+ -+#define BOOT_TARGETS_NAME_ARRAY { \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+#define BOOT_TARGETS_NAME_ARRAY_6180 { \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+ -+/* For old competability */ -+#define DEVICE_CS0 NFLASH_CS -+#define DEVICE_CS1 SPI_CS -+#define DEVICE_CS2 BOOT_ROM_CS -+#define DEVICE_CS3 DEV_BOOCS -+#define MV_BOOTDEVICE_INDEX 0 -+ -+#define START_DEV_CS DEV_CS0 -+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) -+ -+#define PCI_IF0_MEM0 PEX0_MEM -+#define PCI_IF0_IO PEX0_IO -+ -+ -+/* This enumerator defines the Marvell controller target ID */ -+typedef enum _mvTargetId -+{ -+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ -+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ -+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ -+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ -+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ -+ MAX_TARGETS_ID -+}MV_TARGET_ID; -+ -+ -+/* This enumerator described the possible Controller paripheral targets. */ -+/* Controller peripherals are designated memory/IO address spaces that the */ -+/* controller can access. They are also refered as "targets" */ -+typedef enum _mvTarget -+{ -+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ -+ SDRAM_CS0, /* SDRAM chip select 0 */ -+ SDRAM_CS1, /* SDRAM chip select 1 */ -+ SDRAM_CS2, /* SDRAM chip select 2 */ -+ SDRAM_CS3, /* SDRAM chip select 3 */ -+ PEX0_MEM, /* PCI Express 0 Memory */ -+ PEX0_IO, /* PCI Express 0 IO */ -+ INTER_REGS, /* Internal registers */ -+ NFLASH_CS, /* NFLASH_CS */ -+ SPI_CS, /* SPI_CS */ -+ BOOT_ROM_CS, /* BOOT_ROM_CS */ -+ DEV_BOOCS, /* DEV_BOOCS */ -+ CRYPT_ENG, /* Crypto Engine */ -+#ifdef MV_INCLUDE_SAGE -+ SAGE_UNIT, /* SAGE Unit */ -+#endif -+ MAX_TARGETS -+ -+}MV_TARGET; -+ -+#define TARGETS_DEF_ARRAY { \ -+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ -+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ -+ {0xFF, 0xFF }, /* INTER_REGS */ \ -+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ -+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ -+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ -+ {0x00, SAGE_TARGET_ID } \ -+} -+ -+ -+#define TARGETS_NAME_ARRAY { \ -+ "SDRAM_CS0", /* SDRAM_CS0 */ \ -+ "SDRAM_CS1", /* SDRAM_CS1 */ \ -+ "SDRAM_CS2", /* SDRAM_CS2 */ \ -+ "SDRAM_CS3", /* SDRAM_CS3 */ \ -+ "PEX0_MEM", /* PEX0_MEM */ \ -+ "PEX0_IO", /* PEX0_IO */ \ -+ "INTER_REGS", /* INTER_REGS */ \ -+ "NFLASH_CS", /* NFLASH_CS */ \ -+ "SPI_CS", /* SPI_CS */ \ -+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ -+ "DEV_BOOTCS", /* DEV_BOOCS */ \ -+ "CRYPT_ENG", /* CRYPT_ENG */ \ -+ "SAGE_UNIT" /* SAGE_UNIT */ \ -+} -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h -new file mode 100644 -index 0000000..12d2066 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h -@@ -0,0 +1,257 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvSpech -+#define __INCmvCtrlEnvSpech -+ -+#include "mvDeviceId.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#define MV_ARM_SOC -+#define SOC_NAME_PREFIX "MV88F" -+ -+ -+/* units base and port numbers */ -+#ifdef MV_ASMLANGUAGE -+#define XOR_UNIT_BASE(unit) 0x60800 -+#else -+#define MV_XOR_REG_BASE 0x60000 -+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) -+#endif -+ -+#define TDM_REG_BASE 0xD0000 -+#define USB_REG_BASE(dev) 0x50000 -+#define AUDIO_REG_BASE 0xA0000 -+#define SATA_REG_BASE 0x80000 -+#define MV_CESA_REG_BASE 0x3D000 -+#define MV_CESA_TDMA_REG_BASE 0x30000 -+#define MV_SDIO_REG_BASE 0x90000 -+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) -+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) -+#define DRAM_BASE 0x0 -+#define CNTMR_BASE 0x20300 -+#define TWSI_SLAVE_BASE(chanNum) 0x11000 -+#define PEX_IF_BASE(pexIf) 0x40000 -+#define MPP_REG_BASE 0x10000 -+#define TSU_GLOBAL_REG_BASE 0xB4000 -+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 -+ -+#define INTER_REGS_SIZE _1M -+/* This define describes the TWSI interrupt bit and location */ -+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define TWSI0_CPU_MAIN_INT_BIT (1<<29) -+#define TWSI_SPEED 100000 -+ -+#define MV_GPP_MAX_GROUP 2 -+#define MV_CNTMR_MAX_COUNTER 2 -+#define MV_UART_MAX_CHAN 2 -+#define MV_XOR_MAX_UNIT 2 -+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ -+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ -+#define MV_SATA_MAX_CHAN 2 -+ -+#define MV_6281_MPP_MAX_MODULE 2 -+#define MV_6192_MPP_MAX_MODULE 1 -+#define MV_6190_MPP_MAX_MODULE 1 -+#define MV_6180_MPP_MAX_MODULE 2 -+#define MV_6281_MPP_MAX_GROUP 7 -+#define MV_6192_MPP_MAX_GROUP 4 -+#define MV_6190_MPP_MAX_GROUP 4 -+#define MV_6180_MPP_MAX_GROUP 3 -+ -+#define MV_DRAM_MAX_CS 4 -+ -+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ -+#define MV_PCI_MAX_IF 0 -+#define MV_PCI_START_IF 0 -+ -+/* This define describes the maximum number of supported PEX Interfaces */ -+#define MV_INCLUDE_PEX0 -+#define MV_DISABLE_PEX_DEVICE_BAR -+#define MV_PEX_MAX_IF 1 -+#define MV_PEX_START_IF MV_PCI_MAX_IF -+ -+/* This define describes the maximum number of supported PCI Interfaces */ -+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) -+ -+#define MV_ETH_MAX_PORTS 2 -+#define MV_6281_ETH_MAX_PORTS 2 -+#define MV_6192_ETH_MAX_PORTS 2 -+#define MV_6190_ETH_MAX_PORTS 1 -+#define MV_6180_ETH_MAX_PORTS 1 -+ -+#define MV_IDMA_MAX_CHAN 0 -+ -+#define MV_USB_MAX_PORTS 1 -+ -+#define MV_USB_VERSION 1 -+ -+ -+#define MV_6281_NAND 1 -+#define MV_6192_NAND 1 -+#define MV_6190_NAND 1 -+#define MV_6180_NAND 0 -+ -+#define MV_6281_SDIO 1 -+#define MV_6192_SDIO 1 -+#define MV_6190_SDIO 1 -+#define MV_6180_SDIO 1 -+ -+#define MV_6281_TS 1 -+#define MV_6192_TS 1 -+#define MV_6190_TS 0 -+#define MV_6180_TS 0 -+ -+#define MV_6281_AUDIO 1 -+#define MV_6192_AUDIO 1 -+#define MV_6190_AUDIO 0 -+#define MV_6180_AUDIO 1 -+ -+#define MV_6281_TDM 1 -+#define MV_6192_TDM 1 -+#define MV_6190_TDM 0 -+#define MV_6180_TDM 0 -+ -+#define MV_DEVICE_MAX_CS 4 -+ -+/* Others */ -+#define PEX_HOST_BUS_NUM(pciIf) (pciIf) -+#define PEX_HOST_DEV_NUM(pciIf) 0 -+ -+#define PCI_IO(pciIf) (PEX0_IO) -+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) -+/* CESA version #2: One channel, 2KB SRAM, TDMA */ -+#if defined(MV_CESA_CHAIN_MODE_SUPPORT) -+ #define MV_CESA_VERSION 3 -+#else -+#define MV_CESA_VERSION 2 -+#endif -+#define MV_CESA_SRAM_SIZE 2*1024 -+/* This define describes the maximum number of supported Ethernet ports */ -+#define MV_ETH_VERSION 4 -+#define MV_ETH_MAX_RXQ 8 -+#define MV_ETH_MAX_TXQ 8 -+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } -+/* This define describes the the support of USB */ -+#define MV_USB_VERSION 1 -+ -+#define MV_INCLUDE_SDRAM_CS0 -+#define MV_INCLUDE_SDRAM_CS1 -+#define MV_INCLUDE_SDRAM_CS2 -+#define MV_INCLUDE_SDRAM_CS3 -+ -+#define MV_INCLUDE_DEVICE_CS0 -+#define MV_INCLUDE_DEVICE_CS1 -+#define MV_INCLUDE_DEVICE_CS2 -+#define MV_INCLUDE_DEVICE_CS3 -+ -+#define MPP_GROUP_1_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ -+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ -+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ -+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ -+ {0x33330000, 0x33333333, 0x3333} /* MII */ \ -+} -+ -+#define MPP_GROUP_2_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0x11110000, 0x11111111, 0x01} /* TS */ \ -+} -+ -+#ifndef MV_ASMLANGUAGE -+ -+/* This enumerator defines the Marvell Units ID */ -+typedef enum _mvUnitId -+{ -+ DRAM_UNIT_ID, -+ PEX_UNIT_ID, -+ ETH_GIG_UNIT_ID, -+ USB_UNIT_ID, -+ IDMA_UNIT_ID, -+ XOR_UNIT_ID, -+ SATA_UNIT_ID, -+ TDM_UNIT_ID, -+ UART_UNIT_ID, -+ CESA_UNIT_ID, -+ SPI_UNIT_ID, -+ AUDIO_UNIT_ID, -+ SDIO_UNIT_ID, -+ TS_UNIT_ID, -+ MAX_UNITS_ID -+ -+}MV_UNIT_ID; -+ -+#endif -+ -+#endif /* __INCmvCtrlEnvSpech */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c -new file mode 100644 -index 0000000..d22c4fc ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c -@@ -0,0 +1,1048 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#undef MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* typedefs */ -+ -+ -+/* CPU address remap registers offsets are inconsecutive. This struct */ -+/* describes address remap register offsets */ -+typedef struct _ahbToMbusRemapRegOffs -+{ -+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ -+ MV_U32 highRegOffs; /* High 32 bit remap register offset */ -+}AHB_TO_MBUS_REMAP_REG_OFFS; -+ -+/* locals */ -+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); -+ -+/******************************************************************************* -+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK laways. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusInit(void) -+{ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* This function sets -+* address window, also known as address decode window. -+* A new address decode window is set for specified winNum address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the winNum window, allowing CPU to access -+* the winNum window. -+* -+* INPUT: -+* winNum - Windows number. -+* pAddrDecWin - CPU winNum window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU winNum window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* read base register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read control register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; -+ -+#if !defined(MV_RUN_FROM_FLASH) -+ /* To be on the safe side we disable the window before writing the */ -+ /* new values. */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ mvAhbToMbusWinEnable(winNum,MV_FALSE); -+ } -+#endif -+ -+ /* 3) Write to address decode Base Address Register */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); -+ } -+ -+ -+ /* Internal register space have no size */ -+ /* register. Do not perform size register assigment for those targets */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral winNum address window. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU winNum window information data structure. -+* -+* RETURN: -+* MV_OK if winNum exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* Internal register space size have no size register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ else -+ { -+ decRegs.sizeReg = 0; -+ } -+ -+ -+ /* Read base and size */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrDecWin->target = INTER_REGS; -+ pAddrDecWin->enable = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ -+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> -+ ATMWCR_WIN_ATTR_OFFS; -+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> -+ ATMWCR_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ if (INTER_REGS == target) -+ { -+ return MV_AHB_TO_MBUS_INTREG_WIN; -+ } -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if (decWin.target == target) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+ -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinAvailGet - Get First Available window number. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_FALSE) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other winNum window. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) -+{ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ /* Internal registers bar can't be disable or enabled */ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ return (enable ? MV_OK : MV_ERROR); -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* enable the window */ -+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* After a CPU address hits one of PCI address decode windows there is an -+* option to remap the address to a different one. For example, CPU -+* executes a read from PCI winNum window address 0x1200.0000. This -+* can be modified so the address on the PCI bus would be 0x1400.0000 -+* Using the PCI address remap mechanism. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. Must be a PCI winNum. -+* pAddrDecWin - CPU winNum window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddr; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; -+ -+ MV_U32 effectiveBaseAddress=0, -+ baseAddrValue=0,windowSizeValue=0; -+ -+ -+ /* Get registers offsets of given winNum */ -+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) -+ { -+ return 0xffffffff; -+ } -+ -+ /* 1) Set address remap low */ -+ baseAddr = pAddrWin->baseLow; -+ -+ /* Check base address aligment */ -+ /* -+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", -+ baseAddr); -+ return MV_ERROR; -+ } -+ */ -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; -+ -+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); -+ -+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); -+ -+ -+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ -+ baseAddrValue &= ATMWBR_BASE_MASK; -+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; -+ -+ /* Start calculating the effective Base Address */ -+ effectiveBaseAddress = baseAddrValue ; -+ -+ /* The effective base address will be combined from the chopped (if any) -+ remap value (according to the size value and remap mechanism) and the -+ window's base address */ -+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); -+ /* If the effectiveBaseAddress exceed the window boundaries return an -+ invalid value. */ -+ -+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); -+ return 0xffffffff; -+ } -+ -+ return effectiveBaseAddress; -+ -+ -+} -+/******************************************************************************* -+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets -+* -+* DESCRIPTION: -+* -+* INPUT: -+* target1 - CPU Interface target 1 -+* target2 - CPU Interface target 2 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if targets are illigal, or if one of the targets is not -+* associated to a valid window . -+* MV_OK otherwise. -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) -+{ -+ MV_U32 winNum1,winNum2; -+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; -+ MV_U32 remapBaseLow1=0,remapBaseLow2=0; -+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; -+ -+ -+ /* Check parameters */ -+ if (target1 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ if (target2 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ -+ /* get window associated with this target */ -+ winNum1 = mvAhbToMbusWinTargetGet(target1); -+ -+ if (winNum1 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target1,winNum1); -+ return MV_ERROR; -+ -+ } -+ -+ /* get window associated with this target */ -+ winNum2 = mvAhbToMbusWinTargetGet(target2); -+ -+ if (winNum2 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target2,winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ /* now Get original values of both Windows */ -+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* disable both windows */ -+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* now swap targets */ -+ -+ /* first save winDec2 values */ -+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; -+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; -+ winDecTemp.addrWin.size = winDec2.addrWin.size; -+ winDecTemp.enable = winDec2.enable; -+ winDecTemp.target = winDec2.target; -+ -+ /* winDec2 = winDec1 */ -+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; -+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; -+ winDec2.addrWin.size = winDec1.addrWin.size; -+ winDec2.enable = winDec1.enable; -+ winDec2.target = winDec1.target; -+ -+ -+ /* winDec1 = winDecTemp */ -+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; -+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; -+ winDec1.addrWin.size = winDecTemp.addrWin.size; -+ winDec1.enable = winDecTemp.enable; -+ winDec1.target = winDecTemp.target; -+ -+ -+ /* now set the new values */ -+ -+ -+ mvAhbToMbusWinSet(winNum1,&winDec1); -+ mvAhbToMbusWinSet(winNum2,&winDec2); -+ -+ -+ -+ -+ -+ /* now we will treat the remap windows if exist */ -+ -+ -+ /* now check if one or both windows has a remap window -+ as well after the swap ! */ -+ -+ /* if a window had a remap value differnt than the base value -+ before the swap , then after the swap the remap value will be -+ equal to the base value unless both windows has a remap windows*/ -+ -+ /* first get old values */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); -+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); -+ -+ } -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); -+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); -+ -+ -+ } -+ -+ /* now do the swap */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* Two windows has a remap !!! so swap */ -+ -+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); -+ -+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); -+ -+ -+ -+ } -+ else -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); -+ -+ } -+ -+ } -+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); -+ -+ } -+ -+ -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+ -+#if defined(MV_88F1181) -+ -+/******************************************************************************* -+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. -+* -+* DESCRIPTION: -+* This function sets CPU Mbus Arbiter -+* -+* INPUT: -+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At -+* each clock cycle, the crossbar arbiter samples all -+* requests and gives the bus to the next agent according -+* to the "pizza". -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) -+{ -+ MV_U32 sliceNum; -+ MV_U32 xbarCtrl = 0; -+ MV_MBUS_ARB_TARGET xbarTarget; -+ -+ /* 1) Set crossbar control low register */ -+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) -+ { -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control low register */ -+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); -+ -+ xbarCtrl = 0; -+ -+ /* 2) Set crossbar control high register */ -+ for (sliceNum = MRLR_SLICE_NUM; -+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; -+ sliceNum++) -+ { -+ -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control high register */ -+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlSet - Set MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ if (ctrl->highPrio == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ -+ if (ctrl->fixedRoundRobin == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ -+ if (ctrl->starvEn == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlGet - Get MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); -+ -+ if (ctrlReg & MACR_ARB_ARM_TOP) -+ { -+ ctrl->highPrio = MV_TRUE; -+ } -+ else -+ { -+ ctrl->highPrio = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_TARGET_FIXED) -+ { -+ ctrl->fixedRoundRobin = MV_TRUE; -+ } -+ else -+ { -+ ctrl->fixedRoundRobin = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) -+ { -+ ctrl->starvEn = MV_TRUE; -+ } -+ else -+ { -+ ctrl->starvEn = MV_FALSE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+ -+/******************************************************************************* -+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets -+* -+* DESCRIPTION: -+* CPU to PCI address remap registers offsets are inconsecutive. -+* This function returns PCI address remap registers offsets. -+* -+* INPUT: -+* winNum - Address decode window number. See MV_U32 enumerator. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one. -+* -+*******************************************************************************/ -+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) -+{ -+ switch (winNum) -+ { -+ case 0: -+ case 1: -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ case 2: -+ case 3: -+ if((mvCtrlModelGet() == MV_5281_DEV_ID) || -+ (mvCtrlModelGet() == MV_1281_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183L_DEV_ID)) -+ { -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ } -+ else -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ default: -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN win; -+ MV_U32 winNum; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AHB To MBUS Bridge:\n" ); -+ mvOsOutput( "-------------------\n" ); -+ -+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) -+ { -+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h -new file mode 100644 -index 0000000..a1d93b7 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h -@@ -0,0 +1,130 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbush -+#define __INCmvAhbToMbush -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* defines */ -+ -+#if defined(MV_88F1181) -+/* This enumerator defines the Marvell controller possible MBUS arbiter */ -+/* target ports. It is used to define crossbar priority scheame (pizza) */ -+typedef enum _mvMBusArbTargetId -+{ -+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ -+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ -+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ -+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ -+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ -+ MAX_MBUS_ARB_TARGETS -+}MV_MBUS_ARB_TARGET; -+ -+typedef struct _mvMBusArbCtrl -+{ -+ MV_BOOL starvEn; -+ MV_BOOL highPrio; -+ MV_BOOL fixedRoundRobin; -+ -+}MV_MBUS_ARB_CTRL; -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+typedef struct _mvAhbtoMbusDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_AHB_TO_MBUS_DEC_WIN; -+ -+/* mvAhbToMbus.h API list */ -+ -+MV_STATUS mvAhbToMbusInit(MV_VOID); -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); -+ -+#if defined(MV_88F1181) -+ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID); -+ -+ -+#endif /* __INCmvAhbToMbush */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h -new file mode 100644 -index 0000000..c5682e8 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h -@@ -0,0 +1,143 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbusRegsh -+#define __INCmvAhbToMbusRegsh -+ -+/******************************/ -+/* ARM Address Map Registers */ -+/******************************/ -+ -+#define MAX_AHB_TO_MBUS_WINS 9 -+#define MV_AHB_TO_MBUS_INTREG_WIN 8 -+ -+ -+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 -+ -+/* Window Control Register */ -+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ -+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ -+ -+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated -+ with this window*/ -+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) -+ -+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes -+ Associated with this window */ -+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) -+ -+ -+/* -+Used with the Base register to set the address window size and location -+Must be programed from LSB to MSB as sequence of 1’s followed -+by sequence of 0’s. The number of 1’s specifies the size of the window -+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). -+ -+NOTE: A value of 0x0 specifies 64KB size. -+*/ -+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ -+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) -+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 -+ -+/* Window Base Register */ -+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ -+ -+/* -+Used with the size field to set the address window size and location. -+Corresponds to transaction address[31:16] -+*/ -+#define ATMWBR_BASE_OFFS 16 /* Base Address */ -+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) -+#define ATMWBR_BASE_ALIGNMENT 0x10000 -+ -+/* Window Remap Low Register */ -+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ -+ -+/* -+Used with the size field to specifies address bits[31:0] to be driven to -+the target interface.: -+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) -+*/ -+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ -+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) -+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 -+ -+/* Window Remap High Register */ -+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ -+ -+/* -+Specifies address bits[63:32] to be driven to the target interface. -+target_addr[63:32] = (RemapHigh[31:0] -+*/ -+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ -+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) -+ -+ -+#endif /* __INCmvAhbToMbusRegsh */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c -new file mode 100644 -index 0000000..396f003 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c -@@ -0,0 +1,1036 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "mvSysDram.h" -+ -+/*#define MV_DEBUG*/ -+/* defines */ -+ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+/* static functions */ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+MV_TARGET * sampleAtResetTargetArray; -+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; -+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; -+/******************************************************************************* -+* mvCpuIfInit - Initialize Controller CPU interface -+* -+* DESCRIPTION: -+* This function initialize Controller CPU interface: -+* 1. Set CPU interface configuration registers. -+* 2. Set CPU master Pizza arbiter control according to static -+* configuration described in configuration file. -+* 3. Opens CPU address decode windows. DRAM windows are assumed to be -+* already set (auto detection). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) -+{ -+ MV_U32 regVal; -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; -+ -+ if (cpuAddrWinMap == NULL) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); -+ return MV_ERROR; -+ } -+ -+ /*Initialize the boot target array according to device type*/ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; -+ else -+ sampleAtResetTargetArray = sampleAtResetTargetArrayP; -+ -+ /* Set ARM Configuration register */ -+ regVal = MV_REG_READ(CPU_CONFIG_REG); -+ regVal &= ~CPU_CONFIG_DEFAULT_MASK; -+ regVal |= CPU_CONFIG_DEFAULT; -+ MV_REG_WRITE(CPU_CONFIG_REG,regVal); -+ -+ /* First disable all CPU target windows */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) -+ { -+ continue; -+ } -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+#if defined(MV_RUN_FROM_FLASH) -+ /* Don't disable the boot device. */ -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); -+ } -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Resize the bootcs windows before other windows, because this */ -+ /* window is enabled and will cause an overlap if not resized. */ -+ target = DEV_BOOCS; -+ -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* Go through all targets in user table until table terminator */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ -+#if defined(MV_RUN_FROM_FLASH) -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ -+ /* assuming this already has been done earlier. */ -+#ifdef MV_DRAM_AUTO_SIZE -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+ /* If the target attribute is the same as the boot device attribute */ -+ /* then it's stays disable */ -+ if (MV_TARGET_IS_AS_BOOT(target)) -+ { -+ continue; -+ } -+ -+ if((0 == cpuAddrWinMap[target].addrWin.size) || -+ (DIS == cpuAddrWinMap[target].enable)) -+ -+ { -+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+ -+ } -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) -+* address window, also known as address decode window. -+* A new address decode window is set for specified target address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the target window, allowing CPU to access -+* the target window. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - CPU target window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU target window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU target window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the target is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 existingWinNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ /* copy relevant data to MV_DRAM_DEC_WIN structure */ -+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; -+ addrDecWin.enable = pAddrDecWin->enable; -+ -+ -+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ -+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ decWin.addrWin.size = pAddrDecWin->addrWin.size; -+ decWin.enable = pAddrDecWin->enable; -+ decWin.target = target; -+ -+ existingWinNum = mvAhbToMbusWinTargetGet(target); -+ -+ /* check if there is already another Window configured -+ for this target */ -+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& -+ (existingWinNum != pAddrDecWin->winNum)) -+ { -+ /* if we want to enable the new winow number -+ passed by the user , then the old one should -+ be disabled */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ /* be sure it is disabled */ -+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); -+ } -+ } -+ -+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral target address window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU target window information data structure. -+* -+* RETURN: -+* MV_OK if target exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_U32 winNum=0xffffffff; -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", -+ target); -+ return MV_ERROR; -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; -+ pAddrDecWin->enable = addrDecWin.enable; -+ pAddrDecWin->winNum = 0xffffffff; -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return MV_NO_SUCH; -+ -+ } -+ -+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) -+ { -+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", -+ __FUNCTION__, winNum); -+ return MV_ERROR; -+ -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = decWin.addrWin.size; -+ pAddrDecWin->enable = decWin.enable; -+ pAddrDecWin->winNum = winNum; -+ -+ } -+ -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other target window. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_U32 winNum, temp; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* get the window and check if it exist */ -+ temp = mvCpuIfTargetWinGet(target, &addrDecWin); -+ if (MV_NO_SUCH == temp) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ else if( MV_OK != temp) -+ { -+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); -+ return MV_ERROR; -+ } -+ -+ -+ /* check overlap */ -+ -+ if (MV_TRUE == enable) -+ { -+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinEnable(target , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ -+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSizeGet - Get CPU target address window size -+* -+* DESCRIPTION: -+* Get the size of CPU-to-peripheral target window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit size. Function also returns '0' if window is closed. -+* Function returns 0xFFFFFFFF in case of an error. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); -+ return 0; -+ } -+ -+ /* Get the winNum window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0; -+ } -+ -+ /* Check if window is enabled */ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ return (addrDecWin.addrWin.size); -+ } -+ else -+ { -+ return 0; /* Window disabled. return 0 */ -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target low base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit low base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0xffffffff; -+ } -+ return (addrDecWin.addrWin.baseLow); -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target high base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit high base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0; -+ } -+ -+ return (addrDecWin.addrWin.baseHigh); -+} -+ -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCpuIfPexRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pexTarget - Peripheral target enumerator. Must be a PEX target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PEX one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ -+ if (mvCtrlPexMaxIfGet() > 1) -+ { -+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ else -+ { -+ if (!MV_TARGET_IS_PEX0(pexTarget)) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pexTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+ -+#endif -+ -+#if defined(MV_INCLUDE_PCI) -+/******************************************************************************* -+* mvCpuIfPciRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_PCI(pciTarget)) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); -+ return 0xffffffff; -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pciTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+#endif /* MV_INCLUDE_PCI */ -+ -+ -+/******************************************************************************* -+* mvCpuIfPciIfRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+#if defined(MV_INCLUDE_PEX) -+ if (MV_TARGET_IS_PEX(pciIfTarget)) -+ { -+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+#if defined(MV_INCLUDE_PCI) -+ -+ if (MV_TARGET_IS_PCI(pciIfTarget)) -+ { -+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address -+* -+* DESCRIPTION: -+* -+* INPUT: -+* baseAddress - base address to be checked -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the target number that baseAddress belongs to or MAX_TARGETS is not -+* found -+* -+*******************************************************************************/ -+ -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ if ((baseAddress >= win.addrWin.baseLow) && -+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; -+ } -+ } -+ else return MAX_TARGETS; -+ -+ } -+ -+ return target; -+} -+/******************************************************************************* -+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case CPU address decode -+* windows overlapps. -+* This function detects CPU address decode windows overlapping of a -+* specified target. The function does not check the target itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 targetNum; -+ MV_CPU_DEC_WIN addrDecWin; -+ MV_STATUS status; -+ -+ -+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) -+ { -+#if defined(MV_RUN_FROM_FLASH) -+ if(MV_TARGET_IS_AS_BOOT(target)) -+ { -+ if (MV_CHANGE_BOOT_CS(targetNum) == target) -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* don't check our target or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); -+ if(MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ if(MV_OK != status) -+ { -+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); -+ return MV_TRUE; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf( -+ "cpuTargetWinOverlap: Required target %d overlap current %d\n", -+ target, targetNum)); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* mvCpuIfAddDecShow - Print the CPU address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCpuIfAddDecShow(MV_VOID) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "CPU Interface\n" ); -+ mvOsOutput( "-------------\n" ); -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ -+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); -+ -+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); -+ mvOsOutput( "...." ); -+ -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) -+ { -+ mvOsOutput( "no such\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfEnablePex - Enable PCI Express. -+* -+* DESCRIPTION: -+* This function Enable PCI Express. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* pexType - MV_PEX_ROOT_COMPLEX - root complex device -+* MV_PEX_END_POINT - end point device -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV_INCLUDE_PEX) -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) -+{ -+ /* Set pex mode incase S@R not exist */ -+ if( pexType == MV_PEX_END_POINT) -+ { -+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ /* Change pex mode in capability reg */ -+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); -+ -+ } -+ else -+ { -+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ } -+ -+ /* CPU config register Pex enable */ -+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); -+} -+#endif -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h -new file mode 100644 -index 0000000..5755a40 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h -@@ -0,0 +1,120 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfh -+#define __INCmvCpuIfh -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+ -+/* defines */ -+ -+/* typedefs */ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvCpuIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_CPU_DEC_WIN; -+ -+ -+ -+/* mvCpuIfLib.h API list */ -+ -+/* mvCpuIfLib.h API list */ -+ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); -+#endif -+#if defined(MV_INCLUDE_PCI) -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+#endif -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+ -+MV_VOID mvCpuIfAddDecShow(MV_VOID); -+ -+#if defined(MV88F6281) -+MV_STATUS mvCpuIfBridgeReorderWAInit(void); -+#endif -+ -+#endif /* __INCmvCpuIfh */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h -new file mode 100644 -index 0000000..58c04c0 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h -@@ -0,0 +1,304 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfRegsh -+#define __INCmvCpuIfRegsh -+ -+/****************************************/ -+/* ARM Control and Status Registers Map */ -+/****************************************/ -+ -+#define CPU_CONFIG_REG 0x20100 -+#define CPU_CTRL_STAT_REG 0x20104 -+#define CPU_RSTOUTN_MASK_REG 0x20108 -+#define CPU_SYS_SOFT_RST_REG 0x2010C -+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 -+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 -+#define CPU_FTDLL_CONFIG_REG 0x20120 -+#define CPU_L2_CONFIG_REG 0x20128 -+ -+ -+ -+/* ARM Configuration register */ -+/* CPU_CONFIG_REG (CCR) */ -+ -+ -+/* Reset vector location */ -+#define CCR_VEC_INIT_LOC_OFFS 1 -+#define CCR_VEC_INIT_LOC_MASK BIT1 -+/* reset at 0x00000000 */ -+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) -+/* reset at 0xFFFF0000 */ -+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) -+ -+ -+#define CCR_AHB_ERROR_PROP_OFFS 2 -+#define CCR_AHB_ERROR_PROP_MASK BIT2 -+/* Erros are not propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) -+/* Erros are propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) -+ -+ -+#define CCR_ENDIAN_INIT_OFFS 3 -+#define CCR_ENDIAN_INIT_MASK BIT3 -+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) -+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) -+ -+ -+#define CCR_INCR_EN_OFFS 4 -+#define CCR_INCR_EN_MASK BIT4 -+#define CCR_INCR_EN BIT4 -+ -+ -+#define CCR_NCB_BLOCKING_OFFS 5 -+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) -+ -+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 -+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) -+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 -+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) -+#define CCR_ICACH_PREF_BUF_ENABLE BIT16 -+#define CCR_DCACH_PREF_BUF_ENABLE BIT17 -+ -+/* Ratio options for CPU to DDR for 6281/6192/6190 */ -+#define CPU_2_DDR_CLK_1x3 4 -+#define CPU_2_DDR_CLK_1x4 6 -+ -+/* Ratio options for CPU to DDR for 6281 only */ -+#define CPU_2_DDR_CLK_2x9 7 -+#define CPU_2_DDR_CLK_1x5 8 -+#define CPU_2_DDR_CLK_1x6 9 -+ -+/* Ratio options for CPU to DDR for 6180 only */ -+#define CPU_2_DDR_CLK_1x3_1 0x5 -+#define CPU_2_DDR_CLK_1x4_1 0x6 -+ -+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ -+/* CPU to Mbus-L Tick Sample fields in CPU config register */ -+ -+#define TICK_DRV_1x1 0 -+#define TICK_DRV_1x2 0 -+#define TICK_DRV_1x3 1 -+#define TICK_DRV_1x4 2 -+#define TICK_SMPL_1x1 0 -+#define TICK_SMPL_1x2 1 -+#define TICK_SMPL_1x3 0 -+#define TICK_SMPL_1x4 0 -+ -+#define CPU_2_MBUSL_DDR_CLK_1x2 \ -+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x3 \ -+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x4 \ -+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+ -+/* ARM Control and Status register */ -+/* CPU_CTRL_STAT_REG (CCSR) */ -+ -+ -+/* -+This is used to block PCI express\PCI from access Socrates/Feroceon GP -+while ARM boot is still in progress -+*/ -+ -+#define CCSR_PCI_ACCESS_OFFS 0 -+#define CCSR_PCI_ACCESS_MASK BIT0 -+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) -+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) -+ -+#define CCSR_ARM_RESET BIT1 -+#define CCSR_SELF_INT BIT2 -+#define CCSR_BIG_ENDIAN BIT15 -+ -+ -+/* RSTOUTn Mask Register */ -+/* CPU_RSTOUTN_MASK_REG (CRMR) */ -+ -+#define CRMR_PEX_RST_OUT_OFFS 0 -+#define CRMR_PEX_RST_OUT_MASK BIT0 -+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) -+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) -+ -+#define CRMR_WD_RST_OUT_OFFS 1 -+#define CRMR_WD_RST_OUT_MASK BIT1 -+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) -+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) -+ -+#define CRMR_SOFT_RST_OUT_OFFS 2 -+#define CRMR_SOFT_RST_OUT_MASK BIT2 -+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) -+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) -+ -+/* System Software Reset Register */ -+/* CPU_SYS_SOFT_RST_REG (CSSRR) */ -+ -+#define CSSRR_SYSTEM_SOFT_RST BIT0 -+ -+/* AHB to Mbus Bridge Interrupt Cause Register*/ -+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ -+ -+#define CAMCIR_ARM_SELF_INT BIT0 -+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 -+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 -+ -+ -+/* AHB to Mbus Bridge Interrupt Mask Register*/ -+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ -+ -+#define CAMCIR_ARM_SELF_INT_OFFS 0 -+#define CAMCIR_ARM_SELF_INT_MASK BIT0 -+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) -+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) -+ -+ -+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+ -+/* CPU FTDLL Config register (CFCR) fields */ -+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 -+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) -+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 -+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) -+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) -+/* For Orion 2 D2 only */ -+#define CFCR_MRVL_CPU_ID_OFFS 16 -+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 -+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+ -+/* CPU_L2_CONFIG_REG fields */ -+#ifdef MV_CPU_LE -+#define CL2CR_L2_ECC_EN_OFFS 2 -+#define CL2CR_L2_WT_MODE_OFFS 4 -+#else -+#define CL2CR_L2_ECC_EN_OFFS 26 -+#define CL2CR_L2_WT_MODE_OFFS 28 -+#endif -+ -+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) -+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) -+ -+/*******************************************/ -+/* Main Interrupt Controller Registers Map */ -+/*******************************************/ -+ -+#define CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define CPU_MAIN_IRQ_MASK_REG 0x20204 -+#define CPU_MAIN_FIQ_MASK_REG 0x20208 -+#define CPU_ENPOINT_MASK_REG 0x2020C -+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 -+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 -+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 -+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C -+ -+ -+/*******************************************/ -+/* ARM Doorbell Registers Map */ -+/*******************************************/ -+ -+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 -+#define CPU_HOST_TO_ARM_MASK_REG 0x20404 -+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 -+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C -+ -+ -+ -+/* CPU control register map */ -+/* Set bits means value is about to change according to new value */ -+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) -+ -+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) -+ -+/* CPU Control and status defaults */ -+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) -+ -+ -+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) -+ -+#endif /* __INCmvCpuIfRegsh */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c -new file mode 100644 -index 0000000..8475956 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c -@@ -0,0 +1,324 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvSysAudio.h" -+ -+/******************************************************************************* -+* mvAudioWinSet - Set AUDIO target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) -+* address window, also known as address decode window. -+* After setting this target window, the AUDIO will be able to access the -+* target within the address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* pAddrDecWin - AUDIO target window data structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if address window overlapps with other address decode windows. -+* MV_BAD_PARAM if base address is invalid parameter or target is -+* unknown. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAudioWinGet - Get AUDIO peripheral target address window. -+* -+* DESCRIPTION: -+* Get AUDIO peripheral target address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - AUDIO target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> -+ MV_AUDIO_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> -+ MV_AUDIO_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvAudioAddrDecShow - Print the AUDIO address decode map. -+* -+* DESCRIPTION: -+* This function print the AUDIO address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAudioAddrDecShow(MV_VOID) -+{ -+ -+ MV_AUDIO_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) -+ return; -+ -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AUDIO:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvAudioWinGet( i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvAudioWinInit - Initialize the integrated AUDIO target address window. -+* -+* DESCRIPTION: -+* Initialize the AUDIO peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioInit(MV_VOID) -+{ -+ int winNum; -+ MV_AUDIO_DEC_WIN audioWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status; -+ -+ mvAudioHalInit(); -+ -+ /* Initiate Audio address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); -+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); -+ } -+ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ -+ /* We will set the Window to DRAM_CS0 in default */ -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(SDRAM_CS0, -+ &cpuAddrDecWin); -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ audioWin.enable = MV_TRUE; -+ audioWin.target = SDRAM_CS0; -+ -+ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) -+ { -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ return MV_OK; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h -new file mode 100644 -index 0000000..7e078ff ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h -@@ -0,0 +1,123 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysAudioH -+#define __INCMVSysAudioH -+ -+#include "mvCommon.h" -+#include "audio/mvAudio.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***********************************/ -+/* Audio Address Decoding registers*/ -+/***********************************/ -+ -+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 -+#define MV_AUDIO_RECORD_WIN_NUM 0 -+#define MV_AUDIO_PLAYBACK_WIN_NUM 1 -+ -+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) -+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) -+ -+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_AUDIO_WIN_ENABLE_BIT 0 -+#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) -+MV_TARGET tdmaAddrDecPrioTable[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ -+ TBL_TERM -+}; -+ -+/******************************************************************************* -+* mvCesaWinGet - Get TDMA target address window. -+* -+* DESCRIPTION: -+* Get TDMA target address window. -+* -+* INPUT: -+* winNum - TDMA target address decode window number. -+* -+* OUTPUT: -+* pDecWin - TDMA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); -+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to CESA address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case TDMA address decode -+* windows overlapps. -+* This function detects TDMA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - if the given address window overlap current address -+* decode map, -+* MV_FALSE - otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | -+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); -+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+ -+static MV_STATUS mvCesaTdmaAddrDecInit (void) -+{ -+ MV_U32 winNum; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_DEC_WIN cesaWin; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= 2 */ -+ -+ -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) -+{ -+ MV_U32 cesaCryptEngBase; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) -+ { -+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", -+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); -+ return MV_FAIL; -+ } -+#if 0 -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ cesaCryptEngBase = addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+#else -+ cesaCryptEngBase = (MV_U32)pSramBase; -+#endif -+ -+#if 0 /* Already done in the platform init */ -+#if (MV_CESA_VERSION >= 2) -+ mvCesaTdmaAddrDecInit(); -+#endif /* MV_CESA_VERSION >= 2 */ -+#endif -+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, -+ osHandle); -+ -+} -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h -new file mode 100644 -index 0000000..9bc3fee ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSysCesa_h__ -+#define __mvSysCesa_h__ -+ -+ -+#include "mvCommon.h" -+#include "cesa/mvCesa.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***************************** TDMA Registers *************************************/ -+ -+#define MV_CESA_TDMA_ADDR_DEC_WIN 4 -+ -+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 -+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) -+ -+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 -+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 -+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c -new file mode 100644 -index 0000000..7df47b3 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+ -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h -new file mode 100644 -index 0000000..f16b947 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h -@@ -0,0 +1,80 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __sysDram -+#define __sysDram -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c -new file mode 100644 -index 0000000..663acd3 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c -@@ -0,0 +1,658 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "ctrlEnv/sys/mvSysGbe.h" -+ -+ -+ -+typedef struct _mvEthDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_ETH_DEC_WIN; -+ -+MV_TARGET ethAddrDecPrioTap[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEVICE_CS0, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEVICE_CS1, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEVICE_CS2, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEVICE_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_IO, -+#endif -+ TBL_TERM -+}; -+ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); -+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+ -+ -+/******************************************************************************* -+* mvEthWinInit - Initialize ETH address decode windows -+* -+* DESCRIPTION: -+* This function initialize ETH window decode unit. It set the -+* default address decode windows of the unit. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if setting fail. -+*******************************************************************************/ -+/* Configure EthDrv memory map registes. */ -+MV_STATUS mvEthWinInit (int port) -+{ -+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; -+ MV_ETH_DEC_WIN ethWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ static MV_U32 accessProtReg = 0; -+ -+#if (MV_ETH_VERSION <= 1) -+ static MV_BOOL isFirst = MV_TRUE; -+ -+ if(isFirst == MV_FALSE) -+ { -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); -+ return MV_OK; -+ } -+ isFirst = MV_FALSE; -+#endif /* MV_GIGA_ETH_VERSION */ -+ -+ /* Initiate Ethernet address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; -+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; -+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvEthWinEnable(port, winNum, MV_FALSE); -+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); -+ -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvEthWinEnable(port, winNum, MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvETHWinGet - Get dma peripheral target address window. -+* -+* DESCRIPTION: -+* Get ETH peripheral target address window. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - ETH target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinEnable - Enable/disable a ETH to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a ETH to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling ETH accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode target window */ -+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* window number -+* -+*******************************************************************************/ -+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) -+{ -+ MV_ETH_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); -+ return MV_ERROR; -+ } -+ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); -+ return MV_ERROR; -+ } -+ /* Read current protection register */ -+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); -+ -+ /* Clear protection window field */ -+ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); -+ -+ /* Set new protection field value */ -+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); -+ -+ /* Write protection register back */ -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethWinOverlapDetect - Detect ETH address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case ETH address decode -+* windows overlapps. -+* This function detects ETH address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex; -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); -+ -+ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Enabled CPU access to PCI-Express */ -+ mvCpuIfEnablePex(pexIf, pexType); -+ -+ /* Start with bars */ -+ /* First disable all PEX bars*/ -+ for (bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ if (PEX_INTER_REGS_BAR != bar) -+ { -+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ } -+ -+ /* and disable all PEX target windows */ -+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ } -+ -+ /* Now, go through all bars*/ -+ -+ -+ -+/******************************************************************************/ -+/* Internal registers bar */ -+/******************************************************************************/ -+ bar = PEX_INTER_REGS_BAR; -+ -+ /* we only open the bar , no need to open windows for this bar */ -+ -+ /* first get the CS attribute from the CPU Interface */ -+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); -+ return MV_ERROR; -+ } -+ -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexBar.addrWin.size = addrDecWin.addrWin.size; -+ pexBar.enable = MV_TRUE; -+ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+/******************************************************************************/ -+/* DRAM bar */ -+/******************************************************************************/ -+ -+ bar = PEX_DRAM_BAR; -+ -+ pexBar.addrWin.size = 0; -+ -+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) -+ { -+ -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) -+ { -+ continue; -+ } -+ -+ /* first get attributes from CPU If */ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* the base is the base of DRAM CS0 always */ -+ if (SDRAM_CS0 == target ) -+ { -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ -+ } -+ -+ /* increment the bar size to be the sum of the size of all -+ DRAM chips selecs */ -+ pexBar.addrWin.size += addrDecWin.addrWin.size; -+ -+ /* set a Pex window for this target ! -+ DRAM CS always will have a Pex Window , and is not a -+ part of the priority table */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable =MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ /* check if the size of the bar is illeggal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ pexBar.enable = MV_TRUE; -+ -+ /* configure the bar */ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* after the bar was configured then we enable the Pex windows*/ -+ for (winNum = 0;winNum < pexCurrWin ;winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ } -+ } -+ -+/******************************************************************************/ -+/* DEVICE bar */ -+/******************************************************************************/ -+ -+/* Open the Device BAR for non linux only */ -+#ifndef MV_DISABLE_PEX_DEVICE_BAR -+ -+ /* then device bar*/ -+ bar = PEX_DEVICE_BAR; -+ -+ /* save the starting window */ -+ pexStartWindow = pexCurrWin; -+ pexBar.addrWin.size = 0; -+ pexBar.addrWin.baseLow = 0xffffffff; -+ pexBar.addrWin.baseHigh = 0; -+ maxBase = 0; -+ -+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) -+ { -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if (MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* get the minimum base */ -+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) -+ { -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ } -+ -+ /* get the maximum base */ -+ if (addrDecWin.addrWin.baseLow > maxBase) -+ { -+ maxBase = addrDecWin.addrWin.baseLow; -+ sizeOfMaxBase = addrDecWin.addrWin.size; -+ } -+ -+ /* search in the priority table for this target */ -+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; -+ winIndex++) -+ { -+ if (pexDevBarPrioTable[winIndex] != target) -+ { -+ continue; -+ } -+ else if (pexDevBarPrioTable[winIndex] == target) -+ { -+ /*found it */ -+ -+ /* if the index of this target in the prio table is valid -+ then we set the Pex window for this target, a valid index is -+ an index that is lower than the number of the windows that -+ was not configured yet */ -+ -+ /* we subtract 2 always because the default and expantion -+ rom windows are always configured */ -+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) -+ { -+ /* set a Pex window for this target ! */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable = MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, -+ &pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ } -+ } -+ } -+ -+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; -+ pexBar.enable = MV_TRUE; -+ -+ /* check if the size of the bar is illegal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* now enable the windows */ -+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+#endif -+ -+ return mvPexHalInit(pexIf, pexType); -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if PEX BAR target window was set correctly, -+* MV_BAD_PARAM on bad params -+* MV_ERROR otherwise -+* (e.g. address window overlapps with other active PEX target window). -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_TARGET_ATTRIB targetAttribs; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ } -+ -+ -+ -+ /* read base register*/ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_EN; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ } -+ -+ -+ /* clear bit location */ -+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; -+ -+ /* set bar Mapping */ -+ if (pAddrDecWin->targetBar == 1) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; -+ } -+ else if (pAddrDecWin->targetBar == 2) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; -+ -+ -+ /* 3) Write to address decode Base Address Register */ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); -+ } -+ -+ /* write size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT == winNum)|| -+ (MV_PEX_WIN_EXP_ROM == winNum)) -+ { -+ /* clear size because there is no size field*/ -+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; -+ -+ /* clear enable because there is no enable field*/ -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ -+ } -+ -+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); -+ } -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinGet - Get PEX to peripheral target address window -+* -+* DESCRIPTION: -+* Get the PEX to peripheral target address window BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* pAddrBarWin - PEX target window information data structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_DEC_REGS decRegs; -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ /* read base register*/ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ /* read size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (decRegs.sizeReg & PXWCR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ #if 0 -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ #endif -+ -+ -+ /* get target bar */ -+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) -+ { -+ pAddrDecWin->targetBar = 1; -+ } -+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == -+ PXWCR_WIN_BAR_MAP_BAR2 ) -+ { -+ pAddrDecWin->targetBar = 2; -+ } -+ -+ /* attrib and targetId */ -+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> -+ PXWCR_ATTRIB_OFFS; -+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> -+ PXWCR_TARGET_OFFS; -+ -+ targetAttrib.attrib = pAddrDecWin->attrib; -+ targetAttrib.targetId = pAddrDecWin->targetId; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexTargetWinEnable - Enable/disable a PEX BAR window -+* -+* DESCRIPTION: -+* This function enable/disable a PEX BAR window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling PEX accesses for that BAR (before enabling the -+* window it is tested for overlapping). Otherwise, the window will -+* be disabled. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ /* if the address windows is disabled , we only disable the appropriare -+ pex window and ignore other settings */ -+ -+ if (MV_FALSE == enable) -+ { -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -+/******************************************************************************* -+* mvPexTargetWinRemap - Set PEX to target address window remap. -+* -+* DESCRIPTION: -+* The PEX interface supports remap of the BAR original address window. -+* For each BAR it is possible to define a remap address. For example -+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified -+* according to remap register but will also be targeted to the -+* SDRAM CS[0]. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - Peripheral target enumerator accessed by slave. -+* pAddrWin - Address window to be checked. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin) -+{ -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ pexIf, -+ winNum, -+ pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size); -+ -+ return MV_ERROR; -+ } -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ /* Set remap low register value */ -+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); -+ -+ /* Skip base high settings if the BAR has only base low (32-bit) */ -+ if (0 != winRegInfo.remapHighRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); -+ } -+ -+ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexTargetWinRemapEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ if (enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexBarSet - Set PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ MV_U32 regBaseLow; -+ MV_U32 regSize,sizeToReg; -+ -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if (pAddrWin->addrWin.size == 0) -+ { -+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* Check if the window complies with PEX spec */ -+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested bar overlaps with current bars */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ regSize &= ~PXBCR_BAR_SIZE_MASK; -+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; -+ -+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); -+ -+ } -+ -+ /* set size */ -+ -+ -+ -+ /* Read base address low */ -+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_MV_BAR_BASE(barNum))); -+ -+ /* clear current base */ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ regBaseLow &= ~PXBIR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); -+ } -+ else -+ { -+ regBaseLow &= ~PXBR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); -+ } -+ -+ /* if we had a previous value that contain the bar type (MeM\IO), we want to -+ restore it */ -+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; -+ -+ -+ -+ /* write base low */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), -+ regBaseLow); -+ -+ if (pAddrWin->addrWin.baseHigh != 0) -+ { -+ /* Read base address high */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), -+ pAddrWin->addrWin.baseHigh); -+ -+ } -+ -+ /* lastly enable the Bar */ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ } -+ else if (MV_FALSE == pAddrWin->enable) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ -+ } -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexBarGet - Get PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* read base low */ -+ pAddrWin->addrWin.baseLow = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); -+ -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; -+ } -+ else -+ { -+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; -+ } -+ -+ -+ /* read base high */ -+ pAddrWin->addrWin.baseHigh = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); -+ -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* check if enable or not */ -+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) -+ { -+ pAddrWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrWin->enable = MV_FALSE; -+ } -+ -+ /* now get the size */ -+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; -+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; -+ -+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ } -+ else /* PEX_INTER_REGS_BAR */ -+ { -+ pAddrWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrWin->enable = MV_TRUE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexBarEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) -+{ -+ -+ MV_PEX_BAR pexBar; -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ if (MV_TRUE == enable) -+ { -+ return MV_OK; -+ } -+ else -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ if (MV_FALSE == enable) -+ { -+ /* disable bar and quit */ -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ return MV_OK; -+ } -+ -+ /* else */ -+ -+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (MV_TRUE == pexBar.enable) -+ { -+ /* it is already enabled !!! */ -+ return MV_OK; -+ } -+ -+ /* else enable the bar*/ -+ -+ pexBar.enable = MV_TRUE; -+ -+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* pexWinOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, -+ MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 win; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ -+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) -+ { -+ /* don't check our target or illegal targets */ -+ if (winNum == win) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", -+ win); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", -+ winNum, win); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexIsWinWithinBar - Detect if address is within PEX bar boundries -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR addrDecWin; -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) -+ { -+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled bars */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* pexBarOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR barDecWin; -+ -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ /* don't check our target or illegal targets */ -+ if (barNum == bar) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* don'nt check disabled bars */ -+ if (barDecWin.enable == MV_FALSE) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", -+ barNum, bar); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexBarIsValid - Check if the given address window is valid -+* -+* DESCRIPTION: -+* PEX spec restrict BAR base to be aligned to BAR size. -+* This function checks if the given address window is valid. -+* -+* INPUT: -+* baseLow - 32bit low base address. -+* size - Window size. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the address window is valid, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) -+{ -+ -+ /* PCI spec restrict BAR base to be aligned to BAR size */ -+ if(MV_IS_NOT_ALIGN(baseLow, size)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ return MV_TRUE; -+ } -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* pexBarRegInfoGet - Get BAR register information -+* -+* DESCRIPTION: -+* PEX BARs registers offsets are inconsecutive. -+* This function gets a PEX BAR register information like register offsets -+* and function location of the BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - The PEX BAR in question. -+* -+* OUTPUT: -+* pBarRegInfo - BAR register info struct. -+* -+* RETURN: -+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK -+* -+*******************************************************************************/ -+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, -+ MV_U32 winNum, -+ PEX_WIN_REG_INFO *pWinRegInfo) -+{ -+ -+ if ((winNum >= 0)&&(winNum <=3)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if ((winNum >= 4)&&(winNum <=5)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); -+ -+ } -+ else if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = 0; -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if (MV_PEX_WIN_EXP_ROM == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); -+ pWinRegInfo->remapHighRegOffs = 0; -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* pexBarNameGet - Get the string name of PEX BAR. -+* -+* DESCRIPTION: -+* This function get the string name of PEX BAR. -+* -+* INPUT: -+* bar - PEX bar number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string name of PEX BAR. -+* -+*******************************************************************************/ -+const MV_8* pexBarNameGet( MV_U32 bar ) -+{ -+ switch( bar ) -+ { -+ case PEX_INTER_REGS_BAR: -+ return "Internal Regs Bar0...."; -+ case PEX_DRAM_BAR: -+ return "DRAM Bar1............."; -+ case PEX_DEVICE_BAR: -+ return "Devices Bar2.........."; -+ default: -+ return "Bar unknown"; -+ } -+} -+/******************************************************************************* -+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). -+* -+* DESCRIPTION: -+* This function print the PEX address decode map (BARs and windows). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvPexAddrDecShow(MV_VOID) -+{ -+ MV_PEX_BAR pexBar; -+ MV_PEX_DEC_WIN win; -+ MV_U32 pexIf; -+ MV_U32 bar,winNum; -+ -+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "PEX%d:\n", pexIf ); -+ mvOsOutput( "-----\n" ); -+ -+ mvOsOutput( "\nPex Bars \n\n"); -+ -+ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) -+ { -+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); -+ -+ mvOsOutput( "%s ", pexBarNameGet(bar) ); -+ -+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) -+ { -+ if( pexBar.enable ) -+ { -+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); -+ mvSizePrint( pexBar.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ mvOsOutput( "\nPex Decode Windows\n\n"); -+ -+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) -+ { -+ if (win.enable) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ -+ -+ } -+ } -+ -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "default win - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "Expansion ROM - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ -+ } -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h -new file mode 100644 -index 0000000..c1555f6 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCSysPEXH -+#define __INCSysPEXH -+ -+#include "mvCommon.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* 4KB granularity */ -+#define MINIMUM_WINDOW_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 -+#define BAR_SIZE_OFFS 12 -+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) -+ -+ -+ -+#define MV_PEX_WIN_DEFAULT 6 -+#define MV_PEX_WIN_EXP_ROM 7 -+#define PEX_MAX_TARGET_WIN 8 -+ -+ -+#define PEX_MAX_BARS 3 -+#define PEX_INTER_REGS_BAR 0 -+#define PEX_DRAM_BAR 1 -+#define PEX_DEVICE_BAR 2 -+ -+/*************************************/ -+/* PCI Express BAR Control Registers */ -+/*************************************/ -+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) -+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) -+ -+ -+/* PCI Express BAR Control Register */ -+/* PEX_BAR_CTRL_REG (PXBCR) */ -+ -+#define PXBCR_BAR_EN BIT0 -+#define PXBCR_BAR_SIZE_OFFS 16 -+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) -+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 -+ -+ -+ -+/* PCI Express Expansion ROM BAR Control Register */ -+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ -+ -+#define PXERBCR_EXPROM_EN BIT0 -+#define PXERBCR_EXPROMSZ_OFFS 19 -+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) -+ -+/************************************************/ -+/* PCI Express Address Window Control Registers */ -+/************************************************/ -+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ -+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ -+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ -+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ -+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ -+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ -+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ -+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+ -+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) -+ -+/* PCI Express Window Control Register */ -+/* PEX_WIN_CTRL_REG (PXWCR) */ -+ -+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ -+ -+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ -+#define PXWCR_WIN_BAR_MAP_MASK BIT1 -+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) -+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) -+ -+#define PXWCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) -+ -+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) -+ -+#define PXWCR_SIZE_OFFS 16 /* size */ -+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) -+#define PXWCR_SIZE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Base Register */ -+/* PEX_WIN_BASE_REG (PXWBR)*/ -+ -+#define PXWBR_BASE_OFFS 16 /* address[31:16] */ -+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) -+#define PXWBR_BASE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap Register */ -+/* PEX_WIN_REMAP_REG (PXWRR)*/ -+ -+#define PXWRR_REMAP_EN BIT0 -+#define PXWRR_REMAP_OFFS 16 -+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) -+#define PXWRR_REMAP_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap (High) Register */ -+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ -+ -+#define PXWRHR_REMAP_HIGH_OFFS 0 -+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) -+ -+/* PCI Express Default Window Control Register */ -+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ -+ -+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) -+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Control Register */ -+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ -+ -+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) -+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Remap Register */ -+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ -+ -+#define PXWERRR_REMAP_EN BIT0 -+#define PXWERRR_REMAP_OFFS 16 -+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) -+#define PXWERRR_REMAP_ALIGNMENT 0x10000 -+ -+ -+ -+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ -+/* PCI Express BAR0 Internal Register*/ -+/*PEX BAR0_INTER_REG (PXBIR)*/ -+ -+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) -+ -+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ -+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) -+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) -+ -+ -+/* PCI Express BAR0 Internal (High) Register*/ -+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ -+ -+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ -+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ -+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+ -+ -+/* PCI Express BAR1 Register */ -+/* PCI Express BAR2 Register*/ -+/*PEX BAR1_REG (PXBR)*/ -+/*PEX BAR2_REG (PXBR)*/ -+ -+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) -+ -+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ -+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) -+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) -+ -+ -+/* PCI Express BAR1 (High) Register*/ -+/* PCI Express BAR2 (High) Register*/ -+/*PEX BAR1_REG_HIGH (PXBRH)*/ -+/*PEX BAR2_REG_HIGH (PXBRH)*/ -+ -+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ -+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) -+ -+/* PCI Express Expansion ROM BAR Register*/ -+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ -+ -+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) -+ -+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) -+ -+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) -+ -+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexBar -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_BAR; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexRemapWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_REMAP_WIN; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 targetBar; -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_DEC_WIN; -+ -+/* Global Functions prototypes */ -+/* mvPexHalInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+ -+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); -+ -+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin); -+ -+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable); -+ -+/* mvPexBarSet - Set PEX bar address and size */ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarGet - Get PEX bar address and size */ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarEnable - enable\disable a PEX bar*/ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); -+ -+/* mvPexAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPexAddrDecShow(MV_VOID); -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c -new file mode 100644 -index 0000000..4c0485f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c -@@ -0,0 +1,430 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "sata/CoreDriver/mvRegs.h" -+#include "ctrlEnv/sys/mvSysSata.h" -+ -+MV_TARGET sataAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+/******************************************************************************* -+* sataWinOverlapDetect - Detect SATA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case SATA address decode -+* windows overlapps. -+* This function detects SATA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_SATA_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSataWinGet - Get SATA peripheral target address window. -+* -+* DESCRIPTION: -+* Get SATA peripheral target address window. -+* -+* INPUT: -+* winNum - SATA target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - SATA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> -+ MV_SATA_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> -+ MV_SATA_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSataAddrDecShow - Print the SATA address decode map. -+* -+* DESCRIPTION: -+* This function print the SATA address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSataAddrDecShow(MV_VOID) -+{ -+ -+ MV_SATA_DEC_WIN win; -+ int i,j; -+ -+ -+ -+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SATA %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSataWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSataWinInit - Initialize the integrated SATA target address window. -+* -+* DESCRIPTION: -+* Initialize the SATA peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SATA_DEC_WIN sataWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sata address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SATA_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sataWin.enable = MV_TRUE; -+ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h -new file mode 100644 -index 0000000..e401992 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h -@@ -0,0 +1,128 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSataAddrDech -+#define __INCMVSysSataAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSataDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SATA_DEC_WIN; -+ -+ -+#define MV_SATA_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) -+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) -+ -+/* BITs in Bridge Interrupt Cause and Mask registers */ -+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 -+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSdmmcWinGet - Get SDMMC peripheral target address window. -+* -+* DESCRIPTION: -+* Get SDMMC peripheral target address window. -+* -+* INPUT: -+* winNum - SDMMC target address decode window number. -+*d -+* OUTPUT: -+* pAddrDecWin - SDMMC target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> -+ MV_SDMMC_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> -+ MV_SDMMC_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSdmmcAddrDecShow - Print the SDMMC address decode map. -+* -+* DESCRIPTION: -+* This function print the SDMMC address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSdmmcAddrDecShow(MV_VOID) -+{ -+ -+ MV_SDMMC_DEC_WIN win; -+ int i,j=0; -+ -+ -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SDMMC %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. -+* -+* DESCRIPTION: -+* Initialize the SDMMC peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SDMMC_DEC_WIN sdmmcWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sdmmc address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sdmmcWin.enable = MV_TRUE; -+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h -new file mode 100644 -index 0000000..f8357c1 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h -@@ -0,0 +1,125 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSdmmcAddrDech -+#define __INCMVSysSdmmcAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSdmmcDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SDMMC_DEC_WIN; -+ -+ -+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) -+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_SDMMC_WIN_ENABLE_BIT 0 -+#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvTdmWinEnable(winNum, MV_FALSE); -+ -+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); -+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); -+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); -+ -+ /* Write to address base and control registers */ -+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); -+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTdmWinEnable(winNum, MV_TRUE); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinGet - Get peripheral target address window. -+* -+* DESCRIPTION: -+* Get TDM peripheral target address window. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TDM target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+ -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; -+ targetAttrib.targetId = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinEnable - Enable/disable a TDM to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a TDM to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TDM accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) -+{ -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ if (MV_TRUE == enable) -+ { -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* tdmWinOverlapDetect - Detect TDM address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case TDM address decode -+* windows overlapps. -+* This function detects TDM address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ /* Do not check disabled windows */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ /* Get window parameters */ -+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvTdmAddrDecShow - Print the TDM address decode map. -+* -+* DESCRIPTION: -+* This function print the TDM address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvTdmAddrDecShow(MV_VOID) -+{ -+ MV_TDM_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TDM:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if (mvTdmWinGet(i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h -new file mode 100644 -index 0000000..3603095 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h -@@ -0,0 +1,106 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTdmh -+#define __INCmvSysTdmh -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef struct _mvTdmDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+} MV_TDM_DEC_WIN; -+ -+MV_STATUS mvTdmWinInit(MV_VOID); -+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); -+MV_VOID mvTdmAddrDecShow(MV_VOID); -+ -+ -+#define TDM_MBUS_MAX_WIN 4 -+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) -+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) -+ -+/* TDM_WIN_CTRL_REG bits */ -+#define TDM_WIN_ENABLE_OFFS 0 -+#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " -+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new */ -+ /* values */ -+ mvTsuWinEnable(winNum, MV_FALSE); -+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ /* Enable address decode target window */ -+ if(pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTsuWinEnable(winNum,MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinGet -+* -+* DESCRIPTION: -+* Get TSU peripheral target address window. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TSU target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinEnable -+* -+* DESCRIPTION: -+* This function enable/disable a TSU to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TSU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* enable - Enable / disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if(enable == MV_TRUE) -+ { -+ /* First check for overlap with other enabled windows */ -+ /* Get current window. */ -+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping. */ -+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ else -+ { -+ /* Overlap detected */ -+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTsuWinTargetGet -+* -+* DESCRIPTION: -+* Get Window number associated with target -+* -+* INPUT: -+* target - Target ID to get the window number for. -+* OUTPUT: -+* -+* RETURN: -+* window number or 0xFFFFFFFF on error. -+* -+*******************************************************************************/ -+MV_U32 mvTsuWinTargetGet(MV_TARGET target) -+{ -+ MV_TSU_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if(target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) -+ { -+ if(mvTsuWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvTsuWinGet: window returned error\n"); -+ return 0xffffffff; -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if(decWin.target == target) -+ { -+ return winNum; -+ } -+ } -+ } -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* tsuWinOverlapDetect -+* -+* DESCRIPTION: -+* Detect TSU address windows overlapping -+* An unpredicted behaviur is expected in case TSU address decode -+* windows overlapps. -+* This function detects TSU address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 ctrlReg; -+ MV_U32 winNumIndex; -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if(winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); -+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) -+ { -+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ return MV_FALSE; -+} -+ -+ -+/******************************************************************************* -+* mvTsuAddrDecShow -+* -+* DESCRIPTION: -+* Print the TSU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvTsuAddrDecShow(void) -+{ -+ MV_TSU_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TSU:\n"); -+ mvOsOutput( "----\n" ); -+ -+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) -+ { -+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); -+ mvOsOutput( "win%d - ", i ); -+ -+ if(mvTsuWinGet(i, &win ) == MV_OK ) -+ { -+ if(win.enable == MV_TRUE) -+ { -+ mvOsOutput("%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), -+ win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint(win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ { -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+ return; -+} -+ -+ -+/******************************************************************************* -+* mvTsuInit -+* -+* DESCRIPTION: -+* Initialize the TSU unit, and get unit out of reset. -+* -+* INPUT: -+* coreClock - The core clock at which the TSU should operate. -+* mode - The mode on configure the unit into (serial/parallel). -+* memHandle - Memory handle used for memory allocations. -+* OUTPUT: -+* None. -+* RETURN: -+* MV_OK - on success, -+* -+*******************************************************************************/ -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle) -+{ -+ MV_STATUS status; -+ -+ status = mvTsuWinInit(); -+ if(status == MV_OK) -+ status = mvTsuHalInit(coreClock,mode,osHandle); -+ -+ return status; -+} -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h -new file mode 100644 -index 0000000..1478b09 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h -@@ -0,0 +1,110 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTsh -+#define __INCmvSysTsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ts/mvTsu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define TSU_MAX_DECODE_WIN 4 -+ -+ -+/*******************************************/ -+/* TSU Windows Registers */ -+/*******************************************/ -+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) -+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) -+ -+/* TSU windows control register. */ -+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) -+#define TSU_WIN_CTRL_TARGET_OFFS 4 -+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) -+#define TSU_WIN_CTRL_ATTR_OFFS 8 -+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) -+#define TSU_WIN_CTRL_SIZE_OFFS 16 -+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) -+ -+/* TSU windows base register. */ -+#define TSU_WIN_BASE_OFFS 16 -+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) -+ -+MV_STATUS mvTsuWinInit(void); -+ -+void mvTsuAddrDecShow(void); -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTsh */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c -new file mode 100644 -index 0000000..195b5e1 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c -@@ -0,0 +1,497 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ctrlEnv/sys/mvSysUsb.h" -+ -+MV_TARGET usbAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) -+ CRYPT_ENG, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+ -+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) -+{ -+ MV_STATUS status; -+ -+ status = mvUsbWinInit(dev); -+ if(status != MV_OK) -+ return status; -+ -+ return mvUsbHalInit(dev, isHost); -+} -+ -+ -+/******************************************************************************* -+* usbWinOverlapDetect - Detect USB address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case USB address decode -+* windows overlapps. -+* This function detects USB address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | -+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ -+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; -+ -+ if((MV_TARGET_IS_DRAM(pDecWin->target)) && -+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; -+ } -+ else -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; -+ } -+#endif /* MV645xx || MV646xx */ -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_USB_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); -+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinGet - Get USB peripheral target address window. -+* -+* DESCRIPTION: -+* Get USB peripheral target address window. -+* -+* INPUT: -+* winNum - USB target address decode window number. -+* -+* OUTPUT: -+* pDecWin - USB target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); -+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_USB_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to USB address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinInit - -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinInit(int dev) -+{ -+ MV_STATUS status; -+ MV_DEC_WIN usbWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ int winNum; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); -+ } -+ -+ /* Go through all windows in user table until table terminator */ -+ winNum = 0; -+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ usbWin.enable = MV_TRUE; -+ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* Get the default attributes for that target window */ -+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); -+#endif /* MV645xx || MV646xx */ -+ -+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbAddrDecShow - Print the USB address decode map. -+* -+* DESCRIPTION: -+* This function print the USB address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvUsbAddrDecShow(MV_VOID) -+{ -+ MV_DEC_WIN addrDecWin; -+ int i, winNum; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "USB:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ if (pAddrDecWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); -+ return MV_ERROR; -+ } -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ /* Get Base Address and size registers values */ -+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; -+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; -+ /* set target ID */ -+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; -+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; -+ -+ -+ /* Write to address decode Base Address Register */ -+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); -+ -+ /* Write to Size Register */ -+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ if (pAddrDecWin->enable) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinGet - Get xor peripheral target address window. -+* -+* DESCRIPTION: -+* Get xor peripheral target address window. -+* -+* INPUT: -+* winNum - One of the possible XOR memory decode windows. -+* -+* OUTPUT: -+* base - Window base address. -+* size - Window size. -+* enable - window enable/disable. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS xorDecRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_U32 chan=0,chanWinEn; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); -+ return MV_ERROR; -+ } -+ -+ if (NULL == pAddrDecWin) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ -+ { -+ /* Check if enable bit is equal for all channels */ -+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) -+ { -+ mvOsPrintf("%s: ERR. Window enable field must be equal in " -+ "all channels(chan=%d)\n",__FUNCTION__, chan); -+ return MV_ERROR; -+ } -+ } -+ -+ -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; -+ targetAttrib.targetId = -+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; -+ -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ if(chanWinEn) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else pAddrDecWin->enable = MV_FALSE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinEnable - Enable/disable a Xor address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a XOR address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling XOR accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) -+{ -+ MV_XOR_DEC_WIN addrDecWin; -+ MV_U32 chan; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* Get current window */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* Check for overlapping */ -+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) -+ { -+ /* Overlap detected */ -+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* No Overlap. Enable address decode target window */ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorSetProtWinSet - Configure access attributes of a XOR engine -+* to one of the XOR memory windows. -+* -+* DESCRIPTION: -+* Each engine can be configured with access attributes for each of the -+* memory spaces. This function sets access attributes -+* to a given window for the given engine -+* -+* INPUTS: -+* chan - One of the possible engines. -+* winNum - One of the possible XOR memory spaces. -+* access - Protection access rights. -+* write - Write rights. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write) -+{ -+ MV_U32 temp; -+ -+ /* Parameter checking */ -+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); -+ return MV_BAD_PARAM; -+ } -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ (~XEXWCR_WIN_ACC_MASK(winNum)); -+ -+ /* if access is disable */ -+ if (!access) -+ { -+ /* disable access */ -+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); -+ } -+ /* if access is enable */ -+ else -+ { -+ /* if write is enable */ -+ if (write) -+ { -+ /* enable write */ -+ temp |= XEXWCR_WIN_ACC_RW(winNum); -+ } -+ /* if write is disable */ -+ else -+ { -+ /* disable write */ -+ temp |= XEXWCR_WIN_ACC_RO(winNum); -+ } -+ } -+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorPciRemap - Set XOR remap register for PCI address windows. -+* -+* DESCRIPTION: -+* only Windows 0-3 can be remapped. -+* -+* INPUT: -+* winNum - window number -+* pAddrDecWin - pointer to address space window structure -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) -+{ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_REMAP_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* xorWinOverlapDetect - Detect XOR address windows overlaping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case XOR address decode -+* windows overlaps. -+* This function detects XOR address decode windows overlaping of a -+* specified window. The function does not check the window itself for -+* overlaping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex,chan; -+ MV_XOR_DEC_WIN addrDecWin; -+ -+ if (pAddrWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); -+ -+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) -+{ -+ MV_XOR_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "XOR %d:\n", unit ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvXorAddrDecShow - Print the XOR address decode map. -+* -+* DESCRIPTION: -+* This function print the XOR address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvXorAddrDecShow(MV_VOID) -+{ -+ int i; -+ -+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) -+ mvXorAddrDecShowUnit(i); -+ -+} -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h -new file mode 100644 -index 0000000..0a7be8f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCMVSysXorh -+#define __INCMVSysXorh -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ -+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) -+ -+/* XOR Engine [0..1] Window Control Registers (XExWCR) */ -+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) -+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) -+ -+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) -+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+ -+/* XOR Engine Base Address Registers (XEBARx) */ -+#define XEBARX_TARGET_OFFS (0) -+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) -+#define XEBARX_ATTR_OFFS (8) -+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) -+#define XEBARX_BASE_OFFS (16) -+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) -+ -+/* XOR Engine Size Mask Registers (XESMRx) */ -+#define XESMRX_SIZE_MASK_OFFS (16) -+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) -+ -+/* XOR Engine High Address Remap Register (XEHARRx1) */ -+#define XEHARRX_REMAP_OFFS (0) -+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) -+ -+typedef struct _mvXorDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_XOR_DEC_WIN; -+ -+MV_STATUS mvXorInit (MV_VOID); -+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit, -+ MV_U32 winNum, MV_BOOL enable); -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write); -+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); -+ -+MV_VOID mvXorAddrDecShow(MV_VOID); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c b/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c -new file mode 100644 -index 0000000..a327944 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c -@@ -0,0 +1,75 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "device/mvDevice.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h b/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h -new file mode 100644 -index 0000000..a8a382b ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h -@@ -0,0 +1,74 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceH -+#define __INCmvDeviceH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "device/mvDeviceRegs.h" -+ -+ -+#endif /* #ifndef __INCmvDeviceH */ -diff --git a/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h b/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h -new file mode 100644 -index 0000000..599dfe3 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h -@@ -0,0 +1,101 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceRegsH -+#define __INCmvDeviceRegsH -+ -+#ifndef MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* This enumerator describes the Marvell controller possible devices that */ -+/* can be connected to its device interface. */ -+typedef enum _mvDevice -+{ -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEV_CS0 = 0, /* Device connected to dev CS[0] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEV_CS1 = 1, /* Device connected to dev CS[1] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEV_CS2 = 2, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEV_CS3 = 3, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS4) -+ DEV_CS4 = 4, /* Device connected to BOOT dev */ -+#endif -+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS -+}MV_DEVICE; -+ -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#define NAND_CTRL_REG 0x10470 -+ -+#define NAND_ACTCEBOOT_BIT BIT1 -+ -+ -+#endif /* #ifndef __INCmvDeviceRegsH */ -diff --git a/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c b/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c -new file mode 100644 -index 0000000..749b885 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c -@@ -0,0 +1,211 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsCpuArchLib.c - Marvell CPU architecture library -+* -+* DESCRIPTION: -+* This library introduce Marvell API for OS dependent CPU architecture -+* APIs. This library introduce single CPU architecture services APKI -+* cross OS. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include -+#include "mvOs.h" -+ -+static MV_U32 read_p15_c0 (void); -+ -+/* defines */ -+#define ARM_ID_REVISION_OFFS 0 -+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) -+ -+#define ARM_ID_PART_NUM_OFFS 4 -+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) -+ -+#define ARM_ID_ARCH_OFFS 16 -+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) -+ -+#define ARM_ID_VAR_OFFS 20 -+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) -+ -+#define ARM_ID_ASCII_OFFS 24 -+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) -+ -+ -+ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ void *p = kmalloc( size, GFP_KERNEL ); -+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); -+ return p; -+} -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); -+} -+ -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle) -+{ -+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); -+} -+ -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle ) -+{ -+ return kfree( pVirtAddr ); -+} -+ -+int mvOsRand(void) -+{ -+ int rand; -+ get_random_bytes(&rand, sizeof(rand) ); -+ return rand; -+} -+ -+/******************************************************************************* -+* mvOsCpuVerGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Revision -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuRevGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuPartGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Part number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuPartGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuArchGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Architicture number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuArchGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuVarGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuVarGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuAsciiGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuAsciiGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); -+} -+ -+ -+ -+/* -+static unsigned long read_p15_c0 (void) -+*/ -+/* read co-processor 15, register #0 (ID register) */ -+static MV_U32 read_p15_c0 (void) -+{ -+ MV_U32 value; -+ -+ __asm__ __volatile__( -+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" -+ : "=r" (value) -+ : -+ : "memory"); -+ -+ return value; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h b/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h -new file mode 100644 -index 0000000..9122a52 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+#ifndef _MV_OS_LNX_H_ -+#define _MV_OS_LNX_H_ -+ -+ -+#ifdef __KERNEL__ -+/* for kernel space */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dbg-trace.h" -+ -+extern void mv_early_printk(char *fmt,...); -+ -+#define MV_ASM __asm__ __volatile__ -+#define INLINE inline -+#define MV_TRC_REC TRC_REC -+#define mvOsPrintf printk -+#define mvOsEarlyPrintf mv_early_printk -+#define mvOsOutput printk -+#define mvOsSPrintf sprintf -+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) -+#define mvOsFree kfree -+#define mvOsMemcpy memcpy -+#define mvOsSleep(_mils_) mdelay(_mils_) -+#define mvOsTaskLock() -+#define mvOsTaskUnlock() -+#define strtol simple_strtoul -+#define mvOsDelay(x) mdelay(x) -+#define mvOsUDelay(x) udelay(x) -+#define mvCopyFromOs copy_from_user -+#define mvCopyToOs copy_to_user -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+ -+#ifdef MV_NDEBUG -+#define mvOsAssert(cond) -+#else -+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } -+#endif /* MV_NDEBUG */ -+ -+#else /* __KERNEL__ */ -+ -+/* for user space applications */ -+#include -+#include -+#include -+#include -+ -+#define INLINE inline -+#define mvOsPrintf printf -+#define mvOsOutput printf -+#define mvOsMalloc(_size_) malloc(_size_) -+#define mvOsFree free -+#define mvOsAssert(cond) assert(cond) -+ -+#endif /* __KERNEL__ */ -+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ -+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) -+ -+#define mvOsCacheClear(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) -+ -+#define mvOsCacheFlush(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) -+ -+#define mvOsCacheInvalidate(pDev, p, size) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) -+ -+#define mvOsCacheUnmap(pDev, phys, size) \ -+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) -+ -+ -+#define CPU_PHY_MEM(x) (MV_U32)x -+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x -+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x -+ -+ -+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ -+#define MV_MEMIO32_WRITE(addr, data) \ -+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) -+ -+#define MV_MEMIO32_READ(addr) \ -+ ((*((volatile unsigned int*)(addr)))) -+ -+#define MV_MEMIO16_WRITE(addr, data) \ -+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) -+ -+#define MV_MEMIO16_READ(addr) \ -+ ((*((volatile unsigned short*)(addr)))) -+ -+#define MV_MEMIO8_WRITE(addr, data) \ -+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) -+ -+#define MV_MEMIO8_READ(addr) \ -+ ((*((volatile unsigned char*)(addr)))) -+ -+ -+/* No Fast Swap implementation (in assembler) for ARM */ -+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) -+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) -+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) -+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) -+ -+/* 32 and 16 bit read/write in big/little endian mode */ -+ -+/* 16bit write in little endian mode */ -+#define MV_MEMIO_LE16_WRITE(addr, data) \ -+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) -+ -+/* 16bit read in little endian mode */ -+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) -+{ -+ MV_U16 data; -+ -+ data= (MV_U16)MV_MEMIO16_READ(addr); -+ -+ return (MV_U16)MV_16BIT_LE_FAST(data); -+} -+ -+/* 32bit write in little endian mode */ -+#define MV_MEMIO_LE32_WRITE(addr, data) \ -+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) -+ -+/* 32bit read in little endian mode */ -+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) -+{ -+ MV_U32 data; -+ -+ data= (MV_U32)MV_MEMIO32_READ(addr); -+ -+ return (MV_U32)MV_32BIT_LE_FAST(data); -+} -+ -+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) -+{ -+ while(byteCount != 0) -+ { -+ *dstAddr = *srcAddr; -+ dstAddr++; -+ srcAddr++; -+ byteCount--; -+ } -+} -+ -+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) -+{ -+ MV_U64 division = 0; -+ -+ if(divisor == 1) -+ return divided; -+ -+ while(divided >= divisor) -+ { -+ division++; -+ divided -= divisor; -+ } -+ if (modulu != NULL) -+ *modulu = divided; -+ -+ return division; -+} -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+extern MV_U32 *mvUncachedParam; -+ -+static __inline void mvOsBridgeReorderWA(void) -+{ -+ volatile MV_U32 val = 0; -+ -+ val = mvUncachedParam[0]; -+} -+#endif -+ -+ -+/* Flash APIs */ -+#define MV_FL_8_READ MV_MEMIO8_READ -+#define MV_FL_16_READ MV_MEMIO_LE16_READ -+#define MV_FL_32_READ MV_MEMIO_LE32_READ -+#define MV_FL_8_DATA_READ MV_MEMIO8_READ -+#define MV_FL_16_DATA_READ MV_MEMIO16_READ -+#define MV_FL_32_DATA_READ MV_MEMIO32_READ -+#define MV_FL_8_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE -+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE -+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE -+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE -+ -+ -+/* CPU cache information */ -+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+ -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ -+} -+#else -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+static __inline void mvOsPrefetch(const void *ptr) -+{ -+#ifdef CONFIG_USE_DSP -+ __asm__ __volatile__( -+ "pld\t%0" -+ : -+ : "o" (*(char *)ptr) -+ : "cc"); -+#else -+ return; -+#endif -+} -+ -+ -+/* Flush CPU pipe */ -+#define CPU_PIPE_FLUSH -+ -+ -+ -+ -+ -+/* register manipulations */ -+ -+/****************************************************************************** -+* This debug function enable the write of each register that u-boot access to -+* to an array in the DRAM, the function record only MV_REG_WRITE access. -+* The function could not be operate when booting from flash. -+* In order to print the array we use the printreg command. -+******************************************************************************/ -+/* #define REG_DEBUG */ -+#if defined(REG_DEBUG) -+extern int reg_arry[2048][2]; -+extern int reg_arry_index; -+#endif -+ -+/* Marvell controller register read/write macros */ -+#define MV_REG_VALUE(offset) \ -+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) -+ -+#define MV_REG_READ(offset) \ -+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); -+#endif -+ -+#define MV_REG_BYTE_READ(offset) \ -+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))) -+#endif -+ -+ -+ -+/* ARM architecture APIs */ -+MV_U32 mvOsCpuRevGet (MV_VOID); -+MV_U32 mvOsCpuPartGet (MV_VOID); -+MV_U32 mvOsCpuArchGet (MV_VOID); -+MV_U32 mvOsCpuVarGet (MV_VOID); -+MV_U32 mvOsCpuAsciiGet (MV_VOID); -+ -+/* Other APIs */ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+int mvOsRand(void); -+ -+#endif /* _MV_OS_LNX_H_ */ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h b/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h -new file mode 100644 -index 0000000..170481a ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h -@@ -0,0 +1,158 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsLinux.h - O.S. interface header file for Linux -+* -+* DESCRIPTION: -+* This header file contains OS dependent definition under Linux -+* -+* DEPENDENCIES: -+* Linux kernel header files. -+* -+* FILE REVISION NUMBER: -+* $Revision: 1.1 $ -+*******************************************************************************/ -+ -+#ifndef __INCmvOsLinuxh -+#define __INCmvOsLinuxh -+ -+/* Includes */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mvOs.h" -+ -+ -+/* Definitions */ -+#define MV_DEFAULT_QUEUE_DEPTH 2 -+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION -+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+ -+#ifdef CONFIG_MV88F6082 -+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE -+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 -+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+#endif -+ -+/* System dependent macro for flushing CPU write cache */ -+#if defined (MV_BRIDGE_SYNC_REORDER) -+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ -+ wmb(); \ -+ mvOsBridgeReorderWA(); \ -+ } while (0) -+#else -+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() -+#endif /* CONFIG_MV78XX0 */ -+ -+/* System dependent little endian from / to CPU conversions */ -+#define MV_CPU_TO_LE16(x) cpu_to_le16(x) -+#define MV_CPU_TO_LE32(x) cpu_to_le32(x) -+ -+#define MV_LE16_TO_CPU(x) le16_to_cpu(x) -+#define MV_LE32_TO_CPU(x) le32_to_cpu(x) -+ -+#ifdef __BIG_ENDIAN_BITFIELD -+#define MV_BIG_ENDIAN_BITFIELD -+#endif -+ -+/* System dependent register read / write in byte/word/dword variants */ -+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) -+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) -+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) -+#define MV_REG_READ_BYTE(base, offset) readb(base + offset) -+#define MV_REG_READ_WORD(base, offset) readw(base + offset) -+#define MV_REG_READ_DWORD(base, offset) readl(base + offset) -+ -+ -+/* Typedefs */ -+ -+/* System dependant typedefs */ -+typedef void *MV_VOID_PTR; -+typedef u32 *MV_U32_PTR; -+typedef u16 *MV_U16_PTR; -+typedef u8 *MV_U8_PTR; -+typedef char *MV_CHAR_PTR; -+typedef void *MV_BUS_ADDR_T; -+typedef unsigned long MV_CPU_FLAGS; -+ -+ -+/* Structures */ -+/* System dependent structure */ -+typedef struct mvOsSemaphore -+{ -+ int notUsed; -+} MV_OS_SEMAPHORE; -+ -+ -+/* Functions (User implemented)*/ -+ -+/* Semaphore init, take and release */ -+#define mvOsSemInit(x) MV_TRUE -+#define mvOsSemTake(x) -+#define mvOsSemRelease(x) -+ -+/* Interrupt masking and unmasking functions */ -+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); -+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); -+ -+/* Delay function in micro seconds resolution */ -+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); -+ -+/* Typedefs */ -+typedef enum mvBoolean -+{ -+ MV_SFALSE, MV_STRUE -+} MV_BOOLEAN; -+ -+/* System logging function */ -+#include "mvLog.h" -+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ -+#ifdef MV_LOGGER -+#define MV_SATA_SUPPORT_READ_WRITE_LONG -+#endif -+ -+#define MV_IAL_LOG_ID 3 -+ -+#endif /* __INCmvOsLinuxh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h b/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h -new file mode 100644 -index 0000000..8352290 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h -@@ -0,0 +1,375 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvSysHwCfg.h - Marvell system HW configuration file -+* -+* DESCRIPTION: -+* None. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __INCmvSysHwConfigh -+#define __INCmvSysHwConfigh -+ -+#include "../../../../include/linux/autoconf.h" -+ -+#define CONFIG_MARVELL 1 -+ -+/* includes */ -+#define _1K 0x00000400 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/****************************************/ -+/* Soc supporeted Units definitions */ -+/****************************************/ -+ -+#ifdef CONFIG_MV_INCLUDE_PEX -+#define MV_INCLUDE_PEX -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_CESA -+#define MV_INCLUDE_CESA -+#endif -+#ifdef CONFIG_MV_INCLUDE_GIG_ETH -+#define MV_INCLUDE_GIG_ETH -+#endif -+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_SATA -+#endif -+#ifdef CONFIG_MV_INCLUDE_USB -+#define MV_INCLUDE_USB -+#define MV_USB_VOLTAGE_FIX -+#endif -+#ifdef CONFIG_MV_INCLUDE_NAND -+#define MV_INCLUDE_NAND -+#endif -+#ifdef CONFIG_MV_INCLUDE_TDM -+#define MV_INCLUDE_TDM -+#endif -+#ifdef CONFIG_MV_INCLUDE_XOR -+#define MV_INCLUDE_XOR -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_UART -+#define MV_INCLUDE_UART -+#endif -+#ifdef CONFIG_MV_INCLUDE_SPI -+#define MV_INCLUDE_SPI -+#endif -+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD -+#define MV_INCLUDE_SFLASH_MTD -+#endif -+#ifdef CONFIG_MV_INCLUDE_AUDIO -+#define MV_INCLUDE_AUDIO -+#endif -+#ifdef CONFIG_MV_INCLUDE_TS -+#define MV_INCLUDE_TS -+#endif -+#ifdef CONFIG_MV_INCLUDE_SDIO -+#define MV_INCLUDE_SDIO -+#endif -+ -+ -+/* NAND flash stuff */ -+#ifdef CONFIG_MV_NAND_BOOT -+#define MV_NAND_BOOT -+#endif -+#ifdef CONFIG_MV_NAND -+#define MV_NAND -+#endif -+ -+/* SPI flash stuff */ -+#ifdef CONFIG_MV_SPI_BOOT -+#define MV_SPI_BOOT -+#endif -+ -+ -+/****************************************************************/ -+/************* General configuration ********************/ -+/****************************************************************/ -+ -+/* Enable Clock Power Control */ -+#define MV_INCLUDE_CLK_PWR_CNTRL -+ -+/* Disable the DEVICE BAR in the PEX */ -+#define MV_DISABLE_PEX_DEVICE_BAR -+ -+/* Allow the usage of early printings during initialization */ -+#define MV_INCLUDE_EARLY_PRINTK -+ -+/****************************************************************/ -+/************* NFP configuration ********************************/ -+/****************************************************************/ -+#define MV_NFP_SEC_Q_SIZE 64 -+#define MV_NFP_SEC_REQ_Q_SIZE 1000 -+ -+ -+ -+/****************************************************************/ -+/************* CESA configuration ********************/ -+/****************************************************************/ -+ -+#ifdef MV_INCLUDE_CESA -+ -+#define MV_CESA_MAX_CHAN 4 -+ -+/* Use 2K of SRAM */ -+#define MV_CESA_MAX_BUF_SIZE 1600 -+ -+#endif /* MV_INCLUDE_CESA */ -+ -+#if defined(CONFIG_MV_INCLUDE_GIG_ETH) -+ -+#ifdef CONFIG_MV_NFP_STATS -+#define MV_FP_STATISTICS -+#else -+#undef MV_FP_STATISTICS -+#endif -+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_SKB_REUSE_DEFAULT 1 -+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_TX_EN_DEFAULT 0 -+ -+/* un-comment if you want to perform tx_done from within the poll function */ -+/* #define ETH_TX_DONE_ISR */ -+ -+/* put descriptors in uncached memory */ -+/* #define ETH_DESCR_UNCACHED */ -+ -+/* Descriptors location: DRAM/internal-SRAM */ -+#define ETH_DESCR_IN_SDRAM -+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ -+ -+#if defined(ETH_DESCR_IN_SRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" -+#endif -+#elif defined(ETH_DESCR_IN_SDRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" -+#endif -+#else -+ #error "Ethernet descriptors location undefined" -+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ -+ -+/* SW Sync-Barrier: not relevant for 88fxx81*/ -+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ -+/* In RX the CPU theoretically might see himself as the descriptor owner, */ -+/* although the buffer hadn't been written to DRAM yet. Performance cost. */ -+/* #define INCLUDE_SYNC_BARR */ -+ -+/* Buffers cache coherency method (buffers in DRAM) */ -+#ifndef MV_CACHE_COHER_SW -+/* Taken from mvCommon.h */ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+#endif -+ -+/* DRAM cache coherency configuration */ -+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW -+ -+ -+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ -+ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) -+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" -+#elif (ETHER_DRAM_COHER == MV_UNCACHED) -+# define ETH_SDRAM_CONFIG_STR "DRAM uncached" -+#else -+ #error "Ethernet-DRAM undefined" -+#endif /* ETHER_DRAM_COHER */ -+ -+ -+/****************************************************************/ -+/************* Ethernet driver configuration ********************/ -+/****************************************************************/ -+ -+/* port's default queueus */ -+#define ETH_DEF_TXQ 0 -+#define ETH_DEF_RXQ 0 -+ -+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM -+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM -+ -+/* interrupt coalescing setting */ -+#define ETH_TX_COAL 200 -+#define ETH_RX_COAL 200 -+ -+/* Checksum offloading */ -+#define TX_CSUM_OFFLOAD -+#define RX_CSUM_OFFLOAD -+ -+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ -+ -+/****************************************************************/ -+/*************** Telephony configuration ************************/ -+/****************************************************************/ -+#if defined(CONFIG_MV_TDM_LINEAR_MODE) -+ #define MV_TDM_LINEAR_MODE -+#elif defined(CONFIG_MV_TDM_ULAW_MODE) -+ #define MV_TDM_ULAW_MODE -+#endif -+ -+#if defined(CONFIG_MV_TDM_5CHANNELS) -+ #define MV_TDM_5CHANNELS -+#endif -+ -+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) -+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE -+#endif -+ -+/* We use the following registers to store DRAM interface pre configuration */ -+/* auto-detection results */ -+/* IMPORTANT: We are using mask register for that purpose. Before writing */ -+/* to units mask register, make sure main maks register is set to disable */ -+/* all interrupts. */ -+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ -+#define DRAM_BUF_REG1 0x30820 /* sdram config */ -+#define DRAM_BUF_REG2 0x30830 /* sdram mode */ -+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ -+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ -+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ -+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ -+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ -+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ -+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ -+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ -+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ -+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ -+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ -+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ -+ -+/* Following the pre-configuration registers default values restored after */ -+/* auto-detection is done */ -+#define DRAM_BUF_REG_DV 0 -+ -+/* System Mapping */ -+#define SDRAM_CS0_BASE 0x00000000 -+#define SDRAM_CS0_SIZE _256M -+ -+#define SDRAM_CS1_BASE 0x10000000 -+#define SDRAM_CS1_SIZE _256M -+ -+#define SDRAM_CS2_BASE 0x20000000 -+#define SDRAM_CS2_SIZE _256M -+ -+#define SDRAM_CS3_BASE 0x30000000 -+#define SDRAM_CS3_SIZE _256M -+ -+/* PEX */ -+#define PEX0_MEM_BASE 0xe8000000 -+#define PEX0_MEM_SIZE _128M -+ -+#define PEX0_IO_BASE 0xf2000000 -+#define PEX0_IO_SIZE _1M -+ -+/* Device Chip Selects */ -+#define NFLASH_CS_BASE 0xfa000000 -+#define NFLASH_CS_SIZE _2M -+ -+#define SPI_CS_BASE 0xf4000000 -+#define SPI_CS_SIZE _16M -+ -+#define CRYPT_ENG_BASE 0xf0000000 -+#define CRYPT_ENG_SIZE _2M -+ -+#define BOOTDEV_CS_BASE 0xff800000 -+#define BOOTDEV_CS_SIZE _8M -+ -+/* CS2 - BOOTROM */ -+#define DEVICE_CS2_BASE 0xff900000 -+#define DEVICE_CS2_SIZE _1M -+ -+/* PEX Work arround */ -+/* the target we will use for the workarround */ -+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM -+/*a flag that indicates if we are going to use the -+size and base of the target we using for the workarround -+window */ -+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 -+/* if the above flag is 0 then the following values -+will be used for the workarround window base and size, -+otherwise the following defines will be ignored */ -+#define PEX_CONFIG_RW_WA_BASE 0xF3000000 -+#define PEX_CONFIG_RW_WA_SIZE _16M -+ -+/* Internal registers: size is defined in Controllerenvironment */ -+#define INTER_REGS_BASE 0xFEE00000 -+ -+/* DRAM detection stuff */ -+#define MV_DRAM_AUTO_SIZE -+ -+/* Board clock detection */ -+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ -+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ -+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ -+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ -+ -+/* PEX-PCI\PCI-PCI Bridge*/ -+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ -+ -+ -+ -+#endif /* __INCmvSysHwConfigh */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c b/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c -new file mode 100644 -index 0000000..6be5ea8 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvCntmr.h" -+#include "cpu/mvCpu.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern unsigned int whoAmI(void); -+ -+/******************************************************************************* -+* mvCntmrLoad - -+* -+* DESCRIPTION: -+* Load an init Value to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* value - value to be loaded -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) -+{ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrRead - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter value -+*******************************************************************************/ -+MV_U32 mvCntmrRead(MV_U32 countNum) -+{ -+ return MV_REG_READ(CNTMR_VAL_REG(countNum)); -+} -+ -+/******************************************************************************* -+* mvCntmrWrite - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* countVal - value to write -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+*******************************************************************************/ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) -+{ -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlSet - -+* -+* DESCRIPTION: -+* Set the Control to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ -+ if (pCtrl->enable) /* enable counter\timer */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ } -+ else /* disable counter\timer */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ } -+ -+ if ( pCtrl->autoEnable ) /* Auto mode */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); -+ -+ } -+ else /* no auto mode */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); -+ } -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlGet - -+* -+* DESCRIPTION: -+* Get the Control value of a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* Counter\Timer control value -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) -+ { -+ pCtrl->enable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->enable = MV_FALSE; -+ } -+ -+ /* counter mode */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) -+ { -+ pCtrl->autoEnable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->autoEnable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrEnable - -+* -+* DESCRIPTION: -+* Set the Enable-Bit to logic '1' ==> starting the counter -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrEnable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrDisable - -+* -+* DESCRIPTION: -+* Stop the counter/timer running, and returns its Value -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter\timer value -+*******************************************************************************/ -+MV_STATUS mvCntmrDisable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* disable counter\timer */ -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrStart - -+* -+* DESCRIPTION: -+* Combined all the sub-operations above to one function: Load,setMode,Enable -+* -+* INPUT: -+* countNum - counter number -+* value - value of the counter\timer to be set -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl) -+{ -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* load value onto counter\timer */ -+ mvCntmrLoad(countNum,value); -+ -+ /* set the counter to load in the first time */ -+ mvCntmrWrite(countNum,value); -+ -+ /* set control for timer \ cunter and enable */ -+ mvCntmrCtrlSet(countNum,pCtrl); -+ -+ return MV_OK; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h b/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h -new file mode 100644 -index 0000000..b4b1a9d ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrWtdgh -+#define __INCmvTmrWtdgh -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "cntmr/mvCntmrRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+/* This enumerator describe counters\watchdog numbers */ -+typedef enum _mvCntmrID -+{ -+ TIMER0 = 0, -+ TIMER1, -+ WATCHDOG, -+ TIMER2, -+ TIMER3, -+}MV_CNTMR_ID; -+ -+ -+/* Counter / Timer control structure */ -+typedef struct _mvCntmrCtrl -+{ -+ MV_BOOL enable; /* enable */ -+ MV_BOOL autoEnable; /* counter/Timer */ -+}MV_CNTMR_CTRL; -+ -+ -+/* Functions */ -+ -+/* Load an init Value to a given counter/timer */ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); -+ -+/* Returns the value of the given Counter/Timer */ -+MV_U32 mvCntmrRead(MV_U32 countNum); -+ -+/* Write a value of the given Counter/Timer */ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); -+ -+/* Set the Control to a given counter/timer */ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Get the value of a given counter/timer */ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Set the Enable-Bit to logic '1' ==> starting the counter. */ -+MV_STATUS mvCntmrEnable(MV_U32 countNum); -+ -+/* Stop the counter/timer running, and returns its Value. */ -+MV_STATUS mvCntmrDisable(MV_U32 countNum); -+ -+/* Combined all the sub-operations above to one function: Load,setMode,Enable */ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl); -+ -+#endif /* __INCmvTmrWtdgh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h -new file mode 100644 -index 0000000..1cd9041 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrwtdgRegsh -+#define __INCmvTmrwtdgRegsh -+ -+/*******************************************/ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_CTRL_REG (CNTMR_BASE) -+ -+/*For MV78XX0*/ -+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) -+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) -+ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+ -+/* ARM Timers Control Register */ -+/* CPU_TIMERS_CTRL_REG (CTCR) */ -+ -+#define TIMER0_NUM 0 -+#define TIMER1_NUM 1 -+#define WATCHDOG_NUM 2 -+#define TIMER2_NUM 3 -+#define TIMER3_NUM 4 -+ -+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+ -+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 -+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+ -+ -+/* ARM Timer\Watchdog Reload Register */ -+/* CNTMR_RELOAD_REG (TRR) */ -+ -+#define TRG_ARM_TIMER_REL_OFFS 0 -+#define TRG_ARM_TIMER_REL_MASK 0xffffffff -+ -+/* ARM Timer\Watchdog Register */ -+/* CNTMR_VAL_REG (TVRG) */ -+ -+#define TVR_ARM_TIMER_OFFS 0 -+#define TVR_ARM_TIMER_MASK 0xffffffff -+#define TVR_ARM_TIMER_MAX 0xffffffff -+ -+ -+ -+#endif /* __INCmvTmrwtdgRegsh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c b/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c -new file mode 100644 -index 0000000..03d6d09 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c -@@ -0,0 +1,207 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuCntrs.h" -+ -+ -+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = -+{ -+ /*0*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, -+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, -+ }, -+ /*1*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*2*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, -+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*3*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, -+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, -+ MV_CPU_CNTRS_INVALID, -+ } -+}; -+ -+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; -+ -+void mvCpuCntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); -+} -+ -+void program_counter(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ case 2: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); -+ return; -+ -+ case 3: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ int i; -+ -+ /* Find required operations */ -+ for(i=0; inum_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ if(counters_avg >= mvCpuCntrsTbl[i].overhead) -+ counters_avg -= mvCpuCntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuCntrsEventClear(pEvent); -+ mvCpuCntrsReset(); -+} -+ -+void mvCpuCntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_before[1] = mvCpuCntrsRead(1); -+ pEvent->counters_before[3] = mvCpuCntrsRead(3); -+ pEvent->counters_before[0] = mvCpuCntrsRead(0); -+ pEvent->counters_before[2] = mvCpuCntrsRead(2); -+#endif -+} -+ -+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+#if 0 -+ /* order is important - we want to measure the cycle count first here! */ -+ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_after[2] = mvCpuCntrsRead(2); -+ pEvent->counters_after[0] = mvCpuCntrsRead(0); -+ pEvent->counters_after[3] = mvCpuCntrsRead(3); -+ pEvent->counters_after[1] = mvCpuCntrsRead(1); -+#endif -+ -+ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_PERF_CNTRS -+ -+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) -+ -+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) -+ -+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) -+ -+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) -+ -+#else -+ -+#define MV_CPU_CNTRS_READ(counter) -+#define MV_CPU_CNTRS_START(event) -+#define MV_CPU_CNTRS_STOP(event) -+#define MV_CPU_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuCntrs_h__ */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c b/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c -new file mode 100644 -index 0000000..2401002 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuL2Cntrs.h" -+ -+ -+ -+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; -+ -+void mvCpuL2CntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); -+} -+ -+static void mvCpuL2CntrConfig(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); -+ mvCpuL2CntrsTbl[counter].operation = op; -+ mvCpuL2CntrsTbl[counter].opIdx = op; -+ mvCpuL2CntrsTbl[counter].overhead = overhead; -+ mvCpuL2CntrConfig(counter, op); -+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", -+ counter, op, overhead); -+ return MV_OK; -+} -+ -+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ MV_U64 counters_avg; -+ -+ if(pEvent->num_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ -+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) -+ counters_avg -= mvCpuL2CntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuL2CntrsEventClear(pEvent); -+ mvCpuL2CntrsReset(); -+} -+ -+void mvCpuL2CntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); -+} -+ -+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); -+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS -+ -+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) -+ -+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) -+ -+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) -+ -+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) -+ -+#else -+ -+#define MV_CPU_L2_CNTRS_READ(counter) -+#define MV_CPU_L2_CNTRS_START(event) -+#define MV_CPU_L2_CNTRS_STOP(event) -+#define MV_CPU_L2_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuL2Cntrs_h__ */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c -new file mode 100644 -index 0000000..5c6db90 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c -@@ -0,0 +1,1479 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ddr1_2/mvDram.h" -+#include "boardEnv/mvBoardEnvLib.h" -+ -+#undef MV_DEBUG -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 cas2ps(MV_U8 spd_byte); -+/******************************************************************************* -+* mvDramBankGet - Get the DRAM bank paramters. -+* -+* DESCRIPTION: -+* This function retrieves DRAM bank parameters as described in -+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -+* from it. Otherwise, if the DRAM is soldered on board, the function -+* should insert its bank information into MV_DRAM_BANK_INFO struct. -+* -+* INPUT: -+* bankNum - Board DRAM bank number. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* MV_FAIL - Bank parameters could not be read. -+* -+*******************************************************************************/ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_DIMM_INFO dimmInfo; -+ -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); -+ /* zero pBankInfo structure */ -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+ -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[91], spdRawData[92]); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h -new file mode 100644 -index 0000000..6e79d1e ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h -@@ -0,0 +1,191 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr1_2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c -new file mode 100644 -index 0000000..c44dabe ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c -@@ -0,0 +1,1599 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ddr1_2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* DRAM bank presence encoding */ -+#define BANK_PRESENT_CS0 0x1 -+#define BANK_PRESENT_CS0_CS1 0x3 -+#define BANK_PRESENT_CS0_CS2 0x5 -+#define BANK_PRESENT_CS0_CS1_CS2 0x7 -+#define BANK_PRESENT_CS0_CS2_CS3 0xd -+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf -+ -+/* locals */ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+#if defined(MV_INC_BOARD_DDIM) -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -+static MV_U32 sdramModeRegCalc(MV_U32 minCas); -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl); -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk); -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk); -+ -+/******************************************************************************* -+* mvDramIfDetect - Prepare DRAM interface configuration values. -+* -+* DESCRIPTION: -+* This function implements the full DRAM detection and timing -+* configuration for best system performance. -+* Since this routine runs from a ROM device (Boot Flash), its stack -+* resides on RAM, that might be the system DRAM. Changing DRAM -+* configuration values while keeping vital data in DRAM is risky. That -+* is why the function does not preform the configuration setting but -+* prepare those in predefined 32bit registers (in this case IDMA -+* registers are used) for other routine to perform the settings. -+* The function will call for board DRAM SPD information for each DRAM -+* chip select. The function will then analyze those SPD parameters of -+* all DRAM banks in order to decide on DRAM configuration compatible -+* for all DRAM banks. -+* The function will set the CPU DRAM address decode registers. -+* Note: This routine prepares values that will overide configuration of -+* mvDramBasicAsmInit(). -+* -+* INPUT: -+* forcedCl - Forced CAL Latency. If equal to zero, do not force. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -+{ -+ MV_U32 retVal = MV_OK; /* return value */ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; -+ MV_U8 minCas; -+ MV_DRAM_DEC_WIN dramDecWin; -+ -+ dramDecWin.addrWin.baseHigh = 0; -+ -+ busClk = mvBoardSysClkGet(); -+ -+ if (0 == busClk) -+ { -+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); -+ return MV_ERROR; -+ } -+ -+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) -+ mvCpuIfTargetWinEnable(i, MV_FALSE); -+#endif -+ -+ /* we will use bank 0 as the representative of the all the DRAM banks, */ -+ /* since bank 0 must exist. */ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ /* if Bank exist */ -+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) -+ { -+ /* check it isn't SDRAM */ -+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) -+ { -+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); -+ return MV_ERROR; -+ } -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* Init the CPU window decode */ -+ /* Note that the size in Bank info is in MB units */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ if(i == SDRAM_CS0) -+ { -+ MV_U32 sizeToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Size is located at upper 16 bits */ -+ sizeToReg <<= SCSR_SIZE_OFFS; -+ -+ /* enable it */ -+ sizeToReg |= SCSR_WIN_EN; -+ -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ -+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", -+ SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 4\n"); -+ } -+ else -+ { -+ minCas = DDR1_CL_3; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 3\n"); -+ } -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ sdramDDr2OdtConfig(bankInfo); -+ } -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return retVal; -+} -+ -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL */ -+ if (forcedCl) -+ { -+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), -+ (forcedCl % 10)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ else -+ { -+ if (forcedCl == 15) -+ pBankInfo->suportedCasLatencies = 0x02; -+ else if (forcedCl == 20) -+ pBankInfo->suportedCasLatencies = 0x04; -+ else if (forcedCl == 25) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ -+ /* SDRAM DDR2 controller supports CL 3 to 5 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ -+ } -+ else -+ { -+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ -+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ return (BIT0 << j); -+ } -+ } -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); -+ } -+ -+ /* set DDR SDRAM devices configuration */ -+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 8: /* memory is x8 */ -+ sdramConfig |= SDRAM_DCFG_X8_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ sdramConfig |= SDRAM_DCFG_X16_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ mvOsPrintf("DRAM CAS Latency "); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ mvOsPrintf("3.\n"); -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ mvOsPrintf("4.\n"); -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ mvOsPrintf("5.\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR2_MODE_REG_DV; -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ sdramMode |= SDRAM_DDR1_CL_1_5; -+ mvOsPrintf("1.5\n"); -+ break; -+ case DDR1_CL_2: -+ sdramMode |= SDRAM_DDR1_CL_2; -+ mvOsPrintf("2\n"); -+ break; -+ case DDR1_CL_2_5: -+ sdramMode |= SDRAM_DDR1_CL_2_5; -+ mvOsPrintf("2.5\n"); -+ break; -+ case DDR1_CL_3: -+ sdramMode |= SDRAM_DDR1_CL_3; -+ mvOsPrintf("3\n"); -+ break; -+ case DDR1_CL_4: -+ sdramMode |= SDRAM_DDR1_CL_4; -+ mvOsPrintf("4\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR1_MODE_REG_DV; -+ } -+ -+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+ -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ default: -+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -+{ -+ MV_U32 dunitCtrlLow; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ /* Clear StBurstDel field */ -+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; -+ -+#ifdef MV_88W8660 -+ /* Clear address/control output timing field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -+#endif /* MV_88W8660 */ -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstDel bits [27:24] */ -+ /********-********-********-********-********-********* -+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * -+ *********-********-********-********-********-********* -+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * -+ *********-********-********-********-********-********* -+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * -+ *********-********-********-********-********-*********/ -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR2_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ -+ } -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ /* Set Address Control register static configuration bits */ -+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); -+ -+ /* Set address control default value */ -+ addrCtrl |= SDRAM_ADDR_CTRL_DV; -+ -+ /* Clear DSize field */ -+ addrCtrl &= ~SDRAM_DSIZE_MASK; -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 128: /* 128 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_128Mb; -+ break; -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb; -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb; -+ break; -+ default: -+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ /* Micron work around for 133MHz */ -+ if (busClk == 133) -+ tRp += 1; -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ } -+ else -+ { -+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); -+ -+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) -+ { -+ tWtr = 2; -+ } -+ else -+ { -+ tWtr = 1; -+ } -+ -+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ -+ } -+ -+ DB(mvOsPrintf("tWtr = %d\n", tWtr)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ ((tRas - 1) << SDRAM_TRAS_OFFS) | -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timeNs = 0; -+ int bankNum; -+ MV_U32 sdramTw2wCyc = 0; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* tRfc is different for DDR1 and DDR2. */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ MV_U32 bankNum; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ } -+ else -+ { -+ if (pBankInfo[0].deviceDensity == _1G) -+ { -+ timeNs = SDRAM_TRFC_1G; -+ } -+ else -+ { -+ if (200 == busClk) -+ { -+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; -+ } -+ else -+ { -+ timeNs = SDRAM_TRFC_64_512M; -+ } -+ } -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ -+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); -+ -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ sdramTw2wCyc++; -+ } -+ -+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ -+ if (sdramTw2wCyc > 1) -+ sdramTw2wCyc = 1; -+ else -+ sdramTw2wCyc = 0; -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | -+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | -+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | -+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | -+ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); -+ -+} -+ -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* ODT configuration is done according to DIMM presence: -+* -+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ default: -+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); -+ return; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+#endif /* defined(MV_INC_BOARD_DDIM) */ -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.size; -+ } -+ else -+ { -+ return 0; -+ } -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 totalSize = 0, bankSize = 0, bankNum; -+ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ bankSize = mvDramIfBankSizeGet(bankNum); -+ -+ if (-1 == bankSize) -+ { -+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); -+ return -1; -+ } -+ else -+ { -+ totalSize += bankSize; -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); -+ -+ return totalSize; -+} -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.baseLow; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h -new file mode 100644 -index 0000000..8ae67e7 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h -@@ -0,0 +1,179 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+/* includes */ -+#include "ddr1_2/mvDramIfRegs.h" -+#include "ddr1_2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ -+ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR1 supported CAS Latencies */ -+typedef enum _mvDimmDdr1Cas -+{ -+ DDR1_CL_1_5 = 0x02, -+ DDR1_CL_2 = 0x04, -+ DDR1_CL_2_5 = 0x08, -+ DDR1_CL_3 = 0x10, -+ DDR1_CL_4 = 0x40, -+ DDR1_CL_FAULT -+} MV_DIMM_DDR1_CAS; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+#include "ddr1_2/mvDram.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -+MV_VOID _mvDramIfConfig(MV_VOID); -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_32 mvDramIfSizeGet(MV_VOID); -+ -+#if 0 -+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -+#endif -+ -+#endif /* __INCmvDramIfh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h -new file mode 100644 -index 0000000..049595e ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV \ -+ (SDRAM_PERR_WRITE | \ -+ SDRAM_SRMODE | \ -+ SDRAM_SRCLK_GATED) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DV \ -+ (SDRAM_CTRL_POS_RISE | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ SDRAM_LOCKEN_ENABLE) -+ -+#define SDRAM_ADDR_CTRL_DV 0 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+/* TRFC 0x27, TW2W 0x1 */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ -+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ -+ ( 0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* DDR2 ODT default register values */ -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 -+ -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+ -+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR1_MODE_REG_DV 0x00000000 -+#define DDR2_MODE_REG_DV 0x00000400 -+ -+/* DDR SDRAM Timing parameter default values */ -+#define DDR1_TIMING_LOW_DV 0x11602220 -+#define DDR1_TIMING_HIGH_DV 0x0000000d -+ -+#define DDR2_TIMING_LOW_DV 0x11812220 -+#define DDR2_TIMING_HIGH_DV 0x0000030f -+ -+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ -+ (0x7F<< 12) | \ -+ (0x1 << 22)) -+ -+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ -+ -+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x3 << 14) | \ -+ (0x1 << 18) | \ -+ (0x1 << 22)) -+ -+ -+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ -+ -+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_250MHZ 0x445001 -+ -+/* Orion 1 B1 and above */ -+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 -+ -+/* Orion nas */ -+#define FTDLL_DDR2_166MHZ_5182 0x597001 -+ -+/* Orion 2 D0 and above */ -+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 -+ -+#endif /* __INCmvDramIfh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h -new file mode 100644 -index 0000000..f4a2726 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h -@@ -0,0 +1,306 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+/* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -+#define SCSR_WIN_EN BIT0 -+#define SCSR_SIZE_OFFS 16 -+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x10000 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG 0x1400 -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3000 -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 14 -+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DTYPE_OFFS 16 -+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_PERR_OFFS 18 -+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -+#define SDRAM_DCFG_OFFS 20 -+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -+#define SDRAM_SRMODE (1 << 24) -+#define SDRAM_SRCLK_OFFS 25 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CATTH_OFFS 26 -+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) -+ -+ -+/* dunit control register */ -+#define SDRAM_DUNIT_CTRL_REG 0x1404 -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_LOCKEN_OFFS 18 -+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_ST_BURST_DEL_OFFS 24 -+#define SDRAM_ST_BURST_DEL_MAX 0xf -+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) -+ { -+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support same ECC mode */ -+ if(bankInfo[i].errorCheckType != -+ bankInfo[0].errorCheckType) -+ { -+ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS2; -+ MV_DRAM_CS_order[1] = SDRAM_CS3; -+ MV_DRAM_CS_order[2] = SDRAM_CS0; -+ MV_DRAM_CS_order[3] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ } -+ else -+#endif -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS0; -+ MV_DRAM_CS_order[1] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ MV_DRAM_CS_order[2] = SDRAM_CS2; -+ MV_DRAM_CS_order[3] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ } -+ -+ for(j = 0; j < MV_DRAM_MAX_CS; j++) -+ { -+ i = MV_DRAM_CS_order[j]; -+ -+ if (0 == bankInfo[i].size) -+ continue; -+ -+ /* Init the CPU window decode */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+#ifdef MV78XX0 -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -+#else -+ deviceW = 16 /* KW family */; -+#endif -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ -+ numOfAllDevices += bankInfo[i].numberOfDevices; -+ if (i == MV_DRAM_CS_order[0]) -+ { -+ MV_U32 sizeToReg; -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) -+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); -+ sizeToReg |= SCSR_WIN_EN; -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ -+ /* Check if the DRAM size is more then 3GByte */ -+ if (base < 0xC0000000) -+ { -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsOutput("Set default CAS latency 4\n"); -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off ECC*/ -+ temp &= ~BIT18; -+ } -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ TTMode = MV_FALSE; -+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) -+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) -+ { -+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || -+ (numOfAllDevices > 18) ) -+ { -+ mvOsOutput("Enable 2T "); -+ TTMode = MV_TRUE; -+ } -+ } -+ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ -+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off sample stage if no ecc */ -+ temp &= ~SDRAM__D2P_EN;; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG13, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ sdramDDr2OdtConfig(bankInfo); -+ -+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ -+ temp = sdramDdr2TimeLoRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG11, temp); -+ -+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ -+ temp = sdramDdr2TimeHiRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG12, temp); -+#endif -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", -+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", -+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 size = 0, i; -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ size += mvDramIfBankSizeGet(i); -+ -+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); -+ return size; -+} -+ -+/******************************************************************************* -+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -+* -+* DESCRIPTION: -+* The ECC single bit error threshold is the number of single bit -+* errors to happen before the Dunit generates an interrupt. -+* This function set single bit ECC threshold. -+* -+* INPUT: -+* threshold - threshold. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -+{ -+ MV_U32 regVal; -+ -+ if (threshold > SECR_THRECC_MAX) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); -+ regVal &= ~SECR_THRECC_MASK; -+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); -+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); -+ -+ return MV_OK; -+} -+ -+#ifndef MV_STATIC_DRAM_ON_BOARD -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ MV_U32 minCas0 = 0, minCas2 = 0; -+ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * -+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ -+ if (forcedCl) -+ { -+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); -+ -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 50) -+ pBankInfo->suportedCasLatencies = 0x20; -+ else if (forcedCl == 60) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ count = 1; -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ count = 1; -+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo2->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo2->suportedCasLatencies )); -+ -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas0 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas2 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ if (minCas2 > minCas0) -+ return minCas2; -+ else -+ return minCas0; -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) -+ } -+ -+ /* ECC and IERR support */ -+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ -+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ -+ -+ if ( pBankInfo->errorCheckType ) -+ { -+ sdramConfig |= SDRAM_ECC_EN; -+ sdramConfig |= SDRAM_IERR_REPORTE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); -+ } -+ else -+ { -+ sdramConfig |= SDRAM_ECC_DIS; -+ sdramConfig |= SDRAM_IERR_IGNORE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); -+ } -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ DB(mvOsPrintf("DRAM CAS Latency ");) -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ DB(mvOsPrintf("3.\n");) -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ DB(mvOsPrintf("4.\n");) -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ DB(mvOsPrintf("5.\n");) -+ break; -+ case DDR2_CL_6: -+ sdramMode |= SDRAM_DDR2_CL_6; -+ DB(mvOsPrintf("6.\n");) -+ break; -+ default: -+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ -+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - DRAM frequency -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ if (busClk >= MV_BOARD_SYSCLK_267MHZ) -+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; -+ else -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; -+ -+ default: -+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -+{ -+ MV_U32 dunitCtrlLow, cl; -+ MV_U32 sbOutR[4]={3,5,7,9} ; -+ MV_U32 sbOutU[4]={1,3,5,7} ; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* Clear StBurstOutDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; -+ -+ /* Clear StBurstInDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; -+ -+ /* Clear CtrlPos field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; -+ -+ /* Clear 2T field */ -+ dunitCtrlLow &= ~SDRAM_2T_MASK; -+ if (TTMode == MV_TRUE) -+ { -+ dunitCtrlLow |= SDRAM_2T_MODE; -+ } -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstInDel bits [27:24] */ -+ /* 200MHz - 267MHz None reg = CL + 1 */ -+ /* 200MHz - 267MHz reg = CL + 2 */ -+ /* > 267MHz None reg = CL + 2 */ -+ /* > 267MHz reg = CL + 3 */ -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstOutDel bits [23:20] */ -+ /********-********-********-********- -+ * CL=3 | CL=4 | CL=5 | CL=6 | -+ *********-********-********-********- -+ Not Reg. * 0001 | 0011 | 0101 | 0111 | -+ *********-********-********-********- -+ Registered * 0011 | 0101 | 0111 | 1001 | -+ *********-********-********-********/ -+ -+ /* Set Dunit Control low default value */ -+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: cl = 3; break; -+ case DDR2_CL_4: cl = 4; break; -+ case DDR2_CL_5: cl = 5; break; -+ case DDR2_CL_6: cl = 6; break; -+ default: -+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); -+ return -1; -+ } -+ -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ { -+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ else -+ { -+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ -+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); -+ -+ if (busClk <= MV_BOARD_SYSCLK_267MHZ) -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 2; -+ else -+ cl = cl + 1; -+ } -+ else -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 3; -+ else -+ cl = cl + 2; -+ } -+ -+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); -+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; -+ -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -+* -+* DESCRIPTION: Calculate sdram dunit control high register optimized value based -+* on the bus clock. -+* -+* INPUT: -+* busClk - DRAM frequency. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 dunitCtrlHigh; -+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); -+ if(busClk > MV_BOARD_SYSCLK_300MHZ) -+ dunitCtrlHigh |= SDRAM__P2D_EN; -+ else -+ dunitCtrlHigh &= ~SDRAM__P2D_EN; -+ -+ if(busClk > MV_BOARD_SYSCLK_267MHZ) -+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); -+ -+ /* If ECC support we turn on D2P sample */ -+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ -+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) -+ dunitCtrlHigh |= SDRAM__D2P_EN; -+ -+ return dunitCtrlHigh; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ } -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); -+ break; -+ default: -+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); -+ break; -+ default: -+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfoDIMM1->deviceDensity); -+ return -1; -+ } -+ } -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ MV_U32 timeCtrlLow = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+ -+ /* Check extended tRas bit */ -+ if ((tRas - 1) & BIT4) -+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); -+ -+ return timeCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timingHigh; -+ MV_U32 timeNs = 0; -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Set DDR timing high register static configuration bits */ -+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); -+ -+ /* Set DDR timing high register default value */ -+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; -+ -+ /* Clear tRfc field */ -+ timingHigh &= ~SDRAM_TRFC_MASK; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", -+ pBankInfo[bankNum].minRefreshToActiveCmd)); -+ } -+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) -+ { -+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ -+ /* SDRAM timing high */ -+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); -+ -+ return timingHigh; -+} -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; -+ break; -+ default: -+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); -+ return; -+ } -+ /* DDR2 SDRAM ODT ctrl low */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ -+ /* DDR2 SDRAM ODT ctrl high */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ -+ /* DDR2 DUNIT ODT ctrl */ -+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ -+ -+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+/******************************************************************************* -+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing low registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing low reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeLoReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); -+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | -+ SD2TLR_TODT_OFF_RD_MASK | -+ SD2TLR_TODT_ON_CTRL_RD_MASK | -+ SD2TLR_TODT_OFF_CTRL_RD_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas)); -+ cl = 4; -+ } -+ -+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); -+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); -+ -+ /* DDR2 SDRAM timing low */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); -+ -+ return ddr2TimeLoReg; -+} -+ -+/******************************************************************************* -+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing high registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing high reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeHiReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); -+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | -+ SD2THR_TODT_OFF_WR_MASK | -+ SD2THR_TODT_ON_CTRL_WR_MASK | -+ SD2THR_TODT_OFF_CTRL_WR_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas); -+ cl = 4; -+ } -+ -+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); -+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); -+ -+ /* DDR2 SDRAM timin high */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); -+ -+ return ddr2TimeHiReg; -+} -+#endif -+ -+/******************************************************************************* -+* mvDramIfCalGet - Get CAS Latency -+* -+* DESCRIPTION: -+* This function get the CAS Latency. -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* CAS latency times 10 (to avoid using floating point). -+* -+*******************************************************************************/ -+MV_U32 mvDramIfCalGet(void) -+{ -+ MV_U32 sdramCasLat, casLatMask; -+ -+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); -+ -+ switch (casLatMask) -+ { -+ case SDRAM_DDR2_CL_3: -+ sdramCasLat = 30; -+ break; -+ case SDRAM_DDR2_CL_4: -+ sdramCasLat = 40; -+ break; -+ case SDRAM_DDR2_CL_5: -+ sdramCasLat = 50; -+ break; -+ case SDRAM_DDR2_CL_6: -+ sdramCasLat = 60; -+ break; -+ default: -+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); -+ return -1; -+ } -+ -+ return sdramCasLat; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -+* -+* DESCRIPTION: -+* add support in power management. -+* -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+ -+MV_VOID mvDramIfSelfRefreshSet() -+{ -+ MV_U32 operReg; -+ -+ operReg = MV_REG_READ(SDRAM_OPERATION_REG); -+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); -+ /* Read until register is reset to 0 */ -+ while(MV_REG_READ(SDRAM_OPERATION_REG)); -+} -+/******************************************************************************* -+* mvDramIfDimGetSPDversion - return DIMM SPD version. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ if (bankNum >= MV_DRAM_MAX_CS ) -+ { -+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); -+ return ; -+ } -+ memset(&dimmInfo,0,sizeof(dimmInfo)); -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return ; -+ } -+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; -+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -+} -+/******************************************************************************* -+* mvDramIfShow - Show DRAM controller information. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvDramIfShow(void) -+{ -+ int i, sdramCasLat, sdramCsSize; -+ MV_U32 Major=0, Minor=0; -+ -+ mvOsOutput("DRAM Controller info:\n"); -+ -+ mvOsOutput("Total DRAM "); -+ mvSizePrint(mvDramIfSizeGet()); -+ mvOsOutput("\n"); -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ sdramCsSize = mvDramIfBankSizeGet(i); -+ if (sdramCsSize) -+ { -+ if (0 == (i & 1)) -+ { -+ mvDramIfDimGetSPDversion(&Major, &Minor,i); -+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); -+ } -+ mvOsOutput("\tDRAM CS[%d] ", i); -+ mvSizePrint(sdramCsSize); -+ mvOsOutput("\n"); -+ } -+ } -+ sdramCasLat = mvDramIfCalGet(); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) -+ { -+ mvOsOutput("ECC enabled, "); -+ } -+ else -+ { -+ mvOsOutput("ECC Disabled, "); -+ } -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) -+ { -+ mvOsOutput("Registered DIMM\n"); -+ } -+ else -+ { -+ mvOsOutput("Non registered DIMM\n"); -+ } -+ -+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -+} -+/******************************************************************************* -+* mvDramIfGetFirstCS - find the DRAM bank on the lower address -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+*******************************************************************************/ -+MV_U32 mvDramIfGetFirstCS(void) -+{ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ -+ if (DRAM_CS_Order[0] == N_A) -+ { -+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -+#endif -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ return SDRAM_CS2; -+ } -+#endif -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ return SDRAM_CS0; -+ } -+ return DRAM_CS_Order[0]; -+} -+/******************************************************************************* -+* mvDramIfGetCSorder - -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* CS number. -+* -+* OUTPUT: -+* CS order. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -+*******************************************************************************/ -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -+{ -+ return DRAM_CS_Order[csOrder]; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h -new file mode 100644 -index 0000000..b7b596c ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h -@@ -0,0 +1,172 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ddr2/mvDramIfRegs.h" -+#include "ddr2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+ -+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -+#define ECC_DISABLE 1 /* Force ECC to Disable */ -+#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_6 = 0x40, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ MV_BOOL registeredDQMBinputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+#include "ddr2/spd/mvSpd.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -+MV_VOID _mvDramIfConfig(int entryNum); -+ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_U32 mvDramIfSizeGet(MV_VOID); -+MV_U32 mvDramIfCalGet(void); -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -+MV_VOID mvDramIfSelfRefreshSet(void); -+void mvDramIfShow(void); -+MV_U32 mvDramIfGetFirstCS(void); -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -+MV_U32 mvDramCsSizeGet(MV_U32 csNum); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h -new file mode 100644 -index 0000000..b008c23 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h -@@ -0,0 +1,157 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ -+ (SDRAM_SRCLK_KEPT | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ (BIT28 | BIT29)) -+ -+#define SDRAM_ADDR_CTRL_DV 2 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+ -+/* Note: value of 0 in register means one cycle, 1 means two and so on */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ -+ ((0x0 << SDRAM_TR2R_OFFS) | \ -+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ -+ (0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -+#endif -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -+#endif -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -+/* DDR SDRAM Timing parameter default values */ -+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -+#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) -+ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) -+ -+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h -new file mode 100644 -index 0000000..c2458a6 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+ /* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCSR_SIZE_OFFS 24 -+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x1000000 -+#define SCSR_WIN_EN BIT0 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3FFF -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 15 -+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_ECC_OFFS 18 -+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -+#define SDRAM_IERR_OFFS 19 -+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -+#define SDRAM_SRMODE_OFFS 24 -+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) -+ -+/* dunit control low register */ -+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -+#define SDRAM_2T_OFFS 4 -+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) -+ -+#define SDRAM_SRCLK_OFFS 5 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK2DRV_OFFS 13 -+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_SB_OUT_DEL_OFFS 20 -+#define SDRAM_SB_OUT_DEL_MAX 0xf -+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[62]/10, spdRawData[62]%10); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h -new file mode 100644 -index 0000000..ae692ef ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+#define DIMM_SPD_VERSION 62 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c -new file mode 100644 -index 0000000..2acd82b ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c -@@ -0,0 +1,2952 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver -+* -+* DESCRIPTION: -+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet -+* controller. This Gigabit Ethernet Controller driver API controls -+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). -+* 2) Data flow (i.e. port Send, Receive etc'). -+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) -+* 4) MIB counters support (ethReadMibCounter) -+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) -+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. -+* This struct includes configuration information as well as driver -+* internal data needed for its operations. -+* -+* Supported Features: -+* - OS independent. All required OS services are implemented via external -+* OS dependent components (like osLayer or ethOsg) -+* - The user is free from Rx/Tx queue managing. -+* - Simple Gigabit Ethernet port operation API. -+* - Simple Gigabit Ethernet port data flow API. -+* - Data flow and operation API support per queue functionality. -+* - Support cached descriptors for better performance. -+* - PHY access and control API. -+* - Port Configuration API. -+* - Full control over Special and Other Multicast MAC tables. -+* -+*******************************************************************************/ -+/* includes */ -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthGbe.h" -+#include "cpu/mvCpu.h" -+ -+#ifdef INCLUDE_SYNC_BARR -+#include "sys/mvCpuIf.h" -+#endif -+ -+#ifdef MV_RT_DEBUG -+# define ETH_DEBUG -+#endif -+ -+ -+/* locals */ -+MV_BOOL ethDescInSram; -+MV_BOOL ethDescSwCoher; -+ -+/* This array holds the control structure of each port */ -+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; -+ -+/* Ethernet Port Local routines */ -+ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethSetUcastTable(int portNo, int queue); -+ -+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); -+ -+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle); -+ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); -+ -+static void mvEthPortSgmiiConfig(int port); -+ -+ -+ -+/******************************************************************************/ -+/* EthDrv Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthHalInit - Initialize the Giga Ethernet unit -+* -+* DESCRIPTION: -+* This function initialize the Giga Ethernet unit. -+* 1) Configure Address decode windows of the unit -+* 2) Set registers to HW default values. -+* 3) Clear and Disable interrupts -+* -+* INPUT: NONE -+* -+* RETURN: NONE -+* -+* NOTE: this function is called once in the boot process. -+*******************************************************************************/ -+void mvEthHalInit(void) -+{ -+ int port; -+ -+ /* Init static data structures */ -+ for (port=0; port 0) -+ { -+ isSram = MV_TRUE; -+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) -+ isSwCoher = MV_TRUE; -+ #else -+ isSwCoher = MV_FALSE; -+ #endif -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+ if(pIsSram != NULL) -+ *pIsSram = isSram; -+ -+ if(pIsSwCoher != NULL) -+ *pIsSwCoher = isSwCoher; -+} -+ -+ -+ -+/******************************************************************************/ -+/* Port Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthPortInit - Initialize the Ethernet port driver -+* -+* DESCRIPTION: -+* This function initialize the ethernet port. -+* 1) Allocate and initialize internal port Control structure. -+* 2) Create RX and TX descriptor rings for default RX and TX queues -+* 3) Disable RX and TX operations, clear cause registers and -+* mask all interrupts. -+* 4) Set all registers to default values and clean all MAC tables. -+* -+* INPUT: -+* int portNo - Ethernet port number -+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure -+* -+* RETURN: -+* void* - ethernet port handler, that should be passed to the most other -+* functions dealing with this port. -+* -+* NOTE: This function is called once per port when loading the eth module. -+*******************************************************************************/ -+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) -+{ -+ int queue, descSize; -+ ETH_PORT_CTRL* pPortCtrl; -+ -+ /* Check validity of parameters */ -+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || -+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || -+ (pEthPortInit->maxRxPktSize < 1518) ) -+ { -+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); -+ return NULL; -+ } -+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) -+ { -+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", -+ portNo, pEthPortInit->rxDefQ); -+ return NULL; -+ } -+ -+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); -+ if(pPortCtrl == NULL) -+ { -+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", -+ (int)sizeof(ETH_PORT_CTRL), portNo); -+ return NULL; -+ } -+ -+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); -+ ethPortCtrl[portNo] = pPortCtrl; -+ -+ pPortCtrl->portState = MV_UNDEFINED_STATE; -+ -+ pPortCtrl->portNo = portNo; -+ -+ pPortCtrl->osHandle = pEthPortInit->osHandle; -+ -+ /* Copy Configuration parameters */ -+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; -+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; -+ pPortCtrl->portConfig.ejpMode = 0; -+ -+ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; -+ } -+ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; -+ } -+ -+ mvEthPortDisable(pPortCtrl); -+ -+ /* Set the board information regarding PHY address */ -+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); -+ -+ /* Create all requested RX queues */ -+ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for RX descriptors */ -+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->rxQueue[queue].descBuf.memHandle); -+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", -+ pPortCtrl->portNo, queue, descSize, -+ ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->rxQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitRxDescRing(pPortCtrl, queue); -+ } -+ /* Create TX queues */ -+ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for TX descriptors */ -+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->txQueue[queue].descBuf.memHandle); -+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", -+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->txQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitTxDescRing(pPortCtrl, queue); -+ } -+ mvEthDefaultsSet(pPortCtrl); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return pPortCtrl; -+} -+ -+/******************************************************************************* -+* ethPortFinish - Finish the Ethernet port driver -+* -+* DESCRIPTION: -+* This function finish the ethernet port. -+* 1) Down ethernet port if needed. -+* 2) Delete RX and TX descriptor rings for all created RX and TX queues -+* 3) Free internal port Control structure. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: NONE. -+* -+*******************************************************************************/ -+void mvEthPortFinish(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ int queue, portNo = pPortCtrl->portNo; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", -+ portNo); -+ mvEthPortDisable(pPortHndl); -+ } -+ -+ /* Free all allocated RX queues */ -+ for(queue=0; queuerxQueue[queue].descBuf); -+ } -+ -+ /* Free all allocated TX queues */ -+ for(queue=0; queuetxQueue[queue].descBuf); -+ } -+ -+ /* Free port control structure */ -+ mvOsFree(pPortCtrl); -+ -+ ethPortCtrl[portNo] = NULL; -+} -+ -+/******************************************************************************* -+* mvEthDefaultsSet - Set defaults to the ethernet port -+* -+* DESCRIPTION: -+* This function set default values to the ethernet port. -+* 1) Clear Cause registers and Mask all interrupts -+* 2) Clear all MAC tables -+* 3) Set defaults to all registers -+* 4) Reset all created RX and TX descriptors ring -+* 5) Reset PHY -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure -+* NOTE: -+* This function update all the port configuration except those set -+* Initialy by the OsGlue by MV_ETH_PORT_INIT. -+* This function can be called after portDown to return the port setting -+* to defaults. -+*******************************************************************************/ -+MV_STATUS mvEthDefaultsSet(void* pPortHndl) -+{ -+ int ethPortNo, queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_U32 txPrio; -+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; -+ MV_BOARD_MAC_SPEED boardMacCfg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Clear Cause registers */ -+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); -+ -+ /* Mask all interrupts */ -+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); -+ -+ portCfgReg = PORT_CONFIG_VALUE; -+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; -+ -+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); -+ -+ if(boardMacCfg == BOARD_MAC_SPEED_100M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; -+ } -+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; -+ } -+ else -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; -+ } -+ -+ /* build PORT_SDMA_CONFIG_REG */ -+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); -+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ -+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) -+ /* some devices have restricted RX burst size when using HW coherency */ -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); -+#else -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+#endif -+ -+#if defined(MV_CPU_BE) -+ /* big endian */ -+# if defined(MV_ARM) -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_DESC_SWAP_MASK); -+# elif defined(MV_PPC) -+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | -+ ETH_TX_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+# else -+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" -+# endif /* MV_ARM / MV_PPC */ -+ -+#else /* MV_CPU_LE */ -+ /* little endian */ -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+#endif /* MV_CPU_BE / MV_CPU_LE */ -+ -+ pPortCtrl->portRxQueueCmdReg = 0; -+ pPortCtrl->portTxQueueCmdReg = 0; -+ -+#if (MV_ETH_VERSION >= 4) -+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) -+ } -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+ ethSetUcastTable(ethPortNo, -1); -+ mvEthSetSpecialMcastTable(ethPortNo, -1); -+ mvEthSetOtherMcastTable(ethPortNo, -1); -+ -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ /* Update value of PortConfig register accordingly with all RxQueue types */ -+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; -+ -+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Assignment of Tx CTRP of given queue */ -+ txPrio = 0; -+ -+ for(queue=0; queuetxQueue[queue]; -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ ethResetTxDescRing(pPortCtrl, queue); -+ -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), -+ 0x3fffffff); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), -+ 0x03ffffff); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); -+ } -+ } -+ -+ /* Assignment of Rx CRDP of given queue */ -+ for(queue=0; queueportNo; -+ -+ if( (pPortCtrl->portState != MV_ACTIVE) && -+ (pPortCtrl->portState != MV_PAUSED) ) -+ { -+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", -+ ethPortNo, pPortCtrl->portState); -+ return MV_BAD_STATE; -+ } -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port RX. */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); -+ -+ /* Enable port TX. */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ pPortCtrl->portState = MV_ACTIVE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethPortDown - Stop the Ethernet port activity. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE : used for port link down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDown(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int uDelay, mDelay; -+ -+ /* Stop Rx port activity. Check port Rx activity. */ -+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); -+ } -+ -+ /* Stop Tx port activity. Check port Tx activity. */ -+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), -+ (regData << ETH_TXQ_DISABLE_OFFSET) ); -+ } -+ -+ /* Force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait for all Rx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port RX Command register that all Rx queues are stopped */ -+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Wait for all Tx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port TX Command register that all Tx queues are stopped */ -+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Double check to Verify that TX FIFO is Empty */ -+ mDelay = 0; -+ while(MV_TRUE) -+ { -+ do -+ { -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ } -+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || -+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); -+ -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ break; -+ -+ /* Double check */ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && -+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) -+ { -+ break; -+ } -+ else -+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", -+ ethPortNum, mDelay, regData); -+ } -+ -+ /* Do NOT force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait about 2500 tclk cycles */ -+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); -+ mvOsUDelay(uDelay); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ethPortEnable - Enable the Ethernet port and Start RX and TX. -+* -+* DESCRIPTION: -+* This routine enable the Ethernet port and Rx and Tx activity: -+* -+* Note: Each Rx and Tx queue descriptor's list must be initialized prior -+* to calling this function (use etherInitTxDescRing for Tx queues and -+* etherInitRxDescRing for Rx queues). -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to enable the port after ifconfig up. -+*******************************************************************************/ -+MV_STATUS mvEthPortEnable(void* pEthPortHndl) -+{ -+ int ethPortNo; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port */ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); -+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ mvEthMibCountersClear(pEthPortHndl); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ /* If Link is UP, Start RX and TX traffic */ -+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) -+ return( mvEthPortUp(pEthPortHndl) ); -+ -+ return MV_NOT_READY; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to disable the port after ifconfig down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDisable(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int mvDelay; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ /* Stop RX and TX activities */ -+ mvEthPortDown(pEthPortHndl); -+ } -+ -+ /* Reset the Enable bit in the Serial Control Register */ -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_PORT_ENABLE_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+ -+ /* Wait about 2500 tclk cycles */ -+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); -+ for(mvDelay; mvDelay>0; mvDelay--); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Tx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of TX queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pPktInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ ETH_TX_DESC* pTxDesc; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || -+ (pQueueCtrl->resource == 0) ) -+ { -+ /* Free next descriptor */ -+ pQueueCtrl->resource++; -+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; -+ -+ /* pPktInfo is available only in descriptors which are last descriptors */ -+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; -+ if (pPktInfo) -+ pPktInfo->status = pTxDesc->cmdSts; -+ -+ pTxDesc->cmdSts = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ -+ if (pPktInfo) -+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) -+ return pPktInfo; -+ } -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ return NULL; -+} -+ -+ -+ -+/******************************************************************************* -+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pBufInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_RX_DESC* pRxDesc; -+ MV_PKT_INFO* pPktInfo; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if(pQueueCtrl->resource == 0) -+ { -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ -+ return NULL; -+ } -+ /* Free next descriptor */ -+ pQueueCtrl->resource--; -+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; -+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; -+ -+ pPktInfo->status = pRxDesc->cmdSts; -+ pRxDesc->cmdSts = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ return pPktInfo; -+} -+ -+ -+/******************************************************************************/ -+/* Port Configuration functions */ -+/******************************************************************************/ -+/******************************************************************************* -+* mvEthMruGet - Get MRU configuration for Max Rx packet size. -+* -+* INPUT: -+* MV_U32 maxRxPktSize - max packet size. -+* -+* RETURN: MV_U32 - MRU configuration. -+* -+*******************************************************************************/ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) -+{ -+ MV_U32 portSerialCtrlReg = 0; -+ -+ if(maxRxPktSize > 9192) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; -+ else if(maxRxPktSize > 9022) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; -+ else if(maxRxPktSize > 1552) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; -+ else if(maxRxPktSize > 1522) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; -+ else if(maxRxPktSize > 1518) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; -+ else -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; -+ -+ return portSerialCtrlReg; -+} -+ -+/******************************************************************************* -+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path -+* -+* DESCRIPTION: -+* This routine sets the RX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 portSdmaCfgReg; -+ -+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; -+ -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); -+ -+#if (MV_ETH_VERSION >= 2) -+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ -+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path -+* -+* DESCRIPTION: -+* This routine sets the TX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt -+* occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; -+ regVal |= ETH_TX_INTR_COAL_MASK(coal); -+ -+ /* Set TX Coalescing mechanism */ -+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds -+* -+* DESCRIPTION: -+* This routine gets the RX and TX coalescing interrupt values. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the returned numbers are in micro seconds. -+* -+* INPUTs: -+* void* pPortHndl - Ethernet Port handler. -+* -+* OUTPUTs: -+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts -+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts -+* -+* RETURN: -+* MV_STATUS MV_OK - success -+* Others - failure. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) -+{ -+ MV_U32 regVal, coal, usec; -+ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ /* get TX Coalescing */ -+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pTxCoal != NULL) -+ *pTxCoal = usec; -+ -+ /* Get RX Coalescing */ -+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); -+ -+#if (MV_ETH_VERSION >= 2) -+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) -+ { -+ /* Add MSB */ -+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); -+ } -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pRxCoal != NULL) -+ *pRxCoal = usec; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMaxRxSizeSet - -+* -+* DESCRIPTION: -+* Change maximum receive size of the port. This configuration will take place -+* after next call of ethPortSetDefaults() function. -+* -+* INPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) -+ return MV_BAD_PARAM; -+ -+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* MAC Filtering functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* MV_BOOL isPromisc - Promiscous mode -+* MV_TRUE - accept all Broadcast, Multicast -+* and Unicast packets -+* MV_FALSE - accept all Broadcast, -+* specially added Multicast and -+* single Unicast packets -+* -+* RETURN: MV_STATUS MV_OK - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int queue; -+ MV_U32 portCfgReg; -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ /* Set / Clear UPM bit in port configuration register */ -+ if(isPromisc) -+ { -+ /* Accept all multicast packets to RX default queue */ -+ queue = pPortCtrl->portConfig.rxDefQ; -+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); -+ } -+ else -+ { -+ /* Reject all Multicast addresses */ -+ queue = -1; -+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ /* Clear all mcastCount */ -+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); -+ } -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ /* Set Special Multicast and Other Multicast tables */ -+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); -+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); -+ ethSetUcastTable(pPortCtrl->portNo, queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrSet - This function Set the port Unicast address. -+* -+* DESCRIPTION: -+* This function Set the port Ethernet MAC address. This address -+* will be used to send Pause frames if enabled. Packets with this -+* address will be accepted and dispatched to default RX queue -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* char* pAddr - Address to be set -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if(queue != -1) -+ { -+ macL = (pAddr[4] << 8) | (pAddr[5]); -+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | -+ (pAddr[2] << 8) | (pAddr[3] << 0); -+ -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); -+ } -+ -+ /* Accept frames of this address */ -+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrGet - This function returns the port Unicast address. -+* -+* DESCRIPTION: -+* This function returns the port Ethernet MAC address. -+* -+* INPUT: -+* int portNo - Ethernet port number. -+* char* pAddr - Pointer where address will be written to -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(pAddr == NULL) -+ { -+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); -+ return MV_BAD_PARAM; -+ } -+ -+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); -+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); -+ pAddr[0] = (macH >> 24) & 0xff; -+ pAddr[1] = (macH >> 16) & 0xff; -+ pAddr[2] = (macH >> 8) & 0xff; -+ pAddr[3] = macH & 0xff; -+ pAddr[4] = (macL >> 8) & 0xff; -+ pAddr[5] = macL & 0xff; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* MV_U8* pAddr - Address to calculate CRC-8 -+* -+* RETURN: MV_U8 - CRC-8 of this MAC address -+* -+*******************************************************************************/ -+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ int macArray[48]; -+ int crc[8]; -+ int i; -+ unsigned char crcResult = 0; -+ -+ /* Calculate CRC-8 out of the given address */ -+ macH = (pAddr[0] << 8) | (pAddr[1]); -+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | -+ (pAddr[4] << 8) | (pAddr[5] << 0); -+ -+ for(i=0; i<32; i++) -+ macArray[i] = (macL >> i) & 0x1; -+ -+ for(i=32; i<48; i++) -+ macArray[i] = (macH >> (i - 32)) & 0x1; -+ -+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ -+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ -+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ -+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ -+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; -+ -+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ -+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ -+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ -+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ -+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ -+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; -+ -+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ -+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ -+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ -+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ -+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ -+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; -+ -+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ -+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ -+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ -+ macArray[3] ^ macArray[2] ^ macArray[1]; -+ -+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ -+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ -+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ -+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ -+ macArray[3] ^ macArray[2]; -+ -+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ -+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ -+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ -+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ -+ macArray[4] ^ macArray[3]; -+ -+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ -+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ -+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ -+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ -+ macArray[4]; -+ -+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ -+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ -+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ -+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ -+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; -+ -+ for(i=0; i<8; i++) -+ crcResult = crcResult | (crc[i] << i); -+ -+ return crcResult; -+} -+/******************************************************************************* -+* mvEthMcastAddrSet - Multicast address settings. -+* -+* DESCRIPTION: -+* This API controls the MV device MAC multicast support. -+* The MV device supports multicast using two tables: -+* 1) Special Multicast Table for MAC addresses of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* In this case, the function calls ethPortSmcAddr() routine to set the -+* Special Multicast Table. -+* 2) Other Multicast Table for multicast of another type. A CRC-8bit -+* is used as an index to the Other Multicast Table entries in the -+* DA-Filter table. -+* In this case, the function calculates the CRC-8bit value and calls -+* ethPortOmcAddr() routine to set the Other Multicast Table. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* MV_U8* pAddr - Address to be set -+* int queue - RX queue to capture all packets with this -+* Multicast MAC address. -+* -1 means delete this Multicast address. -+* -+* RETURN: MV_STATUS -+* MV_TRUE - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned char crcResult = 0; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", -+ pPortCtrl->portNo, queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if((pAddr[0] == 0x01) && -+ (pAddr[1] == 0x00) && -+ (pAddr[2] == 0x5E) && -+ (pAddr[3] == 0x00) && -+ (pAddr[4] == 0x00)) -+ { -+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ } -+ else -+ { -+ crcResult = mvEthMcastCrc8Get(pAddr); -+ -+ /* Check Add counter for this CRC value */ -+ if(queue == -1) -+ { -+ if(pPortCtrl->mcastCount[crcResult] == 0) -+ { -+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_SUCH; -+ } -+ -+ pPortCtrl->mcastCount[crcResult]--; -+ if(pPortCtrl->mcastCount[crcResult] != 0) -+ { -+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], -+ (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ else -+ { -+ pPortCtrl->mcastCount[crcResult]++; -+ if(pPortCtrl->mcastCount[crcResult] > 1) -+ { -+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethSetUcastTable - Unicast address settings. -+* -+* DESCRIPTION: -+* Set all entries in the Unicast MAC Table queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+static void ethSetUcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xC; offset+=4) -+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); -+} -+ -+/******************************************************************************* -+* mvEthSetSpecialMcastTable - Special Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* mvEthSetOtherMcastTable - Other Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* ethSetUcastAddr - This function Set the port unicast address table -+* -+* DESCRIPTION: -+* This function locates the proper entry in the Unicast table for the -+* specified MAC nibble and sets its properties according to function -+* parameters. -+* -+* INPUT: -+* int ethPortNum - Port number. -+* MV_U8 lastNibble - Unicast MAC Address last nibble. -+* int queue - Rx queue number for this MAC address. -+* value "-1" means remove address -+* -+* OUTPUT: -+* This function add/removes MAC addresses from the port unicast address -+* table. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) -+{ -+ unsigned int unicastReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the Unicast table entry */ -+ lastNibble = (0xf & lastNibble); -+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ -+ regOffset = lastNibble % 4; /* Entry offset within the above register */ -+ -+ -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + -+ tblOffset)); -+ -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified unicast DA table entry */ -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ } -+ else -+ { -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); -+ } -+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), -+ unicastReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetSpecialMcastAddr - Special Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device special MAC multicast support. -+* The Special Multicast Table for MAC addresses supports MAC of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* This function set the Special Multicast Table appropriate entry -+* according to the argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). -+* int queue Rx queue number for this MAC address. -+* int option 0 = Add, 1 = remove address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) -+{ -+ unsigned int smcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the SMC table entry */ -+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ -+ regOffset = lastByte % 4; /* Entry offset within the above register */ -+ -+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Special DA table entry */ -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + -+ tblOffset*4), smcTableReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetOtherMcastAddr - Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device Other MAC multicast support. -+* The Other Multicast Table is used for multicast of another type. -+* A CRC-8bit is used as an index to the Other Multicast Table entries -+* in the DA-Filter table. -+* The function gets the CRC-8bit value from the calling routine and -+* set the Other Multicast Table appropriate entry according to the -+* CRC-8 argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -+* int queue Rx queue number for this MAC address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) -+{ -+ unsigned int omcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the OMC table entry */ -+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ -+ regOffset = crc8 % 4; /* Entry offset within the above register */ -+ -+ omcTableReg = MV_REG_READ( -+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Other DA table entry */ -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), -+ omcTableReg); -+ -+ return MV_TRUE; -+} -+ -+ -+/******************************************************************************/ -+/* MIB Counters functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthMibCounterRead - Read a MIB counter -+* -+* DESCRIPTION: -+* This function reads a MIB counter of a specific ethernet port. -+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or -+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, -+* so pHigh32 pointer should not be NULL in this case. -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* unsigned int mibOffset - MIB counter offset. -+* -+* OUTPUT: -+* MV_U32* pHigh32 - pointer to place where 32 most significant bits -+* of the counter will be stored. -+* -+* RETURN: -+* 32 low sgnificant bits of MIB counter value. -+* -+*******************************************************************************/ -+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, -+ MV_U32* pHigh32) -+{ -+ int portNo; -+ MV_U32 valLow32, valHigh32; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); -+ -+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ -+ /* of a 64-bit MIB Counter. */ -+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || -+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) -+ { -+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); -+ if(pHigh32 != NULL) -+ *pHigh32 = valHigh32; -+ } -+ return valLow32; -+} -+ -+/******************************************************************************* -+* mvEthMibCountersClear - Clear all MIB counters -+* -+* DESCRIPTION: -+* This function clears all MIB counters -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* -+* -+* RETURN: void -+* -+*******************************************************************************/ -+void mvEthMibCountersClear(void* pPortHandle) -+{ -+ int i, portNo; -+ unsigned int dummy; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ /* Perform dummy reads from MIB counters */ -+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return -1; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ rxq = (regValue >> (regOffs*3)); -+ rxq &= 0x7; -+ -+ return rxq; -+} -+ -+/******************************************************************************* -+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tos - TOS value in the IP header of the packet -+* int rxq - RX Queue for packets with the configured TOS value -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+*******************************************************************************/ -+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) -+{ -+ MV_U32 regValue; -+ int regIdx, regOffs; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) -+ { -+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); -+ return MV_BAD_PARAM; -+ } -+ if(tos > 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return MV_BAD_PARAM; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ regValue &= ~(0x7 << (regOffs*3)); -+ regValue |= (rxq << (regOffs*3)); -+ -+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with -+* special priority bits [0-2] -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture VLAN tagged packets with special -+* priority. -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 vlanPrioReg; -+ -+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); -+ return MV_BAD_PARAM; -+ } -+ if(vlanPrio >= 8) -+ { -+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); -+ return MV_BAD_PARAM; -+ } -+ -+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); -+ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); -+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); -+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. -+* -+* DESCRIPTION: -+* This function defines processing of BPDU packets. -+* BPDU packets can be accepted and captured to one of RX queues -+* or can be processing as regular Multicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to -+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, -+* except for the Flow-Control Pause packets). -+* Negative value (-1) means no special processing for BPDU, -+* packets so they will be processed as regular Multicast packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ MV_U32 portCfgExtReg; -+ -+ if(bpduQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ if(bpduQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxBpduQ = bpduQueue; -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxBpduQ = -1; -+ /* no special processing for BPDU packets */ -+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthArpRxQueue - Configure RX queue to capture ARP packets. -+* -+* DESCRIPTION: -+* This function defines processing of ARP (type=0x0806) packets. -+* ARP packets can be accepted and captured to one of RX queues -+* or can be processed as other Broadcast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int arpQueue - Special queue to capture ARP packets (type=0x806). -+* Negative value (-1) means discard ARP packets -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(arpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(arpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxArpQ = arpQueue; -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxArpQ = -1; -+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. -+* -+* DESCRIPTION: -+* This function defines processing of TCP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tcpQueue - Special queue to capture TCP packets. Value "-1" -+* means no special processing for TCP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(tcpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); -+ return MV_BAD_PARAM; -+ } -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(tcpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxTcpQ = tcpQueue; -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxTcpQ = -1; -+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. -+* -+* DESCRIPTION: -+* This function defines processing of UDP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int udpQueue - Special queue to capture UDP packets. Value "-1" -+* means no special processing for UDP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(udpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(udpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxUdpQ = udpQueue; -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxUdpQ = -1; -+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* Speed, Duplex, FlowControl routines */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and Speed. -+* Changing of these parameters are allowed only when port is disabled. -+* This function disable the port if was enabled, change duplex and speed -+* and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* ETH_PORT_SPEED speed - Speed of the port. -+* ETH_PORT_SPEED duplex - Duplex of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. -+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) -+* is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, -+ MV_ETH_PORT_DUPLEX duplex) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ /* Check validity */ -+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) -+ return MV_BAD_PARAM; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ /* Set Speed */ -+ switch(speed) -+ { -+ case MV_ETH_SPEED_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_SPEED_10: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_100: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_1000: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); -+ return MV_BAD_VALUE; -+ } -+ /* Set duplex */ -+ switch(duplex) -+ { -+ case MV_ETH_DUPLEX_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_HALF: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_FULL: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthFlowCtrlSet - Set Flow Control of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and -+* Speed. Changing of these parameters are allowed only when port is -+* disabled. This function disable the port if was enabled, change -+* duplex and speed and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_PORT_FC flowControl - Flow control of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value flowControl parameters is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ switch(flowControl) -+ { -+ case MV_ETH_FC_AN_ADV_DIS: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_AN_ADV_SYM: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_DISABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ case MV_ETH_FC_ENABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthHeaderModeSet - Set port header mode. -+* -+* DESCRIPTION: -+* This function configures the port to work in Marvell-Header mode. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_NOT_SUPPORTED- Feature not supported. -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 mvHeaderReg; -+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); -+ /* Disable header mode. */ -+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; -+ -+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) -+ { -+ /* Enable Header mode. */ -+ mvHeaderReg |= ETH_MVHDR_EN_MASK; -+ -+ /* Clear DA-Prefix & MHMask fields.*/ -+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); -+ -+ if(numRxQ > 1) -+ { -+ switch (headerMode) -+ { -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; -+ break; -+ default: -+ break; -+ } -+ -+ switch (numRxQ) -+ { -+ case (4): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; -+ break; -+ case (8): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); -+ -+ return MV_OK; -+} -+ -+#if (MV_ETH_VERSION >= 4) -+/******************************************************************************* -+* mvEthEjpModeSet - Enable / Disable EJP policy for TX. -+* -+* DESCRIPTION: -+* This function -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_BOOL TRUE - enable EJP mode -+* FALSE - disable EJP mode -+* -+* OUTPUT: MV_STATUS -+* MV_OK - Success -+* Other - Failure -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ pPortCtrl->portConfig.ejpMode = mode; -+ if(mode) -+ { -+ /* EJP enabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ /* EJP disabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); -+ } -+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", -+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), -+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); -+ -+ return MV_OK; -+} -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+/******************************************************************************* -+* mvEthStatusGet - Get major properties of the port . -+* -+* DESCRIPTION: -+* This function get major properties of the port (link, speed, duplex, -+* flowControl, etc) and return them using the single structure. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* OUTPUT: -+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status -+* will be placed. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ MV_U32 regValue; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ pStatus->speed = MV_ETH_SPEED_1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ pStatus->speed = MV_ETH_SPEED_100; -+ else -+ pStatus->speed = MV_ETH_SPEED_10; -+ -+ if(regValue & ETH_LINK_UP_MASK) -+ pStatus->isLinkUp = MV_TRUE; -+ else -+ pStatus->isLinkUp = MV_FALSE; -+ -+ if(regValue & ETH_FULL_DUPLEX_MASK) -+ pStatus->duplex = MV_ETH_DUPLEX_FULL; -+ else -+ pStatus->duplex = MV_ETH_DUPLEX_HALF; -+ -+ -+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) -+ pStatus->flowControl = MV_ETH_FC_ENABLE; -+ else -+ pStatus->flowControl = MV_ETH_FC_DISABLE; -+} -+ -+ -+/******************************************************************************/ -+/* PHY Control Functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthPhyAddrSet - Set the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine set the ethernet port PHY address according to given -+* parameter. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int phyAddr - PHY address -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ regData &= ~ETH_PHY_ADDR_MASK; -+ regData |= phyAddr; -+ -+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); -+ -+ return; -+} -+ -+/******************************************************************************* -+* mvEthPhyAddrGet - Get the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine returns the given ethernet port PHY address. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* -+* RETURN: int - PHY address. -+* -+*******************************************************************************/ -+int mvEthPhyAddrGet(void* pPortHandle) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ return ((regData >> (5 * port)) & 0x1f); -+} -+ -+/******************************************************************************/ -+/* Descriptor handling Functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Rx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int rxQueue Number of Rx queue. -+* int rxDescNum Number of Rx descriptors -+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Rx descriptors and buffers. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; -+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pRxDesc = (ETH_RX_DESC*)pRxDescBase; -+ pRxPrevDesc = pRxDesc; -+ -+ /* initialize the Rx descriptors ring */ -+ for (ix=0; ixbufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ pRxPrevDesc = pRxDesc; -+ if(ix == (rxDescNum-1)) -+ { -+ /* Closing Rx descriptors ring */ -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); -+ } -+ else -+ { -+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pRxDescBase; -+ pQueueCtrl->pUsedDescr = pRxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pRxDescBase; -+ pQueueCtrl->pLastDescr = pRxDesc; -+ pQueueCtrl->resource = 0; -+} -+ -+void ethResetRxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pRxDesc->bufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ } -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg |= (1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); -+ } -+} -+ -+/******************************************************************************* -+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Tx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int txQueue Number of Tx queue. -+* int txDescNum Number of Tx descriptors -+* int txBuffSize Size of Tx buffer -+* MV_U8* pTxDescBase Tx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Tx descriptors and buffers. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; -+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pTxDesc = (ETH_TX_DESC*)pTxDescBase; -+ pTxPrevDesc = pTxDesc; -+ -+ /* initialize the Tx descriptors ring */ -+ for (ix=0; ixbyteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ -+ pTxPrevDesc = pTxDesc; -+ -+ if(ix == (txDescNum-1)) -+ { -+ /* Closing Tx descriptors ring */ -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); -+ } -+ else -+ { -+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pTxDescBase; -+ pQueueCtrl->pUsedDescr = pTxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pTxDescBase; -+ pQueueCtrl->pLastDescr = pTxDesc; -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource = txDescNum - 1; -+} -+ -+void ethResetTxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pTxDesc->byteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ pQueueCtrl->resource++; -+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ } -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); -+ } -+} -+ -+/******************************************************************************* -+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function allocates memory for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. -+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. -+* -+* INPUT: -+* int size - size of memory should be allocated. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle) -+{ -+ MV_U8* pVirt; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if(ethDescInSram == MV_TRUE) -+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ { -+#ifdef ETH_DESCR_UNCACHED -+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr,memHandle); -+#else -+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr, memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+ } -+ memset(pVirt, 0, descSize); -+ -+ return pVirt; -+} -+ -+/******************************************************************************* -+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function frees memory allocated for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. -+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. -+* -+* INPUT: -+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX -+* desriptors. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) -+{ -+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) -+ return; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ { -+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); -+ return; -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#else -+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+} -+ -+/******************************************************************************/ -+/* Other Functions */ -+/******************************************************************************/ -+ -+void mvEthPortPowerUp(int port) -+{ -+ MV_U32 regVal; -+ -+ /* MAC Cause register should be cleared */ -+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); -+ -+ if (mvBoardIsPortInSgmii(port)) -+ mvEthPortSgmiiConfig(port); -+ -+ /* Cancel Port Reset */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ regVal &= (~ETH_PORT_RESET_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); -+} -+ -+void mvEthPortPowerDown(int port) -+{ -+ MV_U32 regVal; -+ -+ /* Port must be DISABLED */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) -+ { -+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", -+ port, regVal); -+ return; -+ } -+ -+ /* Port Reset (Read after write the register as a precaution) */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); -+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); -+} -+ -+static void mvEthPortSgmiiConfig(int port) -+{ -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ -+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); -+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+} -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c -new file mode 100644 -index 0000000..62edcb5 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c -@@ -0,0 +1,748 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthDebug.c - Source file for user friendly debug functions -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthDebug.h" -+ -+/* #define mvOsPrintf printf */ -+ -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+/******************************************************************************/ -+/* Debug functions */ -+/******************************************************************************/ -+void ethRxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthRxCoalSet(pHndl, usec); -+ } -+} -+ -+void ethTxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTxCoalSet(pHndl, usec); -+ } -+} -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthEjpModeSet(pHndl, mode); -+ } -+} -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthBpduRxQueue(pHndl, bpduQueue); -+ } -+} -+ -+void ethArpRxQ(int port, int arpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthArpRxQueue(pHndl, arpQueue); -+ } -+} -+ -+void ethTcpRxQ(int port, int tcpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTcpRxQueue(pHndl, tcpQueue); -+ } -+} -+ -+void ethUdpRxQ(int port, int udpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthUdpRxQueue(pHndl, udpQueue); -+ } -+} -+ -+void ethTxPolicyRegs(int port) -+{ -+ int queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); -+ -+ if(pPortCtrl == NULL) -+ { -+ return; -+ } -+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", -+ port, pPortCtrl->portConfig.ejpMode); -+ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) -+ mvOsPrintf("%d, ", queue); -+ } -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); -+ -+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", -+ ETH_TX_QUEUE_COMMAND_REG(port), -+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_FIXED_PRIO_CFG_REG(port), -+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_RATE_CFG_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", -+ ETH_MAX_TRANSMIT_UNIT_REG(port), -+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); -+ -+ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), -+ ((macH >> 8) & 0xff), (macH & 0xff), -+ ((macL >> 8) & 0xff), (macL & 0xff) ); -+ -+ for (i=0; i<4; i++) -+ { -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); -+ for(j=0; j<4; j++) -+ { -+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; -+ -+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, -+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); -+ } -+ } -+} -+ -+void ethMcastAdd(int port, char* macStr, int queue) -+{ -+ void* pHndl; -+ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvMacStrToHex(macStr, macAddr); -+ mvEthMcastAddrSet(pHndl, macAddr, queue); -+ } -+} -+ -+void ethPortMcast(int port) -+{ -+ int tblIdx, regIdx; -+ MV_U32 regVal; -+ -+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", -+ port); -+ -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+} -+ -+ -+/* Print status of Ethernet port */ -+void mvEthPortShow(void* pHndl) -+{ -+ MV_U32 regValue, rxCoal, txCoal; -+ int speed, queue, port; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ -+ port = pPortCtrl->portNo; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", -+ port, ETH_PORT_STATUS_REG(port), regValue); -+ -+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", -+ ethDescInSram, ethDescSwCoher); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ speed = 1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ speed = 100; -+ else -+ speed = 10; -+ -+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); -+ -+ /* Link, Speed, Duplex, FlowControl */ -+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", -+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", -+ speed, -+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", -+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); -+ -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", -+ rxCoal, txCoal); -+ -+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", -+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, -+ pPortCtrl->portConfig.rxBpduQ, -+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Print all RX and TX queues */ -+ for(queue=0; queuerxQueue[queue].pFirstDescr, -+ mvEthRxResourceGet(pPortCtrl, queue) ); -+ } -+ mvOsPrintf("\n"); -+ for(queue=0; queuetxQueue[queue].pFirstDescr, -+ mvEthTxResourceGet(pPortCtrl, queue) ); -+ } -+} -+ -+/* Print RX and TX queue of the Ethernet port */ -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) -+{ -+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ ETH_QUEUE_CTRL *pQueueCtrl; -+ MV_U32 regValue; -+ ETH_RX_DESC *pRxDescr; -+ ETH_TX_DESC *pTxDescr; -+ int i, port = pPortCtrl->portNo; -+ -+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); -+ -+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); -+ -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), -+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, -+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, -+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); -+ -+ ETH_DESCR_INV(pPortCtrl, pRxDescr); -+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); -+ i++; -+ } while (pRxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); -+ } -+ -+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); -+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); -+ -+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); -+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, -+ (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), -+ pTxDescr->cmdSts, pTxDescr->byteCnt, -+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, -+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); -+ -+ ETH_DESCR_INV(pPortCtrl, pTxDescr); -+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); -+ i++; -+ } while (pTxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); -+ } -+} -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h -new file mode 100644 -index 0000000..b772a74 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h -@@ -0,0 +1,146 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __MV_ETH_DEBUG_H__ -+#define __MV_ETH_DEBUG_H__ -+ -+#if 0 -+/* -+ ** Externs -+ */ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int bpduQueue); -+void ethTcpRxQ(int port, int bpduQueue); -+void ethUdpRxQ(int port, int bpduQueue); -+void ethMcastAdd(int port, char* macStr, int queue); -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolicy( int port); -+void ethTxPolicy( int port); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int rxQueue, int rxQuota); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+void print_egiga_stat(void *sc, unsigned int port); -+void ethPortStatus (int port); -+void ethPortQueues( int port, int rxQueue, int txQueue, int mode); -+void ethPortMcast(int port); -+void ethPortRegs(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+ -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+ -+#ifdef CONFIG_MV_ETH_HEADER -+void run_com_header(const char *buffer); -+#endif -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int queue, int quota); -+void ethRxPolicy(int port); -+void ethTxPolDef(int port, int txQ, char* headerHexStr); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethTxPolicy(int port); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+#endif -+#endif /* 0 */ -+ -+ -+ -+ -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int arpQueue); -+void ethTcpRxQ(int port, int tcpQueue); -+void ethUdpRxQ(int port, int udpQueue); -+void ethTxPolicyRegs(int port); -+void ethPortRegs(int port); -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethPortStatus(int port); -+void ethPortQueues(int port, int rxQueue, int txQueue, int mode); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+void ethMcastAdd(int port, char* macStr, int queue); -+void ethPortMcast(int port); -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+#endif -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h -new file mode 100644 -index 0000000..83ad6ad ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration specific to -+* the Marvell Gigabit Ethernet Controller. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __mvEthGbe_h__ -+#define __mvEthGbe_h__ -+ -+extern MV_BOOL ethDescInSram; -+extern MV_BOOL ethDescSwCoher; -+extern ETH_PORT_CTRL* ethPortCtrl[]; -+ -+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) -+{ -+#if defined (ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ return mvSramVirtToPhy(pDesc); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); -+} -+/* Return port handler */ -+#define mvEthPortHndlGet(port) ethPortCtrl[port] -+ -+/* Used as WA for HW/SW race on TX */ -+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) -+{ -+ int deep = 0; -+ MV_U32 txCurrReg, txEnReg; -+ ETH_TX_DESC* pTxLastDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) -+ { -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return 0; -+ } -+ -+ pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ pTxLastDesc = pQueueCtrl->pCurrentDescr; -+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ /* All descriptors are processed, no chance for race */ -+ return 0; -+ } -+ -+ /* Check distance betwee HW and SW location: */ -+ /* If distance between HW and SW pointers is less than max_deep descriptors */ -+ /* Race condition is possible, so wait end of TX and restart TXQ */ -+ while(deep < max_deep) -+ { -+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ int count = 0; -+ -+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) -+ { -+ count++; -+ if(count > 10000) -+ { -+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", -+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); -+ break; -+ } -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ } -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return count; -+ } -+ deep++; -+ } -+ /* Distance between HW and SW pointers is more than max_deep descriptors, */ -+ /* So NO race condition - do nothing */ -+ return -1; -+} -+ -+ -+/* defines */ -+#define ETH_CSUM_MIN_BYTE_COUNT 72 -+ -+/* Tailgate and Kirwood have only 2K TX FIFO */ -+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) -+#define ETH_CSUM_MAX_BYTE_COUNT 1600 -+#else -+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 -+#endif /* MV_ETH_VERSION */ -+ -+#define ETH_MV_HEADER_SIZE 2 -+#define ETH_MV_TX_EN -+ -+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -+#define MIN_TX_BUFF_LOAD 8 -+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) -+ -+/* Default port configuration value */ -+#define PORT_CONFIG_VALUE \ -+ ETH_DEF_RX_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ -+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR -+ -+/* Default port extend configuration value */ -+#define PORT_CONFIG_EXTEND_VALUE 0 -+ -+#define PORT_SERIAL_CONTROL_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE | \ -+ ETH_SET_FULL_DUPLEX_MASK -+ -+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_MII_SPEED_100_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+ -+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_GMII_SPEED_1000_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_IN_BAND_AN_EN_MASK | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+/* Function headers: */ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+/* Interrupt Coalesting functions */ -+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); -+ -+/******************************************************************************/ -+/* Data Flow functions */ -+/******************************************************************************/ -+static INLINE void mvEthPortTxRestart(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+} -+ -+/* Get number of Free resources in specific TX queue */ -+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->txQueue[txQueue].resource); -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->rxQueue[rxQueue].resource); -+} -+ -+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->txQueue[txQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->rxQueue[rxQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvEthPortTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pPktInfo parameter. -+* Single buffer only. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource == 0) -+ return MV_NO_RESOURCE; -+ -+ pTxCurrDesc->byteCnt = pBufInfo->dataSize; -+ -+ /* Flash Buffer */ -+ if(pPktInfo->pktSize != 0) -+ { -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#endif -+ pPktInfo->pktSize = 0; -+ } -+ else -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortSgTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pBufInfo parameter. It -+* supports transmitting of a packet spaned over multiple buffers. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxFirstDesc; -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo, bufCount; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ MV_U8* pTxBuf; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource < pPktInfo->numFrags) -+ return MV_NO_RESOURCE; -+ -+ /* Remember first desc */ -+ pTxFirstDesc = pTxCurrDesc; -+ -+ bufCount = 0; -+ while(MV_TRUE) -+ { -+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) -+ { -+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ -+ /* to 64-bit boundary. Two options here: */ -+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ -+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ -+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ -+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; -+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); -+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); -+ } -+ else -+ { -+ /* Flash Buffer */ -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#endif -+ } -+ -+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; -+ bufCount++; -+ -+ if(bufCount >= pPktInfo->numFrags) -+ break; -+ -+ if(bufCount > 1) -+ { -+ /* There is middle buffer of the packet Not First and Not Last */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ /* Go to next descriptor and next buffer */ -+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ } -+ /* Set last desc with DMA ownership and interrupt enable. */ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ if(bufCount == 1) -+ { -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ else -+ { -+ /* Last but not First */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ /* Update First when more than one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxFirstDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_FIRST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); -+ } -+ /* Update txQueue state */ -+ pQueueCtrl->resource -= bufCount; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortTxDone - Free all used Tx descriptors and mBlks. -+* -+* DESCRIPTION: -+* This routine returns the transmitted packet information to the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. -+* MV_EMPTY - No transmitted packets to return. TX Queue is empty. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - There is transmitted packet in the queue, -+* 'pPktInfo' filled with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_TX_DESC* pTxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_PKT_INFO* pPktInfo; -+ MV_U32 commandStatus; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ while(MV_TRUE) -+ { -+ /* No more used descriptors */ -+ commandStatus = pTxUsedDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); -+ return NULL; -+ } -+ if( (pTxUsedDesc == pTxCurrDesc) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return NULL; -+ } -+ pQueueCtrl->resource++; -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); -+ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) -+ { -+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; -+ pPktInfo->status = commandStatus; -+ return pPktInfo; -+ } -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRx - Get new received packets from Rx queue. -+* -+* DESCRIPTION: -+* This routine returns the received data to the caller. There is no -+* data copying during routine operation. All information is returned -+* using pointer to packet information struct passed from the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_NO_RESOURCE - No free resources in RX queue. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - New packet received and 'pBufInfo' structure filled -+* with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_RX_DESC *pRxCurrDesc; -+ MV_U32 commandStatus; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ -+ /* Check resources */ -+ if(pQueueCtrl->resource == 0) -+ { -+ mvOsPrintf("ethPortRx: no more resources\n"); -+ return NULL; -+ } -+ while(MV_TRUE) -+ { -+ /* Get the Rx Desc ring 'curr and 'used' indexes */ -+ pRxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ commandStatus = pRxCurrDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ /* Nothing to receive... */ -+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); -+ return NULL; -+ } -+ -+ /* Valid RX only if FIRST and LAST bits are set */ -+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == -+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) -+ { -+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; -+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; -+ pPktInfo->status = commandStatus; -+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; -+ -+ pQueueCtrl->resource--; -+ /* Update 'curr' in data structure */ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ -+#ifdef INCLUDE_SYNC_BARR -+ mvCpuIfSyncBarr(DRAM_TARGET); -+#endif -+ return pPktInfo; -+ } -+ else -+ { -+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+#ifdef ETH_DEBUG -+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " -+ "status=0x%08x, byteCnt=%d, pData=0x%x\n", -+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); -+#endif /* ETH_DEBUG */ -+ -+ /* move buffer from pCurrentDescr position to pUsedDescr position */ -+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; -+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; -+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. -+* -+* DESCRIPTION: -+* This routine returns a Rx buffer back to the Rx ring. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_ERROR - Unexpected Fatal error. -+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be -+* returned to this queue. -+* MV_FULL - Buffer returned successfully and RX queue became full. -+* More buffers should not be returned at the time. -+* MV_OK - Buffer returned successfully and there are more free -+* places in the queue. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) -+{ -+ ETH_RX_DESC* pRxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ /* Get 'used' Rx descriptor */ -+ pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+ /* Check that ring is not FULL */ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", -+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, -+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; -+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; -+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Invalidate data buffer accordingly with pktSize */ -+ if(pPktInfo->pktSize != 0) -+ { -+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); -+ pPktInfo->pktSize = 0; -+ } -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ pQueueCtrl->resource++; -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ -+ /* If ring became Full return MV_FULL */ -+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) -+ return MV_FULL; -+ -+ return MV_OK; -+} -+ -+ -+#endif /* __mvEthGbe_h__ */ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h -new file mode 100644 -index 0000000..0f57ee7 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h -@@ -0,0 +1,700 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvEthRegsh -+#define __INCmvEthRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/****************************************/ -+/* Ethernet Unit Registers */ -+/****************************************/ -+#define ETH_REG_BASE MV_ETH_REG_BASE -+ -+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) -+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) -+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) -+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) -+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) -+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) -+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) -+ -+ -+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) -+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) -+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) -+ -+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) -+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) -+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) -+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) -+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) -+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) -+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) -+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) -+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) -+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) -+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) -+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) -+ -+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) -+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) -+ -+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) -+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) -+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) -+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) -+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) -+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) -+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) -+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) -+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) -+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) -+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) -+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) -+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) -+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) -+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) -+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) -+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) -+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) -+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) -+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) -+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) -+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) -+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) -+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) -+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) -+ -+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) -+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) -+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) -+ -+#if (MV_ETH_VERSION >= 4) -+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) -+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) -+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) -+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) -+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) -+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) -+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) -+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) -+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) -+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) -+ -+/* Phy address register definitions */ -+#define ETH_PHY_ADDR_OFFS 0 -+#define ETH_PHY_ADDR_MASK (0x1f <= 4) -+#define ETH_TX_EJP_RESET_BIT 0 -+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) -+ -+#define ETH_TX_EJP_ENABLE_BIT 2 -+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) -+ -+#define ETH_TX_LEGACY_WRR_BIT 3 -+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+/***** BITs of Ethernet Port Status reg (PSR) *****/ -+#define ETH_LINK_UP_BIT 1 -+#define ETH_LINK_UP_MASK (1<= 4) -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); -+ -+/* Marvell Header control */ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+ -+/* PHY routines */ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); -+int mvEthPhyAddrGet(void* pPortHandle); -+ -+/* Power management routines */ -+void mvEthPortPowerDown(int port); -+void mvEthPortPowerUp(int port); -+ -+/******************** ETH PRIVATE ************************/ -+ -+/*#define UNCACHED_TX_BUFFERS*/ -+/*#define UNCACHED_RX_BUFFERS*/ -+ -+ -+/* Port attributes */ -+/* Size of a Tx/Rx descriptor used in chain list data structure */ -+#define ETH_RX_DESC_ALIGNED_SIZE 32 -+#define ETH_TX_DESC_ALIGNED_SIZE 32 -+ -+#define TX_DISABLE_TIMEOUT_MSEC 1000 -+#define RX_DISABLE_TIMEOUT_MSEC 1000 -+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 -+#define PORT_DISABLE_WAIT_TCLOCKS 5000 -+ -+/* Macros that save access to desc in order to find next desc pointer */ -+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) -+ -+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) -+ -+ -+/* Queue specific information */ -+typedef struct -+{ -+ void* pFirstDescr; -+ void* pLastDescr; -+ void* pCurrentDescr; -+ void* pUsedDescr; -+ int resource; -+ MV_BUF_INFO descBuf; -+} ETH_QUEUE_CTRL; -+ -+ -+/* Ethernet port specific infomation */ -+typedef struct _ethPortCtrl -+{ -+ int portNo; -+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ -+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ -+ -+ MV_ETH_PORT_CFG portConfig; -+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; -+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; -+ -+ /* Register images - For DP */ -+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ -+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ -+ -+ MV_STATE portState; -+ -+ MV_U8 mcastCount[256]; -+ MV_U32* hashPtr; -+ void *osHandle; -+} ETH_PORT_CTRL; -+ -+/************** MACROs ****************/ -+ -+/* MACROs to Flush / Invalidate TX / RX Buffers */ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsCacheClear(NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsIoVirtToPhy(NULL, (pAddr)); -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ -+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) -+#define ETH_DESCR_INV(pPortCtrl, pDescr) -+ -+#else -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#define ETH_DESCR_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#endif /* ETH_DESCR_UNCACHED */ -+ -+#include "eth/gbe/mvEthGbe.h" -+ -+#endif /* __mvEth_h__ */ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c b/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c -new file mode 100644 -index 0000000..d7a5132 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c -@@ -0,0 +1,362 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "gpp/mvGpp.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); -+ -+/******************************************************************************* -+* mvGppTypeSet - Enable a GPP (OUT) pin -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP type per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to input and GPP15 to output. -+* mvGppTypeSet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ mask &= 0x2; -+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); -+ } /*End of WA*/ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP blink per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to be static and GPP15 to be blinking. -+* mvGppBlinkEn(0, (GPP8 | GPP15), -+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP polarity per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to the actual pin value and GPP15 to be inverted. -+* mvGppPolaritySet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppPolarityGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP polatity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 regVal; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); -+ return MV_ERROR; -+ } -+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); -+ -+ return (regVal & mask); -+} -+ -+/******************************************************************************* -+* mvGppValueGet - Get a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function get GPP value. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppValueGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP activity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); -+ -+ gppData &= mask; -+ -+ return gppData; -+ -+} -+ -+/******************************************************************************* -+* mvGppValueSet - Set a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function set value for given GPP pin list. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ MV_U32 outEnable, tmp; -+ MV_U32 i; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* verify that the gpp pin is configured as output */ -+ /* Note that in the register out enabled -> bit = '0'. */ -+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); -+ outEnable &= 0xfffffffd; -+ outEnable |= (tmp & 0x2); -+ } /*End of WA*/ -+ -+ for (i = 0 ; i < 32 ;i++) -+ { -+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) -+ { -+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ -+ "value to GPP %d in input mode.\n", i); -+ return MV_ERROR; -+ } -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* gppRegSet - Set a specific GPP pin on a specific GPP register -+* -+* DESCRIPTION: -+* This function set a specific GPP pin on a specific GPP register -+* -+* INPUT: -+* regOffs - GPP Register offset -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(regOffs); -+ -+ gppData &= ~mask; -+ -+ gppData |= (value & mask); -+ -+ MV_REG_WRITE(regOffs, gppData); -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h b/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h -new file mode 100644 -index 0000000..801472d ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h -@@ -0,0 +1,118 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppH -+#define __INCmvGppH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "gpp/mvGppRegs.h" -+ -+/* These macros describes the GPP type. Each of the GPPs pins can */ -+/* be assigned to act as a general purpose input or output pin. */ -+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ -+#define MV_GPP_OUT 0 /* GPP output */ -+ -+ -+/* These macros describes the GPP Out Enable. */ -+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ -+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ -+ -+/* These macros describes the GPP Out Blinking. */ -+/* When set and the corresponding bit in GPIO Data Out Enable Control */ -+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ -+/* 2^24 TCLK clocks). */ -+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ -+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ -+ -+ -+/* These macros describes the GPP Polarity. */ -+/* When set to 1 GPIO Data In Register reflects the inverted value of the */ -+/* corresponding pin. */ -+ -+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ -+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ -+ -+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); -+ -+/* mvGppValueGet - Get a GPP Pin list value.*/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); -+ -+ -+/* mvGppValueSet - Set a GPP Pin list value. */ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+#endif /* #ifndef __INCmvGppH */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h -new file mode 100644 -index 0000000..14b199f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h -@@ -0,0 +1,116 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppRegsH -+#define __INCmvGppRegsH -+ -+#define MV_GPP0 BIT0 -+#define MV_GPP1 BIT1 -+#define MV_GPP2 BIT2 -+#define MV_GPP3 BIT3 -+#define MV_GPP4 BIT4 -+#define MV_GPP5 BIT5 -+#define MV_GPP6 BIT6 -+#define MV_GPP7 BIT7 -+#define MV_GPP8 BIT8 -+#define MV_GPP9 BIT9 -+#define MV_GPP10 BIT10 -+#define MV_GPP11 BIT11 -+#define MV_GPP12 BIT12 -+#define MV_GPP13 BIT13 -+#define MV_GPP14 BIT14 -+#define MV_GPP15 BIT15 -+#define MV_GPP16 BIT16 -+#define MV_GPP17 BIT17 -+#define MV_GPP18 BIT18 -+#define MV_GPP19 BIT19 -+#define MV_GPP20 BIT20 -+#define MV_GPP21 BIT21 -+#define MV_GPP22 BIT22 -+#define MV_GPP23 BIT23 -+#define MV_GPP24 BIT24 -+#define MV_GPP25 BIT25 -+#define MV_GPP26 BIT26 -+#define MV_GPP27 BIT27 -+#define MV_GPP28 BIT28 -+#define MV_GPP29 BIT29 -+#define MV_GPP30 BIT30 -+#define MV_GPP31 BIT31 -+ -+ -+/* registers offsets */ -+ -+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) -+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) -+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) -+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) -+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) -+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) -+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) -+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) -+ -+#define GPP_DATA_OUT_SET_REG 0x10120 -+#define GPP_DATA_OUT_CLEAR_REG 0x10124 -+ -+#endif /* #ifndef __INCmvGppRegsH */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c -new file mode 100644 -index 0000000..5ee430c ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c -@@ -0,0 +1,669 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPciIf.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+ -+#if defined(MV_INCLUDE_PCI) -+#include "ctrlEnv/sys/mvSysPci.h" -+#endif -+ -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvPciInit - Initialize PCI interfaces -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ -+ MV_PCI_MOD pciMod; -+ -+ if (PCI_IF_MODE_HOST == pciIfmode) -+ { -+ pciMod = MV_PCI_MOD_HOST; -+ } -+ else if (PCI_IF_MODE_DEVICE == pciIfmode) -+ { -+ pciMod = MV_PCI_MOD_DEVICE; -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Bus %d mode %d neither host nor device!\n", -+ __FUNCTION__, pciIf, pciIfmode); -+ return MV_FAIL; -+ } -+ -+ return mvPciInit(pciIf - MV_PCI_START_IF, pciMod); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ -+ MV_PEX_TYPE pexType; -+ -+ if (PCI_IF_MODE_HOST == pciIfmode) -+ { -+ pexType = MV_PEX_ROOT_COMPLEX; -+ } -+ else if (PCI_IF_MODE_DEVICE == pciIfmode) -+ { -+ pexType = MV_PEX_END_POINT; -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Bus %d type %d neither root complex nor" \ -+ " end point\n", __FUNCTION__, pciIf, pciIfmode); -+ return MV_FAIL; -+ } -+ return mvPexInit(pciIf - MV_PEX_START_IF, pexType); -+ -+ #else -+ return MV_OK; -+ #endif -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return MV_FAIL; -+ -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciConfigRead(pciIf - MV_PCI_START_IF, -+ bus, -+ dev, -+ func, -+ regOff); -+ #else -+ return 0xffffffff; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexConfigRead(pciIf - MV_PEX_START_IF, -+ bus, -+ dev, -+ func, -+ regOff); -+ #else -+ return 0xffffffff; -+ #endif -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0; -+ -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciConfigWrite(pciIf - MV_PCI_START_IF, -+ bus, -+ dev, -+ func, -+ regOff, -+ data); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexConfigWrite(pciIf - MV_PEX_START_IF, -+ bus, -+ dev, -+ func, -+ regOff, -+ data); -+ #else -+ return MV_OK; -+ #endif -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return MV_FAIL; -+ -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciMasterEnable(pciIf - MV_PCI_START_IF, -+ enable); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexMasterEnable(pciIf - MV_PEX_START_IF, -+ enable); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return MV_FAIL; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciSlaveEnable(pciIf - MV_PCI_START_IF,bus,dev, -+ enable); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexSlaveEnable(pciIf - MV_PEX_START_IF,bus,dev, -+ enable); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return MV_FAIL; -+ -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciLocalBusNumSet(pciIf - MV_PCI_START_IF, -+ busNum); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexLocalBusNumSet(pciIf - MV_PEX_START_IF, -+ busNum); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return MV_FAIL; -+ -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciLocalBusNumGet(pciIf - MV_PCI_START_IF); -+ #else -+ return 0xFFFFFFFF; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexLocalBusNumGet(pciIf - MV_PEX_START_IF); -+ #else -+ return 0xFFFFFFFF; -+ #endif -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n",__FUNCTION__, pciIf); -+ } -+ -+ return 0; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciLocalDevNumSet(pciIf - MV_PCI_START_IF, -+ devNum); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexLocalDevNumSet(pciIf - MV_PEX_START_IF, -+ devNum); -+ #else -+ return MV_OK; -+ #endif -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return MV_FAIL; -+ -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf) -+{ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PCI) -+ return mvPciLocalDevNumGet(pciIf - MV_PCI_START_IF); -+ #else -+ return 0xFFFFFFFF; -+ #endif -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ #if defined(MV_INCLUDE_PEX) -+ return mvPexLocalDevNumGet(pciIf - MV_PEX_START_IF); -+ #else -+ return 0xFFFFFFFF; -+ #endif -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf) -+{ -+ -+ if ((pciIf >= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) -+ { -+ return PCI_IF_TYPE_CONVEN_PCIX; -+ } -+ else if ((pciIf >= MV_PEX_START_IF) && -+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) -+ { -+ return PCI_IF_TYPE_PEX; -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ return (pciIf - MV_PCI_START_IF); -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ return (pciIf - MV_PEX_START_IF); -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h -new file mode 100644 -index 0000000..5f7caaa ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h -@@ -0,0 +1,134 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFH -+#define __INCPCIIFH -+ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIfRegs.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+#if defined(MV_INCLUDE_PCI) -+#include "pci/mvPci.h" -+#endif -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef enum _mvPCIIfType -+{ -+ PCI_IF_TYPE_CONVEN_PCIX, -+ PCI_IF_TYPE_PEX -+ -+}PCI_IF_TYPE; -+ -+typedef enum _mvPCIIfMode -+{ -+ PCI_IF_MODE_HOST, -+ PCI_IF_MODE_DEVICE -+}PCI_IF_MODE; -+ -+ -+/* Global Functions prototypes */ -+ -+/* mvPciIfInit - Initialize PCI interfaces*/ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); -+ -+/* mvPciIfConfigRead - Read from configuration space */ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciIfConfigWrite - Write to configuration space */ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, -+ MV_BOOL enable); -+ -+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); -+ -+/* mvPciIfTypeGet - Get PCI If type*/ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); -+ -+/* mvPciIfAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPciIfAddrDecShow(MV_VOID); -+ -+#endif /* #ifndef __INCPCIIFH */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h -new file mode 100644 -index 0000000..754e837 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFREGSH -+#define __INCPCIIFREGSH -+ -+ -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/***************************************/ -+/* PCI Configuration registers */ -+/***************************************/ -+ -+/*********************************************/ -+/* PCI Configuration, Function 0, Registers */ -+/*********************************************/ -+ -+ -+/* Standard registers */ -+#define PCI_DEVICE_AND_VENDOR_ID 0x000 -+#define PCI_STATUS_AND_COMMAND 0x004 -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PCI_CAPABILTY_LIST_POINTER 0x034 -+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -+ -+ -+/* PCI Device and Vendor ID Register (PDVIR) */ -+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) -+ -+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ -+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) -+ -+/* PCI Status and Command Register (PSCR) */ -+#define PSCR_IO_EN BIT0 /* IO Enable */ -+#define PSCR_MEM_EN BIT1 /* Memory Enable */ -+#define PSCR_MASTER_EN BIT2 /* Master Enable */ -+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ -+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ -+#define PSCR_VGA BIT5 /* VGA Palette Snoops */ -+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ -+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ -+#define PSCR_CAP_LIST BIT20 /* Capability List Support */ -+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ -+#define PSCR_UDF_EN BIT22 /* User definable features */ -+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ -+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ -+ -+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ -+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) -+ -+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ -+#define PSCR_MABORT BIT29 /* Recieved Master Abort */ -+#define PSCR_SYSERR BIT30 /* Signalled system error */ -+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+/* PCI configuration register offset=0x08 fields -+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ -+ -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) -+ -+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) -+ -+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) -+ -+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) -+ -+/* PCI configuration register offset=0x0C fields -+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ -+ -+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) -+ -+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ -+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) -+ -+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) -+ -+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ -+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) -+ -+ -+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) -+ -+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ -+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ -+ -+ -+/* PCI Bar Base Low Register (PBBLR) */ -+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) -+ -+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+ -+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to -+ address bits [31:4] */ -+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) -+ -+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to -+ address bits [31:2] */ -+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) -+ -+ -+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ -+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) -+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) -+ -+ -+/* PCI Bar Base High Fegister (PBBHR) */ -+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ -+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+/* PCI configuration register offset=0x2C fields -+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ -+ -+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) -+ -+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) -+ -+/* PCI configuration register offset=0x30 fields -+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ -+ -+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ -+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) -+ -+/* PCI configuration register offset=0x34 fields -+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ -+ -+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) -+ -+/* PCI configuration register offset=0x3C fields -+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ -+ -+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) -+ -+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) -+ -+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ -+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) -+ -+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ -+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) -+ -+#endif /* #ifndef __INCPCIIFREGSH */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c -new file mode 100644 -index 0000000..6de1b0c ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c -@@ -0,0 +1,1006 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvPciUtils.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+ #define mvOsPrintf printf -+#else -+ #define DB(x) -+#endif -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+ -+ -+ -+ -+ -+/******************************************************************************* -+* mvPciScan - Scan a PCI interface bus -+* -+* DESCRIPTION: -+* Performs a full scan on a PCI interface and returns all possible details -+* on the agents found on the bus. -+* -+* INPUT: -+* pciIf - PCI Interface -+* pPciAgents - Pointer to an Array of the pci agents to be detected -+* pPciAgentsNum - pPciAgents array maximum number of elements -+* -+* OUTPUT: -+* pPciAgents - Array of the pci agents detected on the bus -+* pPciAgentsNum - Number of pci agents detected on the bus -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPciScan(MV_U32 pciIf, -+ MV_PCI_DEVICE *pPciAgents, -+ MV_U32 *pPciAgentsNum) -+{ -+ -+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; -+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); -+ MV_PCI_DEVICE *pPciDevice; -+ MV_PCI_DEVICE *pMainDevice; -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPexMaxIfGet()) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgents) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); -+ /* Master enable the MV PCI master */ -+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); -+ return MV_ERROR; -+ -+ } -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); -+ -+ /* go through all busses */ -+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) -+ { -+ /* go through all possible devices on the local bus */ -+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) -+ { -+ /* always start with function equal to zero */ -+ funcIndex=0; -+ -+ pPciDevice=&pPciAgents[detectedDevNum]; -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); -+ -+ if (MV_ERROR == pciDetectDevice(pciIf, -+ busIndex, -+ devIndex, -+ funcIndex, -+ pPciDevice)) -+ { -+ /* no device detected , try the next address */ -+ continue; -+ } -+ -+ /* We are here ! means we have detected a device*/ -+ /* always we start with only one function per device */ -+ pMainDevice = pPciDevice; -+ pPciDevice->funtionsNum = 1; -+ -+ -+ /* move on */ -+ detectedDevNum++; -+ -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); -+ return MV_ERROR; -+ } -+ -+ /* check the detected device if it is a multi functional device then -+ scan all device functions*/ -+ if (pPciDevice->isMultiFunction == MV_TRUE) -+ { -+ /* start with function number 1 because we have already detected -+ function 0 */ -+ for (funcIndex=1; funcIndexfuntionsNum++; -+ detectedDevNum++; -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); -+ return MV_ERROR; -+ } -+ -+ -+ } -+ } -+ -+ } -+ -+ } -+ -+ /* return the number of devices actually detected on the bus ! */ -+ *pPciAgentsNum = detectedDevNum; -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* pciDetectDevice - Detect a pci device parameters -+* -+* DESCRIPTION: -+* This function detect if a pci agent exist on certain address ! -+* and if exists then it fills all possible information on the -+* agent -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* MV_ERROR if no device , MV_OK otherwise -+* -+*******************************************************************************/ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData; -+ -+ /* no Parameters checking ! because it is static function and it is assumed -+ that all parameters were checked in the calling function */ -+ -+ -+ /* Try read the PCI Vendor ID and Device ID */ -+ -+ /* We will scan only ourselves and the PCI slots that exist on the -+ board, because we may have a case that we have one slot that has -+ a Cardbus connector, and because CardBus answers all IDsels we want -+ to scan only this slot and ourseleves. -+ -+ */ -+ #if defined(MV_INCLUDE_PCI) -+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && -+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) -+ { -+ -+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) -+ { -+ return MV_ERROR; -+ } -+ } -+ #endif /* defined(MV_INCLUDE_PCI) */ -+ -+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); -+ -+ if (PCI_ERROR_CODE == pciData) -+ { -+ /* no device exist */ -+ return MV_ERROR; -+ } -+ -+ /* we are here ! means a device is detected */ -+ -+ /* fill basic information */ -+ pPciAgent->busNumber=bus; -+ pPciAgent->deviceNum=dev; -+ pPciAgent->function=func; -+ -+ /* Fill the PCI Vendor ID and Device ID */ -+ -+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; -+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; -+ -+ /* Read Status and command */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_STATUS_AND_COMMAND); -+ -+ -+ /* Fill related Status and Command information*/ -+ -+ if (pciData & PSCR_TAR_FAST_BB) -+ { -+ pPciAgent->isFastB2BCapable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isFastB2BCapable = MV_FALSE; -+ } -+ -+ if (pciData & PSCR_CAP_LIST) -+ { -+ pPciAgent->isCapListSupport=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isCapListSupport=MV_FALSE; -+ } -+ -+ if (pciData & PSCR_66MHZ_EN) -+ { -+ pPciAgent->is66MHZCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->is66MHZCapable=MV_FALSE; -+ } -+ -+ /* Read Class Code and Revision */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CLASS_CODE_AND_REVISION_ID); -+ -+ -+ pPciAgent->baseClassCode = -+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; -+ -+ pPciAgent->subClassCode = -+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; -+ -+ pPciAgent->progIf = -+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; -+ -+ pPciAgent->revisionID = -+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; -+ -+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); -+ -+ -+ -+ pPciAgent->pciCacheLine= -+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; -+ pPciAgent->pciLatencyTimer= -+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; -+ -+ switch (pciData & PBHTLTCLR_HEADER_MASK) -+ { -+ case PBHTLTCLR_HEADER_STANDARD: -+ -+ pPciAgent->pciHeader=MV_PCI_STANDARD; -+ break; -+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: -+ -+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; -+ break; -+ -+ } -+ -+ if (pciData & PBHTLTCLR_MULTI_FUNC) -+ { -+ pPciAgent->isMultiFunction=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isMultiFunction=MV_FALSE; -+ } -+ -+ if (pciData & PBHTLTCLR_BISTCAP) -+ { -+ pPciAgent->isBISTCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isBISTCapable=MV_FALSE; -+ } -+ -+ -+ /* read this device pci bars */ -+ -+ pciDetectDeviceBars(pciIf, -+ bus,dev,func, -+ pPciAgent); -+ -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ -+ /* Read P2P_BUSSES_NUM */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_BUSSES_NUM); -+ -+ pPciAgent->p2pPrimBusNum = -+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecBusNum = -+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSubBusNum = -+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecLatencyTimer = -+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; -+ -+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_SEC_STATUS); -+ -+ pPciAgent->p2pSecStatus = -+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; -+ -+ -+ pPciAgent->p2pIObase = -+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; -+ -+ /* clear low address (should be zero)*/ -+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pIOLimit = -+ (pciData & PIBLSS_IO_LIMIT_MASK); -+ -+ /* fill low address with 0xfff */ -+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; -+ -+ -+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) -+ { -+ case PIBLSS_ADD_CAP_16BIT: -+ -+ pPciAgent->bIO32 = MV_FALSE; -+ -+ break; -+ case PIBLSS_ADD_CAP_32BIT: -+ -+ pPciAgent->bIO32 = MV_TRUE; -+ -+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_UPPER_16); -+ -+ pPciAgent->p2pIObase |= -+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; -+ -+ -+ pPciAgent->p2pIOLimit |= -+ (pciData & PRBU_IO_UPP_LIMIT_MASK); -+ -+ break; -+ -+ } -+ -+ -+ /* Read P2P_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_MEM_BASE_LIMIT); -+ -+ pPciAgent->p2pMemBase = -+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; -+ -+ /* clear low address */ -+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pMemLimit = -+ (pciData & PMBL_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; -+ -+ -+ /* Read P2P_PREF_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_MEM_BASE_LIMIT); -+ -+ -+ pPciAgent->p2pPrefMemBase = -+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; -+ -+ /* get high address only */ -+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; -+ -+ -+ -+ pPciAgent->p2pPrefMemLimit = -+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; -+ -+ switch (pciData & PRMBL_ADD_CAP_MASK) -+ { -+ case PRMBL_ADD_CAP_32BIT: -+ -+ pPciAgent->bPrefMem64 = MV_FALSE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = 0; -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = 0; -+ -+ break; -+ case PRMBL_ADD_CAP_64BIT: -+ -+ pPciAgent->bPrefMem64 = MV_TRUE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_BASE_UPPER_32); -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_LIMIT_UPPER_32); -+ -+ break; -+ -+ } -+ -+ } -+ else /* no bridge */ -+ { -+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); -+ -+ -+ pPciAgent->subSysVenID = -+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; -+ pPciAgent->subSysID = -+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; -+ -+ -+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_EXPANSION_ROM_BASE_ADDR_REG); -+ -+ -+ if (pciData & PERBAR_EXPROMEN) -+ { -+ pPciAgent->isExpRom = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isExpRom = MV_FALSE; -+ } -+ -+ pPciAgent->expRomAddr = -+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; -+ -+ } -+ -+ -+ if (MV_TRUE == pPciAgent->isCapListSupport) -+ { -+ /* Read PCI_CAPABILTY_LIST_POINTER */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CAPABILTY_LIST_POINTER); -+ -+ pPciAgent->capListPointer = -+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; -+ -+ } -+ -+ /* Read PCI_INTERRUPT_PIN_AND_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_INTERRUPT_PIN_AND_LINE); -+ -+ -+ pPciAgent->irqLine= -+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; -+ -+ pPciAgent->intPin= -+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; -+ -+ pPciAgent->minGrant= -+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; -+ pPciAgent->maxLatency= -+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; -+ -+ mvPciClassNameGet(pPciAgent->baseClassCode, -+ (MV_8 *)pPciAgent->type); -+ -+ return MV_OK; -+ -+ -+} -+ -+/******************************************************************************* -+* pciDetectDeviceBars - Detect a pci device bars -+* -+* DESCRIPTION: -+* This function detects all pci agent bars -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* detected bars number -+* -+*******************************************************************************/ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData,barIndex,detectedBar=0; -+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; -+ MV_U32 pciMaxBars=0; -+ -+ pPciAgent->barsNum=0; -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ pciMaxBars = 2; -+ } -+ else /* no bridge */ -+ { -+ pciMaxBars = 6; -+ } -+ -+ /* read this device pci bars */ -+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) -+ { -+ /* Read PCI_MEMORY_BAR_BASE_ADDR */ -+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ pPciAgent->pciBar[detectedBar].barOffset = -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex); -+ -+ /* check if the bar is 32bit or 64bit bar */ -+ switch (pciData & PBBLR_TYPE_MASK) -+ { -+ case PBBLR_TYPE_32BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; -+ break; -+ case PBBLR_TYPE_64BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; -+ break; -+ -+ } -+ -+ /* check if it is memory or IO bar */ -+ if (pciData & PBBLR_IOSPACE) -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; -+ } -+ -+ /* if it is memory bar then check if it is prefetchable */ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ if (pciData & PBBLR_PREFETCH_EN) -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_MEM_BASE_MASK; -+ -+ -+ } -+ else /* IO Bar */ -+ { -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_IO_BASE_MASK; -+ -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseHigh=0; -+ -+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) -+ { -+ barIndex++; -+ -+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ -+ } -+ -+ /* calculating full base address (64bit) */ -+ pPciAgent->pciBar[detectedBar].barBaseAddr = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr |= -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; -+ -+ -+ -+ /* get the sizes of the the bar */ -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh=0; -+ -+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && -+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) -+ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ /* start with sizelow ( original value was saved in tmpBaseLow ) */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); -+ -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ tmpBaseLow); -+ -+ -+ /* now do the same for BaseHigh */ -+ -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseHigh); -+ -+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& -+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ -+ /* we though this was a 64bit bar , and it seems this -+ was wrong ! so decrement barIndex */ -+ barIndex--; -+ continue; -+ } -+ -+ /* calculate the full 64 bit size */ -+ -+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ else -+ { -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ -+ -+ -+ } -+ else /* 32bit bar */ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ continue; -+ } -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseLow); -+ -+ /* calculate size low */ -+ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ pPciAgent->pciBar[detectedBar].barSize = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; -+ -+ -+ } -+ -+ /* we are here ! this means we have already detected a bar for -+ this device , now move on */ -+ -+ detectedBar++; -+ pPciAgent->barsNum++; -+ } -+ -+ return detectedBar; -+} -+ -+ -+/******************************************************************************* -+* mvPciClassNameGet - get PCI class name -+* -+* DESCRIPTION: -+* This function returns the PCI class name -+* -+* INPUT: -+* baseClassCode - Base Class Code. -+* -+* OUTPUT: -+* pType - the class name -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) -+{ -+ -+ switch(baseClassCode) -+ { -+ case 0x0: -+ strcpy(pType,"Old generation device"); -+ break; -+ case 0x1: -+ strcpy(pType,"Mass storage controller"); -+ break; -+ case 0x2: -+ strcpy(pType,"Network controller"); -+ break; -+ case 0x3: -+ strcpy(pType,"Display controller"); -+ break; -+ case 0x4: -+ strcpy(pType,"Multimedia device"); -+ break; -+ case 0x5: -+ strcpy(pType,"Memory controller"); -+ break; -+ case 0x6: -+ strcpy(pType,"Bridge Device"); -+ break; -+ case 0x7: -+ strcpy(pType,"Simple Communication controllers"); -+ break; -+ case 0x8: -+ strcpy(pType,"Base system peripherals"); -+ break; -+ case 0x9: -+ strcpy(pType,"Input Devices"); -+ break; -+ case 0xa: -+ strcpy(pType,"Docking stations"); -+ break; -+ case 0xb: -+ strcpy(pType,"Processors"); -+ break; -+ case 0xc: -+ strcpy(pType,"Serial bus controllers"); -+ break; -+ case 0xd: -+ strcpy(pType,"Wireless controllers"); -+ break; -+ case 0xe: -+ strcpy(pType,"Intelligent I/O controllers"); -+ break; -+ case 0xf: -+ strcpy(pType,"Satellite communication controllers"); -+ break; -+ case 0x10: -+ strcpy(pType,"Encryption/Decryption controllers"); -+ break; -+ case 0x11: -+ strcpy(pType,"Data acquisition and signal processing controllers"); -+ break; -+ default: -+ strcpy(pType,"Unknown device"); -+ break; -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h -new file mode 100644 -index 0000000..444f53c ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h -@@ -0,0 +1,323 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvPciUtilsh -+#define __INCmvPciUtilsh -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIf.h" -+#include "pci/mvPciRegs.h" -+ -+ -+ -+/* PCI base address low bar mask */ -+#define PCI_ERROR_CODE 0xffffffff -+ -+#define PCI_BRIDGE_CLASS 0x6 -+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 -+ -+ -+#define P2P_BUSSES_NUM 0x18 -+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C -+#define P2P_MEM_BASE_LIMIT 0x20 -+#define P2P_PREF_MEM_BASE_LIMIT 0x24 -+#define P2P_PREF_BASE_UPPER_32 0x28 -+#define P2P_PREF_LIMIT_UPPER_32 0x2C -+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 -+#define P2P_EXP_ROM 0x38 -+ -+/* P2P_BUSSES_NUM (PBM) */ -+ -+#define PBM_PRIME_BUS_NUM_OFFS 0 -+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) -+ -+#define PBM_SEC_BUS_NUM_OFFS 8 -+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) -+ -+#define PBM_SUB_BUS_NUM_OFFS 16 -+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) -+ -+#define PBM_SEC_LAT_TMR_OFFS 24 -+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) -+ -+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ -+ -+#define PIBLSS_IO_BASE_OFFS 0 -+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) -+ -+#define PIBLSS_ADD_CAP_OFFS 0 -+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) -+ -+#define PIBLSS_LOW_ADDR_OFFS 0 -+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) -+ -+#define PIBLSS_HIGH_ADDR_OFFS 12 -+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) -+ -+#define PIBLSS_IO_LIMIT_OFFS 8 -+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) -+ -+#define PIBLSS_SEC_STATUS_OFFS 16 -+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) -+ -+ -+/* P2P_MEM_BASE_LIMIT (PMBL)*/ -+ -+#define PMBL_MEM_BASE_OFFS 0 -+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) -+ -+#define PMBL_MEM_LIMIT_OFFS 16 -+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) -+ -+ -+#define PMBL_LOW_ADDR_OFFS 0 -+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) -+ -+#define PMBL_HIGH_ADDR_OFFS 20 -+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) -+ -+ -+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ -+ -+#define PRMBL_PREF_MEM_BASE_OFFS 0 -+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) -+ -+#define PRMBL_PREF_MEM_LIMIT_OFFS 16 -+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set command register */ -+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); -+ -+ /* Upodate device max outstanding split tarnsaction */ -+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && -+ (command & PCR_PCI_TO_CPU_ORDER_EN)) -+ { -+ /* Read PCI-X command register */ -+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); -+ -+ /* clear bits 22:20 */ -+ regVal &= 0xff8fffff; -+ -+ /* set reset value */ -+ regVal |= (0x3 << 20); -+ -+ /* Write back the value */ -+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciModeGet - Get PCI interface mode. -+* -+* DESCRIPTION: -+* This function returns the given PCI interface mode. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* pPciMode - Pointer to PCI mode structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -+{ -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciMode) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Read pci mode register */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ -+ switch (pciMode & PMR_PCI_MODE_MASK) -+ { -+ case PMR_PCI_MODE_CONV: -+ pPciMode->pciType = MV_PCI_CONV; -+ -+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) -+ { -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ } -+ else -+ { -+ pPciMode->pciSpeed = 33000000; /* 33MHZ */ -+ } -+ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_66MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_100MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 100000000; /* 100MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_133MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 133000000; /* 133MHZ */ -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ switch (pciMode & PMR_PCI_64_MASK) -+ { -+ case PMR_PCI_64_64BIT: -+ pPciMode->pciWidth = MV_PCI_64; -+ break; -+ -+ case PMR_PCI_64_32BIT: -+ pPciMode->pciWidth = MV_PCI_32; -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciRetrySet - Set PCI retry counters -+* -+* DESCRIPTION: -+* This function specifies the number of times the PCI controller -+* retries a transaction before it quits. -+* Applies to the PCI Master when acting as a requester. -+* Applies to the PCI slave when acting as a completer (PCI-X mode). -+* A 0x00 value means a "retry forever". -+* -+* INPUT: -+* pciIf - PCI interface number. -+* counter - Number of times PCI controller retry. Use counter value -+* up to PRR_RETRY_CNTR_MAX. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -+{ -+ MV_U32 pciRetry; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (counter >= PRR_RETRY_CNTR_MAX) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Reading PCI retry register */ -+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); -+ -+ pciRetry &= ~PRR_RETRY_CNTR_MASK; -+ -+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); -+ -+ /* write new value */ -+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciDiscardTimerSet - Set PCI discard timer -+* -+* DESCRIPTION: -+* This function set PCI discard timer. -+* In conventional PCI mode: -+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -+* read buffers (non-completed delayed read) before invalidate the buffer. -+* Set to '0' to disable the timer. The PCI slave waits for delayed -+* read completion forever. -+* In PCI-X mode: -+* Specifies the number of PCLK cycles the PCI master waits for split -+* completion transaction, before it invalidates the pre-allocated read -+* buffer. -+* Set to '0' to disable the timer. The PCI master waits for split -+* completion forever. -+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -+* unless using the "wait for ever" setting 0x0. -+* NOTE: Must not be updated while there are pending read requests. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciDiscardTimer; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pClkCycles >= PDTR_TIMER_MIN) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", -+ pClkCycles); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Read PCI Discard Timer */ -+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); -+ -+ pciDiscardTimer &= ~PDTR_TIMER_MASK; -+ -+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); -+ -+ /* Write new value */ -+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); -+ -+ return MV_OK; -+ -+} -+ -+/* PCI Arbiter routines */ -+ -+/******************************************************************************* -+* mvPciArbEnable - PCI arbiter enable/disable -+* -+* DESCRIPTION: -+* This fuction enable/disables a given PCI interface arbiter. -+* NOTE: Arbiter setting can not be changed while in work. It should only -+* be set once. -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 regVal; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Set PCI Arbiter Control register according to default configuration */ -+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Make sure arbiter disabled before changing its values */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; -+ -+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ -+ -+ if (MV_TRUE == enable) -+ { -+ regVal |= PACR_ARB_ENABLE; -+ } -+ else -+ { -+ regVal &= ~PACR_ARB_ENABLE; -+ } -+ -+ /* Write to register */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbParkDis - Disable arbiter parking on agent -+* -+* DESCRIPTION: -+* This function disables the PCI arbiter from parking on the given agent -+* list. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pciAgentMask - When a bit in the mask is set to '1', parking on -+* the associated PCI master is disabled. Mask bit -+* refers to bit 0 - 6. For example disable parking on PCI -+* agent 3 set pciAgentMask 0x4 (bit 3 is set). -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -+{ -+ MV_U32 pciArbiterCtrl; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Arbiter must be disabled before changing parking */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* do the change */ -+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; -+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -+* -+* DESCRIPTION: -+* This function sets the maximum number of cycles that the arbiter -+* waits for a PCI master to respond to its grant assertion. If a -+* PCI agent fails to respond within this time, the PCI arbiter aborts -+* the transaction and performs a new arbitration cycle. -+* NOTE: Value must be greater than '1' for conventional PCI and -+* greater than '5' for PCI-X. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -+* master detection is disabled. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciArbiterCtrl; -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Checking PCI mode and if pClkCycles is legal value */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ pciMode &= PMR_PCI_MODE_MASK; -+ -+ if (PMR_PCI_MODE_CONV == pciMode) -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) -+ return MV_ERROR; -+ } -+ else -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) -+ return MV_ERROR; -+ } -+ -+ pClkCycles <<= PACR_BROKEN_VAL_OFFS; -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; -+ pciArbiterCtrl |= pClkCycles; -+ -+ /* Arbiter must be disabled before changing broken detection */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ /* Read the Data returned in the PCI Data register */ -+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); -+ -+ return pciData; -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PCI Data register */ -+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= PSCR_MASTER_EN; -+ } -+ else -+ { -+ pciCommandStatus &= ~PSCR_MASTER_EN; -+ } -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ else -+ { -+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ -+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCI-X then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_BN_MASK; -+ -+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; -+ -+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ -+ } -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ pciP2PConfig &= PPCR_BUS_NUM_MASK; -+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCIX then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_DN_MASK; -+ -+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; -+ -+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; -+ -+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= PPCR_DEV_NUM_MASK; -+ -+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -+} -+ -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h -new file mode 100644 -index 0000000..3c521db ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCPCIH -+#define __INCPCIH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "pci/mvPciRegs.h" -+ -+ -+/* NOTE not supported in this driver: -+ -+ Built In Self Test (BIST) -+ Vital Product Data (VPD) -+ Message Signaled Interrupt (MSI) -+ Power Management -+ Compact PCI Hot Swap -+ Header retarget -+ -+Registers not supported: -+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -+*/ -+ -+/* defines */ -+/* The number of supported PCI interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PCI unit */ -+/* configuration header. This creates a loop where calling PCI */ -+/* configuration read/write routine results a call to get PCI configuration */ -+/* information etc. This macro defines a default PCI interface. This PCI */ -+/* interface is sure to exist. */ -+#define PCI_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both conventional PCI and PCI-X. */ -+/* This enumeration describes the PCI type. */ -+typedef enum _mvPciType -+{ -+ MV_PCI_CONV, /* Conventional PCI */ -+ MV_PCIX /* PCI-X */ -+}MV_PCI_TYPE; -+ -+typedef enum _mvPciMod -+{ -+ MV_PCI_MOD_HOST, -+ MV_PCI_MOD_DEVICE -+}MV_PCI_MOD; -+ -+ -+/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -+/* This enumerator describes PCI width */ -+typedef enum _mvPciWidth -+{ -+ MV_PCI_32, /* PCI width 32bit */ -+ MV_PCI_64 /* PCI width 64bit */ -+}MV_PCI_WIDTH; -+ -+/* This structure describes the PCI unit configured type, speed and width. */ -+typedef struct _mvPciMode -+{ -+ MV_PCI_TYPE pciType; /* PCI type */ -+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ -+ MV_PCI_WIDTH pciWidth; /* PCI bus width */ -+}MV_PCI_MODE; -+ -+/* mvPciInit - Initialize PCI interfaces*/ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); -+ -+/* mvPciCommandSet - Set PCI comman register value.*/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); -+ -+/* mvPciModeGet - Get PCI interface mode.*/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); -+ -+/* mvPciRetrySet - Set PCI retry counters*/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); -+ -+/* mvPciDiscardTimerSet - Set PCI discard timer*/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciArbEnable - PCI arbiter enable/disable*/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciArbParkDis - Disable arbiter parking on agent */ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); -+ -+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciConfigRead - Read from configuration space */ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciConfigWrite - Write to configuration space */ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); -+ -+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); -+ -+ -+#endif /* #ifndef __INCPCIH */ -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h -new file mode 100644 -index 0000000..9ae555f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h -@@ -0,0 +1,411 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIREGSH -+#define __INCPCIREGSH -+ -+ -+#include "pci-if/mvPciIfRegs.h" -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/* enumerators */ -+ -+/* This enumerator described the possible PCI slave targets. */ -+/* PCI slave targets are designated memory/IO address spaces that the */ -+/* PCI slave targets can access. They are also refered as "targets" */ -+/* this enumeratoe order is determined by the content of : -+ PCI_BASE_ADDR_ENABLE_REG */ -+ -+ -+/* registers offsetes defines */ -+ -+ -+ -+/*************************/ -+/* PCI control registers */ -+/*************************/ -+/* maen : should add new registers */ -+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ -+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ -+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ -+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+ -+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) -+ -+/* PCI Dll Control (PDC)*/ -+#define PDC_DLL_EN BIT0 -+ -+ -+/* PCI Command Register (PCR) */ -+#define PCR_MASTER_BYTE_SWAP_EN BIT0 -+#define PCR_MASTER_WR_COMBINE_EN BIT4 -+#define PCR_MASTER_RD_COMBINE_EN BIT5 -+#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -+#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -+#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -+#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -+#define PCR_MASTER_WORD_SWAP_EN BIT10 -+#define PCR_SLAVE_WORD_SWAP_EN BIT11 -+#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -+#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -+#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -+#define PCR_MASTER_DAC_EN BIT17 -+#define PCR_MASTER_M64_ALLIGN BIT18 -+#define PCR_ERRORS_PROPAGATION_EN BIT19 -+#define PCR_SLAVE_SWAP_ENABLE BIT20 -+#define PCR_MASTER_SWAP_ENABLE BIT21 -+#define PCR_MASTER_INT_SWAP_EN BIT22 -+#define PCR_LOOP_BACK_ENABLE BIT23 -+#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -+#define PCR_SLAVE_INTREG_BYTE_SWAP \ -+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_NO_SWAP \ -+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_BYTE_WORD \ -+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_WORD_SWAP \ -+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_RESET_REASSERTION_EN BIT26 -+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -+#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -+#define PCR_PCI_TO_CPU_ORDER_EN BIT30 -+ -+/* PCI Mode Register (PMR) */ -+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) -+ -+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) -+ -+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) -+ -+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ -+ -+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) -+ -+ -+/* PCI Retry Register (PRR) */ -+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -+#define PRR_RETRY_CNTR_MAX 0xff -+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) -+ -+ -+/* PCI Discard Timer Register (PDTR) */ -+#define PDTR_TIMER_OFFS 0 /* Timer */ -+#define PDTR_TIMER_MAX 0xffff -+#define PDTR_TIMER_MIN 0x7F -+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) -+ -+ -+/* PCI Arbiter Control Register (PACR) */ -+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ -+ -+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -+#define PACR_BROKEN_VAL_CONV_MIN 0x2 -+#define PACR_BROKEN_VAL_PCIX_MIN 0x6 -+ -+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -+#define PACR_PARK_DIS_MAX_AGENT 0x3f -+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); -+ -+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) -+ { -+ case PXCR_DEV_TYPE_CTRL_CMPLX: -+ pexMode->pexType = MV_PEX_ROOT_COMPLEX; -+ break; -+ case PXCR_DEV_TYPE_CTRL_POINT: -+ pexMode->pexType = MV_PEX_END_POINT; -+ break; -+ -+ } -+ -+ /* Check if we have link */ -+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) -+ { -+ pexMode->pexLinkUp = MV_FALSE; -+ -+ /* If there is no link, the auto negotiation data is worthless */ -+ pexMode->pexWidth = MV_PEX_WITDH_INVALID; -+ } -+ else -+ { -+ pexMode->pexLinkUp = MV_TRUE; -+ -+ /* We have link. The link width is now valid */ -+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); -+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> -+ PXLCSR_NEG_LNK_WDTH_OFFS); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/* PEX configuration space read write */ -+ -+/******************************************************************************* -+* mvPexConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -+} -+ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", -+ pexIf, bus, dev, func, regOff)); -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ /* Speed up the process. In case on no link, return MV_ERROR */ -+ if ((dev != localDev) || (bus != localBus)) -+ { -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ /* in PCI Express we have only one device number */ -+ /* and this number is the first number we encounter -+ else that the localDev*/ -+ /* spec pex define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ if(func != 0 ) /* i.e bridge */ -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ /* Creating PEX address to be passed */ -+ pexData = (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ -+ pexData |= PXCAR_CONFIG_EN; -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); -+ -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* cleaning Master Abort */ -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ PXSAC_MABORT); -+#if 0 -+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ -+ /* This guideline is relevant for all devices except of the following devices: -+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above -+ 88F6183 A0 and above, 88F6183L */ -+ if ( ( (dev != localDev) || (bus != localBus) ) && -+ ( -+ !(MV_5281_DEV_ID == mvCtrlModelGet())&& -+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& -+ !(MV_1281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6192_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6190_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6180_DEV_ID == mvCtrlModelGet())&& -+ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) -+ )) -+ { -+ -+ /* PCI-Express configuration read work-around */ -+ -+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar -+ and read the data from there */ -+ /* -+ Need to configure the 2 free Punit (AHB to MBus bridge) -+ address decoding windows: -+ Configure the flash Window to handle Configuration space requests -+ for PEX0/1: -+ 1. write 0x7931/0x7941 to the flash window and the size, -+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn -+ 2. write base to flash window -+ -+ Configuration transactions from the CPU should write/read the data -+ to/from address of the form: -+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) -+ addr[27:24] = extended register number -+ addr[23:16] = bus number -+ addr[15:11] = device number -+ addr[10:8] = function number -+ addr[7:0] = register number -+ */ -+ -+ #include "ctrlEnv/sys/mvAhbToMbus.h" -+ { -+ MV_U32 winNum; -+ MV_AHB_TO_MBUS_DEC_WIN originWin; -+ MV_U32 pciAddr=0; -+ MV_U32 remapLow=0,remapHigh=0; -+ -+ /* -+ We will use DEV_CS2\Flash window for this workarround -+ */ -+ -+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); -+ -+ /* save remap values if exist */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); -+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); -+ -+ } -+ -+ -+ /* save the original window values */ -+ mvAhbToMbusWinGet(winNum,&originWin); -+ -+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ originWin.addrWin.baseLow); -+ -+ /*pciAddr = originWin.addrWin.baseLow;*/ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( -+ (MV_U32)originWin.addrWin.baseLow); -+ -+ } -+ else -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ PEX_CONFIG_RW_WA_BASE); -+ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); -+ } -+ -+ -+ /* remap should be as base */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); -+ -+ } -+ -+ /* extended register space */ -+ pciAddr |= (bus << 16); -+ pciAddr |= (dev << 11); -+ pciAddr |= (func << 8); -+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ -+ pexData = *(MV_U32*)pciAddr; -+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ -+ -+ /* restore the original window values */ -+ mvAhbToMbusWinSet(winNum,&originWin); -+ -+ /* restore original remap values*/ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); -+ -+ } -+ } -+ } -+ else -+#endif -+ { -+ /* Read the Data returned in the PEX Data register */ -+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); -+ -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); -+ -+ return pexData; -+ -+} -+ -+/******************************************************************************* -+* mvPexConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -+} -+ -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ /* in PCI Express we have only one device number other than ourselves*/ -+ /* and this number is the first number we encounter -+ else than the localDev that can be any valid dev number*/ -+ /* pex spec define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ } -+ -+ /* if we are not accessing ourselves , then check the link */ -+ if ((dev != localDev) || (bus != localBus) ) -+ { -+ /* workarround */ -+ /* when no link return MV_ERROR */ -+ -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ -+ pexData =0; -+ -+ /* Creating PEX address to be passed */ -+ pexData |= (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ pexData |= PXCAR_CONFIG_EN; -+ -+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", -+ pexIf,bus,func,dev,regOff,data,pexData) ); -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ /* Clear CPU pipe. Important where CPU can perform OOO execution */ -+ CPU_PIPE_FLUSH; -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PEX Data register */ -+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexMasterEnable - Enable/disale PEX interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_STATUS_AND_COMMAND)); -+ -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= PXSAC_MASTER_EN; -+ } -+ else -+ { -+ pexCommandStatus &= ~PXSAC_MASTER_EN; -+ } -+ -+ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ pexCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PEX slave is allowed to respond to PEX IO space access (bit 0) -+* and PEX memory space access (bit 1). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* dev - PEX device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ RegOffs = PEX_STATUS_AND_COMMAND; -+ -+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ else -+ { -+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ -+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexLocalBusNumSet - Set PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local bus number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; -+ -+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalBusNumGet - Get PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_BUS_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalDevNumSet - Set PEX interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local device number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; -+ -+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexLocalDevNumGet - Get PEX interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_DEV_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -+} -+ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -+{ -+ -+ MV_U32 regAddr; -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -+} -+ -+ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -+{ -+ -+ MV_U32 regAddr; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (((regOffset & 0x3fff) << 16) | value); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+} -+ -+/******************************************************************************* -+* mvPexActiveStateLinkPMEnable -+* -+* DESCRIPTION: -+* Enable Active Link State Power Management -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 reg; -+ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXPMER_L1_ASPM_EN_MASK; -+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); -+ -+ /* Enable / Disable L0/1 entry */ -+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) -+ & ~PXLCSR_ASPM_CNT_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexForceX1 -+* -+* DESCRIPTION: -+* shut down lanes 1-3 if recognize that attached to an x1 end-point -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_U32 mvPexForceX1(MV_U32 pexIf) -+{ -+ MV_U32 regData = 0; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; -+ regData |= PXCR_CONF_LINK_X1; -+ -+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); -+ return MV_OK; -+} -+ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -+{ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_FALSE; -+ } -+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -+} -+ -+ -+MV_VOID mvPexPowerDown(MV_U32 pexIf) -+{ -+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ { -+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); -+ } -+ else -+ { -+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); -+ } -+} -+ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h -new file mode 100644 -index 0000000..e84fdf9 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h -@@ -0,0 +1,168 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXH -+#define __INCPEXH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+ -+/* NOTE not supported in this driver:*/ -+ -+ -+/* defines */ -+/* The number of supported PEX interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PEX unit */ -+/* configuration header. This creates a loop where calling PEX */ -+/* configuration read/write routine results a call to get PEX configuration */ -+/* information etc. This macro defines a default PEX interface. This PEX */ -+/* interface is sure to exist. */ -+#define PEX_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both root complex and end point devices */ -+/* This enumeration describes the PEX type. */ -+typedef enum _mvPexType -+{ -+ MV_PEX_ROOT_COMPLEX, /* root complex device */ -+ MV_PEX_END_POINT /* end point device */ -+}MV_PEX_TYPE; -+ -+typedef enum _mvPexWidth -+{ -+ MV_PEX_WITDH_X1 = 1, -+ MV_PEX_WITDH_X2, -+ MV_PEX_WITDH_X3, -+ MV_PEX_WITDH_X4, -+ MV_PEX_WITDH_INVALID -+}MV_PEX_WIDTH; -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexMode -+{ -+ MV_PEX_TYPE pexType; -+ MV_PEX_WIDTH pexWidth; -+ MV_BOOL pexLinkUp; -+}MV_PEX_MODE; -+ -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+/* mvPexModeGet - Get Pex If mode */ -+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); -+ -+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); -+ -+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); -+ -+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); -+ -+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -+/* mvPexForceX1 - Force PEX interface to X1 mode. */ -+MV_U32 mvPexForceX1(MV_U32 pexIf); -+ -+/* mvPexIsPowerUp - Is PEX interface Power up? */ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); -+ -+/* mvPexPowerDown - Power Down */ -+MV_VOID mvPexPowerDown(MV_U32 pexIf); -+ -+/* mvPexPowerUp - Power Up */ -+MV_VOID mvPexPowerUp(MV_U32 pexIf); -+ -+/* mvPexPhyRegRead - Pex phy read */ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); -+ -+/* mvPexPhyRegWrite - Pex phy write */ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); -+ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+#endif /* #ifndef __INCPEXH */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h -new file mode 100644 -index 0000000..ea19e2f ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXREGSH -+#define __INCPEXREGSH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MAX_PEX_DEVICES 32 -+#define MAX_PEX_FUNCS 8 -+#define MAX_PEX_BUSSES 256 -+ -+ -+ -+/*********************************************************/ -+/* PCI Express Configuration Cycles Generation Registers */ -+/*********************************************************/ -+ -+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -+/* PCI Express Configuration Address Register */ -+/* PEX_CFG_ADDR_REG (PXCAR)*/ -+ -+#define PXCAR_REG_NUM_OFFS 2 -+#define PXCAR_REG_NUM_MAX 0x3F -+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -+#define PXCAR_FUNC_NUM_OFFS 8 -+#define PXCAR_FUNC_NUM_MAX 0x7 -+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -+#define PXCAR_DEVICE_NUM_OFFS 11 -+#define PXCAR_DEVICE_NUM_MAX 0x1F -+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -+#define PXCAR_BUS_NUM_OFFS 16 -+#define PXCAR_BUS_NUM_MAX 0xFF -+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -+#define PXCAR_EXT_REG_NUM_OFFS 24 -+#define PXCAR_EXT_REG_NUM_MAX 0xF -+ -+/* in pci express register address is now the legacy register address (8 bits) -+with the new extended register address (more 4 bits) , below is the mask of -+the upper 4 bits of the full register address */ -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -+#define PXCAR_CONFIG_EN BIT31 -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) -+ -+/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -+/* The new PCI Express extend the register offset by an extra 4-bits. */ -+/* The below macro assign 10-bit register offset into the apprpreate */ -+/* fields in the CFG_ADDR_REG */ -+#define PXCAR_REG_OFFS_SET(regOffs) \ -+ ( (regOff & PXCAR_REG_NUM_MASK) | \ -+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) -+ -+/***********************************/ -+/* PCI Express Interrupt registers */ -+/***********************************/ -+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) -+ -+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ -+ /* of the PCI Express */ -+/* PCI Express Interrupt Cause */ -+/* PEX_INT_CAUSE_REG (PXICR)*/ -+/* PEX_INT_MASK_REG*/ -+/* -+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -+no affect. Bits[24:27} are set and cleared upon reception of interrupt -+emulation messages. -+ -+Mask bit per cause bit. If a bit is set to 1, the corresponding event is -+enabled. Mask does not affect setting of the Interrupt Cause register bits; -+it only affects the assertion of the interrupt .*/ -+ -+ -+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction -+ while master is disabled */ -+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to -+ PCI Express internal register*/ -+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ -+ -+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -+#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -+#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -+#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -+#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ -+ -+ -+/********************************************/ -+/* PCI Express Control and Status Registers */ -+/********************************************/ -+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) -+ -+ -+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -+/* PCI Express Control Register */ -+/* PEX_CTRL_REG (PXCR) */ -+ -+#define PXCR_CONF_LINK_OFFS 0 -+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -+#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable */ -+ -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable*/ -+ -+#define PXCR_RSRV1_OFFS 5 -+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) -+ -+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) -+ -+ -+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) -+ -+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ -+ -+/* PCI Express Status Register */ -+/* PEX_STATUS_REG (PXSR) */ -+ -+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ -+ -+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) -+ -+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -+ -+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ -+ -+ -+/* PCI Express Completion Timeout Register */ -+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ -+ -+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) -+ -+/* PCI Express Power Management Extended Register */ -+/* PEX_PWR_MNG_EXT_REG (PXPMER) */ -+ -+#define PXPMER_L1_ASPM_EN_OFFS 1 -+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) -+ -+/* PCI Express Flow Control Register */ -+/* PEX_FLOW_CTRL_REG (PXFCR)*/ -+ -+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit -+ Initial Value.*/ -+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) -+ -+ -+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers -+ Flow Control Credit Initial Value*/ -+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) -+ -+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control -+ Credit Initial Value Infinite*/ -+ -+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) -+ -+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) -+ -+/* PCI Express Acknowledge Timers (4X) Register */ -+/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+/* PCI Express Acknowledge Timers (1X) Register */ -+/* PEX_ACK_TMR_1X_REG (PXAT1R) */ -+ -+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout -+ Value for 1X Link*/ -+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) -+ -+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout -+ Value for 1X*/ -+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+ -+/* PCI Express TL Control Register */ -+/* PEX_TL_CTRL_REG (PXTCR) */ -+ -+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) -+ -+/* PCI Express Debug MAC Control Register */ -+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ -+ -+#define PXDMCR_LINKUP BIT4 -+ -+ -+ -+/**********************************************/ -+/* PCI Express Configuration Header Registers */ -+/**********************************************/ -+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) -+ -+#define PEX_DEVICE_AND_VENDOR_ID 0x000 -+#define PEX_STATUS_AND_COMMAND 0x004 -+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -+#define PEX_BAR0_INTER_REG 0x010 -+#define PEX_BAR0_INTER_REG_HIGH 0x014 -+#define PEX_BAR1_REG 0x018 -+#define PEX_BAR1_REG_HIGH 0x01C -+#define PEX_BAR2_REG 0x020 -+#define PEX_BAR2_REG_HIGH 0x024 -+ -+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PEX_CAPABILTY_LIST_POINTER 0x034 -+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C -+ -+/* capability list */ -+#define PEX_POWER_MNG_CAPABILITY 0x040 -+#define PEX_POWER_MNG_STATUS_CONTROL 0x044 -+ -+#define PEX_MSI_MESSAGE_CONTROL 0x050 -+#define PEX_MSI_MESSAGE_ADDR 0x054 -+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -+#define PEX_MSI_MESSAGE_DATA 0x05C -+ -+#define PEX_CAPABILITY_REG 0x60 -+#define PEX_DEV_CAPABILITY_REG 0x64 -+#define PEX_DEV_CTRL_STAT_REG 0x68 -+#define PEX_LINK_CAPABILITY_REG 0x6C -+#define PEX_LINK_CTRL_STAT_REG 0x70 -+ -+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -+#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -+#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -+#define PEX_CORRECT_ERR_STAT_REG 0x110 -+#define PEX_CORRECT_ERR_MASK_REG 0x114 -+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 -+ -+ -+ -+/* PCI Express Device and Vendor ID Register*/ -+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ -+ -+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) -+ -+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) -+ -+ -+/* PCI Express Command and Status Register*/ -+/*PEX_STATUS_AND_COMMAND (PXSAC)*/ -+ -+#define PXSAC_IO_EN BIT0 /* IO Enable */ -+#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -+#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -+#define PXSAC_SYSERR BIT30 /* Signalled system error */ -+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+ -+/* PCI Express Class Code and Revision ID Register*/ -+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ -+ -+#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) -+ -+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) -+ -+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) -+ -+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) -+ -+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) -+ -+ -+/* PCI Express BIST, Header Type and Cache Line Size Register*/ -+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ -+ -+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) -+ -+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) -+ -+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) -+ -+ -+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) -+ -+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -+#define PXBHTLTCL_BISTCAP_OFFS 31 -+#define PXBHTLTCL_BISTCAP_MASK BIT31 -+#define PXBHTLTCL_BISTCAP_VAL 0 -+ -+ -+/* PCI Express Subsystem Device and Vendor ID */ -+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ -+ -+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) -+ -+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) -+ -+ -+/* PCI Express Capability List Pointer Register*/ -+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ -+ -+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) -+ -+/* PCI Express Interrupt Pin and Line Register */ -+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ -+ -+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) -+ -+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) -+ -+ -+/* PCI Express Power Management Capability Header Register*/ -+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ -+ -+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) -+ -+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) -+ -+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) -+ -+#define PXPMC_DSI BIT21/* Device Specific Initialization */ -+ -+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) -+ -+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ -+ -+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ -+ -+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) -+ -+/* PCI Express Power Management Control and Status Register*/ -+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ -+ -+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) -+ -+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ -+ -+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) -+ -+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) -+ -+#define PXPMSC_PME_STAT BIT15/* PME Status */ -+ -+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) -+ -+ -+/* PCI Express MSI Message Control Register*/ -+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ -+ -+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) -+ -+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) -+ -+#define PXMMC_MSI_EN BIT18 /* MSI Enable */ -+ -+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) -+ -+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) -+ -+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ -+ -+ -+/* PCI Express MSI Message Address Register*/ -+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ -+ -+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to -+ Address[31:2] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) -+ -+ -+/* PCI Express MSI Message Address (High) Register */ -+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ -+ -+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to -+ Address[63:32] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) -+ -+ -+/* PCI Express MSI Message Data Register*/ -+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ -+ -+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) -+ -+ -+/* PCI Express Capability Register*/ -+/*PEX_CAPABILITY_REG (PXCR)*/ -+ -+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) -+ -+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) -+ -+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) -+ -+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) -+ -+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ -+ -+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) -+ -+ -+/* PCI Express Device Capabilities Register */ -+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ -+ -+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) -+ -+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+ -+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+ -+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -+#define PXDCR_ATT_BUT_PRS_MASK BIT12 -+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 -+ -+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -+#define PXDCR_ATT_IND_PRS_MASK BIT13 -+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 -+ -+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -+#define PXDCR_PWR_IND_PRS_MASK BIT14 -+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 -+ -+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit -+ Value*/ -+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) -+ -+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit -+ Scale */ -+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) -+ -+/* PCI Express Device Control Status Register */ -+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ -+ -+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) -+ Reporting Enable*/ -+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ -+ -+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ -+ -+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+ -+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ -+ -+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -+#define PXDCSR_TRANS_PEND_MASK BIT21 -+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) -+ -+ -+/* PCI Express Link Capabilities Register*/ -+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ -+ -+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) -+ -+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) -+ -+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) -+ -+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) -+ -+/* PCI Express Link Control Status Register */ -+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ -+ -+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) -+ -+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -+#define PXLCSR_RCB_MASK BIT3 -+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) -+ -+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ -+ -+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) -+ -+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) -+ -+#define PXLCSR_LNK_TRN BIT27 /* Link Training */ -+ -+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -+#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) -+ -+/* PCI Express Advanced Error Report Header Register */ -+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ -+ -+/* PCI Express Uncorrectable Error Status Register*/ -+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ -+ -+/* PCI Express Uncorrectable Error Mask Register */ -+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ -+ -+/* PCI Express Uncorrectable Error Severity Register */ -+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ -+ -+/* PCI Express Correctable Error Status Register */ -+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ -+ -+/* PCI Express Correctable Error Mask Register */ -+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ -+ -+/* PCI Express Advanced Error Capability and Control Register*/ -+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ -+ -+/* PCI Express Header Log First DWORD Register*/ -+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ -+ -+/* PCI Express Header Log Second DWORD Register*/ -+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ -+ -+/* PCI Express Header Log Third DWORD Register*/ -+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ -+ -+/* PCI Express Header Log Fourth DWORD Register*/ -+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* #ifndef __INCPEXREGSH */ -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c -new file mode 100644 -index 0000000..59d0383 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c -@@ -0,0 +1,313 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPex.h" -+ -+//#define MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+typedef struct -+{ -+ MV_U32 data; -+ MV_U32 mask; -+}PEX_HEADER_DATA; -+ -+/* local function forwad decleration */ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff); -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); -+ -+ -+PEX_HEADER_DATA configHdr[16] = -+{ -+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ -+{0x00100007, 0x0000ffff}, /*[status register, command register] */ -+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ -+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ -+{0x00000000, 0x00000000}, /*[base address 0] */ -+{0x00000000, 0x00000000}, /*[base address 1] */ -+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ -+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ -+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ -+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ -+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ -+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ -+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ -+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ -+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ -+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ -+}; -+ -+ -+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ -+ (data & configHdr[offset/4].mask)) -+#define HEADER_READ(offset) configHdr[offset/4].data -+ -+/******************************************************************************* -+* mvVrtBrgPexInit - Initialize PEX interfaces -+* -+* DESCRIPTION: -+* -+* This function is responsible of intialization of the Pex Interface , It -+* configure the Pex Bars and Windows in the following manner: -+* -+* Assumptions : -+* Bar0 is always internal registers bar -+* Bar1 is always the DRAM bar -+* Bar2 is always the Device bar -+* -+* 1) Sets the Internal registers bar base by obtaining the base from -+* the CPU Interface -+* 2) Sets the DRAM bar base and size by getting the base and size from -+* the CPU Interface when the size is the sum of all enabled DRAM -+* chip selects and the base is the base of CS0 . -+* 3) Sets the Device bar base and size by getting these values from the -+* CPU Interface when the base is the base of the lowest base of the -+* Device chip selects, and the -+* -+* -+* INPUT: -+* -+* pexIf - PEX interface number. -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) -+{ -+ /* reset PEX tree to recover previous U-boot/Boot configurations */ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ resetPexConfig(pexIf, localBus, 1); -+ return MV_OK; -+} -+ -+ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_U32 val; -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+/* on the local device allow only device #0 & #1 */ -+ return 0xffffffff; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ return HEADER_READ(regOff); -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return 0xffffffff; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+} -+ -+ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_STATUS status; -+ -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+ /* on the local device allow only device #0 & #1 */ -+ return MV_ERROR; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ HEADER_WRITE(data, regOff); -+ return MV_OK; -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+ -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+} -+ -+ -+ -+ -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) -+{ -+ MV_U32 tData; -+ MV_U32 i; -+ -+ /* restore the PEX configuration to initialization state */ -+ /* in case PEX P2P call recursive and reset config */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); -+ if(tData != 0xffffffff) -+ { -+ /* agent had been found - check whether P2P */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); -+ if((tData & 0xffff0000) == 0x06040000) -+ {/* P2P */ -+ /* get the sec bus and the subordinate */ -+ MV_U32 secBus; -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); -+ secBus = ((tData >> 8) & 0xff); -+ /* now scan on sec bus */ -+ for(i = 0;i < 0xff;i++) -+ { -+ resetPexConfig(pexIf, secBus, i); -+ } -+ /* now reset this device */ -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ } -+ } -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h -new file mode 100644 -index 0000000..0741713 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCVRTBRGPEXH -+#define __INCVRTBRGPEXH -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+ -+#endif /* #ifndef __INCPEXH */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c b/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c -new file mode 100644 -index 0000000..2643699 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c -@@ -0,0 +1,1522 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvOs.h" -+#include "sflash/mvSFlash.h" -+#include "sflash/mvSFlashSpec.h" -+#include "spi/mvSpi.h" -+#include "spi/mvSpiCmnd.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* Globals */ -+static MV_SFLASH_DEVICE_PARAMS sflash[] = { -+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P32_SECTOR_SIZE, -+ MV_M25P32_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P32", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P32_DEVICE_ID, -+ MV_M25P32_MAX_SPI_FREQ, -+ MV_M25P32_MAX_FAST_SPI_FREQ, -+ MV_M25P32_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P64_SECTOR_SIZE, -+ MV_M25P64_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P64", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P64_DEVICE_ID, -+ MV_M25P64_MAX_SPI_FREQ, -+ MV_M25P64_MAX_FAST_SPI_FREQ, -+ MV_M25P64_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P128_SECTOR_SIZE, -+ MV_M25P128_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P128", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P128_DEVICE_ID, -+ MV_M25P128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ }, -+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_MX25L_WREN_CMND_OPCD, -+ MV_MX25L_WRDI_CMND_OPCD, -+ MV_MX25L_RDID_CMND_OPCD, -+ MV_MX25L_RDSR_CMND_OPCD, -+ MV_MX25L_WRSR_CMND_OPCD, -+ MV_MX25L_READ_CMND_OPCD, -+ MV_MX25L_FAST_RD_CMND_OPCD, -+ MV_MX25L_PP_CMND_OPCD, -+ MV_MX25L_SE_CMND_OPCD, -+ MV_MX25L_BE_CMND_OPCD, -+ MV_MX25L_RES_CMND_OPCD, -+ MV_MX25L_DP_CMND_OPCD, -+ MV_MX25L6405_SECTOR_SIZE, -+ MV_MX25L6405_SECTOR_NUMBER, -+ MV_MXIC_PAGE_SIZE, -+ "MXIC MX25L6405", -+ MV_MXIC_MANF_ID, -+ MV_MX25L6405_DEVICE_ID, -+ MV_MX25L6405_MAX_SPI_FREQ, -+ MV_MX25L6405_MAX_FAST_SPI_FREQ, -+ MV_MX25L6405_FAST_READ_DUMMY_BYTES -+ }, -+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_S25FL_WREN_CMND_OPCD, -+ MV_S25FL_WRDI_CMND_OPCD, -+ MV_S25FL_RDID_CMND_OPCD, -+ MV_S25FL_RDSR_CMND_OPCD, -+ MV_S25FL_WRSR_CMND_OPCD, -+ MV_S25FL_READ_CMND_OPCD, -+ MV_S25FL_FAST_RD_CMND_OPCD, -+ MV_S25FL_PP_CMND_OPCD, -+ MV_S25FL_SE_CMND_OPCD, -+ MV_S25FL_BE_CMND_OPCD, -+ MV_S25FL_RES_CMND_OPCD, -+ MV_S25FL_DP_CMND_OPCD, -+ MV_S25FL128_SECTOR_SIZE, -+ MV_S25FL128_SECTOR_NUMBER, -+ MV_S25FL_PAGE_SIZE, -+ "SPANSION S25FL128", -+ MV_SPANSION_MANF_ID, -+ MV_S25FL128_DEVICE_ID, -+ MV_S25FL128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ } -+}; -+ -+/* Static Functions */ -+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); -+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ -+ MV_U8* pPageBuff, MV_U32 buffSize); -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ -+ MV_U8* manId, MV_U16* devId); -+ -+/******************************************************************************* -+* mvWriteEnable - serialize the write enable sequence -+* -+* DESCRIPTION: -+* transmit the sequence for write enable -+* -+********************************************************************************/ -+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdWREN; -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); -+} -+ -+/******************************************************************************* -+* mvStatusRegGet - Retrieve the value of the status register -+* -+* DESCRIPTION: -+* perform the RDSR sequence to get the 8bit status register -+* -+********************************************************************************/ -+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; -+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; -+ -+ -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRDSR; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, -+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) -+ return ret; -+ -+ *pStatReg = sr[0]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared -+* -+* DESCRIPTION: -+* Block waiting for the WIP (write in progress) to be cleared -+* -+********************************************************************************/ -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U32 i; -+ MV_U8 stat; -+ -+ for (i=0; iindex].opcdWRSR; -+ cmd[1] = sr; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ mvOsDelay(1); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashPageWr - Write up to 256 Bytes in the same page -+* -+* DESCRIPTION: -+* Write a buffer up to the page size in length provided that the whole address -+* range is within the same page (alligned to page bounderies) -+* -+*******************************************************************************/ -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pPageBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; -+ -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that we do not cross the page bounderies */ -+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > -+ sflash[pFlinfo->index].pageSize) -+ { -+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* Issue the Write enable command prior the page program command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPP; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from -+* the device using the default RDID opcode and the default WREN opcode. -+* -+* DESCRIPTION: -+* This is used to detect a generic device that uses the default opcodes -+* for the WREN and RDID. -+* -+********************************************************************************/ -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* Use the default RDID opcode to read the IDs */ -+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ -+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *manId = id[0]; -+ *devId = 0; -+ *devId |= (id[1] << 8); -+ *devId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/* -+##################################################################################### -+##################################################################################### -+*/ -+ -+/******************************************************************************* -+* mvSFlashInit - Initialize the serial flash device -+* -+* DESCRIPTION: -+* Perform the neccessary initialization and configuration -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pFlinfo->baseAddr: base address in fast mode. -+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI -+* flash device does not support read Id command with -+* the standard opcode, then the user should supply this -+* as an input to skip the autodetection process!!!! -+* -+* OUTPUT: -+* pFlinfo: pointer to the Flash information structure after detection -+* pFlinfo->manufacturerId: Manufacturer ID -+* pFlinfo->deviceId: Device ID -+* pFlinfo->sectorSize: size of the sector (all sectors are the same). -+* pFlinfo->sectorNumber: number of sectors. -+* pFlinfo->pageSize: size of the page. -+* pFlinfo->index: Index of the detected flash in the sflash tabel -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 manf; -+ MV_U16 dev; -+ MV_U32 indx; -+ MV_BOOL detectFlag = MV_FALSE; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ -+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* First try to read the Manufacturer and Device IDs */ -+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* loop over the whole table and look for the appropriate SFLASH */ -+ for (indx=0; indxmanufacturerId = manf; -+ pFlinfo->deviceId = dev; -+ pFlinfo->index = indx; -+ detectFlag = MV_TRUE; -+ } -+ } -+ -+ if(!detectFlag) -+ { -+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); -+ return MV_FAIL; -+ } -+ -+ /* fill the info based on the model detected */ -+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; -+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; -+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; -+ -+ /* Set the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* As default lock the SR */ -+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashSectorErase - Erasse a single sector of the serial flash -+* -+* DESCRIPTION: -+* Issue the erase sector command and address -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* secNumber: sector Number to erase (0 -> (sectorNumber-1)) -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; -+ -+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); -+#if 0 -+ MV_U32 i; -+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); -+ MV_U32 erasedWord = 0xFFFFFFFF; -+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); -+ MV_BOOL eraseNeeded = MV_FALSE; -+#endif -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the sector number is valid */ -+ if (secNumber >= pFlinfo->sectorNumber) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* we don't want to access SPI in direct mode from in-direct API, -+ becasue of timing issue between CS asserts. */ -+#if 0 -+ /* First compare to FF and check if erase is needed */ -+ for (i=0; iindex].opcdSE; -+ cmd[1] = ((secAddr >> 16) & 0xFF); -+ cmd[2] = ((secAddr >> 8) & 0xFF); -+ cmd[3] = (secAddr & 0xFF); -+ -+ /* Issue the Write enable command prior the sector erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashChipErase - Erasse the whole serial flash -+* -+* DESCRIPTION: -+* Issue the bulk (chip) erase command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdBE; -+ -+ /* Issue the Write enable command prior the Bulk erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashBlockRd - Read from the serial flash -+* -+* DESCRIPTION: -+* Issue the read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdREAD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); -+} -+ -+/******************************************************************************* -+* mvSFlashFastBlockRd - Fast read from the serial flash -+* -+* DESCRIPTION: -+* Issue the fast read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ MV_STATUS ret; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set the SPI frequency to the MAX allowed for fast-read operations */ -+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ -+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, -+ sflash[pFlinfo->index].spiFastRdDummyBytes); -+ -+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+ -+/******************************************************************************* -+* mvSFlashBlockWr - Write a buffer with any size -+* -+* DESCRIPTION: -+* write regardless of the page boundaries and size limit per Page -+* program command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset within the flash region -+* pWriteBuff: pointer to the buffer holding the data to program -+* buffSize: size of the buffer to write -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 data2write = buffSize; -+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); -+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); -+ MV_U32 writeOffset = offset; -+ -+ /* check for NULL pointer */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pWriteBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the buffer size does not exceed the flash size */ -+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) -+ { -+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* check if the total block size is less than the first chunk remainder */ -+ if (data2write < preAllSz) -+ preAllSz = data2write; -+ -+ /* check if programing does not start at a 64byte alligned offset */ -+ if (preAllSz) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += preAllSz; -+ data2write -= preAllSz; -+ pWriteBuff += preAllSz; -+ } -+ -+ /* program the data that fits in complete page chunks */ -+ while (data2write >= sflash[pFlinfo->index].pageSize) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += sflash[pFlinfo->index].pageSize; -+ data2write -= sflash[pFlinfo->index].pageSize; -+ pWriteBuff += sflash[pFlinfo->index].pageSize; -+ } -+ -+ /* program the last partial chunk */ -+ if (data2write) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) -+ return ret; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashIdGet - Get the manufacturer and device IDs. -+* -+* DESCRIPTION: -+* Get the Manufacturer and device IDs from the serial flash through -+* writing the RDID command then reading 3 bytes of data. In case that -+* this command was called for the first time in order to detect the -+* manufacturer and device IDs, then the default RDID opcode will be used -+* unless the device index is indicated by the user (in case the SPI flash -+* does not use the default RDID opcode). -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pManId: pointer to the 8bit variable to hold the manufacturing ID -+* pDevId: pointer to the 16bit variable to hold the device ID -+* -+* OUTPUT: -+* pManId: pointer to the 8bit variable holding the manufacturing ID -+* pDevId: pointer to the 16bit variable holding the device ID -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); -+ else -+ cmd[0] = sflash[pFlinfo->index].opcdRDID; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *pManId = id[0]; -+ *pDevId = 0; -+ *pDevId |= (id[1] << 8); -+ *pDevId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionSet - Set the Write-Protected region -+* -+* DESCRIPTION: -+* Set the Write-Protected region -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* wpRegion: which region will be protected -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) -+{ -+ MV_U8 wpMask; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_M25P_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_M25P_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_M25P_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_M25P_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_M25P_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_M25P_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_M25P_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_M25P_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_MX25L_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_128; -+ break; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_MX25L_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is SPANSION then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_S25FL_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_S25FL_STATUS_BP_ALL; -+ break; -+ -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Verify that the SRWD bit is always set - register is s/w locked */ -+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, wpMask); -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionGet - Get the Write-Protected region configured -+* -+* DESCRIPTION: -+* Get from the chip the Write-Protected region configured -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pWpRegion: pointer to the variable to return the WP region in -+* -+* OUTPUT: -+* wpRegion: pointer to the variable holding the WP region configured -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pWpRegion == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) -+ { -+ case MV_M25P_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_M25P_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) -+ { -+ case MV_MX25L_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_128: -+ *pWpRegion = MV_WP_UPR_1OF128; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_MX25L_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) -+ { -+ case MV_S25FL_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_S25FL_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp -+* pin should be low to take effect -+* -+* DESCRIPTION: -+* Lock the access to the Status Register for writing. This will -+* cause the flash to enter the hardware protection mode if the W/Vpp -+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but -+* the register will continue to be writable if WREN sequence was used. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ if (srLock) -+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ else -+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, reg); -+} -+ -+/******************************************************************************* -+* mvSFlashSizeGet - Get the size of the SPI flash -+* -+* DESCRIPTION: -+* based on the sector number and size of each sector calculate the total -+* size of the flash memory. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode -+* -+* DESCRIPTION: -+* Enter a special power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode -+* -+* DESCRIPTION: -+* Exit the deep power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRES; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ /* add the delay needed for the device to wake up */ -+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashModelGet - Retreive the string with the device manufacturer and model -+* -+* DESCRIPTION: -+* Retreive the string with the device manufacturer and model -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string indicating the device manufacturer and model -+* -+* -+*******************************************************************************/ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return unknModel; -+ } -+ -+ return sflash[pFlinfo->index].deviceModel; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h b/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h -new file mode 100644 -index 0000000..5bb160b ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h -@@ -0,0 +1,166 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashH -+#define __INCmvSFlashH -+ -+#include "mvTypes.h" -+ -+/* MCAROS */ -+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) -+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) -+ -+/* Constants */ -+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF -+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ -+#define MV_SFLASH_BASIC_SPI_FREQ 10000000 -+/* enumerations */ -+typedef enum -+{ -+ MV_WP_NONE, /* Unprotect the whole chip */ -+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ -+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ -+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ -+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ -+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ -+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ -+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ -+ MV_WP_ALL /* Write protect the whole chip */ -+} MV_SFLASH_WP_REGION; -+ -+/* Type Definitions */ -+typedef struct -+{ -+ MV_U8 opcdWREN; /* Write enable opcode */ -+ MV_U8 opcdWRDI; /* Write disable opcode */ -+ MV_U8 opcdRDID; /* Read ID opcode */ -+ MV_U8 opcdRDSR; /* Read Status Register opcode */ -+ MV_U8 opcdWRSR; /* Write Status register opcode */ -+ MV_U8 opcdREAD; /* Read opcode */ -+ MV_U8 opcdFSTRD; /* Fast Read opcode */ -+ MV_U8 opcdPP; /* Page program opcode */ -+ MV_U8 opcdSE; /* Sector erase opcode */ -+ MV_U8 opcdBE; /* Bulk erase opcode */ -+ MV_U8 opcdRES; /* Read electronic signature */ -+ MV_U8 opcdPwrSave; /* Go into power save mode */ -+ MV_U32 sectorSize; /* Size of each sector */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* size of each page */ -+ const char * deviceModel; /* string with the device model */ -+ MV_U32 manufacturerId; /* The manufacturer ID */ -+ MV_U32 deviceId; /* Device ID */ -+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ -+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ -+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ -+} MV_SFLASH_DEVICE_PARAMS; -+ -+typedef struct -+{ -+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ -+ MV_U8 manufacturerId; /* Manufacturer ID */ -+ MV_U16 deviceId; /* Device ID */ -+ MV_U32 sectorSize; /* Size of each sector - all the same */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* Page size - affect allignment */ -+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ -+} MV_SFLASH_INFO; -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); -+ -+/* erase */ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); -+ -+/* Read */ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+ -+/* write regardless of the page boundaries and size limit per Page program command */ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize); -+/* Get IDs */ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); -+ -+/* Set and Get the Write Protection region - if the Status register is not locked */ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); -+ -+/* Lock the status register for writing - W/Vpp pin should be low to take effect */ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); -+ -+/* Get the regions sizes */ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); -+ -+/* Cause the falsh device to go into power save mode */ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); -+ -+/* Retreive the string with the device manufacturer and model */ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); -+ -+#endif /* __INCmvSFlashH */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h b/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h -new file mode 100644 -index 0000000..cef4255 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h -@@ -0,0 +1,233 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashSpecH -+#define __INCmvSFlashSpecH -+ -+/* Constants */ -+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ -+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ -+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ -+ -+/* Status Register Bit Masks */ -+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ -+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ -+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ -+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) -+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) -+ -+#define MV_SFLASH_MAX_WAIT_LOOP 1000000 -+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 -+ -+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 -+ -+/********************************/ -+/* ST M25Pxxx Device Specific */ -+/********************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_M25PXXX_ST_MANF_ID 0x20 -+#define MV_M25P32_DEVICE_ID 0x2016 -+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P64_DEVICE_ID 0x2017 -+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P128_DEVICE_ID 0x2018 -+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 -+ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_M25P32_SECTOR_NUMBER 64 -+#define MV_M25P64_SECTOR_NUMBER 128 -+#define MV_M25P128_SECTOR_NUMBER 64 -+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 3bits */ -+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* MXIC MX25L6405 Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_MXIC_MANF_ID 0xC2 -+#define MV_MX25L6405_DEVICE_ID 0x2017 -+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 -+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_MX25L6405_SECTOR_NUMBER 128 -+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* SPANSION S25FL128P Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_SPANSION_MANF_ID 0x01 -+#define MV_S25FL128_DEVICE_ID 0x2018 -+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 -+ -+/* Sector Sizes and population per device model*/ -+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_S25FL128_SECTOR_NUMBER 64 -+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+#endif /* __INCmvSFlashSpecH */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c -new file mode 100644 -index 0000000..efdd6ae ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c -@@ -0,0 +1,576 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#define mvOsPrintf printf -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpi16bitDataTxRx - Transmt and receive data -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i> 8) & 0xFF); -+ -+#elif defined(MV_CPU_BE) -+ -+ /* perform the data write to the buffer in two stages with 8bit each */ -+ MV_U8 * bptr = (MV_U8 *)pRxData; -+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ *bptr = ((data >> 8) & 0xFF); -+ ++bptr; -+ *bptr = (data & 0xFF); -+ -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ } -+ else -+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpi8bitDataTxRx - Transmt and receive data (8bits) -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i serialBaudRate) -+ continue; -+ -+ /* check for exact fit */ -+ if ((cpuClk / preScale[i]) == serialBaudRate) -+ { -+ bestPrescaleIndx = i; -+ break; -+ } -+ -+ /* check if this is better than the previous one */ -+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) -+ { -+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); -+ bestPrescaleIndx = i; -+ } -+ } -+ -+ if (bestPrescaleIndx > 14) -+ { -+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* configure the Prescale */ -+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); -+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); -+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer -+* -+* DESCRIPTION: -+* Assert The chip select - used to select an external SPI device -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsAssert(MV_VOID) -+{ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToSPI(); -+ mvOsUDelay(1); -+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+} -+ -+/******************************************************************************* -+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a -+* SPI transfer sequence -+* -+* DESCRIPTION: -+* DeAssert the chip select pin -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsDeassert(MV_VOID) -+{ -+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToDefault(); -+} -+ -+/******************************************************************************* -+* mvSpiRead - Read a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. Chip select is not -+* handled at this level. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to hold the received data -+* buffSize: length of the pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer to the buffer with the received data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if (pRxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) -+ return ret; -+ /* increment the pointers */ -+ pRxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiWrite - Transmit a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Transmit a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. No chip select -+* action is taken. -+* -+* INPUT: -+* pTxBuff: Pointer to the buffer holding the TX data -+* buffSize: length of the pTxBuff -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ -+ /* check for null parameters */ -+ if (pTxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpiReadWrite - Read and Write a buffer simultanuosely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. The SPI chip -+* select is not handled implicitely. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) -+ return ret; -+ pRxBuff++; -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h -new file mode 100644 -index 0000000..c3db297 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h -@@ -0,0 +1,94 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpihH -+#define __INCmvSpihH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSpiInit (MV_U32 serialBaudRate); -+ -+/* Set the Frequency of the Spi clock */ -+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); -+ -+/* Assert the SPI chip select */ -+MV_VOID mvSpiCsAssert (MV_VOID); -+ -+/* De-assert the SPI chip select */ -+MV_VOID mvSpiCsDeassert (MV_VOID); -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* serialize a buffer on the TX line - Rx is ignored */ -+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* read from the RX line by writing dummy values to the TX line */ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); -+ -+#endif /* __INCmvSpihH */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c -new file mode 100644 -index 0000000..a5d5a64 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c -@@ -0,0 +1,249 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer followed by -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pTxDataBuff: Pointer to the data buffer to transmit -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, -+ MV_U32 txDataSize) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ -+ /* check for null parameters */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pTxDataBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pCmndBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Then write the data buffer */ -+#ifndef CONFIG_MARVELL -+ if (txDataSize) -+#else -+ if ((txDataSize) && (pTxDataBuff != NULL)) -+#endif -+ { -+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenRead - Serialize a command then read a data buffer -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer then read -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pRxDataBuff: Pointer to the buffer to read the data in -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* pRxDataBuff: Pointer to the buffer holding the data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ MV_U8 dummyByte; -+ -+ /* check for null parameters */ -+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Read dummy bytes before real data. */ -+ while(dummyBytesToRead) -+ { -+ mvSpiRead(&dummyByte,1); -+ dummyBytesToRead--; -+ } -+ -+ /* Then write the data buffer */ -+ if ((rxDataSize) && (pRxDataBuff != NULL)) -+ { -+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h -new file mode 100644 -index 0000000..329e26b ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiCmndhH -+#define __INCmvSpiCmndhH -+ -+#include "mvTypes.h" -+ -+/* Function Prototypes */ -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* write command - write a command and then write data */ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); -+ -+/* read command - write a command and then read data by writing dummy data */ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); -+ -+#endif /* __INCmvSpiCmndhH */ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h -new file mode 100644 -index 0000000..e943787 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiSpecH -+#define __INCmvSpiSpecH -+ -+/* Constants */ -+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 -+#define MV_SPI_16_BIT_CHUNK_SIZE 2 -+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF -+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF -+ -+/* Marvell Flash Device Controller Registers */ -+#define MV_SPI_CTRLR_OFST 0x10600 -+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) -+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) -+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) -+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) -+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) -+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) -+ -+/* Serial Memory Interface Control Register Masks */ -+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ -+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ -+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) -+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) -+ -+/* Serial Memory Interface Configuration Register Masks */ -+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ -+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ -+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ -+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) -+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) -+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) -+ -+#endif /* __INCmvSpiSpecH */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c b/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c -new file mode 100644 -index 0000000..12d27b3 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c -@@ -0,0 +1,1023 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTwsi.h" -+#include "mvTwsiSpec.h" -+#include "cpu/mvCpu.h" -+ -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum); -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum); -+static MV_VOID twsiAckBitSet(MV_U8 chanNum); -+static MV_U32 twsiStsGet(MV_U8 chanNum); -+static MV_VOID twsiReset(MV_U8 chanNum); -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); -+ -+ -+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) -+{ -+ if(timeout >= TWSI_TIMEOUT_VALUE) -+ { -+ DB(mvOsPrintf("%s",pString)); -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+ -+} -+/******************************************************************************* -+* mvTwsiStartBitSet - Set start bit on the bus -+* -+* DESCRIPTION: -+* This routine sets the start bit on the TWSI bus. -+* The routine first checks for interrupt flag condition, then it sets -+* the start bit in the TWSI Control register. -+* If the interrupt flag condition check previously was set, the function -+* will clear it. -+* The function then wait for the start bit to be cleared by the HW. -+* Then it waits for the interrupt flag to be set and eventually, the -+* TWSI status is checked to be 0x8 or 0x10(repeated start bit). -+* -+* INPUT: -+* chanNum - TWSI channel. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK is start bit was set successfuly on the bus. -+* MV_FAIL if interrupt flag was set before setting start bit. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) -+{ -+ MV_BOOL isIntFlag = MV_FALSE; -+ MV_U32 timeout, temp; -+ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); -+ /* check Int flag */ -+ if(twsiMainIntGet(chanNum)) -+ isIntFlag = MV_TRUE; -+ /* set start Bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); -+ -+ /* in case that the int flag was set before i.e. repeated start bit */ -+ if(isIntFlag){ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); -+ twsiIntFlgClr(chanNum); -+ } -+ -+ /* wait for interrupt */ -+ timeout = 0; -+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ -+ /* check that start bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvTwsiStopBitSet - Set stop bit on the bus -+* -+* DESCRIPTION: -+* This routine set the stop bit on the TWSI bus. -+* The function then wait for the stop bit to be cleared by the HW. -+* Finally the function checks for status of 0xF8. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is stop bit was set successfuly on the bus. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) -+{ -+ MV_U32 timeout, temp; -+ -+ /* Generate stop bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for stop bit to come down */ -+ timeout = 0; -+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ /* check that the stop bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiMainIntGet - Get twsi bit from main Interrupt cause. -+* -+* DESCRIPTION: -+* This routine returns the twsi interrupt flag value. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* get the int flag bit */ -+ -+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); -+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* twsiIntFlgClr - Clear Interrupt flag. -+* -+* DESCRIPTION: -+* This routine clears the interrupt flag. It does NOT poll the interrupt -+* to make sure the clear. After clearing the interrupt, it waits for at -+* least 1 miliseconds. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* wait for 1 mili to prevent TWSI register write after write problems */ -+ mvOsDelay(1); -+ /* clear the int flag bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); -+ -+ /* wait for 1 mili sec for the clear to take effect */ -+ mvOsDelay(1); -+ -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiAckBitSet - Set acknowledge bit on the bus -+* -+* DESCRIPTION: -+* This routine set the acknowledge bit on the TWSI bus. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiAckBitSet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /*Set the Ack bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); -+ -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* This routine: -+* -Reset the TWSI. -+* -Initialize the TWSI clock baud rate according to given frequancy -+* parameter based on Tclk frequancy and enables TWSI slave. -+* -Set the ack bit. -+* -Assign the TWSI slave address according to the TWSI address Type. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* frequancy - TWSI frequancy in KHz. (up to 100KHZ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Actual frequancy. -+* -+*******************************************************************************/ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) -+{ -+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; -+ MV_U32 power; -+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; -+ -+ if(frequancy > 100000) -+ { -+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); -+ /* Calucalte N and M for the TWSI clock baud rate */ -+ for(n = 0 ; n < 8 ; n++) -+ { -+ for(m = 0 ; m < 16 ; m++) -+ { -+ power = 2 << n; /* power = 2^(n+1) */ -+ freq = Tclk/(10*(m+1)*power); -+ margin = MV_ABS(frequancy - freq); -+ if(margin < minMargin) -+ { -+ minMargin = margin; -+ actualFreq = freq; -+ actualN = n; -+ actualM = m; -+ } -+ } -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); -+ /* Reset the TWSI logic */ -+ twsiReset(chanNum); -+ -+ /* Set the baud rate */ -+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); -+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); -+ -+ /* Enable the TWSI and slave */ -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); -+ -+ /* set the TWSI slave address */ -+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ -+ { -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_SLAVE_ADDR_10BIT_CONST; -+ /* set GCE bit */ -+ if(generalCallEnable) -+ val |= TWSI_SLAVE_ADDR_GCE_ENA; -+ /* write slave address */ -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); -+ -+ /* writing the 8 least significant bits of the 10 bit address*/ -+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); -+ } -+ else /*7 bit address*/ -+ { -+ /* set the 7 Bits address */ -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); -+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); -+ } -+ -+ /* unmask twsi int */ -+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ -+ return actualFreq; -+} -+ -+ -+/******************************************************************************* -+* twsiStsGet - Get the TWSI status value. -+* -+* DESCRIPTION: -+* This routine returns the TWSI status value. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - the TWSI status. -+* -+*******************************************************************************/ -+static MV_U32 twsiStsGet(MV_U8 chanNum) -+{ -+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); -+ -+} -+ -+/******************************************************************************* -+* twsiReset - Reset the TWSI. -+* -+* DESCRIPTION: -+* Resets the TWSI logic and sets all TWSI registers to their reset values. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+static MV_VOID twsiReset(MV_U8 chanNum) -+{ -+ /* Reset the TWSI logic */ -+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); -+ -+ /* wait for 2 mili sec */ -+ mvOsDelay(2); -+ -+ return; -+} -+ -+ -+ -+ -+/******************************* POLICY ****************************************/ -+ -+ -+ -+/******************************************************************************* -+* mvTwsiAddrSet - Set address on TWSI bus. -+* -+* DESCRIPTION: -+* This function Set address (7 or 10 Bit address) on the Twsi Bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiAddr - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) -+{ -+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ -+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ /* 10 Bit address */ -+ if(pTwsiAddr->type == ADDR10_BIT) -+ { -+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ /* 7 Bit address */ -+ else -+ { -+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ -+} -+ -+/******************************************************************************* -+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* There are two address phases: -+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB -+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit -+* to the Data register. Then it clears interrupt flag which drive -+* the address on the TWSI bus. The function then waits for interrupt -+* flag to be active and status 0x18 (write) or 0x40 (read) to be set. -+* 2) write the rest of 10-bit address to data register and clears -+* interrupt flag which drive the address on the TWSI bus. The -+* function then waits for interrupt flag to be active and status -+* 0xD0 (write) or 0xE0 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_DATA_ADDR_10BIT_CONST; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ /* set 8 LSB of the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* This function writes 7 bit address plus a write or read bit to the -+* Data register. Then it clears interrupt flag which drive the address on -+* the TWSI bus. The function then waits for interrupt flag to be active -+* and status 0x18 (write) or 0x40 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* set the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't -+ want error messeges in case DIMM doesn't exist. */ -+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ -+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataWrite - Trnasmit a data block over TWSI bus. -+* -+* DESCRIPTION: -+* This function writes a given data block to TWSI bus in 8 bit granularity. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* The function writes data to data register. It then clears -+* interrupt flag which drives the data on the TWSI bus. -+* The function then waits for interrupt flag to be active and status -+* 0x28 to be set. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* pBlock - Data block. -+* blockSize - number of chars in pBlock. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if transmiting the block completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeWr = blockSize; -+ -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeWr) -+ { -+ /* write the data*/ -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); -+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ -+ blockSize - blockSizeWr, *pBlock)); -+ pBlock++; -+ blockSizeWr--; -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) -+ { -+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); -+ return MV_FAIL; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataReceive - Receive data block from TWSI bus. -+* -+* DESCRIPTION: -+* This function receive data block from TWSI bus in 8bit granularity -+* into pBlock buffer. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* It clears the interrupt flag which allows the next data to be -+* received from TWSI bus. -+* The function waits for interrupt flag to be active, -+* and status reg is 0x50. -+* Then the function reads data from data register, and copies it to -+* the given buffer. -+* -+* INPUT: -+* chanNum - TWSI channel -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if receive transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeRd = blockSize; -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeRd) -+ { -+ if(blockSizeRd == 1) -+ { -+ /* clear ack and Int flag */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ temp &= ~(TWSI_CONTROL_ACK); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); -+ } -+ twsiIntFlgClr(chanNum); -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); -+ return MV_FAIL; -+ } -+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); -+ return MV_FAIL; -+ } -+ -+ /* read the data*/ -+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); -+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ -+ blockSize - blockSizeRd,*pBlock)); -+ pBlock++; -+ blockSizeRd--; -+ } -+ -+ return MV_OK; -+} -+ -+ -+ -+/******************************************************************************* -+* twsiTargetOffsSet - Set TWST target offset on TWSI bus. -+* -+* DESCRIPTION: -+* The function support TWSI targets that have inside address space (for -+* example EEPROMs). The function: -+* 1) Convert the given offset into pBlock and size. -+* in case the offset should be set to a TWSI slave which support -+* more then 256 bytes offset, the offset setting will be done -+* in 2 transactions. -+* 2) Use twsiDataTransmit to place those on the bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* offset - offset to be set on the EEPROM device. -+* moreThen256 - whether the EEPROM device support more then 256 byte offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the offset completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) -+{ -+ MV_U8 offBlock[2]; -+ MV_U32 offSize; -+ -+ if(moreThen256 == MV_TRUE) -+ { -+ offBlock[0] = (offset >> 8) & 0xff; -+ offBlock[1] = offset & 0xff; -+ offSize = 2; -+ } -+ else -+ { -+ offBlock[0] = offset & 0xff; -+ offSize = 1; -+ } -+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ -+ offSize,offBlock[0],offBlock[1])); -+ return twsiDataTransmit(chanNum, offBlock, offSize); -+ -+} -+ -+/******************************************************************************* -+* mvTwsiRead - Read data block from a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* if(EEPROM device) -+* -) mvTwsiAddrSet(w); -+* -) twsiTargetOffsSet(); -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(r); -+* -) twsiDataReceive(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiSlave - Twsi Slave structure. -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ } -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); -+ -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ -+ twsiAckBitSet(chanNum); -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTwsiWrite - Write data block to a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(); -+* -)if(EEPROM device) -+* -) twsiTargetOffsSet(); -+* -) twsiDataTransmit(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* eepromAddress - eeprom address. -+* blockSize - number of bytes to write. -+* pBlock - Data block. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully. -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+* NOTE: Part of the EEPROM, required that the offset will be aligned to the -+* max write burst supported. -+*******************************************************************************/ -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); -+ } -+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h b/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h -new file mode 100644 -index 0000000..c3eddd1 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvTwsiH -+#define __INCmvTwsiH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* need to update this includes */ -+#include "twsi/mvTwsiSpec.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+ -+/* The TWSI interface supports both 7-bit and 10-bit addressing. */ -+/* This enumerator describes addressing type. */ -+typedef enum _mvTwsiAddrType -+{ -+ ADDR7_BIT, /* 7 bit address */ -+ ADDR10_BIT /* 10 bit address */ -+}MV_TWSI_ADDR_TYPE; -+ -+/* This structure describes TWSI address. */ -+typedef struct _mvTwsiAddr -+{ -+ MV_U32 address; /* address */ -+ MV_TWSI_ADDR_TYPE type; /* Address type */ -+}MV_TWSI_ADDR; -+ -+/* This structure describes a TWSI slave. */ -+typedef struct _mvTwsiSlave -+{ -+ MV_TWSI_ADDR slaveAddr; -+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ -+ MV_U32 offset; /* offset in the slave. */ -+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ -+}MV_TWSI_SLAVE; -+ -+/* This enumerator describes TWSI protocol commands. */ -+typedef enum _mvTwsiCmd -+{ -+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ -+ MV_TWSI_READ /* TWSI read command - 1 according to spec */ -+}MV_TWSI_CMD; -+ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); -+ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); -+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiH */ -+ -diff --git a/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h b/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h -new file mode 100644 -index 0000000..ebb6db7 ---- /dev/null -+++ b/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h -@@ -0,0 +1,160 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/****************************************/ -+/* TWSI Registers */ -+/****************************************/ -+#ifndef __INCmvTwsiSpech -+#define __INCmvTwsiSpech -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) -+ -+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 -+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 -+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) -+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 -+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 -+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) -+#define TWSI_EXTENDED_SLAVE_OFFS 0 -+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) -+ -+ -+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) -+#define TWSI_DATA_COMMAND_OFFS 0x0 -+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 -+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) -+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 -+#define TWSI_DATA_ADDR_10BIT_MASK 0x300 -+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) -+#define TWSI_CONTROL_ACK BIT2 -+#define TWSI_CONTROL_INT_FLAG_SET BIT3 -+#define TWSI_CONTROL_STOP_BIT BIT4 -+#define TWSI_CONTROL_START_BIT BIT5 -+#define TWSI_CONTROL_ENA BIT6 -+#define TWSI_CONTROL_INT_ENA BIT7 -+ -+ -+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) -+#define TWSI_BAUD_RATE_N_OFFS 0 -+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) -+#define TWSI_BAUD_RATE_M_OFFS 3 -+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) -+ -+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) -+ -+/* defines */ -+#define TWSI_TIMEOUT_VALUE 0x500 -+ -+/* TWSI status codes */ -+#define TWSI_BUS_ERROR 0x00 -+#define TWSI_START_CON_TRA 0x08 -+#define TWSI_REPEATED_START_CON_TRA 0x10 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 -+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 -+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 -+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 -+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 -+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 -+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 -+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 -+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 -+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 -+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 -+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiSpech */ -diff --git a/crypto/ocf/ocf-bench.c b/crypto/ocf/ocf-bench.c -new file mode 100644 -index 0000000..d325231 ---- /dev/null -+++ b/crypto/ocf/ocf-bench.c -@@ -0,0 +1,436 @@ -+/* -+ * A loadable module that benchmarks the OCF crypto speed from kernel space. -+ * -+ * Copyright (C) 2004-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK -+#define BENCH_IXP_ACCESS_LIB 1 -+#endif -+#ifdef BENCH_IXP_ACCESS_LIB -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+/* -+ * support for access lib version 1.4 -+ */ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+/* -+ * the number of simultaneously active requests -+ */ -+static int request_q_len = 20; -+module_param(request_q_len, int, 0); -+MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); -+/* -+ * how many requests we want to have processed -+ */ -+static int request_num = 1024; -+module_param(request_num, int, 0); -+MODULE_PARM_DESC(request_num, "run for at least this many requests"); -+/* -+ * the size of each request -+ */ -+static int request_size = 1500; -+module_param(request_size, int, 0); -+MODULE_PARM_DESC(request_size, "size of each request"); -+ -+/* -+ * a structure for each request -+ */ -+typedef struct { -+ struct work_struct work; -+#ifdef BENCH_IXP_ACCESS_LIB -+ IX_MBUF mbuf; -+#endif -+ unsigned char *buffer; -+} request_t; -+ -+static request_t *requests; -+ -+static int outstanding; -+static int total; -+ -+/*************************************************************************/ -+/* -+ * OCF benchmark routines -+ */ -+ -+static uint64_t ocf_cryptoid; -+static int ocf_init(void); -+static int ocf_cb(struct cryptop *crp); -+static void ocf_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ocf_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ocf_init(void) -+{ -+ int error; -+ struct cryptoini crie, cria; -+ struct cryptodesc crda, crde; -+ -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&crde, 0, sizeof(crde)); -+ memset(&crda, 0, sizeof(crda)); -+ -+ cria.cri_alg = CRYPTO_SHA1_HMAC; -+ cria.cri_klen = 20 * 8; -+ cria.cri_key = "0123456789abcdefghij"; -+ -+ crie.cri_alg = CRYPTO_3DES_CBC; -+ crie.cri_klen = 24 * 8; -+ crie.cri_key = "0123456789abcdefghijklmn"; -+ -+ crie.cri_next = &cria; -+ -+ error = crypto_newsession(&ocf_cryptoid, &crie, 0); -+ if (error) { -+ printk("crypto_newsession failed %d\n", error); -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+ocf_cb(struct cryptop *crp) -+{ -+ request_t *r = (request_t *) crp->crp_opaque; -+ -+ if (crp->crp_etype) -+ printk("Error in OCF processing: %d\n", crp->crp_etype); -+ total++; -+ crypto_freereq(crp); -+ crp = NULL; -+ -+ if (total > request_num) { -+ outstanding--; -+ return 0; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ocf_request_wq); -+#else -+ INIT_WORK(&r->work, ocf_request, r); -+#endif -+ schedule_work(&r->work); -+ return 0; -+} -+ -+ -+static void -+ocf_request(void *arg) -+{ -+ request_t *r = arg; -+ struct cryptop *crp = crypto_getreq(2); -+ struct cryptodesc *crde, *crda; -+ -+ if (!crp) { -+ outstanding--; -+ return; -+ } -+ -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ -+ crda->crd_skip = 0; -+ crda->crd_flags = 0; -+ crda->crd_len = request_size; -+ crda->crd_inject = request_size; -+ crda->crd_alg = CRYPTO_SHA1_HMAC; -+ crda->crd_key = "0123456789abcdefghij"; -+ crda->crd_klen = 20 * 8; -+ -+ crde->crd_skip = 0; -+ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; -+ crde->crd_len = request_size; -+ crde->crd_inject = request_size; -+ crde->crd_alg = CRYPTO_3DES_CBC; -+ crde->crd_key = "0123456789abcdefghijklmn"; -+ crde->crd_klen = 24 * 8; -+ -+ crp->crp_ilen = request_size + 64; -+ crp->crp_flags = CRYPTO_F_CBIMM; -+ crp->crp_buf = (caddr_t) r->buffer; -+ crp->crp_callback = ocf_cb; -+ crp->crp_sid = ocf_cryptoid; -+ crp->crp_opaque = (caddr_t) r; -+ crypto_dispatch(crp); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ocf_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ocf_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#ifdef BENCH_IXP_ACCESS_LIB -+/*************************************************************************/ -+/* -+ * CryptoAcc benchmark routines -+ */ -+ -+static IxCryptoAccCtx ixp_ctx; -+static UINT32 ixp_ctx_id; -+static IX_MBUF ixp_pri; -+static IX_MBUF ixp_sec; -+static int ixp_registered = 0; -+ -+static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, -+ IxCryptoAccStatus status); -+static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, -+ IxCryptoAccStatus status); -+static void ixp_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ixp_init(void) -+{ -+ IxCryptoAccStatus status; -+ -+ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp_ctx.cipherCtx.cipherKeyLen = 24; -+ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); -+ -+ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp_ctx.authCtx.authDigestLen = 12; -+ ixp_ctx.authCtx.aadLen = 0; -+ ixp_ctx.authCtx.authKeyLen = 20; -+ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); -+ -+ ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; -+ -+ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; -+ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; -+ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ -+ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, -+ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { -+ while (!ixp_registered) -+ schedule(); -+ return ixp_registered < 0 ? -1 : 0; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ return -1; -+} -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) -+ return; -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ ixp_registered = 1; -+ else -+ ixp_registered = -1; -+} -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ request_t *r = NULL; -+ -+ total++; -+ if (total > request_num) { -+ outstanding--; -+ return; -+ } -+ -+ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { -+ printk("crappo %p %p\n", sbufp, r); -+ outstanding--; -+ return; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ixp_request_wq); -+#else -+ INIT_WORK(&r->work, ixp_request, r); -+#endif -+ schedule_work(&r->work); -+} -+ -+static void -+ixp_request(void *arg) -+{ -+ request_t *r = arg; -+ IxCryptoAccStatus status; -+ -+ memset(&r->mbuf, 0, sizeof(r->mbuf)); -+ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; -+ IX_MBUF_MDATA(&r->mbuf) = r->buffer; -+ IX_MBUF_PRIV(&r->mbuf) = r; -+ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, -+ 0, request_size, 0, request_size, request_size, r->buffer); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("status1 = %d\n", status); -+ outstanding--; -+ return; -+ } -+ return; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ixp_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#endif /* BENCH_IXP_ACCESS_LIB */ -+/*************************************************************************/ -+ -+int -+ocfbench_init(void) -+{ -+ int i, jstart, jstop; -+ -+ printk("Crypto Speed tests\n"); -+ -+ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); -+ if (!requests) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < request_q_len; i++) { -+ /* +64 for return data */ -+ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); -+ if (!requests[i].buffer) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ memset(requests[i].buffer, '0' + i, request_size + 128); -+ } -+ -+ /* -+ * OCF benchmark -+ */ -+ printk("OCF: testing ...\n"); -+ ocf_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ocf_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("OCF: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+ -+#ifdef BENCH_IXP_ACCESS_LIB -+ /* -+ * IXP benchmark -+ */ -+ printk("IXP: testing ...\n"); -+ ixp_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ixp_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("IXP: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+#endif /* BENCH_IXP_ACCESS_LIB */ -+ -+ for (i = 0; i < request_q_len; i++) -+ kfree(requests[i].buffer); -+ kfree(requests); -+ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ -+} -+ -+static void __exit ocfbench_exit(void) -+{ -+} -+ -+module_init(ocfbench_init); -+module_exit(ocfbench_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); -diff --git a/crypto/ocf/ocf-compat.h b/crypto/ocf/ocf-compat.h -new file mode 100644 -index 0000000..212f971 ---- /dev/null -+++ b/crypto/ocf/ocf-compat.h -@@ -0,0 +1,294 @@ -+#ifndef _BSD_COMPAT_H_ -+#define _BSD_COMPAT_H_ 1 -+/****************************************************************************/ -+/* -+ * Provide compat routines for older linux kernels and BSD kernels -+ * -+ * Written by David McCullough -+ * Copyright (C) 2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this file -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+/****************************************************************************/ -+#ifdef __KERNEL__ -+/* -+ * fake some BSD driver interface stuff specifically for OCF use -+ */ -+ -+typedef struct ocf_device *device_t; -+ -+typedef struct { -+ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); -+ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); -+ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); -+ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); -+} device_method_t; -+#define DEVMETHOD(id, func) id: func -+ -+struct ocf_device { -+ char name[32]; /* the driver name */ -+ char nameunit[32]; /* the driver name + HW instance */ -+ int unit; -+ device_method_t methods; -+ void *softc; -+}; -+ -+#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ -+ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) -+#define CRYPTODEV_FREESESSION(dev, sid) \ -+ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) -+#define CRYPTODEV_PROCESS(dev, crp, hint) \ -+ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) -+#define CRYPTODEV_KPROCESS(dev, krp, hint) \ -+ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) -+ -+#define device_get_name(dev) ((dev)->name) -+#define device_get_nameunit(dev) ((dev)->nameunit) -+#define device_get_unit(dev) ((dev)->unit) -+#define device_get_softc(dev) ((dev)->softc) -+ -+#define softc_device_decl \ -+ struct ocf_device _device; \ -+ device_t -+ -+#define softc_device_init(_sc, _name, _unit, _methods) \ -+ if (1) {\ -+ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ -+ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ -+ (_sc)->_device.unit = _unit; \ -+ (_sc)->_device.methods = _methods; \ -+ (_sc)->_device.softc = (void *) _sc; \ -+ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ -+ } else -+ -+#define softc_get_device(_sc) (&(_sc)->_device) -+ -+/* -+ * iomem support for 2.4 and 2.6 kernels -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_iomem_t unsigned long -+ -+/* -+ * implement simple workqueue like support for older kernels -+ */ -+ -+#include -+ -+#define work_struct tq_struct -+ -+#define INIT_WORK(wp, fp, ap) \ -+ do { \ -+ (wp)->sync = 0; \ -+ (wp)->routine = (fp); \ -+ (wp)->data = (ap); \ -+ } while (0) -+ -+#define schedule_work(wp) \ -+ do { \ -+ queue_task((wp), &tq_immediate); \ -+ mark_bh(IMMEDIATE_BH); \ -+ } while (0) -+ -+#define flush_scheduled_work() run_task_queue(&tq_immediate) -+ -+#else -+#define ocf_iomem_t void __iomem * -+ -+#include -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+#define files_fdtable(files) (files) -+#endif -+ -+#ifdef MODULE_PARM -+#undef module_param /* just in case */ -+#define module_param(a,b,c) MODULE_PARM(a,"i") -+#endif -+ -+#define bzero(s,l) memset(s,0,l) -+#define bcopy(s,d,l) memcpy(d,s,l) -+#define bcmp(x, y, l) memcmp(x,y,l) -+ -+#define MIN(x,y) ((x) < (y) ? (x) : (y)) -+ -+#define device_printf(dev, a...) ({ \ -+ printk("%s: ", device_get_nameunit(dev)); printk(a); \ -+ }) -+ -+#undef printf -+#define printf(fmt...) printk(fmt) -+ -+#define KASSERT(c,p) if (!(c)) { printk p ; } else -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_daemonize(str) \ -+ daemonize(); \ -+ spin_lock_irq(¤t->sigmask_lock); \ -+ sigemptyset(¤t->blocked); \ -+ recalc_sigpending(current); \ -+ spin_unlock_irq(¤t->sigmask_lock); \ -+ sprintf(current->comm, str); -+#else -+#define ocf_daemonize(str) daemonize(str); -+#endif -+ -+#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) -+#define TAILQ_EMPTY(q) list_empty(q) -+#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) -+#define strtoul simple_strtoul -+ -+#define pci_get_vendor(dev) ((dev)->vendor) -+#define pci_get_device(dev) ((dev)->device) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define pci_set_consistent_dma_mask(dev, mask) (0) -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef htole32 -+#define htole32(x) cpu_to_le32(x) -+#endif -+#ifndef htobe32 -+#define htobe32(x) cpu_to_be32(x) -+#endif -+#ifndef htole16 -+#define htole16(x) cpu_to_le16(x) -+#endif -+#ifndef htobe16 -+#define htobe16(x) cpu_to_be16(x) -+#endif -+ -+/* older kernels don't have these */ -+ -+#include -+#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) -+#define IRQ_NONE -+#define IRQ_HANDLED -+#define IRQ_WAKE_THREAD -+#define IRQ_RETVAL -+#define irqreturn_t void -+typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); -+#endif -+#ifndef IRQF_SHARED -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) -+# define strlcpy(dest,src,len) \ -+ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) -+#endif -+ -+#ifndef MAX_ERRNO -+#define MAX_ERRNO 4095 -+#endif -+#ifndef IS_ERR_VALUE -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) -+#include -+#endif -+#ifndef IS_ERR_VALUE -+#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) -+#endif -+#endif -+ -+/* -+ * common debug for all -+ */ -+#if 1 -+#define dprintk(a...) do { if (debug) printk(a); } while(0) -+#else -+#define dprintk(a...) -+#endif -+ -+#ifndef SLAB_ATOMIC -+/* Changed in 2.6.20, must use GFP_ATOMIC now */ -+#define SLAB_ATOMIC GFP_ATOMIC -+#endif -+ -+/* -+ * need some additional support for older kernels */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) -+#define pci_register_driver_compat(driver, rc) \ -+ do { \ -+ if ((rc) > 0) { \ -+ (rc) = 0; \ -+ } else if (rc == 0) { \ -+ (rc) = -ENODEV; \ -+ } else { \ -+ pci_unregister_driver(driver); \ -+ } \ -+ } while (0) -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) -+#else -+#define pci_register_driver_compat(driver,rc) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+#include -+#include -+ -+static inline void sg_set_page(struct scatterlist *sg, struct page *page, -+ unsigned int len, unsigned int offset) -+{ -+ sg->page = page; -+ sg->offset = offset; -+ sg->length = len; -+} -+ -+static inline void *sg_virt(struct scatterlist *sg) -+{ -+ return page_address(sg->page) + sg->offset; -+} -+ -+#define sg_init_table(sg, n) -+ -+#endif -+ -+#ifndef late_initcall -+#define late_initcall(init) module_init(init) -+#endif -+ -+#endif /* __KERNEL__ */ -+ -+/****************************************************************************/ -+#endif /* _BSD_COMPAT_H_ */ -diff --git a/crypto/ocf/ocfnull/Makefile b/crypto/ocf/ocfnull/Makefile -new file mode 100644 -index 0000000..044bcac ---- /dev/null -+++ b/crypto/ocf/ocfnull/Makefile -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/ocfnull/ocfnull.c b/crypto/ocf/ocfnull/ocfnull.c -new file mode 100644 -index 0000000..3df150d ---- /dev/null -+++ b/crypto/ocf/ocfnull/ocfnull.c -@@ -0,0 +1,203 @@ -+/* -+ * An OCF module for determining the cost of crypto versus the cost of -+ * IPSec processing outside of OCF. This modules gives us the effect of -+ * zero cost encryption, of course you will need to run it at both ends -+ * since it does no crypto at all. -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static int32_t null_id = -1; -+static u_int32_t null_sesnum = 0; -+ -+static int null_process(device_t, struct cryptop *, int); -+static int null_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int null_freesession(device_t, u_int64_t); -+ -+#define debug ocfnull_debug -+int ocfnull_debug = 0; -+module_param(ocfnull_debug, int, 0644); -+MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} nulldev; -+ -+static device_method_t null_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, null_newsession), -+ DEVMETHOD(cryptodev_freesession,null_freesession), -+ DEVMETHOD(cryptodev_process, null_process), -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (null_sesnum == 0) -+ null_sesnum++; -+ *sid = null_sesnum++; -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+null_freesession(device_t arg, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > null_sesnum) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ return 0; -+} -+ -+ -+/* -+ * Process a request. -+ */ -+static int -+null_process(device_t arg, struct cryptop *crp, int hint) -+{ -+ unsigned int lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= null_sesnum || lid == 0) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+null_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, null_init); -+ -+ memset(&nulldev, 0, sizeof(nulldev)); -+ softc_device_init(&nulldev, "ocfnull", 0, null_methods); -+ -+ null_id = crypto_get_driverid(softc_get_device(&nulldev), -+ CRYPTOCAP_F_HARDWARE); -+ if (null_id < 0) -+ panic("ocfnull: crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(null_id,alg,0,0) -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+null_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(null_id); -+ null_id = -1; -+} -+ -+module_init(null_init); -+module_exit(null_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); -diff --git a/crypto/ocf/pasemi/Makefile b/crypto/ocf/pasemi/Makefile -new file mode 100644 -index 0000000..b0a3980 ---- /dev/null -+++ b/crypto/ocf/pasemi/Makefile -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_PASEMI) += pasemi.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/pasemi/pasemi.c b/crypto/ocf/pasemi/pasemi.c -new file mode 100644 -index 0000000..c3bb931 ---- /dev/null -+++ b/crypto/ocf/pasemi/pasemi.c -@@ -0,0 +1,1009 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pasemi_fnu.h" -+ -+#define DRV_NAME "pasemi" -+ -+#define TIMER_INTERVAL 1000 -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev); -+static struct pasdma_status volatile * dma_status; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug"); -+ -+static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->postop = 0; -+ desc->quad[0] = hdr; -+ desc->quad_cnt = 1; -+ desc->size = 1; -+} -+ -+static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) -+{ -+ desc->quad[desc->quad_cnt++] = val; -+ desc->size = (desc->quad_cnt + 1) / 2; -+} -+ -+static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->quad[0] |= hdr; -+} -+ -+static int pasemi_desc_size(struct pasemi_desc *desc) -+{ -+ return desc->size; -+} -+ -+static void pasemi_ring_add_desc( -+ struct pasemi_fnu_txring *ring, -+ struct pasemi_desc *desc, -+ struct cryptop *crp) { -+ int i; -+ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; -+ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; -+ -+ for (i = 0; i < desc->quad_cnt; i += 2) { -+ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ ring->desc[ring_index] = desc->quad[i]; -+ ring->desc[ring_index + 1] = desc->quad[i + 1]; -+ ring->next_to_fill++; -+ } -+ -+ if (desc->quad_cnt & 1) -+ ring->desc[ring_index + 1] = 0; -+} -+ -+static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) -+{ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), -+ incr); -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct pasemi_session *ses = NULL, **sespp; -+ int sesn, blksz = 0; -+ u64 ccmd = 0; -+ unsigned long flags; -+ struct pasemi_desc init_desc; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return -EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (ALG_IS_SIG(c->cri_alg)) { -+ if (macini) -+ return -EINVAL; -+ macini = c; -+ } else if (ALG_IS_CIPHER(c->cri_alg)) { -+ if (encini) -+ return -EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); -+ return -EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return -EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return -EINVAL; -+ ccmd = DMA_CALGO_DES; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return -EINVAL; -+ ccmd = DMA_CALGO_3DES; -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return -EINVAL; -+ ccmd = DMA_CALGO_AES; -+ break; -+ case CRYPTO_ARC4: -+ if (encini->cri_klen != 128) -+ return -EINVAL; -+ ccmd = DMA_CALGO_ARC; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return -EINVAL; -+ } -+ } -+ -+ if (macini) { -+ switch (macini->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ blksz = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ blksz = 20; -+ break; -+ default: -+ DPRINTF("UNKNOWN macini->cri_alg %d\n", -+ macini->cri_alg); -+ return -EINVAL; -+ } -+ if (((macini->cri_klen + 7) / 8) > blksz) { -+ DPRINTF("key length %d bigger than blksize %d not supported\n", -+ ((macini->cri_klen + 7) / 8), blksz); -+ return -EINVAL; -+ } -+ } -+ -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn] == NULL) { -+ sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } else if (sc->sc_sessions[sesn]->used == 0) { -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sespp = (struct pasemi_session **) -+ kzalloc(sc->sc_nsessions * 2 * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sespp == NULL) -+ return -ENOMEM; -+ memcpy(sespp, sc->sc_sessions, -+ sc->sc_nsessions * sizeof(struct pasemi_session *)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = sespp; -+ sesn = sc->sc_nsessions; -+ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ if (ses == NULL) -+ return -ENOMEM; -+ sc->sc_nsessions *= 2; -+ } -+ -+ ses->used = 1; -+ -+ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnlock, flags); -+ -+ /* ARC4 has to be processed by the even channel */ -+ if (encini && (encini->cri_alg == CRYPTO_ARC4)) -+ ses->chan = sc->sc_lastchn & ~1; -+ else -+ ses->chan = sc->sc_lastchn; -+ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; -+ -+ spin_unlock_irqrestore(&sc->sc_chnlock, flags); -+ -+ txring = &sc->tx[ses->chan]; -+ -+ if (encini) { -+ ses->ccmd = ccmd; -+ -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ get_random_bytes(ses->civ, sizeof(ses->civ)); -+ -+ ses->keysz = (encini->cri_klen - 63) / 64; -+ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); -+ } -+ if (macini) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ memcpy(ses->hkey, macini->cri_key, blksz); -+ else { -+ /* Load initialization constants(RFC 1321, 3174) */ -+ ses->hiv[0] = 0x67452301efcdab89ULL; -+ ses->hiv[1] = 0x98badcfe10325476ULL; -+ ses->hiv[2] = 0xc3d2e1f000000000ULL; -+ } -+ ses->hseq = 0ULL; -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ return ERESTART; -+ } -+ -+ if (encini) { -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_incr(sc, ses->chan, -+ pasemi_desc_size(&init_desc)); -+ } -+ -+ txring->sesn = sesn; -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ *sidp = PASEMI_SID(sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+pasemi_freesession(device_t dev, u_int64_t tid) -+{ -+ struct pasemi_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc == NULL) -+ return -EINVAL; -+ session = PASEMI_SESSION(sid); -+ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) -+ return -EINVAL; -+ -+ pci_unmap_single(sc->dma_pdev, -+ sc->sc_sessions[session]->dma_addr, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ memset(sc->sc_sessions[session], 0, -+ sizeof(struct pasemi_session)); -+ -+ return 0; -+} -+ -+static int -+pasemi_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ -+ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t ivp; -+ struct pasemi_desc init_desc, work_desc; -+ struct pasemi_session *ses; -+ struct sk_buff *skb; -+ struct uio *uiop; -+ unsigned long flags; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) -+ return -EINVAL; -+ -+ crp->crp_etype = 0; -+ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) -+ return -EINVAL; -+ -+ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = -EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (ALG_IS_SIG(crd1->crd_alg)) { -+ maccrd = crd1; -+ if (crd2 == NULL) -+ enccrd = NULL; -+ else if (ALG_IS_CIPHER(crd2->crd_alg) && -+ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) -+ enccrd = crd2; -+ else -+ goto erralg; -+ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { -+ enccrd = crd1; -+ if (crd2 == NULL) -+ maccrd = NULL; -+ else if (ALG_IS_SIG(crd2->crd_alg) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) -+ maccrd = crd2; -+ else -+ goto erralg; -+ } else -+ goto erralg; -+ -+ chsel = ses->chan; -+ -+ txring = &sc->tx[chsel]; -+ -+ if (enccrd && !maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x40; -+ srclen = crp->crp_ilen; -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I -+ | XCT_FUN_FUN(chsel)); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); -+ else -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); -+ } else if (enccrd && maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x68; -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Encrypt -> Authenticate */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ srclen = maccrd->crd_skip + maccrd->crd_len; -+ } else { -+ /* Authenticate -> Decrypt */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC -+ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ work_desc.postop = PASEMI_CHECK_SIG; -+ srclen = crp->crp_ilen; -+ } -+ -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); -+ } else if (!enccrd && maccrd) { -+ srclen = maccrd->crd_len; -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ } -+ -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_AES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | -+ XCT_FUN_BCM_CBC); -+ ivsize = 2 * sizeof(u64); -+ break; -+ case CRYPTO_ARC4: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); -+ ivsize = 0; -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", -+ enccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ /* If IV is not present in the buffer already, it has to be copied there */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ /* IV is provided expicitly in descriptor */ -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ /* IV is provided in the packet */ -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ ivp); -+ } -+ } -+ -+ if (maccrd) { -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_MD5_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", -+ maccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk(DRV_NAME ": skb frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(skb->len, pci_map_single( -+ sc->dma_pdev, skb->data, -+ skb->len, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR( -+ srclen, pci_map_single( -+ sc->dma_pdev, skb->data, -+ srclen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk(DRV_NAME ": iov frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ /* crp_olen is never set; always use crp_ilen */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ srclen, DMA_TO_DEVICE))); -+ } else { -+ /* using contig buffers */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, srclen, -+ DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { -+ txring->sesn = PASEMI_SESSION(crp->crp_sid); -+ reinit = 1; -+ } -+ -+ if (enccrd) { -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); -+ } -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ err = ERESTART; -+ goto errout; -+ } -+ -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_add_desc(txring, &work_desc, crp); -+ -+ pasemi_ring_incr(sc, chsel, -+ pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)); -+ -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); -+ -+ return 0; -+ -+erralg: -+ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", -+ crd1->crd_alg, crd2->crd_alg); -+ err = -EINVAL; -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) -+{ -+ int i, j, ring_idx; -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ u16 delta_cnt; -+ int flags, loops = 10; -+ int desc_size; -+ struct cryptop *crp; -+ -+ spin_lock_irqsave(&ring->clean_lock, flags); -+ -+ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] -+ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) -+ && loops--) { -+ -+ for (i = 0; i < delta_cnt; i++) { -+ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; -+ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; -+ if (crp) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { -+ /* Need to make sure signature matched, -+ * if not - return error */ -+ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) -+ crp->crp_etype = -EINVAL; -+ } -+ crypto_done(TX_DESC_INFO(ring, -+ ring->next_to_clean).cf_crp); -+ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ -+ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; -+ -+ ring->next_to_clean++; -+ for (j = 1; j < desc_size; j++) { -+ ring_idx = 2 * -+ (ring->next_to_clean & -+ (TX_RING_SIZE-1)); -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), -+ PCI_DMA_TODEVICE); -+ if (ring->desc[ring_idx + 1]) -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN( -+ ring->desc[ -+ ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } else { -+ for (j = 0; j < desc_size; j++) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } -+ } -+ -+ ring->total_pktcnt += delta_cnt; -+ } -+ spin_unlock_irqrestore(&ring->clean_lock, flags); -+ -+ return 0; -+} -+ -+static void sweepup_tx(struct pasemi_softc *sc) -+{ -+ int i; -+ -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_clean_tx(sc, i); -+} -+ -+static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct pasemi_softc *sc = arg; -+ unsigned int reg; -+ int chan = irq - sc->base_irq; -+ int chan_index = sc->base_chan + chan; -+ u64 stat = dma_status->tx_sta[chan_index]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (!(stat & PAS_STATUS_CAUSE_M)) -+ return IRQ_NONE; -+ -+ pasemi_clean_tx(sc, chan); -+ -+ stat = dma_status->tx_sta[chan_index]; -+ -+ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | -+ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); -+ -+ if (stat & PAS_STATUS_SOFT) -+ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); -+ -+ -+ return IRQ_HANDLED; -+} -+ -+static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ u32 val; -+ int chan_index = chan + sc->base_chan; -+ int ret; -+ struct pasemi_fnu_txring *ring; -+ -+ ring = &sc->tx[chan]; -+ -+ spin_lock_init(&ring->fill_lock); -+ spin_lock_init(&ring->clean_lock); -+ -+ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * -+ TX_RING_SIZE, GFP_KERNEL); -+ if (!ring->desc_info) -+ return -ENOMEM; -+ -+ /* Allocate descriptors */ -+ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ &ring->dma, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); -+ -+ ring->total_pktcnt = 0; -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), -+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); -+ -+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); -+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), -+ PAS_DMA_TXCHAN_CFG_TY_FUNC | -+ PAS_DMA_TXCHAN_CFG_TATTR(chan) | -+ PAS_DMA_TXCHAN_CFG_WT(2)); -+ -+ /* enable tx channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_EN); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), -+ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); -+ -+ ring->next_to_fill = 0; -+ ring->next_to_clean = 0; -+ -+ snprintf(ring->irq_name, sizeof(ring->irq_name), -+ "%s%d", "crypto", chan); -+ -+ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); -+ ret = request_irq(ring->irq, (irq_handler_t) -+ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); -+ if (ret) { -+ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", -+ ring->irq, ret); -+ ring->irq = -1; -+ return ret; -+ } -+ -+ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); -+ -+ return 0; -+} -+ -+static device_method_t pasemi_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, pasemi_newsession), -+ DEVMETHOD(cryptodev_freesession, pasemi_freesession), -+ DEVMETHOD(cryptodev_process, pasemi_process), -+}; -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+ -+static int __devinit -+pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct pasemi_softc *sc; -+ int ret, i; -+ -+ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); -+ -+ sc = kzalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ -+ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); -+ -+ pci_set_drvdata(pdev, sc); -+ -+ spin_lock_init(&sc->sc_chnlock); -+ -+ sc->sc_sessions = (struct pasemi_session **) -+ kzalloc(PASEMI_INITIAL_SESSIONS * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sc->sc_sessions == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; -+ sc->sc_lastchn = 0; -+ sc->base_irq = pdev->irq + 6; -+ sc->base_chan = 6; -+ sc->sc_cid = -1; -+ sc->dma_pdev = pdev; -+ -+ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); -+ if (!sc->iob_pdev) { -+ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ /* This is hardcoded and ugly, but we have some firmware versions -+ * who don't provide the register space in the device tree. Luckily -+ * they are at well-known locations so we can just do the math here. -+ */ -+ sc->dma_regs = -+ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); -+ sc->iob_regs = -+ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); -+ if (!sc->dma_regs || !sc->iob_regs) { -+ dev_err(&pdev->dev, "Can't map registers\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dma_status = __ioremap(0xfd800000, 0x1000, 0); -+ if (!dma_status) { -+ ret = -ENODEV; -+ dev_err(&pdev->dev, "Can't map dmastatus space\n"); -+ goto out; -+ } -+ -+ sc->tx = (struct pasemi_fnu_txring *) -+ kzalloc(sizeof(struct pasemi_fnu_txring) -+ * 8, GFP_KERNEL); -+ if (!sc->tx) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialize the h/w */ -+ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, -+ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | -+ PAS_DMA_COM_CFG_FWF)); -+ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); -+ -+ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { -+ sc->sc_num_channels++; -+ ret = pasemi_dma_setup_tx_resources(sc, i); -+ if (ret) -+ goto out; -+ } -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), -+ CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk(DRV_NAME ":"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ -+ return 0; -+ -+out: -+ pasemi_dma_remove(pdev); -+ return ret; -+} -+ -+#define MAX_RETRIES 5000 -+ -+static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ int chan_index = chan + sc->base_chan; -+ int retries; -+ u32 stat; -+ -+ /* Stop the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_ST); -+ -+ for (retries = 0; retries < MAX_RETRIES; retries++) { -+ stat = in_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); -+ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) -+ break; -+ cond_resched(); -+ } -+ -+ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) -+ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", -+ chan_index); -+ -+ /* Disable the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ 0); -+ -+ if (ring->desc_info) -+ kfree((void *) ring->desc_info); -+ if (ring->desc) -+ dma_free_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ (void *) ring->desc, ring->dma); -+ if (ring->irq != -1) -+ free_irq(ring->irq, sc); -+ -+ del_timer(&ring->crypto_timer); -+} -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev) -+{ -+ struct pasemi_softc *sc = pci_get_drvdata(pdev); -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc->sc_cid >= 0) { -+ crypto_unregister_all(sc->sc_cid); -+ } -+ -+ if (sc->tx) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_free_tx_resources(sc, i); -+ -+ kfree(sc->tx); -+ } -+ if (sc->sc_sessions) { -+ for (i = 0; i < sc->sc_nsessions; i++) -+ kfree(sc->sc_sessions[i]); -+ kfree(sc->sc_sessions); -+ } -+ if (sc->iob_pdev) -+ pci_dev_put(sc->iob_pdev); -+ if (sc->dma_regs) -+ iounmap(sc->dma_regs); -+ if (sc->iob_regs) -+ iounmap(sc->iob_regs); -+ kfree(sc); -+} -+ -+static struct pci_device_id pasemi_dma_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, -+}; -+ -+MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); -+ -+static struct pci_driver pasemi_dma_driver = { -+ .name = "pasemi_dma", -+ .id_table = pasemi_dma_pci_tbl, -+ .probe = pasemi_dma_probe, -+ .remove = __devexit_p(pasemi_dma_remove), -+}; -+ -+static void __exit pasemi_dma_cleanup_module(void) -+{ -+ pci_unregister_driver(&pasemi_dma_driver); -+ __iounmap(dma_status); -+ dma_status = NULL; -+} -+ -+int pasemi_dma_init_module(void) -+{ -+ return pci_register_driver(&pasemi_dma_driver); -+} -+ -+module_init(pasemi_dma_init_module); -+module_exit(pasemi_dma_cleanup_module); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); -+MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); -diff --git a/crypto/ocf/pasemi/pasemi_fnu.h b/crypto/ocf/pasemi/pasemi_fnu.h -new file mode 100644 -index 0000000..1a0dcc8 ---- /dev/null -+++ b/crypto/ocf/pasemi/pasemi_fnu.h -@@ -0,0 +1,410 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and -+ * hardware register layouts. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef PASEMI_FNU_H -+#define PASEMI_FNU_H -+ -+#include -+ -+#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) -+#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) -+#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } -+ -+/* Must be a power of two */ -+#define RX_RING_SIZE 512 -+#define TX_RING_SIZE 512 -+#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) -+#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) -+#define MAX_DESC_SIZE 8 -+#define PASEMI_INITIAL_SESSIONS 10 -+#define PASEMI_FNU_CHANNELS 8 -+ -+/* DMA descriptor */ -+struct pasemi_desc { -+ u64 quad[2*MAX_DESC_SIZE]; -+ int quad_cnt; -+ int size; -+ int postop; -+}; -+ -+/* -+ * Holds per descriptor data -+ */ -+struct pasemi_desc_info { -+ int desc_size; -+ int desc_postop; -+#define PASEMI_CHECK_SIG 0x1 -+ -+ struct cryptop *cf_crp; -+}; -+ -+/* -+ * Holds per channel data -+ */ -+struct pasemi_fnu_txring { -+ volatile u64 *desc; -+ volatile struct -+ pasemi_desc_info *desc_info; -+ dma_addr_t dma; -+ struct timer_list crypto_timer; -+ spinlock_t fill_lock; -+ spinlock_t clean_lock; -+ unsigned int next_to_fill; -+ unsigned int next_to_clean; -+ u16 total_pktcnt; -+ int irq; -+ int sesn; -+ char irq_name[10]; -+}; -+ -+/* -+ * Holds data specific to a single pasemi device. -+ */ -+struct pasemi_softc { -+ softc_device_decl sc_cdev; -+ struct pci_dev *dma_pdev; /* device backpointer */ -+ struct pci_dev *iob_pdev; /* device backpointer */ -+ void __iomem *dma_regs; -+ void __iomem *iob_regs; -+ int base_irq; -+ int base_chan; -+ int32_t sc_cid; /* crypto tag */ -+ int sc_nsessions; -+ struct pasemi_session **sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ -+ /* pointer to the array of txring datastructures, one txring per channel */ -+ struct pasemi_fnu_txring *tx; -+ -+ /* -+ * mutual exclusion for the channel scheduler -+ */ -+ spinlock_t sc_chnlock; -+ /* last channel used, for now use round-robin to allocate channels */ -+ int sc_lastchn; -+}; -+ -+struct pasemi_session { -+ u64 civ[2]; -+ u64 keysz; -+ u64 key[4]; -+ u64 ccmd; -+ u64 hkey[4]; -+ u64 hseq; -+ u64 giv[2]; -+ u64 hiv[4]; -+ -+ int used; -+ dma_addr_t dma_addr; -+ int chan; -+}; -+ -+/* status register layout in IOB region, at 0xfd800000 */ -+struct pasdma_status { -+ u64 rx_sta[64]; -+ u64 tx_sta[20]; -+}; -+ -+#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ -+ (alg == CRYPTO_3DES_CBC) || \ -+ (alg == CRYPTO_AES_CBC) || \ -+ (alg == CRYPTO_ARC4) || \ -+ (alg == CRYPTO_NULL_CBC)) -+ -+#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ -+ (alg == CRYPTO_MD5_HMAC) || \ -+ (alg == CRYPTO_SHA1) || \ -+ (alg == CRYPTO_SHA1_HMAC) || \ -+ (alg == CRYPTO_NULL_HMAC)) -+ -+enum { -+ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ -+ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ -+ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ -+ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ -+ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ -+}; -+ -+/* All these registers live in the PCI configuration space for the DMA PCI -+ * device. Use the normal PCI config access functions for them. -+ */ -+ -+#define PAS_DMA_COM_CFG_FWF 0x18000000 -+ -+#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ -+#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ -+ -+#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ -+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ -+#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ -+#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ -+#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ -+#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ -+#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ -+#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ -+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ -+#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c -+#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 -+#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ -+ PAS_DMA_TXCHAN_CFG_TATTR_M) -+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 -+#define PAS_DMA_TXCHAN_CFG_WT_S 6 -+#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ -+ PAS_DMA_TXCHAN_CFG_WT_M) -+#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 -+#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 -+#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ -+#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ -+#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ -+#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ -+ PAS_DMA_TXCHAN_BASEL_BRBL_M) -+#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff -+#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 -+#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ -+ PAS_DMA_TXCHAN_BASEU_BRBH_M) -+/* # of cache lines worth of buffer ring */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 -+#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ -+ PAS_DMA_TXCHAN_BASEU_SIZ_M) -+ -+#define PAS_STATUS_PCNT_M 0x000000000000ffffull -+#define PAS_STATUS_PCNT_S 0 -+#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull -+#define PAS_STATUS_DCNT_S 16 -+#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull -+#define PAS_STATUS_BPCNT_S 32 -+#define PAS_STATUS_CAUSE_M 0xf000000000000000ull -+#define PAS_STATUS_TIMER 0x1000000000000000ull -+#define PAS_STATUS_ERROR 0x2000000000000000ull -+#define PAS_STATUS_SOFT 0x4000000000000000ull -+#define PAS_STATUS_INT 0x8000000000000000ull -+ -+#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) -+#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) -+#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_RXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 -+#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_TXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 -+ -+#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ -+ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) -+ -+/* Transmit descriptor fields */ -+#define XCT_MACTX_T 0x8000000000000000ull -+#define XCT_MACTX_ST 0x4000000000000000ull -+#define XCT_MACTX_NORES 0x0000000000000000ull -+#define XCT_MACTX_8BRES 0x1000000000000000ull -+#define XCT_MACTX_24BRES 0x2000000000000000ull -+#define XCT_MACTX_40BRES 0x3000000000000000ull -+#define XCT_MACTX_I 0x0800000000000000ull -+#define XCT_MACTX_O 0x0400000000000000ull -+#define XCT_MACTX_E 0x0200000000000000ull -+#define XCT_MACTX_VLAN_M 0x0180000000000000ull -+#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull -+#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull -+#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull -+#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull -+#define XCT_MACTX_CRC_M 0x0060000000000000ull -+#define XCT_MACTX_CRC_NOP 0x0000000000000000ull -+#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull -+#define XCT_MACTX_CRC_PAD 0x0040000000000000ull -+#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull -+#define XCT_MACTX_SS 0x0010000000000000ull -+#define XCT_MACTX_LLEN_M 0x00007fff00000000ull -+#define XCT_MACTX_LLEN_S 32ull -+#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ -+ XCT_MACTX_LLEN_M) -+#define XCT_MACTX_IPH_M 0x00000000f8000000ull -+#define XCT_MACTX_IPH_S 27ull -+#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ -+ XCT_MACTX_IPH_M) -+#define XCT_MACTX_IPO_M 0x0000000007c00000ull -+#define XCT_MACTX_IPO_S 22ull -+#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ -+ XCT_MACTX_IPO_M) -+#define XCT_MACTX_CSUM_M 0x0000000000000060ull -+#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull -+#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull -+#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull -+#define XCT_MACTX_V6 0x0000000000000010ull -+#define XCT_MACTX_C 0x0000000000000004ull -+#define XCT_MACTX_AL2 0x0000000000000002ull -+ -+#define XCT_PTR_T 0x8000000000000000ull -+#define XCT_PTR_LEN_M 0x7ffff00000000000ull -+#define XCT_PTR_LEN_S 44 -+#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ -+ XCT_PTR_LEN_M) -+#define XCT_PTR_ADDR_M 0x00000fffffffffffull -+#define XCT_PTR_ADDR_S 0 -+#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ -+ XCT_PTR_ADDR_M) -+ -+/* Function descriptor fields */ -+#define XCT_FUN_T 0x8000000000000000ull -+#define XCT_FUN_ST 0x4000000000000000ull -+#define XCT_FUN_NORES 0x0000000000000000ull -+#define XCT_FUN_8BRES 0x1000000000000000ull -+#define XCT_FUN_24BRES 0x2000000000000000ull -+#define XCT_FUN_40BRES 0x3000000000000000ull -+#define XCT_FUN_I 0x0800000000000000ull -+#define XCT_FUN_O 0x0400000000000000ull -+#define XCT_FUN_E 0x0200000000000000ull -+#define XCT_FUN_FUN_S 54 -+#define XCT_FUN_FUN_M 0x01c0000000000000ull -+#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ -+ XCT_FUN_FUN_M) -+#define XCT_FUN_CRM_NOP 0x0000000000000000ull -+#define XCT_FUN_CRM_SIG 0x0008000000000000ull -+#define XCT_FUN_CRM_ENC 0x0010000000000000ull -+#define XCT_FUN_CRM_DEC 0x0018000000000000ull -+#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull -+#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull -+#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull -+#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull -+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull -+#define XCT_FUN_LLEN_S 32ULL -+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ -+ XCT_FUN_LLEN_M) -+#define XCT_FUN_SHL_M 0x00000000f8000000ull -+#define XCT_FUN_SHL_S 27ull -+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ -+ XCT_FUN_SHL_M) -+#define XCT_FUN_CHL_M 0x0000000007c00000ull -+#define XCT_FUN_CHL_S 22ull -+#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ -+ XCT_FUN_CHL_M) -+#define XCT_FUN_HSZ_M 0x00000000003c0000ull -+#define XCT_FUN_HSZ_S 18ull -+#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ -+ XCT_FUN_HSZ_M) -+#define XCT_FUN_ALG_DES 0x0000000000000000ull -+#define XCT_FUN_ALG_3DES 0x0000000000008000ull -+#define XCT_FUN_ALG_AES 0x0000000000010000ull -+#define XCT_FUN_ALG_ARC 0x0000000000018000ull -+#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull -+#define XCT_FUN_BCM_ECB 0x0000000000000000ull -+#define XCT_FUN_BCM_CBC 0x0000000000001000ull -+#define XCT_FUN_BCM_CFB 0x0000000000002000ull -+#define XCT_FUN_BCM_OFB 0x0000000000003000ull -+#define XCT_FUN_BCM_CNT 0x0000000000003800ull -+#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull -+#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull -+#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull -+#define XCT_FUN_BCP_ZRO 0x0000000000000200ull -+#define XCT_FUN_BCP_PL 0x0000000000000400ull -+#define XCT_FUN_BCP_INCR 0x0000000000000600ull -+#define XCT_FUN_SIG_MD5 (0ull << 4) -+#define XCT_FUN_SIG_SHA1 (2ull << 4) -+#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) -+#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) -+#define XCT_FUN_A 0x0000000000000008ull -+#define XCT_FUN_C 0x0000000000000004ull -+#define XCT_FUN_AL2 0x0000000000000002ull -+#define XCT_FUN_SE 0x0000000000000001ull -+ -+#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) -+#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ -+ 0x8000000000000000ull) -+ -+#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull -+#define XCT_CTRL_HDR_FUN_NUM_S 54 -+#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull -+#define XCT_CTRL_HDR_LEN_S 32 -+#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull -+#define XCT_CTRL_HDR_REG_S 0 -+ -+#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ -+ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ -+ & XCT_CTRL_HDR_FUN_NUM_M) | \ -+ ((((long)(len)) << \ -+ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ -+ ((((long)(reg)) << \ -+ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) -+ -+/* Function config command options */ -+#define DMA_CALGO_DES 0x00 -+#define DMA_CALGO_3DES 0x01 -+#define DMA_CALGO_AES 0x02 -+#define DMA_CALGO_ARC 0x03 -+ -+#define DMA_FN_CIV0 0x02 -+#define DMA_FN_CIV1 0x03 -+#define DMA_FN_HKEY0 0x0a -+ -+#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ -+ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) -+ -+#endif /* PASEMI_FNU_H */ -diff --git a/crypto/ocf/random.c b/crypto/ocf/random.c -new file mode 100644 -index 0000000..b5d97e1 ---- /dev/null -+++ b/crypto/ocf/random.c -@@ -0,0 +1,322 @@ -+/* -+ * A system independant way of adding entropy to the kernels pool -+ * this way the drivers can focus on the real work and we can take -+ * care of pushing it to the appropriate place in the kernel. -+ * -+ * This should be fast and callable from timers/interrupts -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_OCF_FIPS -+#include "rndtest.h" -+#endif -+ -+#ifndef HAS_RANDOM_INPUT_WAIT -+#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+/* -+ * a hack to access the debug levels from the crypto driver -+ */ -+extern int crypto_debug; -+#define debug crypto_debug -+ -+/* -+ * a list of all registered random providers -+ */ -+static LIST_HEAD(random_ops); -+static int started = 0; -+static int initted = 0; -+ -+struct random_op { -+ struct list_head random_list; -+ u_int32_t driverid; -+ int (*read_random)(void *arg, u_int32_t *buf, int len); -+ void *arg; -+}; -+ -+static int random_proc(void *arg); -+ -+static pid_t randomproc = (pid_t) -1; -+static spinlock_t random_lock; -+ -+/* -+ * just init the spin locks -+ */ -+static int -+crypto_random_init(void) -+{ -+ spin_lock_init(&random_lock); -+ initted = 1; -+ return(0); -+} -+ -+/* -+ * Add the given random reader to our list (if not present) -+ * and start the thread (if not already started) -+ * -+ * we have to assume that driver id is ok for now -+ */ -+int -+crypto_rregister( -+ u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), -+ void *arg) -+{ -+ unsigned long flags; -+ int ret = 0; -+ struct random_op *rops, *tmp; -+ -+ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, -+ __FUNCTION__, driverid, read_random, arg); -+ -+ if (!initted) -+ crypto_random_init(); -+ -+#if 0 -+ struct cryptocap *cap; -+ -+ cap = crypto_checkdriver(driverid); -+ if (!cap) -+ return EINVAL; -+#endif -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid && rops->read_random == read_random) -+ return EEXIST; -+ } -+ -+ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); -+ if (!rops) -+ return ENOMEM; -+ -+ rops->driverid = driverid; -+ rops->read_random = read_random; -+ rops->arg = arg; -+ -+ spin_lock_irqsave(&random_lock, flags); -+ list_add_tail(&rops->random_list, &random_ops); -+ if (!started) { -+ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (randomproc < 0) { -+ ret = randomproc; -+ printk("crypto: crypto_rregister cannot start random thread; " -+ "error %d", ret); -+ } else -+ started = 1; -+ } -+ spin_unlock_irqrestore(&random_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(crypto_rregister); -+ -+int -+crypto_runregister_all(u_int32_t driverid) -+{ -+ struct random_op *rops, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid) { -+ list_del(&rops->random_list); -+ kfree(rops); -+ } -+ } -+ -+ spin_lock_irqsave(&random_lock, flags); -+ if (list_empty(&random_ops) && started) -+ kill_proc(randomproc, SIGKILL, 1); -+ spin_unlock_irqrestore(&random_lock, flags); -+ return(0); -+} -+EXPORT_SYMBOL(crypto_runregister_all); -+ -+/* -+ * while we can add entropy to random.c continue to read random data from -+ * the drivers and push it to random. -+ */ -+static int -+random_proc(void *arg) -+{ -+ int n; -+ int wantcnt; -+ int bufcnt = 0; -+ int retval = 0; -+ int *buf = NULL; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ sprintf(current->comm, "ocf-random"); -+#else -+ daemonize("ocf-random"); -+ allow_signal(SIGKILL); -+#endif -+ -+ (void) get_fs(); -+ set_fs(get_ds()); -+ -+#ifdef CONFIG_OCF_FIPS -+#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) -+#else -+#define NUM_INT 32 -+#endif -+ -+ /* -+ * some devices can transferr their RNG data direct into memory, -+ * so make sure it is device friendly -+ */ -+ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); -+ if (NULL == buf) { -+ printk("crypto: RNG could not allocate memory\n"); -+ retval = -ENOMEM; -+ goto bad_alloc; -+ } -+ -+ wantcnt = NUM_INT; /* start by adding some entropy */ -+ -+ /* -+ * its possible due to errors or driver removal that we no longer -+ * have anything to do, if so exit or we will consume all the CPU -+ * doing nothing -+ */ -+ while (!list_empty(&random_ops)) { -+ struct random_op *rops, *tmp; -+ -+#ifdef CONFIG_OCF_FIPS -+ if (wantcnt) -+ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ -+#endif -+ -+ /* see if we can get enough entropy to make the world -+ * a better place. -+ */ -+ while (bufcnt < wantcnt && bufcnt < NUM_INT) { -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ -+ n = (*rops->read_random)(rops->arg, &buf[bufcnt], -+ NUM_INT - bufcnt); -+ -+ /* on failure remove the random number generator */ -+ if (n == -1) { -+ list_del(&rops->random_list); -+ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", -+ rops->driverid); -+ kfree(rops); -+ } else if (n > 0) -+ bufcnt += n; -+ } -+ /* give up CPU for a bit, just in case as this is a loop */ -+ schedule(); -+ } -+ -+ -+#ifdef CONFIG_OCF_FIPS -+ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { -+ dprintk("crypto: buffer had fips errors, discarding\n"); -+ bufcnt = 0; -+ } -+#endif -+ -+ /* -+ * if we have a certified buffer, we can send some data -+ * to /dev/random and move along -+ */ -+ if (bufcnt > 0) { -+ /* add what we have */ -+ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); -+ bufcnt = 0; -+ } -+ -+ /* give up CPU for a bit so we don't hog while filling */ -+ schedule(); -+ -+ /* wait for needing more */ -+ wantcnt = random_input_wait(); -+ -+ if (wantcnt <= 0) -+ wantcnt = 0; /* try to get some info again */ -+ else -+ /* round up to one word or we can loop forever */ -+ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); -+ if (wantcnt > NUM_INT) { -+ wantcnt = NUM_INT; -+ } -+ -+ if (signal_pending(current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ } -+ -+ kfree(buf); -+ -+bad_alloc: -+ spin_lock_irq(&random_lock); -+ randomproc = (pid_t) -1; -+ started = 0; -+ spin_unlock_irq(&random_lock); -+ -+ return retval; -+} -+ -diff --git a/crypto/ocf/rndtest.c b/crypto/ocf/rndtest.c -new file mode 100644 -index 0000000..b31e1a6 ---- /dev/null -+++ b/crypto/ocf/rndtest.c -@@ -0,0 +1,300 @@ -+/* $OpenBSD$ */ -+ -+/* -+ * OCF/Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rndtest.h" -+ -+static struct rndtest_stats rndstats; -+ -+static void rndtest_test(struct rndtest_state *); -+ -+/* The tests themselves */ -+static int rndtest_monobit(struct rndtest_state *); -+static int rndtest_runs(struct rndtest_state *); -+static int rndtest_longruns(struct rndtest_state *); -+static int rndtest_chi_4(struct rndtest_state *); -+ -+static int rndtest_runs_check(struct rndtest_state *, int, int *); -+static void rndtest_runs_record(struct rndtest_state *, int, int *); -+ -+static const struct rndtest_testfunc { -+ int (*test)(struct rndtest_state *); -+} rndtest_funcs[] = { -+ { rndtest_monobit }, -+ { rndtest_runs }, -+ { rndtest_chi_4 }, -+ { rndtest_longruns }, -+}; -+ -+#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) -+ -+static void -+rndtest_test(struct rndtest_state *rsp) -+{ -+ int i, rv = 0; -+ -+ rndstats.rst_tests++; -+ for (i = 0; i < RNDTEST_NTESTS; i++) -+ rv |= (*rndtest_funcs[i].test)(rsp); -+ rsp->rs_discard = (rv != 0); -+} -+ -+ -+extern int crypto_debug; -+#define rndtest_verbose 2 -+#define rndtest_report(rsp, failure, fmt, a...) \ -+ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } -+ -+#define RNDTEST_MONOBIT_MINONES 9725 -+#define RNDTEST_MONOBIT_MAXONES 10275 -+ -+static int -+rndtest_monobit(struct rndtest_state *rsp) -+{ -+ int i, ones = 0, j; -+ u_int8_t r; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ r = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, r <<= 1) -+ if (r & 0x80) -+ ones++; -+ } -+ if (ones > RNDTEST_MONOBIT_MINONES && -+ ones < RNDTEST_MONOBIT_MAXONES) { -+ if (rndtest_verbose > 1) -+ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", -+ RNDTEST_MONOBIT_MINONES, ones, -+ RNDTEST_MONOBIT_MAXONES); -+ return (0); -+ } else { -+ if (rndtest_verbose) -+ rndtest_report(rsp, 1, -+ "monobit failed (%d ones)", ones); -+ rndstats.rst_monobit++; -+ return (-1); -+ } -+} -+ -+#define RNDTEST_RUNS_NINTERVAL 6 -+ -+static const struct rndtest_runs_tabs { -+ u_int16_t min, max; -+} rndtest_runs_tab[] = { -+ { 2343, 2657 }, -+ { 1135, 1365 }, -+ { 542, 708 }, -+ { 251, 373 }, -+ { 111, 201 }, -+ { 111, 201 }, -+}; -+ -+static int -+rndtest_runs(struct rndtest_state *rsp) -+{ -+ int i, j, ones, zeros, rv = 0; -+ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; -+ u_int8_t c; -+ -+ bzero(onei, sizeof(onei)); -+ bzero(zeroi, sizeof(zeroi)); -+ ones = zeros = 0; -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ ones++; -+ rndtest_runs_record(rsp, zeros, zeroi); -+ zeros = 0; -+ } else { -+ zeros++; -+ rndtest_runs_record(rsp, ones, onei); -+ ones = 0; -+ } -+ } -+ } -+ rndtest_runs_record(rsp, ones, onei); -+ rndtest_runs_record(rsp, zeros, zeroi); -+ -+ rv |= rndtest_runs_check(rsp, 0, zeroi); -+ rv |= rndtest_runs_check(rsp, 1, onei); -+ -+ if (rv) -+ rndstats.rst_runs++; -+ -+ return (rv); -+} -+ -+static void -+rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) -+{ -+ if (len == 0) -+ return; -+ if (len > RNDTEST_RUNS_NINTERVAL) -+ len = RNDTEST_RUNS_NINTERVAL; -+ len -= 1; -+ intrv[len]++; -+} -+ -+static int -+rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) -+{ -+ int i, rv = 0; -+ -+ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { -+ if (src[i] < rndtest_runs_tab[i].min || -+ src[i] > rndtest_runs_tab[i].max) { -+ rndtest_report(rsp, 1, -+ "%s interval %d failed (%d, %d-%d)", -+ val ? "ones" : "zeros", -+ i + 1, src[i], rndtest_runs_tab[i].min, -+ rndtest_runs_tab[i].max); -+ rv = -1; -+ } else { -+ rndtest_report(rsp, 0, -+ "runs pass %s interval %d (%d < %d < %d)", -+ val ? "ones" : "zeros", -+ i + 1, rndtest_runs_tab[i].min, src[i], -+ rndtest_runs_tab[i].max); -+ } -+ } -+ return (rv); -+} -+ -+static int -+rndtest_longruns(struct rndtest_state *rsp) -+{ -+ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; -+ u_int8_t c; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ zeros = 0; -+ ones++; -+ if (ones > maxones) -+ maxones = ones; -+ } else { -+ ones = 0; -+ zeros++; -+ if (zeros > maxzeros) -+ maxzeros = zeros; -+ } -+ } -+ } -+ -+ if (maxones < 26 && maxzeros < 26) { -+ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", -+ maxones, maxzeros); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", -+ maxones, maxzeros); -+ rndstats.rst_longruns++; -+ return (-1); -+ } -+} -+ -+/* -+ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, -+ * but it is really the chi^2 test over 4 bits (the poker test as described -+ * by Knuth vol 2 is something different, and I take him as authoritative -+ * on nomenclature over NIST). -+ */ -+#define RNDTEST_CHI4_K 16 -+#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) -+ -+/* -+ * The unnormalized values are used so that we don't have to worry about -+ * fractional precision. The "real" value is found by: -+ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) -+ */ -+#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ -+#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ -+ -+static int -+rndtest_chi_4(struct rndtest_state *rsp) -+{ -+ unsigned int freq[RNDTEST_CHI4_K], i, sum; -+ -+ for (i = 0; i < RNDTEST_CHI4_K; i++) -+ freq[i] = 0; -+ -+ /* Get number of occurances of each 4 bit pattern */ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; -+ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; -+ } -+ -+ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) -+ sum += freq[i] * freq[i]; -+ -+ if (sum >= 1563181 && sum <= 1576929) { -+ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); -+ rndstats.rst_chi++; -+ return (-1); -+ } -+} -+ -+int -+rndtest_buf(unsigned char *buf) -+{ -+ struct rndtest_state rsp; -+ -+ memset(&rsp, 0, sizeof(rsp)); -+ rsp.rs_buf = buf; -+ rndtest_test(&rsp); -+ return(rsp.rs_discard); -+} -+ -diff --git a/crypto/ocf/rndtest.h b/crypto/ocf/rndtest.h -new file mode 100644 -index 0000000..e9d8ec8 ---- /dev/null -+++ b/crypto/ocf/rndtest.h -@@ -0,0 +1,54 @@ -+/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ -+/* $OpenBSD$ */ -+ -+/* -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* Some of the tests depend on these values */ -+#define RNDTEST_NBYTES 2500 -+#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) -+ -+struct rndtest_state { -+ int rs_discard; /* discard/accept random data */ -+ u_int8_t *rs_buf; -+}; -+ -+struct rndtest_stats { -+ u_int32_t rst_discard; /* number of bytes discarded */ -+ u_int32_t rst_tests; /* number of test runs */ -+ u_int32_t rst_monobit; /* monobit test failures */ -+ u_int32_t rst_runs; /* 0/1 runs failures */ -+ u_int32_t rst_longruns; /* longruns failures */ -+ u_int32_t rst_chi; /* chi^2 failures */ -+}; -+ -+extern int rndtest_buf(unsigned char *buf); -diff --git a/crypto/ocf/safe/Makefile b/crypto/ocf/safe/Makefile -new file mode 100644 -index 0000000..9a36b08 ---- /dev/null -+++ b/crypto/ocf/safe/Makefile -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_SAFE) += safe.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/safe/md5.c b/crypto/ocf/safe/md5.c -new file mode 100644 -index 0000000..fa10789 ---- /dev/null -+++ b/crypto/ocf/safe/md5.c -@@ -0,0 +1,308 @@ -+/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); -+ -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) -+ -+#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) -+#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) -+#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) -+#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) -+ -+#define ROUND1(a, b, c, d, k, s, i) { \ -+ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND2(a, b, c, d, k, s, i) { \ -+ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND3(a, b, c, d, k, s, i) { \ -+ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND4(a, b, c, d, k, s, i) { \ -+ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define Sa 7 -+#define Sb 12 -+#define Sc 17 -+#define Sd 22 -+ -+#define Se 5 -+#define Sf 9 -+#define Sg 14 -+#define Sh 20 -+ -+#define Si 4 -+#define Sj 11 -+#define Sk 16 -+#define Sl 23 -+ -+#define Sm 6 -+#define Sn 10 -+#define So 15 -+#define Sp 21 -+ -+#define MD5_A0 0x67452301 -+#define MD5_B0 0xefcdab89 -+#define MD5_C0 0x98badcfe -+#define MD5_D0 0x10325476 -+ -+/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ -+static const u_int32_t T[65] = { -+ 0, -+ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, -+ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, -+ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, -+ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, -+ -+ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, -+ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, -+ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, -+ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, -+ -+ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, -+ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, -+ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, -+ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, -+ -+ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, -+ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, -+ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, -+ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, -+}; -+ -+static const u_int8_t md5_paddat[MD5_BUFLEN] = { -+ 0x80, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+}; -+ -+static void md5_calc(u_int8_t *, md5_ctxt *); -+ -+void md5_init(ctxt) -+ md5_ctxt *ctxt; -+{ -+ ctxt->md5_n = 0; -+ ctxt->md5_i = 0; -+ ctxt->md5_sta = MD5_A0; -+ ctxt->md5_stb = MD5_B0; -+ ctxt->md5_stc = MD5_C0; -+ ctxt->md5_std = MD5_D0; -+ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); -+} -+ -+void md5_loop(ctxt, input, len) -+ md5_ctxt *ctxt; -+ u_int8_t *input; -+ u_int len; /* number of bytes */ -+{ -+ u_int gap, i; -+ -+ ctxt->md5_n += len * 8; /* byte to bit */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ -+ if (len >= gap) { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ -+ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { -+ md5_calc((u_int8_t *)(input + i), ctxt); -+ } -+ -+ ctxt->md5_i = len - i; -+ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); -+ } else { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ len); -+ ctxt->md5_i += len; -+ } -+} -+ -+void md5_pad(ctxt) -+ md5_ctxt *ctxt; -+{ -+ u_int gap; -+ -+ /* Don't count up padding. Keep md5_n. */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ if (gap > 8) { -+ bcopy(md5_paddat, -+ (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap - sizeof(ctxt->md5_n)); -+ } else { -+ /* including gap == 8 */ -+ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ bcopy((md5_paddat + gap), -+ (void *)ctxt->md5_buf, -+ MD5_BUFLEN - sizeof(ctxt->md5_n)); -+ } -+ -+ /* 8 byte word */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ ctxt->md5_buf[56] = ctxt->md5_n8[7]; -+ ctxt->md5_buf[57] = ctxt->md5_n8[6]; -+ ctxt->md5_buf[58] = ctxt->md5_n8[5]; -+ ctxt->md5_buf[59] = ctxt->md5_n8[4]; -+ ctxt->md5_buf[60] = ctxt->md5_n8[3]; -+ ctxt->md5_buf[61] = ctxt->md5_n8[2]; -+ ctxt->md5_buf[62] = ctxt->md5_n8[1]; -+ ctxt->md5_buf[63] = ctxt->md5_n8[0]; -+#endif -+ -+ md5_calc(ctxt->md5_buf, ctxt); -+} -+ -+void md5_result(digest, ctxt) -+ u_int8_t *digest; -+ md5_ctxt *ctxt; -+{ -+ /* 4 byte words */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_st8[0], digest, 16); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; -+ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; -+ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; -+ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; -+ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; -+ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; -+ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; -+ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; -+#endif -+} -+ -+static void md5_calc(b64, ctxt) -+ u_int8_t *b64; -+ md5_ctxt *ctxt; -+{ -+ u_int32_t A = ctxt->md5_sta; -+ u_int32_t B = ctxt->md5_stb; -+ u_int32_t C = ctxt->md5_stc; -+ u_int32_t D = ctxt->md5_std; -+#if BYTE_ORDER == LITTLE_ENDIAN -+ u_int32_t *X = (u_int32_t *)b64; -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ /* 4 byte words */ -+ /* what a brute force but fast! */ -+ u_int32_t X[16]; -+ u_int8_t *y = (u_int8_t *)X; -+ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; -+ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; -+ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; -+ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; -+ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; -+ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; -+ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; -+ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; -+ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; -+ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; -+ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; -+ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; -+ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; -+ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; -+ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; -+ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; -+#endif -+ -+ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); -+ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); -+ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); -+ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); -+ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); -+ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); -+ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); -+ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); -+ -+ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); -+ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); -+ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); -+ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); -+ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); -+ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); -+ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); -+ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); -+ -+ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); -+ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); -+ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); -+ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); -+ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); -+ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); -+ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); -+ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); -+ -+ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); -+ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); -+ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); -+ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); -+ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); -+ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); -+ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); -+ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); -+ -+ ctxt->md5_sta += A; -+ ctxt->md5_stb += B; -+ ctxt->md5_stc += C; -+ ctxt->md5_std += D; -+} -diff --git a/crypto/ocf/safe/md5.h b/crypto/ocf/safe/md5.h -new file mode 100644 -index 0000000..690f5bf ---- /dev/null -+++ b/crypto/ocf/safe/md5.h -@@ -0,0 +1,76 @@ -+/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#ifndef _NETINET6_MD5_H_ -+#define _NETINET6_MD5_H_ -+ -+#define MD5_BUFLEN 64 -+ -+typedef struct { -+ union { -+ u_int32_t md5_state32[4]; -+ u_int8_t md5_state8[16]; -+ } md5_st; -+ -+#define md5_sta md5_st.md5_state32[0] -+#define md5_stb md5_st.md5_state32[1] -+#define md5_stc md5_st.md5_state32[2] -+#define md5_std md5_st.md5_state32[3] -+#define md5_st8 md5_st.md5_state8 -+ -+ union { -+ u_int64_t md5_count64; -+ u_int8_t md5_count8[8]; -+ } md5_count; -+#define md5_n md5_count.md5_count64 -+#define md5_n8 md5_count.md5_count8 -+ -+ u_int md5_i; -+ u_int8_t md5_buf[MD5_BUFLEN]; -+} md5_ctxt; -+ -+extern void md5_init(md5_ctxt *); -+extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); -+extern void md5_pad(md5_ctxt *); -+extern void md5_result(u_int8_t *, md5_ctxt *); -+ -+/* compatibility */ -+#define MD5_CTX md5_ctxt -+#define MD5Init(x) md5_init((x)) -+#define MD5Update(x, y, z) md5_loop((x), (y), (z)) -+#define MD5Final(x, y) \ -+do { \ -+ md5_pad((y)); \ -+ md5_result((x), (y)); \ -+} while (0) -+ -+#endif /* ! _NETINET6_MD5_H_*/ -diff --git a/crypto/ocf/safe/safe.c b/crypto/ocf/safe/safe.c -new file mode 100644 -index 0000000..87984f7 ---- /dev/null -+++ b/crypto/ocf/safe/safe.c -@@ -0,0 +1,2288 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * SafeNet SafeXcel-1141 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "safe"); \ -+ printk a; \ -+ } \ -+ } while (0) -+#else -+#define DPRINTF(a) -+#endif -+ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#define LITTLE_ENDIAN 1234 -+#define BIG_ENDIAN 4321 -+#ifdef __LITTLE_ENDIAN -+#define BYTE_ORDER LITTLE_ENDIAN -+#endif -+#ifdef __BIG_ENDIAN -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+#include -+#include -+#include -+#include -+ -+u_int8_t hmac_ipad_buffer[64] = { -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 -+}; -+ -+u_int8_t hmac_opad_buffer[64] = { -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C -+}; -+#endif /* HMAC_HACK */ -+ -+/* add proc entry for this */ -+struct safe_stats safestats; -+ -+#define debug safe_debug -+int safe_debug = 0; -+module_param(safe_debug, int, 0644); -+MODULE_PARM_DESC(safe_debug, "Enable debug"); -+ -+static void safe_callback(struct safe_softc *, struct safe_ringentry *); -+static void safe_feed(struct safe_softc *, struct safe_ringentry *); -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+static void safe_rng_init(struct safe_softc *); -+int safe_rngbufsize = 8; /* 32 bytes each read */ -+module_param(safe_rngbufsize, int, 0644); -+MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); -+int safe_rngmaxalarm = 8; /* max alarms before reset */ -+module_param(safe_rngmaxalarm, int, 0644); -+MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); -+#endif /* SAFE_NO_RNG */ -+ -+static void safe_totalreset(struct safe_softc *sc); -+static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); -+static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); -+static int safe_kstart(struct safe_softc *sc); -+static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); -+static void safe_kfeed(struct safe_softc *sc); -+static void safe_kpoll(unsigned long arg); -+static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, -+ u_int32_t len, struct crparam *n); -+ -+static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int safe_freesession(device_t, u_int64_t); -+static int safe_process(device_t, struct cryptop *, int); -+ -+static device_method_t safe_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, safe_newsession), -+ DEVMETHOD(cryptodev_freesession,safe_freesession), -+ DEVMETHOD(cryptodev_process, safe_process), -+ DEVMETHOD(cryptodev_kprocess, safe_kprocess), -+}; -+ -+#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) -+#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) -+ -+#define SAFE_MAX_CHIPS 8 -+static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; -+ -+/* -+ * split our buffers up into safe DMAable byte fragments to avoid lockup -+ * bug in 1141 HW on rev 1.0. -+ */ -+ -+static int -+pci_map_linear( -+ struct safe_softc *sc, -+ struct safe_operand *buf, -+ void *addr, -+ int len) -+{ -+ dma_addr_t tmp; -+ int chunk, tlen = len; -+ -+ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); -+ -+ buf->mapsize += len; -+ while (len > 0) { -+ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; -+ buf->segs[buf->nsegs].ds_addr = tmp; -+ buf->segs[buf->nsegs].ds_len = chunk; -+ buf->segs[buf->nsegs].ds_tlen = tlen; -+ buf->nsegs++; -+ tmp += chunk; -+ len -= chunk; -+ tlen = 0; -+ } -+ return 0; -+} -+ -+/* -+ * map in a given uio buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); -+ iov++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ pci_map_linear(sc, buf, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size); -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) { -+ if (buf->segs[i].ds_tlen) { -+ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); -+ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ } -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ buf->segs[i].ds_tlen = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+ -+/* -+ * SafeXcel Interrupt routine -+ */ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+safe_intr(int irq, void *arg) -+#else -+safe_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct safe_softc *sc = arg; -+ int stat; -+ unsigned long flags; -+ -+ stat = READ_REG(sc, SAFE_HM_STAT); -+ -+ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); -+ -+ if (stat == 0) /* shared irq, not for us */ -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ -+ -+ if ((stat & SAFE_INT_PE_DDONE)) { -+ /* -+ * Descriptor(s) done; scan the ring and -+ * process completed operations. -+ */ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ while (sc->sc_back != sc->sc_front) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ /* -+ * safe_process marks ring entries that were allocated -+ * but not used with a csr of zero. This insures the -+ * ring front pointer never needs to be set backwards -+ * in the event that an entry is allocated but not used -+ * because of a setup error. -+ */ -+ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); -+ if (re->re_desc.d_csr != 0) { -+ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { -+ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { -+ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ sc->sc_nqchip--; -+ safe_callback(sc, re); -+ } -+ if (++(sc->sc_back) == sc->sc_ringtop) -+ sc->sc_back = sc->sc_ring; -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & SAFE_INT_PE_ERROR) { -+ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), -+ (int)READ_REG(sc, SAFE_PE_DMASTAT)); -+ safestats.st_dmaerr++; -+ safe_totalreset(sc); -+#if 0 -+ safe_feed(sc); -+#endif -+ } -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+ DPRINTF(("%s: wakeup crypto %x\n", __func__, -+ sc->sc_needwakeup)); -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * safe_feed() - post a request to chip -+ */ -+static void -+safe_feed(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ sc->sc_nqchip++; -+ if (sc->sc_nqchip > safestats.st_maxqchip) -+ safestats.st_maxqchip = sc->sc_nqchip; -+ /* poke h/w to check descriptor ring, any value can be written */ -+ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); -+} -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+safe_setup_enckey(struct safe_session *ses, caddr_t key) -+{ -+ int i; -+ -+ bcopy(key, ses->ses_key, ses->ses_klen / 8); -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_key); i++) -+ ses->ses_key[i] = htole32(ses->ses_key[i]); -+} -+ -+static void -+safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#if 0 -+ /* -+ * this code prevents SHA working on a BE host, -+ * so it is obviously wrong. I think the byte -+ * swap setup we do with the chip fixes this for us -+ */ -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_hminner); i++) { -+ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); -+ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); -+ } -+#endif -+#else /* HMAC_HACK */ -+ printk("safe: md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct safe_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sidp == NULL || cri == NULL || sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ if (encini) { /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return (EINVAL); -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return (EINVAL); -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return (EINVAL); -+ break; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct safe_session *) -+ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct safe_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct safe_session *) -+ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct safe_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct safe_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct safe_session)); -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = encini->cri_klen; -+ if (encini->cri_key != NULL) -+ safe_setup_enckey(ses, encini->cri_key); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ -+ if (macini->cri_key != NULL) { -+ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+safe_freesession(device_t dev, u_int64_t tid) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = SAFE_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return (ret); -+} -+ -+ -+static int -+safe_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int err = 0, i, nicealign, uniform; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int bypass, oplen, ivsize; -+ caddr_t iv; -+ int16_t coffset; -+ struct safe_session *ses; -+ struct safe_ringentry *re; -+ struct safe_sarec *sa; -+ struct safe_pdesc *pd; -+ u_int32_t cmd0, cmd1, staterec; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ safestats.st_invalid++; -+ return (EINVAL); -+ } -+ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ safestats.st_badsession++; -+ return (EINVAL); -+ } -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { -+ safestats.st_ringfull++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (ERESTART); -+ } -+ re = sc->sc_front; -+ -+ staterec = re->re_sa.sa_staterec; /* save */ -+ /* NB: zero everything but the PE descriptor */ -+ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); -+ re->re_sa.sa_staterec = staterec; /* restore */ -+ -+ re->re_crp = crp; -+ re->re_sesn = SAFE_SESSION(crp->crp_sid); -+ -+ re->re_src.nsegs = 0; -+ re->re_dst.nsegs = 0; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ re->re_src_skb = (struct sk_buff *)crp->crp_buf; -+ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ re->re_src_io = (struct uio *)crp->crp_buf; -+ re->re_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ sa = &re->re_sa; -+ ses = &sc->sc_sessions[re->re_sesn]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ safestats.st_nodesc++; -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ -+ cmd1 = 0; -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ cmd0 |= SAFE_SA_CMD0_OP_HASH; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_NULL_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ cmd0 |= SAFE_SA_CMD0_OP_BOTH; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ safe_setup_enckey(ses, enccrd->crd_key); -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_3DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_AES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ if (ses->ses_klen == 128) -+ cmd1 |= SAFE_SA_CMD1_AES128; -+ else if (ses->ses_klen == 192) -+ cmd1 |= SAFE_SA_CMD1_AES192; -+ else -+ cmd1 |= SAFE_SA_CMD1_AES256; -+ ivsize = 4*sizeof(u_int32_t); -+ } else { -+ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; -+ ivsize = 0; -+ } -+ -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ cmd0 |= SAFE_SA_CMD0_OUTBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; -+ } else { -+ cmd0 |= SAFE_SA_CMD0_INBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, -+ re->re_sastate.sa_saved_iv, ivsize); -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)re->re_sastate.sa_saved_iv); -+ } -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; -+ } -+ /* -+ * For basic encryption use the zero pad algorithm. -+ * This pads results to an 8-byte boundary and -+ * suppresses padding verification for inbound (i.e. -+ * decrypt) operations. -+ * -+ * NB: Not sure if the 8-byte pad boundary is a problem. -+ */ -+ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; -+ -+ /* XXX assert key bufs have the same size */ -+ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); -+ } -+ -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ safe_setup_mackey(ses, maccrd->crd_alg, -+ maccrd->crd_key, maccrd->crd_klen / 8); -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_MD5; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_SHA1; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else { -+ cmd0 |= SAFE_SA_CMD0_HASH_NULL; -+ } -+ /* -+ * Digest data is loaded from the SA and the hash -+ * result is saved to the state block where we -+ * retrieve it for return to the caller. -+ */ -+ /* XXX assert digest bufs have the same size */ -+ bcopy(ses->ses_hminner, sa->sa_indigest, -+ sizeof(sa->sa_indigest)); -+ bcopy(ses->ses_hmouter, sa->sa_outdigest, -+ sizeof(sa->sa_outdigest)); -+ -+ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ bypass = maccrd->crd_skip; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ if (coffset < 0) { -+ DPRINTF(("%s: hash does not precede crypt; " -+ "mac skip %u enc skip %u\n", -+ __func__, maccrd->crd_skip, enccrd->crd_skip)); -+ safestats.st_skipmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+ oplen = enccrd->crd_skip + enccrd->crd_len; -+ if (maccrd->crd_skip + maccrd->crd_len != oplen) { -+ DPRINTF(("%s: hash amount %u != crypt amount %u\n", -+ __func__, maccrd->crd_skip + maccrd->crd_len, -+ oplen)); -+ safestats.st_lenmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+#ifdef SAFE_DEBUG -+ if (debug) { -+ printf("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, -+ maccrd->crd_inject); -+ printf("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, -+ enccrd->crd_inject); -+ printf("bypass %d coffset %d oplen %d\n", -+ bypass, coffset, oplen); -+ } -+#endif -+ if (coffset & 3) { /* offset must be 32-bit aligned */ -+ DPRINTF(("%s: coffset %u misaligned\n", -+ __func__, coffset)); -+ safestats.st_coffmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ coffset >>= 2; -+ if (coffset > 255) { /* offset must be <256 dwords */ -+ DPRINTF(("%s: coffset %u too big\n", -+ __func__, coffset)); -+ safestats.st_cofftoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Tell the hardware to copy the header to the output. -+ * The header is defined as the data from the end of -+ * the bypass to the start of data to be encrypted. -+ * Typically this is the inline IV. Note that you need -+ * to do this even if src+dst are the same; it appears -+ * that w/o this bit the crypted data is written -+ * immediately after the bypass data. -+ */ -+ cmd1 |= SAFE_SA_CMD1_HDRCOPY; -+ /* -+ * Disable IP header mutable bit handling. This is -+ * needed to get correct HMAC calculations. -+ */ -+ cmd1 |= SAFE_SA_CMD1_MUTABLE; -+ } else { -+ if (enccrd) { -+ bypass = enccrd->crd_skip; -+ oplen = bypass + enccrd->crd_len; -+ } else { -+ bypass = maccrd->crd_skip; -+ oplen = bypass + maccrd->crd_len; -+ } -+ coffset = 0; -+ } -+ /* XXX verify multiple of 4 when using s/g */ -+ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ -+ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); -+ safestats.st_bypasstoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } -+ nicealign = safe_dmamap_aligned(sc, &re->re_src); -+ uniform = safe_dmamap_uniform(sc, &re->re_src); -+ -+ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", -+ nicealign, uniform, re->re_src.nsegs)); -+ if (re->re_src.nsegs > 1) { -+ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + -+ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); -+ for (i = 0; i < re->re_src_nsegs; i++) { -+ /* NB: no need to check if there's space */ -+ pd = sc->sc_spfree; -+ if (++(sc->sc_spfree) == sc->sc_springtop) -+ sc->sc_spfree = sc->sc_spring; -+ -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus source particle descriptor; flags %x", -+ pd->pd_flags)); -+ pd->pd_addr = re->re_src_segs[i].ds_addr; -+ pd->pd_size = re->re_src_segs[i].ds_len; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_IGATHER; -+ } else { -+ /* -+ * No need for gather, reference the operand directly. -+ */ -+ re->re_desc.d_src = re->re_src_segs[0].ds_addr; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* -+ * Hash op; no destination needed. -+ */ -+ } else { -+ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { -+ if (!nicealign) { -+ safestats.st_iovmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ if (uniform != 1) { -+ device_printf(sc->sc_dev, "!uniform source\n"); -+ if (!uniform) { -+ /* -+ * There's no way to handle the DMA -+ * requirements with this uio. We -+ * could create a separate DMA area for -+ * the result and then copy it back, -+ * but for now we just bail and return -+ * an error. Note that uio requests -+ * > SAFE_MAX_DSIZE are handled because -+ * the DMA map and segment list for the -+ * destination wil result in a -+ * destination particle list that does -+ * the necessary scatter DMA. -+ */ -+ safestats.st_iovnotuniform++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else -+ re->re_dst = re->re_src; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (re->re_dst.nsegs > 1) { -+ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + -+ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); -+ for (i = 0; i < re->re_dst_nsegs; i++) { -+ pd = sc->sc_dpfree; -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus dest particle descriptor; flags %x", -+ pd->pd_flags)); -+ if (++(sc->sc_dpfree) == sc->sc_dpringtop) -+ sc->sc_dpfree = sc->sc_dpring; -+ pd->pd_addr = re->re_dst_segs[i].ds_addr; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_OSCATTER; -+ } else { -+ /* -+ * No need for scatter, reference the operand directly. -+ */ -+ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; -+ } -+ } -+ -+ /* -+ * All done with setup; fillin the SA command words -+ * and the packet engine descriptor. The operation -+ * is now ready for submission to the hardware. -+ */ -+ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; -+ sa->sa_cmd1 = cmd1 -+ | (coffset << SAFE_SA_CMD1_OFFSET_S) -+ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ -+ | SAFE_SA_CMD1_SRPCI -+ ; -+ /* -+ * NB: the order of writes is important here. In case the -+ * chip is scanning the ring because of an outstanding request -+ * it might nab this one too. In that case we need to make -+ * sure the setup is complete before we write the length -+ * field of the descriptor as it signals the descriptor is -+ * ready for processing. -+ */ -+ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; -+ if (maccrd) -+ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; -+ wmb(); -+ re->re_desc.d_len = oplen -+ | SAFE_PE_LEN_READY -+ | (bypass << SAFE_PE_LEN_BYPASS_S) -+ ; -+ -+ safestats.st_ipackets++; -+ safestats.st_ibytes += oplen; -+ -+ if (++(sc->sc_front) == sc->sc_ringtop) -+ sc->sc_front = sc->sc_ring; -+ -+ /* XXX honor batching */ -+ safe_feed(sc, re); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (0); -+ -+errout: -+ if (re->re_src.map != re->re_dst.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ if (re->re_src.map) -+ pci_unmap_operand(sc, &re->re_src); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } else { -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ } -+ return (err); -+} -+ -+static void -+safe_callback(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp = (struct cryptop *)re->re_crp; -+ struct cryptodesc *crd; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_opackets++; -+ safestats.st_obytes += re->re_dst.mapsize; -+ -+ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { -+ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", -+ re->re_desc.d_csr, -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); -+ safestats.st_peoperr++; -+ crp->crp_etype = EIO; /* something more meaningful? */ -+ } -+ -+ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ pci_unmap_operand(sc, &re->re_src); -+ -+ /* -+ * If result was written to a differet mbuf chain, swap -+ * it in as the return value and reclaim the original. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { -+ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); -+ /* kfree_skb(skb) */ -+ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ -+ return; -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { -+ /* copy out IV for future use */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int i; -+ int ivsize; -+ -+ if (crd->crd_alg == CRYPTO_DES_CBC || -+ crd->crd_alg == CRYPTO_3DES_CBC) { -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (crd->crd_alg == CRYPTO_AES_CBC) { -+ ivsize = 4*sizeof(u_int32_t); -+ } else -+ continue; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); -+ for (i = 0; -+ i < ivsize/sizeof(sc->sc_sessions[re->re_sesn].ses_iv[0]); -+ i++) -+ sc->sc_sessions[re->re_sesn].ses_iv[i] = -+ cpu_to_le32(sc->sc_sessions[re->re_sesn].ses_iv[i]); -+ break; -+ } -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { -+ /* copy out ICV result */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || -+ crd->crd_alg == CRYPTO_SHA1_HMAC || -+ crd->crd_alg == CRYPTO_NULL_HMAC)) -+ continue; -+ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { -+ /* -+ * SHA-1 ICV's are byte-swapped; fix 'em up -+ * before copy them to their destination. -+ */ -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); -+ } else { -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); -+ } -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[re->re_sesn].ses_mlen, -+ (caddr_t)re->re_sastate.sa_saved_indigest); -+ break; -+ } -+ } -+ crypto_done(crp); -+} -+ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+#define SAFE_RNG_MAXWAIT 1000 -+ -+static void -+safe_rng_init(struct safe_softc *sc) -+{ -+ u_int32_t w, v; -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, 0); -+ /* use default value according to the manual */ -+ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ /* -+ * There is a bug in rev 1.0 of the 1140 that when the RNG -+ * is brought out of reset the ready status flag does not -+ * work until the RNG has finished its internal initialization. -+ * -+ * So in order to determine the device is through its -+ * initialization we must read the data register, using the -+ * status reg in the read in case it is initialized. Then read -+ * the data register until it changes from the first read. -+ * Once it changes read the data register until it changes -+ * again. At this time the RNG is considered initialized. -+ * This could take between 750ms - 1000ms in time. -+ */ -+ i = 0; -+ w = READ_REG(sc, SAFE_RNG_OUT); -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) { -+ w = v; -+ break; -+ } -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+ -+ /* Wait Until data changes again */ -+ i = 0; -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) -+ break; -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+} -+ -+static __inline void -+safe_rng_disable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline void -+safe_rng_enable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline u_int32_t -+safe_rng_read(struct safe_softc *sc) -+{ -+ int i; -+ -+ i = 0; -+ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) -+ ; -+ return READ_REG(sc, SAFE_RNG_OUT); -+} -+ -+static int -+safe_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct safe_softc *sc = (struct safe_softc *) arg; -+ int i, rc; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_rng++; -+ /* -+ * Fetch the next block of data. -+ */ -+ if (maxwords > safe_rngbufsize) -+ maxwords = safe_rngbufsize; -+ if (maxwords > SAFE_RNG_MAXBUFSIZ) -+ maxwords = SAFE_RNG_MAXBUFSIZ; -+retry: -+ /* read as much as we can */ -+ for (rc = 0; rc < maxwords; rc++) { -+ if (READ_REG(sc, SAFE_RNG_STAT) != 0) -+ break; -+ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); -+ } -+ if (rc == 0) -+ return 0; -+ /* -+ * Check the comparator alarm count and reset the h/w if -+ * it exceeds our threshold. This guards against the -+ * hardware oscillators resonating with external signals. -+ */ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { -+ u_int32_t freq_inc, w; -+ -+ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, -+ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); -+ safestats.st_rngalarm++; -+ safe_rng_enable_short_cycle(sc); -+ freq_inc = 18; -+ for (i = 0; i < 64; i++) { -+ w = READ_REG(sc, SAFE_RNG_CNFG); -+ freq_inc = ((w + freq_inc) & 0x3fL); -+ w = ((w & ~0x3fL) | freq_inc); -+ WRITE_REG(sc, SAFE_RNG_CNFG, w); -+ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ (void) safe_rng_read(sc); -+ DELAY(25); -+ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { -+ safe_rng_disable_short_cycle(sc); -+ goto retry; -+ } -+ freq_inc = 1; -+ } -+ safe_rng_disable_short_cycle(sc); -+ } else -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ return(rc); -+} -+#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ -+ -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+safe_reset_board(struct safe_softc *sc) -+{ -+ u_int32_t v; -+ /* -+ * Reset the device. The manual says no delay -+ * is needed between marking and clearing reset. -+ */ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG) &~ -+ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | -+ SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v -+ | SAFE_PE_DMACFG_PERESET -+ | SAFE_PE_DMACFG_PDRRESET -+ | SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+safe_init_board(struct safe_softc *sc) -+{ -+ u_int32_t v, dwords; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG); -+ v &=~ ( SAFE_PE_DMACFG_PEMODE -+ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+ ); -+ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+#if 0 -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+#endif -+ ; -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+ -+#ifdef __BIG_ENDIAN -+ /* tell the safenet that we are 4321 and not 1234 */ -+ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); -+#endif -+ -+ if (sc->sc_chiprev == SAFE_REV(1,0)) { -+ /* -+ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where -+ * "target mode transfers" done while the chip is DMA'ing -+ * >1020 bytes cause the hardware to lockup. To avoid this -+ * we reduce the max PCI transfer size and use small source -+ * particle descriptors (<= 256 bytes). -+ */ -+ WRITE_REG(sc, SAFE_DMA_CFG, 256); -+ device_printf(sc->sc_dev, -+ "Reduce max DMA size to %u words for rev %u.%u WAR\n", -+ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), -+ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), -+ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); -+ sc->sc_max_dsize = 256; -+ } else { -+ sc->sc_max_dsize = SAFE_MAX_DSIZE; -+ } -+ -+ /* NB: operands+results are overlaid */ -+ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); -+ /* -+ * Configure ring entry size and number of items in the ring. -+ */ -+ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, -+ ("PE ring entry not 32-bit aligned!")); -+ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); -+ WRITE_REG(sc, SAFE_PE_RINGCFG, -+ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); -+ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ -+ -+ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_PARTSIZE, -+ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); -+ /* -+ * NB: destination particles are fixed size. We use -+ * an mbuf cluster and require all results go to -+ * clusters or smaller. -+ */ -+ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); -+ -+ /* it's now safe to enable PE mode, do it */ -+ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); -+ -+ /* -+ * Configure hardware to use level-triggered interrupts and -+ * to interrupt after each descriptor is processed. -+ */ -+ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); -+ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); -+ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); -+ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); -+} -+ -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller in splimp() -+ */ -+static void -+safe_cleanchip(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc->sc_nqchip != 0) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+ while (re != sc->sc_front) { -+ if (re->re_desc.d_csr != 0) -+ safe_free_entry(sc, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } -+ sc->sc_back = re; -+ sc->sc_nqchip = 0; -+ } -+} -+ -+/* -+ * free a safe_q -+ * It is assumed that the caller is within splimp(). -+ */ -+static int -+safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* -+ * Free header MCR -+ */ -+ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) -+#ifdef NOTYET -+ m_freem(re->re_dst_m); -+#else -+ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)re->re_crp; -+ -+ re->re_desc.d_csr = 0; -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller is in splimp() -+ */ -+static void -+safe_totalreset(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safe_reset_board(sc); -+ safe_init_board(sc); -+ safe_cleanchip(sc); -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+/* -+ * Is the operand suitable for direct DMA as the destination -+ * of an operation. The hardware requires that each ``particle'' -+ * but the last in an operation result have the same size. We -+ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns -+ * 0 if some segment is not a multiple of of this size, 1 if all -+ * segments are exactly this size, or 2 if segments are at worst -+ * a multple of this size. -+ */ -+static int -+safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int result = 1; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (op->nsegs > 0) { -+ int i; -+ -+ for (i = 0; i < op->nsegs-1; i++) { -+ if (op->segs[i].ds_len % sc->sc_max_dsize) -+ return (0); -+ if (op->segs[i].ds_len != sc->sc_max_dsize) -+ result = 2; -+ } -+ } -+ return (result); -+} -+ -+static int -+safe_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct safe_pkq *q; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) { -+ krp->krp_status = EINVAL; -+ goto err; -+ } -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ memset(q, 0, sizeof(*q)); -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ list_add_tail(&q->pkq_list, &sc->sc_pkq); -+ safe_kfeed(sc); -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+#define SAFE_CRK_PARAM_BASE 0 -+#define SAFE_CRK_PARAM_EXP 1 -+#define SAFE_CRK_PARAM_MOD 2 -+ -+static int -+safe_kstart(struct safe_softc *sc) -+{ -+ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; -+ int exp_bits, mod_bits, base_bits; -+ u_int32_t op, a_off, b_off, c_off, d_off; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { -+ krp->krp_status = EINVAL; -+ return (1); -+ } -+ -+ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ if (base_bits > 2048) -+ goto too_big; -+ if (base_bits <= 0) /* 5. base not zero */ -+ goto too_small; -+ -+ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ if (exp_bits > 2048) -+ goto too_big; -+ if (exp_bits <= 0) /* 1. exponent word length > 0 */ -+ goto too_small; /* 4. exponent not zero */ -+ -+ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ if (mod_bits > 2048) -+ goto too_big; -+ if (mod_bits <= 32) /* 2. modulus word length > 1 */ -+ goto too_small; /* 8. MSW of modulus != zero */ -+ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ -+ goto too_small; -+ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) -+ goto bad_domain; /* 6. modulus is odd */ -+ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) -+ goto too_small; /* make sure result will fit */ -+ -+ /* 7. modulus > base */ -+ if (mod_bits < base_bits) -+ goto too_small; -+ if (mod_bits == base_bits) { -+ u_int8_t *basep, *modp; -+ int i; -+ -+ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + -+ ((base_bits + 7) / 8) - 1; -+ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + -+ ((mod_bits + 7) / 8) - 1; -+ -+ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { -+ if (*modp < *basep) -+ goto too_small; -+ if (*modp > *basep) -+ break; -+ } -+ } -+ -+ /* And on the 9th step, he rested. */ -+ -+ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); -+ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); -+ if (mod_bits > 1024) { -+ op = SAFE_PK_FUNC_EXP4; -+ a_off = 0x000; -+ b_off = 0x100; -+ c_off = 0x200; -+ d_off = 0x300; -+ } else { -+ op = SAFE_PK_FUNC_EXP16; -+ a_off = 0x000; -+ b_off = 0x080; -+ c_off = 0x100; -+ d_off = 0x180; -+ } -+ sc->sc_pk_reslen = b_off - a_off; -+ sc->sc_pk_resoff = d_off; -+ -+ /* A is exponent, B is modulus, C is base, D is result */ -+ safe_kload_reg(sc, a_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); -+ safe_kload_reg(sc, b_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); -+ safe_kload_reg(sc, c_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); -+ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); -+ -+ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); -+ -+ return (0); -+ -+too_big: -+ krp->krp_status = E2BIG; -+ return (1); -+too_small: -+ krp->krp_status = ERANGE; -+ return (1); -+bad_domain: -+ krp->krp_status = EDOM; -+ return (1); -+} -+ -+static int -+safe_ksigbits(struct safe_softc *sc, struct crparam *cr) -+{ -+ u_int plen = (cr->crp_nbits + 7) / 8; -+ int i, sig = plen * 8; -+ u_int8_t c, *p = cr->crp_p; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = plen - 1; i >= 0; i--) { -+ c = p[i]; -+ if (c != 0) { -+ while ((c & 0x80) == 0) { -+ sig--; -+ c <<= 1; -+ } -+ break; -+ } -+ sig -= 8; -+ } -+ return (sig); -+} -+ -+static void -+safe_kfeed(struct safe_softc *sc) -+{ -+ struct safe_pkq *q, *tmp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) -+ return; -+ if (sc->sc_pkq_cur != NULL) -+ return; -+ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { -+ sc->sc_pkq_cur = q; -+ list_del(&q->pkq_list); -+ if (safe_kstart(sc) != 0) { -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ } else { -+ /* op started, start polling */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ break; -+ } -+ } -+} -+ -+static void -+safe_kpoll(unsigned long arg) -+{ -+ struct safe_softc *sc = NULL; -+ struct safe_pkq *q; -+ struct crparam *res; -+ int i; -+ u_int32_t buf[64]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (arg >= SAFE_MAX_CHIPS) -+ return; -+ sc = safe_chip_idx[arg]; -+ if (!sc) { -+ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); -+ return; -+ } -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ if (sc->sc_pkq_cur == NULL) -+ goto out; -+ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { -+ /* still running, check back later */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ goto out; -+ } -+ -+ q = sc->sc_pkq_cur; -+ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; -+ bzero(buf, sizeof(buf)); -+ bzero(res->crp_p, (res->crp_nbits + 7) / 8); -+ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) -+ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + -+ sc->sc_pk_resoff + (i << 2))); -+ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); -+ /* -+ * reduce the bits that need copying if possible -+ */ -+ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); -+ res->crp_nbits = safe_ksigbits(sc, res); -+ -+ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) -+ WRITE_REG(sc, i, 0); -+ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ -+ safe_kfeed(sc); -+out: -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+} -+ -+static void -+safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, -+ struct crparam *n) -+{ -+ u_int32_t buf[64], i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ bzero(buf, sizeof(buf)); -+ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); -+ -+ for (i = 0; i < len >> 2; i++) -+ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), -+ cpu_to_le32(buf[i])); -+} -+ -+#ifdef SAFE_DEBUG -+static void -+safe_dump_dmastatus(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_DMA_ENDIAN) -+ , READ_REG(sc, SAFE_DMA_SRCADDR) -+ , READ_REG(sc, SAFE_DMA_DSTADDR) -+ , READ_REG(sc, SAFE_DMA_STAT) -+ ); -+} -+ -+static void -+safe_dump_intrstate(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_HI_CFG) -+ , READ_REG(sc, SAFE_HI_MASK) -+ , READ_REG(sc, SAFE_HI_DESC_CNT) -+ , READ_REG(sc, SAFE_HU_STAT) -+ , READ_REG(sc, SAFE_HM_STAT) -+ ); -+} -+ -+static void -+safe_dump_ringstate(struct safe_softc *sc, const char *tag) -+{ -+ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); -+ -+ /* NB: assume caller has lock on ring */ -+ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", -+ tag, -+ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), -+ (unsigned long)(sc->sc_back - sc->sc_ring), -+ (unsigned long)(sc->sc_front - sc->sc_ring)); -+} -+ -+static void -+safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) -+{ -+ int ix, nsegs; -+ -+ ix = re - sc->sc_ring; -+ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" -+ , tag -+ , re, ix -+ , re->re_desc.d_csr -+ , re->re_desc.d_src -+ , re->re_desc.d_dst -+ , re->re_desc.d_sa -+ , re->re_desc.d_len -+ ); -+ if (re->re_src.nsegs > 1) { -+ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { -+ printf(" spd[%u] %p: %p size %u flags %x" -+ , ix, &sc->sc_spring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr -+ , sc->sc_spring[ix].pd_size -+ , sc->sc_spring[ix].pd_flags -+ ); -+ if (sc->sc_spring[ix].pd_size == 0) -+ printf(" (zero!)"); -+ printf("\n"); -+ if (++ix == SAFE_TOTAL_SPART) -+ ix = 0; -+ } -+ } -+ if (re->re_dst.nsegs > 1) { -+ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { -+ printf(" dpd[%u] %p: %p flags %x\n" -+ , ix, &sc->sc_dpring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr -+ , sc->sc_dpring[ix].pd_flags -+ ); -+ if (++ix == SAFE_TOTAL_DPART) -+ ix = 0; -+ } -+ } -+ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); -+ printf("sa: key %x %x %x %x %x %x %x %x\n" -+ , re->re_sa.sa_key[0] -+ , re->re_sa.sa_key[1] -+ , re->re_sa.sa_key[2] -+ , re->re_sa.sa_key[3] -+ , re->re_sa.sa_key[4] -+ , re->re_sa.sa_key[5] -+ , re->re_sa.sa_key[6] -+ , re->re_sa.sa_key[7] -+ ); -+ printf("sa: indigest %x %x %x %x %x\n" -+ , re->re_sa.sa_indigest[0] -+ , re->re_sa.sa_indigest[1] -+ , re->re_sa.sa_indigest[2] -+ , re->re_sa.sa_indigest[3] -+ , re->re_sa.sa_indigest[4] -+ ); -+ printf("sa: outdigest %x %x %x %x %x\n" -+ , re->re_sa.sa_outdigest[0] -+ , re->re_sa.sa_outdigest[1] -+ , re->re_sa.sa_outdigest[2] -+ , re->re_sa.sa_outdigest[3] -+ , re->re_sa.sa_outdigest[4] -+ ); -+ printf("sr: iv %x %x %x %x\n" -+ , re->re_sastate.sa_saved_iv[0] -+ , re->re_sastate.sa_saved_iv[1] -+ , re->re_sastate.sa_saved_iv[2] -+ , re->re_sastate.sa_saved_iv[3] -+ ); -+ printf("sr: hashbc %u indigest %x %x %x %x %x\n" -+ , re->re_sastate.sa_saved_hashbc -+ , re->re_sastate.sa_saved_indigest[0] -+ , re->re_sastate.sa_saved_indigest[1] -+ , re->re_sastate.sa_saved_indigest[2] -+ , re->re_sastate.sa_saved_indigest[3] -+ , re->re_sastate.sa_saved_indigest[4] -+ ); -+} -+ -+static void -+safe_dump_ring(struct safe_softc *sc, const char *tag) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ printf("\nSafeNet Ring State:\n"); -+ safe_dump_intrstate(sc, tag); -+ safe_dump_dmastatus(sc, tag); -+ safe_dump_ringstate(sc, tag); -+ if (sc->sc_nqchip) { -+ struct safe_ringentry *re = sc->sc_back; -+ do { -+ safe_dump_request(sc, tag, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } while (re != sc->sc_front); -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+} -+#endif /* SAFE_DEBUG */ -+ -+ -+static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct safe_softc *sc = NULL; -+ u32 mem_start, mem_len, cmd; -+ int i, rc, devinfo; -+ dma_addr_t raddr; -+ static int num_chips = 0; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("safe: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ if (pci_set_mwi(dev)) { -+ printk("safe: pci_set_mwi failed!"); -+ return(-ENODEV); -+ } -+ -+ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "safe", num_chips, safe_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_pcidev = dev; -+ if (num_chips < SAFE_MAX_CHIPS) { -+ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ INIT_LIST_HEAD(&sc->sc_pkq); -+ spin_lock_init(&sc->sc_pkmtx); -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ /* we read its hardware registers as memory */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_base_addr) { -+ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", -+ mem_start, mem_start + mem_len - 1); -+ goto out; -+ } -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto out; -+ } -+ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); -+ goto out; -+ } -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); -+ -+ if (!(cmd & PCI_COMMAND_MEMORY)) { -+ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); -+ goto out; -+ } -+ -+ if (!(cmd & PCI_COMMAND_MASTER)) { -+ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); -+ goto out; -+ } -+ -+ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); -+ goto out; -+ } -+ sc->sc_irq = dev->irq; -+ -+ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & -+ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); -+ -+ /* -+ * Allocate packet engine descriptors. -+ */ -+ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ &sc->sc_ringalloc.dma_paddr); -+ if (!sc->sc_ringalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); -+ goto out; -+ } -+ -+ /* -+ * Hookup the static portion of all our data structures. -+ */ -+ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; -+ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; -+ sc->sc_front = sc->sc_ring; -+ sc->sc_back = sc->sc_ring; -+ raddr = sc->sc_ringalloc.dma_paddr; -+ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); -+ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { -+ struct safe_ringentry *re = &sc->sc_ring[i]; -+ -+ re->re_desc.d_sa = raddr + -+ offsetof(struct safe_ringentry, re_sa); -+ re->re_sa.sa_staterec = raddr + -+ offsetof(struct safe_ringentry, re_sastate); -+ -+ raddr += sizeof (struct safe_ringentry); -+ } -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ /* -+ * Allocate scatter and gather particle descriptors. -+ */ -+ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), -+ &sc->sc_spalloc.dma_paddr); -+ if (!sc->sc_spalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; -+ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; -+ sc->sc_spfree = sc->sc_spring; -+ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ &sc->sc_dpalloc.dma_paddr); -+ if (!sc->sc_dpalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; -+ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; -+ sc->sc_dpfree = sc->sc_dpring; -+ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto out; -+ } -+ -+ printf("%s:", device_get_nameunit(sc->sc_dev)); -+ -+ devinfo = READ_REG(sc, SAFE_DEVINFO); -+ if (devinfo & SAFE_DEVINFO_RNG) { -+ sc->sc_flags |= SAFE_FLAGS_RNG; -+ printf(" rng"); -+ } -+ if (devinfo & SAFE_DEVINFO_PKEY) { -+ printf(" key"); -+ sc->sc_flags |= SAFE_FLAGS_KEY; -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); -+#if 0 -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); -+#endif -+ init_timer(&sc->sc_pkto); -+ sc->sc_pkto.function = safe_kpoll; -+ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); -+ } -+ if (devinfo & SAFE_DEVINFO_DES) { -+ printf(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_AES) { -+ printf(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_MD5) { -+ printf(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_SHA1) { -+ printf(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printf(" null"); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); -+ /* XXX other supported algorithms */ -+ printf("\n"); -+ -+ safe_reset_board(sc); /* reset h/w */ -+ safe_init_board(sc); /* init h/w */ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+ if (sc->sc_flags & SAFE_FLAGS_RNG) { -+ safe_rng_init(sc); -+ crypto_rregister(sc->sc_cid, safe_read_random, sc); -+ } -+#endif /* SAFE_NO_RNG */ -+ -+ return (0); -+ -+out: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ kfree(sc); -+ return(-ENODEV); -+} -+ -+static void safe_remove(struct pci_dev *dev) -+{ -+ struct safe_softc *sc = pci_get_drvdata(dev); -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* XXX wait/abort active ops */ -+ -+ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ -+ -+ del_timer_sync(&sc->sc_pkto); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ safe_cleanchip(sc); -+ -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ sc->sc_irq = -1; -+ sc->sc_ringalloc.dma_vaddr = NULL; -+ sc->sc_spalloc.dma_vaddr = NULL; -+ sc->sc_dpalloc.dma_vaddr = NULL; -+} -+ -+static struct pci_device_id safe_pci_tbl[] = { -+ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(pci, safe_pci_tbl); -+ -+static struct pci_driver safe_driver = { -+ .name = "safe", -+ .id_table = safe_pci_tbl, -+ .probe = safe_probe, -+ .remove = safe_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init safe_init (void) -+{ -+ struct safe_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); -+ -+ rc = pci_register_driver(&safe_driver); -+ pci_register_driver_compat(&safe_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit safe_exit (void) -+{ -+ pci_unregister_driver(&safe_driver); -+} -+ -+module_init(safe_init); -+module_exit(safe_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); -diff --git a/crypto/ocf/safe/safereg.h b/crypto/ocf/safe/safereg.h -new file mode 100644 -index 0000000..d3461f9 ---- /dev/null -+++ b/crypto/ocf/safe/safereg.h -@@ -0,0 +1,421 @@ -+/*- -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ -+ */ -+#ifndef _SAFE_SAFEREG_H_ -+#define _SAFE_SAFEREG_H_ -+ -+/* -+ * Register definitions for SafeNet SafeXcel-1141 crypto device. -+ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ -+ -+/* SafeNet */ -+#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ -+ -+#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ -+#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ -+#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ -+#define SAFE_PE_SA 0x000c /* Packet Engine SA */ -+#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ -+#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ -+#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ -+#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ -+#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ -+#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ -+#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ -+#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ -+#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ -+#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ -+#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ -+#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ -+#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ -+#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ -+#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ -+#define SAFE_DEVID 0x0084 /* Device ID */ -+#define SAFE_DEVINFO 0x0088 /* Device Info */ -+#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ -+#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ -+#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ -+#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ -+#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ -+#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ -+#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ -+#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ -+#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ -+#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ -+#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ -+#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ -+#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ -+#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ -+#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ -+#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ -+#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ -+#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ -+#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ -+#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ -+#define SAFE_PK_FUNC 0x081c /* Public Key Function */ -+#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ -+#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ -+ -+#define SAFE_RNG_OUT 0x0100 /* RNG Output */ -+#define SAFE_RNG_STAT 0x0104 /* RNG Status */ -+#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ -+#define SAFE_RNG_A 0x010c /* RNG A */ -+#define SAFE_RNG_B 0x0110 /* RNG B */ -+#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ -+#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ -+#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ -+#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ -+#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ -+#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ -+#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ -+#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ -+ -+#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ -+#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ -+#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ -+#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ -+#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ -+#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ -+#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ -+#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ -+#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ -+#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ -+#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ -+#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ -+#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ -+#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ -+#define SAFE_PE_CSR_XECODE_S 20 -+#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ -+#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ -+#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ -+#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ -+#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ -+#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ -+#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ -+#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ -+#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ -+#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ -+#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ -+#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ -+#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ -+#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ -+#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ -+ -+/* -+ * Check the CSR to see if the PE has returned ownership to -+ * the host. Note that before processing a descriptor this -+ * must be done followed by a check of the SAFE_PE_LEN register -+ * status bits to avoid premature processing of a descriptor -+ * on its way back to the host. -+ */ -+#define SAFE_PE_CSR_IS_DONE(_csr) \ -+ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) -+ -+#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ -+#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ -+#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ -+#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ -+#define SAFE_PE_LEN_BYPASS_S 24 -+ -+#define SAFE_PE_LEN_IS_DONE(_len) \ -+ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) -+ -+/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ -+#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ -+#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ -+#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ -+#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ -+ -+#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ -+#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ -+#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ -+ -+#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ -+#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ -+ -+#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ -+#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ -+#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ -+#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ -+#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ -+#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ -+#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ -+#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ -+#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ -+#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ -+#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ -+#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ -+#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ -+#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ -+#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ -+#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ -+#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ -+ -+#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ -+#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ -+#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ -+#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ -+#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ -+#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ -+#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ -+#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ -+#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ -+#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ -+#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ -+#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ -+#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ -+#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ -+ -+#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ -+#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ -+#define SAFE_PE_RINGCFG_OFFSET_S 16 -+ -+#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ -+ -+#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ -+ -+#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ -+#define SAFE_PE_ERNGSTAT_NEXT_S 16 -+ -+#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ -+#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ -+ -+#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ -+#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ -+#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 -+#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 -+#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 -+#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ -+#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 -+#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 -+#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 -+ -+#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ -+#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ -+ -+#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ -+#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ -+#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ -+ -+#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ_S 4 -+#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ -+#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ -+#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ -+#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ -+#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ -+#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ -+#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ -+#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ -+#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ -+#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ -+#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ -+ -+#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) -+#define SAFE_REV_MAJ(_chiprev) \ -+ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) -+#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) -+ -+#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ -+#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ -+#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ -+#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ -+#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ -+#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ -+#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ -+#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ -+#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ -+#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ -+#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ -+#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ -+ -+#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ -+ -+#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ -+#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ -+#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ -+#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ -+#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ -+#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ -+#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ -+#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ -+#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ -+#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ -+ -+/* -+ * Packet engine descriptor. Note that d_csr is a copy of the -+ * SAFE_PE_CSR register and all definitions apply, and d_len -+ * is a copy of the SAFE_PE_LEN register and all definitions apply. -+ * d_src and d_len may point directly to contiguous data or to a -+ * list of ``particle descriptors'' when using scatter/gather i/o. -+ */ -+struct safe_desc { -+ u_int32_t d_csr; /* per-packet control/status */ -+ u_int32_t d_src; /* source address */ -+ u_int32_t d_dst; /* destination address */ -+ u_int32_t d_sa; /* SA address */ -+ u_int32_t d_len; /* length, bypass, status */ -+}; -+ -+/* -+ * Scatter/Gather particle descriptor. -+ * -+ * NB: scatter descriptors do not specify a size; this is fixed -+ * by the setting of the SAFE_PE_PARTCFG register. -+ */ -+struct safe_pdesc { -+ u_int32_t pd_addr; /* particle address */ -+#ifdef __BIG_ENDIAN -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#else -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#endif -+}; -+ -+#define SAFE_PD_READY 0x0001 /* ready for processing */ -+#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ -+ -+/* -+ * Security Association (SA) Record (Rev 1). One of these is -+ * required for each operation processed by the packet engine. -+ */ -+struct safe_sarec { -+ u_int32_t sa_cmd0; -+ u_int32_t sa_cmd1; -+ u_int32_t sa_resv0; -+ u_int32_t sa_resv1; -+ u_int32_t sa_key[8]; /* DES/3DES/AES key */ -+ u_int32_t sa_indigest[5]; /* inner digest */ -+ u_int32_t sa_outdigest[5]; /* outer digest */ -+ u_int32_t sa_spi; /* SPI */ -+ u_int32_t sa_seqnum; /* sequence number */ -+ u_int32_t sa_seqmask[2]; /* sequence number mask */ -+ u_int32_t sa_resv2; -+ u_int32_t sa_staterec; /* address of state record */ -+ u_int32_t sa_resv3[2]; -+ u_int32_t sa_samgmt0; /* SA management field 0 */ -+ u_int32_t sa_samgmt1; /* SA management field 0 */ -+}; -+ -+#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ -+#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ -+#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ -+#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ -+#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ -+#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ -+#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ -+#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ -+#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ -+#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ -+#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ -+#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ -+#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ -+#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ -+#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ -+#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ -+#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ -+#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ -+#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ -+#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ -+#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ -+#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ -+#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ -+#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ -+#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ -+#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ -+#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ -+#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ -+#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ -+#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ -+#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ -+#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ -+#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ -+#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ -+#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ -+#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ -+#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ -+#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ -+#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ -+#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ -+#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ -+#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ -+#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ -+ -+#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ -+#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ -+#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ -+#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ -+#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ -+#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ -+#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ -+#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ -+#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ -+#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ -+#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ -+#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ -+#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ -+#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ -+#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ -+#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ -+#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ -+#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ -+#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ -+#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS -+#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ -+#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ -+#define SAFE_SA_CMD1_OFFSET_S 16 -+#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ -+#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ -+#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ -+#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ -+ -+/* -+ * Security Associate State Record (Rev 1). -+ */ -+struct safe_sastate { -+ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ -+ u_int32_t sa_saved_hashbc; /* saved hash byte count */ -+ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ -+}; -+#endif /* _SAFE_SAFEREG_H_ */ -diff --git a/crypto/ocf/safe/safevar.h b/crypto/ocf/safe/safevar.h -new file mode 100644 -index 0000000..9039a5d ---- /dev/null -+++ b/crypto/ocf/safe/safevar.h -@@ -0,0 +1,230 @@ -+/*- -+ * The linux port of this code done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ -+ */ -+#ifndef _SAFE_SAFEVAR_H_ -+#define _SAFE_SAFEVAR_H_ -+ -+/* Maximum queue length */ -+#ifndef SAFE_MAX_NQUEUE -+#define SAFE_MAX_NQUEUE 60 -+#endif -+ -+#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ -+#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ -+#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ -+#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ -+#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ -+/* total src+dst particle descriptors */ -+#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+ -+#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ -+ -+#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) -+#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#ifdef __KERNEL__ -+/* -+ * State associated with the allocation of each chunk -+ * of memory setup for DMA. -+ */ -+struct safe_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+}; -+ -+/* -+ * Cryptographic operand state. One of these exists for each -+ * source and destination operand passed in from the crypto -+ * subsystem. When possible source and destination operands -+ * refer to the same memory. More often they are distinct. -+ * We track the virtual address of each operand as well as -+ * where each is mapped for DMA. -+ */ -+struct safe_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ } u; -+ void *map; -+ int mapsize; /* total number of bytes in segs */ -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ int ds_tlen; -+ } segs[SAFE_MAX_PART]; -+ int nsegs; -+}; -+ -+/* -+ * Packet engine ring entry and cryptographic operation state. -+ * The packet engine requires a ring of descriptors that contain -+ * pointers to various cryptographic state. However the ring -+ * configuration register allows you to specify an arbitrary size -+ * for ring entries. We use this feature to collect most of the -+ * state for each cryptographic request into one spot. Other than -+ * ring entries only the ``particle descriptors'' (scatter/gather -+ * lists) and the actual operand data are kept separate. The -+ * particle descriptors must also be organized in rings. The -+ * operand data can be located aribtrarily (modulo alignment constraints). -+ * -+ * Note that the descriptor ring is mapped onto the PCI bus so -+ * the hardware can DMA data. This means the entire ring must be -+ * contiguous. -+ */ -+struct safe_ringentry { -+ struct safe_desc re_desc; /* command descriptor */ -+ struct safe_sarec re_sa; /* SA record */ -+ struct safe_sastate re_sastate; /* SA state record */ -+ -+ struct cryptop *re_crp; /* crypto operation */ -+ -+ struct safe_operand re_src; /* source operand */ -+ struct safe_operand re_dst; /* destination operand */ -+ -+ int re_sesn; /* crypto session ID */ -+ int re_flags; -+#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ -+#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ -+}; -+ -+#define re_src_skb re_src.u.skb -+#define re_src_io re_src.u.io -+#define re_src_map re_src.map -+#define re_src_nsegs re_src.nsegs -+#define re_src_segs re_src.segs -+#define re_src_mapsize re_src.mapsize -+ -+#define re_dst_skb re_dst.u.skb -+#define re_dst_io re_dst.u.io -+#define re_dst_map re_dst.map -+#define re_dst_nsegs re_dst.nsegs -+#define re_dst_segs re_dst.segs -+#define re_dst_mapsize re_dst.mapsize -+ -+struct rndstate_test; -+ -+struct safe_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_mlen; /* hmac length in bytes */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+}; -+ -+struct safe_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+}; -+ -+struct safe_softc { -+ softc_device_decl sc_dev; -+ u32 sc_irq; -+ -+ struct pci_dev *sc_pcidev; -+ ocf_iomem_t sc_base_addr; -+ -+ u_int sc_chiprev; /* major/minor chip revision */ -+ int sc_flags; /* device specific flags */ -+#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ -+#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ -+ int sc_suspended; -+ int sc_needwakeup; /* notify crypto layer */ -+ int32_t sc_cid; /* crypto tag */ -+ -+ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ -+ struct safe_ringentry *sc_ring; /* PE ring */ -+ struct safe_ringentry *sc_ringtop; /* PE ring top */ -+ struct safe_ringentry *sc_front; /* next free entry */ -+ struct safe_ringentry *sc_back; /* next pending entry */ -+ int sc_nqchip; /* # passed to chip */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+ struct safe_pdesc *sc_spring; /* src particle ring */ -+ struct safe_pdesc *sc_springtop; /* src particle ring top */ -+ struct safe_pdesc *sc_spfree; /* next free src particle */ -+ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ -+ struct safe_pdesc *sc_dpring; /* dest particle ring */ -+ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ -+ struct safe_pdesc *sc_dpfree; /* next free dest particle */ -+ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ -+ int sc_nsessions; /* # of sessions */ -+ struct safe_session *sc_sessions; /* sessions */ -+ -+ struct timer_list sc_pkto; /* PK polling */ -+ spinlock_t sc_pkmtx; /* PK lock */ -+ struct list_head sc_pkq; /* queue of PK requests */ -+ struct safe_pkq *sc_pkq_cur; /* current processing request */ -+ u_int32_t sc_pk_reslen, sc_pk_resoff; -+ -+ int sc_max_dsize; /* maximum safe DMA size */ -+}; -+#endif /* __KERNEL__ */ -+ -+struct safe_stats { -+ u_int64_t st_ibytes; -+ u_int64_t st_obytes; -+ u_int32_t st_ipackets; -+ u_int32_t st_opackets; -+ u_int32_t st_invalid; /* invalid argument */ -+ u_int32_t st_badsession; /* invalid session id */ -+ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ -+ u_int32_t st_nodesc; /* op submitted w/o descriptors */ -+ u_int32_t st_badalg; /* unsupported algorithm */ -+ u_int32_t st_ringfull; /* PE descriptor ring full */ -+ u_int32_t st_peoperr; /* PE marked error */ -+ u_int32_t st_dmaerr; /* PE DMA error */ -+ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ -+ u_int32_t st_skipmismatch; /* enc part begins before auth part */ -+ u_int32_t st_lenmismatch; /* enc length different auth length */ -+ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ -+ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ -+ u_int32_t st_iovmisaligned; /* iov op not aligned */ -+ u_int32_t st_iovnotuniform; /* iov op not suitable */ -+ u_int32_t st_unaligned; /* unaligned src caused copy */ -+ u_int32_t st_notuniform; /* non-uniform src caused copy */ -+ u_int32_t st_nomap; /* bus_dmamap_create failed */ -+ u_int32_t st_noload; /* bus_dmamap_load_* failed */ -+ u_int32_t st_nombuf; /* MGET* failed */ -+ u_int32_t st_nomcl; /* MCLGET* failed */ -+ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ -+ u_int32_t st_rng; /* RNG requests */ -+ u_int32_t st_rngalarm; /* RNG alarm requests */ -+ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ -+}; -+#endif /* _SAFE_SAFEVAR_H_ */ -diff --git a/crypto/ocf/safe/sha1.c b/crypto/ocf/safe/sha1.c -new file mode 100644 -index 0000000..4e360e2 ---- /dev/null -+++ b/crypto/ocf/safe/sha1.c -@@ -0,0 +1,279 @@ -+/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); -+ -+#include -+#include -+#include -+#include -+ -+#include -+#endif -+ -+/* sanity check */ -+#if BYTE_ORDER != BIG_ENDIAN -+# if BYTE_ORDER != LITTLE_ENDIAN -+# define unsupported 1 -+# endif -+#endif -+ -+#ifndef unsupported -+ -+/* constant table */ -+static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; -+#define K(t) _K[(t) / 20] -+ -+#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) -+#define F1(b, c, d) (((b) ^ (c)) ^ (d)) -+#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) -+#define F3(b, c, d) (((b) ^ (c)) ^ (d)) -+ -+#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) -+ -+#undef H -+#define H(n) (ctxt->h.b32[(n)]) -+#define COUNT (ctxt->count) -+#define BCOUNT (ctxt->c.b64[0] / 8) -+#define W(n) (ctxt->m.b32[(n)]) -+ -+#define PUTBYTE(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ ctxt->c.b64[0] += 8; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+#define PUTPAD(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+static void sha1_step(struct sha1_ctxt *); -+ -+static void -+sha1_step(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ u_int32_t a, b, c, d, e; -+ size_t t, s; -+ u_int32_t tmp; -+ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ struct sha1_ctxt tctxt; -+ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); -+ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; -+ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; -+ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; -+ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; -+ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; -+ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; -+ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; -+ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; -+ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; -+ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; -+ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; -+ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; -+ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; -+ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; -+ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; -+ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; -+ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; -+ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; -+ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; -+ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; -+ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; -+ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; -+ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; -+ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; -+ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; -+ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; -+ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; -+ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; -+ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; -+ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; -+ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; -+ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; -+#endif -+ -+ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); -+ -+ for (t = 0; t < 20; t++) { -+ s = t & 0x0f; -+ if (t >= 16) { -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ } -+ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 20; t < 40; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 40; t < 60; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 60; t < 80; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ -+ H(0) = H(0) + a; -+ H(1) = H(1) + b; -+ H(2) = H(2) + c; -+ H(3) = H(3) + d; -+ H(4) = H(4) + e; -+ -+ bzero(&ctxt->m.b8[0], 64); -+} -+ -+/*------------------------------------------------------------*/ -+ -+void -+sha1_init(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ bzero(ctxt, sizeof(struct sha1_ctxt)); -+ H(0) = 0x67452301; -+ H(1) = 0xefcdab89; -+ H(2) = 0x98badcfe; -+ H(3) = 0x10325476; -+ H(4) = 0xc3d2e1f0; -+} -+ -+void -+sha1_pad(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ size_t padlen; /*pad length in bytes*/ -+ size_t padstart; -+ -+ PUTPAD(0x80); -+ -+ padstart = COUNT % 64; -+ padlen = 64 - padstart; -+ if (padlen < 8) { -+ bzero(&ctxt->m.b8[padstart], padlen); -+ COUNT += padlen; -+ COUNT %= 64; -+ sha1_step(ctxt); -+ padstart = COUNT % 64; /* should be 0 */ -+ padlen = 64 - padstart; /* should be 64 */ -+ } -+ bzero(&ctxt->m.b8[padstart], padlen - 8); -+ COUNT += (padlen - 8); -+ COUNT %= 64; -+#if BYTE_ORDER == BIG_ENDIAN -+ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); -+ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); -+ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); -+ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); -+#else -+ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); -+ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); -+ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); -+ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); -+#endif -+} -+ -+void -+sha1_loop(ctxt, input, len) -+ struct sha1_ctxt *ctxt; -+ const u_int8_t *input; -+ size_t len; -+{ -+ size_t gaplen; -+ size_t gapstart; -+ size_t off; -+ size_t copysiz; -+ -+ off = 0; -+ -+ while (off < len) { -+ gapstart = COUNT % 64; -+ gaplen = 64 - gapstart; -+ -+ copysiz = (gaplen < len - off) ? gaplen : len - off; -+ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); -+ COUNT += copysiz; -+ COUNT %= 64; -+ ctxt->c.b64[0] += copysiz * 8; -+ if (COUNT % 64 == 0) -+ sha1_step(ctxt); -+ off += copysiz; -+ } -+} -+ -+void -+sha1_result(ctxt, digest0) -+ struct sha1_ctxt *ctxt; -+ caddr_t digest0; -+{ -+ u_int8_t *digest; -+ -+ digest = (u_int8_t *)digest0; -+ sha1_pad(ctxt); -+#if BYTE_ORDER == BIG_ENDIAN -+ bcopy(&ctxt->h.b8[0], digest, 20); -+#else -+ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; -+ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; -+ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; -+ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; -+ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; -+ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; -+ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; -+ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; -+ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; -+ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; -+#endif -+} -+ -+#endif /*unsupported*/ -diff --git a/crypto/ocf/safe/sha1.h b/crypto/ocf/safe/sha1.h -new file mode 100644 -index 0000000..0e19d90 ---- /dev/null -+++ b/crypto/ocf/safe/sha1.h -@@ -0,0 +1,72 @@ -+/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#ifndef _NETINET6_SHA1_H_ -+#define _NETINET6_SHA1_H_ -+ -+struct sha1_ctxt { -+ union { -+ u_int8_t b8[20]; -+ u_int32_t b32[5]; -+ } h; -+ union { -+ u_int8_t b8[8]; -+ u_int64_t b64[1]; -+ } c; -+ union { -+ u_int8_t b8[64]; -+ u_int32_t b32[16]; -+ } m; -+ u_int8_t count; -+}; -+ -+#ifdef __KERNEL__ -+extern void sha1_init(struct sha1_ctxt *); -+extern void sha1_pad(struct sha1_ctxt *); -+extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); -+extern void sha1_result(struct sha1_ctxt *, caddr_t); -+ -+/* compatibilty with other SHA1 source codes */ -+typedef struct sha1_ctxt SHA1_CTX; -+#define SHA1Init(x) sha1_init((x)) -+#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) -+#define SHA1Final(x, y) sha1_result((y), (x)) -+#endif /* __KERNEL__ */ -+ -+#define SHA1_RESULTLEN (160/8) -+ -+#endif /*_NETINET6_SHA1_H_*/ -diff --git a/crypto/ocf/talitos/Makefile b/crypto/ocf/talitos/Makefile -new file mode 100644 -index 0000000..2591b8a ---- /dev/null -+++ b/crypto/ocf/talitos/Makefile -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_TALITOS) += talitos.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff --git a/crypto/ocf/talitos/talitos.c b/crypto/ocf/talitos/talitos.c -new file mode 100644 -index 0000000..0cef3bd ---- /dev/null -+++ b/crypto/ocf/talitos/talitos.c -@@ -0,0 +1,1359 @@ -+/* -+ * crypto/ocf/talitos/talitos.c -+ * -+ * An OCF-Linux module that uses Freescale's SEC to do the crypto. -+ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * This code written by Kim A. B. Phillips -+ * some code copied from files with the following: -+ * Copyright (C) 2004-2007 David McCullough -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * --------------------------------------------------------------------------- -+ * -+ * NOTES: -+ * -+ * The Freescale SEC (also known as 'talitos') resides on the -+ * internal bus, and runs asynchronous to the processor core. It has -+ * a wide gamut of cryptographic acceleration features, including single- -+ * pass IPsec (also known as algorithm chaining). To properly utilize -+ * all of the SEC's performance enhancing features, further reworking -+ * of higher level code (framework, applications) will be necessary. -+ * -+ * The following table shows which SEC version is present in which devices: -+ * -+ * Devices SEC version -+ * -+ * 8272, 8248 SEC 1.0 -+ * 885, 875 SEC 1.2 -+ * 8555E, 8541E SEC 2.0 -+ * 8349E SEC 2.01 -+ * 8548E SEC 2.1 -+ * -+ * The following table shows the features offered by each SEC version: -+ * -+ * Max. chan- -+ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU -+ * -+ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 -+ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 -+ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 -+ * -+ * Each execution unit in the SEC has two modes of execution; channel and -+ * slave/debug. This driver employs the channel infrastructure in the -+ * device for convenience. Only the RNG is directly accessed due to the -+ * convenience of its random fifo pool. The relationship between the -+ * channels and execution units is depicted in the following diagram: -+ * -+ * ------- ------------ -+ * ---| ch0 |---| | -+ * ------- | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | | | | | | -+ * ---| ch1 |---| | | | | | | -+ * ------- | | ------ ------ ------ ------ ------ -+ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | -+ * ------- | | ------ ------ ------ ------ ------ -+ * ---| ch2 |---| | | | | | | -+ * ------- | | | | | | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | -+ * ---| ch3 |---| | -+ * ------- ------------ -+ * -+ * Channel ch0 may drive an aes operation to the aes unit (AESU), -+ * and, at the same time, ch1 may drive a message digest operation -+ * to the mdeu. Each channel has an input descriptor FIFO, and the -+ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a -+ * a buffer overrun error is triggered. The controller is responsible -+ * for fetching the data from descriptor pointers, and passing the -+ * data to the appropriate EUs. The controller also writes the -+ * cryptographic operation's result to memory. The SEC notifies -+ * completion by triggering an interrupt and/or setting the 1st byte -+ * of the hdr field to 0xff. -+ * -+ * TODO: -+ * o support more algorithms -+ * o support more versions of the SEC -+ * o add support for linux 2.4 -+ * o scatter-gather (sg) support -+ * o add support for public key ops (PKEU) -+ * o add statistics -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* dma_map_single() */ -+#include -+ -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) -+#include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+#include -+#endif -+ -+#include -+#include -+ -+#define DRV_NAME "talitos" -+ -+#include "talitos_dev.h" -+#include "talitos_soft.h" -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+const char talitos_driver_name[] = "Talitos OCF"; -+const char talitos_driver_version[] = "0.2"; -+ -+static int talitos_newsession(device_t dev, u_int32_t *sidp, -+ struct cryptoini *cri); -+static int talitos_freesession(device_t dev, u_int64_t tid); -+static int talitos_process(device_t dev, struct cryptop *crp, int hint); -+static void dump_talitos_status(struct talitos_softc *sc); -+static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, -+ int chsel); -+static void talitos_doneprocessing(struct talitos_softc *sc); -+static void talitos_init_device(struct talitos_softc *sc); -+static void talitos_reset_device_master(struct talitos_softc *sc); -+static void talitos_reset_device(struct talitos_softc *sc); -+static void talitos_errorprocessing(struct talitos_softc *sc); -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); -+static int talitos_remove(struct of_device *ofdev); -+#else -+static int talitos_probe(struct platform_device *pdev); -+static int talitos_remove(struct platform_device *pdev); -+#endif -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); -+static void talitos_rng_init(struct talitos_softc *sc); -+#endif -+ -+static device_method_t talitos_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, talitos_newsession), -+ DEVMETHOD(cryptodev_freesession,talitos_freesession), -+ DEVMETHOD(cryptodev_process, talitos_process), -+}; -+ -+#define debug talitos_debug -+int talitos_debug = 0; -+module_param(talitos_debug, int, 0644); -+MODULE_PARM_DESC(talitos_debug, "Enable debug"); -+ -+static inline void talitos_write(volatile unsigned *addr, u32 val) -+{ -+ out_be32(addr, val); -+} -+ -+static inline u32 talitos_read(volatile unsigned *addr) -+{ -+ u32 val; -+ val = in_be32(addr); -+ return val; -+} -+ -+static void dump_talitos_status(struct talitos_softc *sc) -+{ -+ unsigned int v, v_hi, i, *ptr; -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); -+ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR_HI); -+ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR_HI); -+ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; -+ for (i = 0; i < 16; i++) { -+ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); -+ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi, i); -+ } -+ return; -+} -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * pull random numbers off the RNG FIFO, not exceeding amount available -+ */ -+static int -+talitos_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct talitos_softc *sc = (struct talitos_softc *) arg; -+ int rc; -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* check for things like FIFO underflow */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (unlikely(v)) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return 0; -+ } -+ /* -+ * OFL is number of available 64-bit words, -+ * shift and convert to a 32-bit word count -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); -+ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); -+ if (maxwords > v) -+ maxwords = v; -+ for (rc = 0; rc < maxwords; rc++) { -+ buf[rc] = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ if (maxwords & 1) { -+ /* -+ * RNG will complain with an AE in the RNGISR -+ * if we don't complete the pairs of 32-bit reads -+ * to its 64-bit register based FIFO -+ */ -+ v = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ -+ return rc; -+} -+ -+static void -+talitos_rng_init(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* reset RNG EU */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); -+ v |= TALITOS_RNGRCR_HI_SR; -+ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); -+ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) -+ & TALITOS_RNGSR_HI_RD) == 0) -+ cpu_relax(); -+ /* -+ * we tell the RNG to start filling the RNG FIFO -+ * by writing the RNGDSR -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); -+ /* -+ * 64 bits of data will be pushed onto the FIFO every -+ * 256 SEC cycles until the FIFO is full. The RNG then -+ * attempts to keep the FIFO full. -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (v) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return; -+ } -+ /* -+ * n.b. we need to add a FIPS test here - if the RNG is going -+ * to fail, it's going to fail at reset time -+ */ -+ return; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct talitos_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5 || -+ c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1 || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return EINVAL; -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return EINVAL; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) { -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return EINVAL; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct talitos_session *) -+ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, sizeof(struct talitos_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ /* allocating session */ -+ sesn = sc->sc_nsessions; -+ ses = (struct talitos_session *) kmalloc( -+ (sesn + 1) * sizeof(struct talitos_session), -+ SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, -+ (sesn + 1) * sizeof(struct talitos_session)); -+ memcpy(ses, sc->sc_sessions, -+ sesn * sizeof(struct talitos_session)); -+ memset(sc->sc_sessions, 0, -+ sesn * sizeof(struct talitos_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = (encini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); -+ if (macini) { -+ /* doing hash on top of cipher */ -+ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_hmac, macini->cri_key, -+ ses->ses_hmac_len); -+ } -+ } else if (macini) { -+ /* doing hash */ -+ ses->ses_klen = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); -+ } -+ -+ /* back compat way of determining MSC result len */ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ } -+ -+ /* really should make up a template td here, -+ * and only fill things like i/o and direction in process() */ -+ -+ /* assign session ID */ -+ *sidp = TALITOS_SID(sc->sc_num, sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+talitos_freesession(device_t dev, u_int64_t tid) -+{ -+ struct talitos_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ if (sc == NULL) -+ return EINVAL; -+ session = TALITOS_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ memset(&sc->sc_sessions[session], 0, -+ sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return ret; -+} -+ -+/* -+ * launch device processing - it will come back with done notification -+ * in the form of an interrupt and/or HDR_DONE_BITS in header -+ */ -+static int -+talitos_submit( -+ struct talitos_softc *sc, -+ struct talitos_desc *td, -+ int chsel) -+{ -+ u_int32_t v; -+ -+ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); -+ return 0; -+} -+ -+static int -+talitos_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ int i, err = 0, ivsize; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t iv; -+ struct talitos_session *ses; -+ struct talitos_desc *td; -+ unsigned long flags; -+ /* descriptor mappings */ -+ int hmac_key, hmac_data, cipher_iv, cipher_key, -+ in_fifo, out_fifo, cipher_iv_out; -+ static int chsel = -1; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ return EINVAL; -+ } -+ crp->crp_etype = 0; -+ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ return EINVAL; -+ } -+ -+ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* reuse channel that already had/has requests for the required EU */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) -+ break; -+ } -+ if (i == sc->sc_num_channels) { -+ /* -+ * haven't seen this algo the last sc_num_channels or more -+ * use round robin in this case -+ * nb: sc->sc_num_channels must be power of 2 -+ */ -+ chsel = (chsel + 1) & (sc->sc_num_channels - 1); -+ } else { -+ /* -+ * matches channel with same target execution unit; -+ * use same channel in this case -+ */ -+ chsel = i; -+ } -+ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; -+ -+ /* release the channel scheduler lock */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* acquire the selected channel fifo lock */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); -+ -+ /* find and reserve next available descriptor-cryptop pair */ -+ for (i = 0; i < sc->sc_chfifo_len; i++) { -+ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { -+ /* -+ * ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 for MD/HMAC descs -+ */ -+ memset(&sc->sc_chnfifo[chsel][i].cf_desc, -+ 0, sizeof(*td)); -+ /* reserve it with done notification request bit */ -+ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= -+ TALITOS_DONE_NOTIFY; -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); -+ -+ if (i == sc->sc_chfifo_len) { -+ /* fifo full */ -+ err = ERESTART; -+ goto errout; -+ } -+ -+ td = &sc->sc_chnfifo[chsel][i].cf_desc; -+ sc->sc_chnfifo[chsel][i].cf_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ /* prevent compiler warning */ -+ hmac_key = 0; -+ hmac_data = 0; -+ if (crd2 == NULL) { -+ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ cipher_iv = 1; -+ cipher_key = 2; -+ in_fifo = 3; -+ cipher_iv_out = 5; -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ out_fifo = 5; -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ out_fifo = 4; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { -+ td->hdr |= TD_TYPE_IPSEC_ESP; -+ } else { -+ DPRINTF("unimplemented: multiple descriptor ipsec\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ hmac_key = 0; -+ hmac_data = 1; -+ cipher_iv = 2; -+ cipher_key = 3; -+ in_fifo = 4; -+ out_fifo = 5; -+ cipher_iv_out = 6; -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ /* assign in_fifo and out_fifo based on input/output struct type */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk("%s: skb frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = skb->len; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = skb->len; -+ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ struct uio *uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk("%s: iov frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ /* crp_olen is never set; always use crp_ilen */ -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } else { -+ /* using contig buffers */ -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ td->hdr |= TALITOS_MODE0_DEU_3DES; -+ /* FALLTHROUGH */ -+ case CRYPTO_DES_CBC: -+ td->hdr |= TALITOS_SEL0_DEU -+ | TALITOS_MODE0_DEU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_DEU_ENC; -+ ivsize = 2*sizeof(u_int32_t); -+ DPRINTF("%cDES ses %d ch %d len %d\n", -+ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_AES_CBC: -+ td->hdr |= TALITOS_SEL0_AESU -+ | TALITOS_MODE0_AESU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_AESU_ENC; -+ ivsize = 4*sizeof(u_int32_t); -+ DPRINTF("AES ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ default: -+ printk("%s: unimplemented enccrd->crd_alg %d\n", -+ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ td->hdr |= TALITOS_DIR_OUTBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } else { -+ td->hdr |= TALITOS_DIR_INBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ iv = enccrd->crd_iv; -+ bcopy(enccrd->crd_iv, iv, ivsize); -+ } else { -+ iv = (caddr_t) ses->ses_iv; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } -+ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_iv].len = ivsize; -+ /* -+ * we don't need the cipher iv out length/pointer -+ * field to do ESP IPsec. Therefore we set the len field as 0, -+ * which tells the SEC not to do anything with this len/ptr -+ * field. Previously, when length/pointer as pointing to iv, -+ * it gave us corruption of packets. -+ */ -+ td->ptr[cipher_iv_out].len = 0; -+ } -+ if (enccrd && maccrd) { -+ /* this is ipsec only for now */ -+ td->hdr |= TALITOS_SEL1_MDEU -+ | TALITOS_MODE1_MDEU_INIT -+ | TALITOS_MODE1_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5; -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ /* ipsec only for now */ -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ td->ptr[in_fifo].ptr += enccrd->crd_skip; -+ td->ptr[in_fifo].len = enccrd->crd_len; -+ td->ptr[out_fifo].ptr += enccrd->crd_skip; -+ td->ptr[out_fifo].len = enccrd->crd_len; -+ /* bytes of HMAC to postpend to ciphertext */ -+ td->ptr[out_fifo].extent = ses->ses_mlen; -+ td->ptr[hmac_data].ptr += maccrd->crd_skip; -+ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; -+ } -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ } -+ } -+ if (!enccrd && maccrd) { -+ /* single MD5 or SHA */ -+ td->hdr |= TALITOS_SEL0_MDEU -+ | TALITOS_MODE0_MDEU_INIT -+ | TALITOS_MODE0_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5; -+ DPRINTF("MD5 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1; -+ DPRINTF("SHA1 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ DPRINTF("cannot do the order\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_IOV) -+ td->ptr[out_fifo].ptr += maccrd->crd_inject; -+ -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, -+ DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ } -+ } -+ else { -+ /* using process key (session data has duplicate) */ -+ td->ptr[cipher_key].ptr = dma_map_single(NULL, -+ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; -+ } -+ /* descriptor complete - GO! */ -+ return talitos_submit(sc, td, chsel); -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+/* go through all channels descriptors, notifying OCF what has -+ * _and_hasn't_ successfully completed and reset the device -+ * (otherwise it's up to decoding desc hdrs!) -+ */ -+static void talitos_errorprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* disable further scheduling until under control */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ if (debug) dump_talitos_status(sc); -+ /* go through descriptors, try and salvage those successfully done, -+ * and EIO those that weren't -+ */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ != TALITOS_HDR_DONE_BITS) { -+ /* this one didn't finish */ -+ /* signify in crp->etype */ -+ sc->sc_chnfifo[i][j].cf_crp->crp_etype -+ = EIO; -+ } -+ } else -+ continue; /* free entry */ -+ /* either way, notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) -+ talitos_rng_init(sc); -+#endif -+ -+ /* Okay. Stand by. */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ return; -+} -+ -+/* go through all channels descriptors, notifying OCF what's been done */ -+static void talitos_doneprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* go through descriptors looking for done bits */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ /* descriptor has done bits set? */ -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ == TALITOS_HDR_DONE_BITS) { -+ /* notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ return; -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+talitos_intr(int irq, void *arg) -+#else -+talitos_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct talitos_softc *sc = arg; -+ u_int32_t v, v_hi; -+ -+ /* ack */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); -+ -+ if (unlikely(v & TALITOS_ISR_ERROR)) { -+ /* Okay, Houston, we've had a problem here. */ -+ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ talitos_errorprocessing(sc); -+ } else -+ if (likely(v & TALITOS_ISR_DONE)) { -+ talitos_doneprocessing(sc); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+talitos_init_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* init all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); -+ v |= TALITOS_CH_CCCR_HI_CDWE -+ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ -+ talitos_write(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); -+ } -+ /* enable all interrupts */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v |= TALITOS_IMR_ALL; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ v |= TALITOS_IMR_HI_ERRONLY; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); -+ return; -+} -+ -+/* -+ * set the master reset bit on the device. -+ */ -+static void -+talitos_reset_device_master(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); -+ -+ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) -+ cpu_relax(); -+ -+ return; -+} -+ -+/* -+ * Resets the device. Values in the registers are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+talitos_reset_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * Master reset -+ * errata documentation: warning: certain SEC interrupts -+ * are not fully cleared by writing the MCR:SWR bit, -+ * set bit twice to completely reset -+ */ -+ talitos_reset_device_master(sc); /* once */ -+ talitos_reset_device_master(sc); /* and once again */ -+ -+ /* reset all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR); -+ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); -+ } -+} -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) -+#else -+static int talitos_probe(struct platform_device *pdev) -+#endif -+{ -+ struct talitos_softc *sc = NULL; -+ struct resource *r; -+#ifdef CONFIG_PPC_MERGE -+ struct device *device = &ofdev->dev; -+ struct device_node *np = ofdev->node; -+ const unsigned int *prop; -+ int err; -+ struct resource res; -+#endif -+ static int num_chips = 0; -+ int rc; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+#ifndef CONFIG_PPC_MERGE -+ sc->sc_dev = pdev; -+#endif -+ sc->sc_num = num_chips++; -+ -+#ifdef CONFIG_PPC_MERGE -+ dev_set_drvdata(device, sc); -+#else -+ platform_set_drvdata(sc->sc_dev, sc); -+#endif -+ -+ /* get the irq line */ -+#ifdef CONFIG_PPC_MERGE -+ err = of_address_to_resource(np, 0, &res); -+ if (err) -+ return -EINVAL; -+ r = &res; -+ -+ sc->sc_irq = irq_of_parse_and_map(np, 0); -+#else -+ /* get a pointer to the register memory */ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ sc->sc_irq = platform_get_irq(pdev, 0); -+#endif -+ rc = request_irq(sc->sc_irq, talitos_intr, 0, -+ device_get_nameunit(sc->sc_cdev), sc); -+ if (rc) { -+ printk(KERN_ERR "%s: failed to hook irq %d\n", -+ device_get_nameunit(sc->sc_cdev), sc->sc_irq); -+ sc->sc_irq = -1; -+ goto out; -+ } -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); -+ if (!sc->sc_base_addr) { -+ printk(KERN_ERR "%s: failed to ioremap\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* figure out our SEC's properties and capabilities */ -+ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 -+ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); -+ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); -+ -+#ifdef CONFIG_PPC_MERGE -+ /* get SEC properties from device tree, defaulting to SEC 2.0 */ -+ -+ prop = of_get_property(np, "num-channels", NULL); -+ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; -+ -+ prop = of_get_property(np, "channel-fifo-len", NULL); -+ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; -+ -+ prop = of_get_property(np, "exec-units-mask", NULL); -+ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; -+ -+ prop = of_get_property(np, "descriptor-types-mask", NULL); -+ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; -+#else -+ /* bulk should go away with openfirmware flat device tree support */ -+ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { -+ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; -+ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; -+ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; -+ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; -+ } else { -+ printk(KERN_ERR "%s: failed to id device\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+#endif -+ -+ /* + 1 is for the meta-channel lock used by the channel scheduler */ -+ sc->sc_chnfifolock = (spinlock_t *) kmalloc( -+ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); -+ if (!sc->sc_chnfifolock) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels + 1; i++) { -+ spin_lock_init(&sc->sc_chnfifolock[i]); -+ } -+ -+ sc->sc_chnlastalg = (int *) kmalloc( -+ sc->sc_num_channels * sizeof(int), GFP_KERNEL); -+ if (!sc->sc_chnlastalg) -+ goto out; -+ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); -+ -+ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( -+ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo[i]) -+ goto out; -+ memset(sc->sc_chnfifo[i], 0, -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); -+ } -+ -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR "%s: could not get crypto driver id\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk("%s:", device_get_nameunit(sc->sc_cdev)); -+ -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { -+ printk(" rng"); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ talitos_rng_init(sc); -+ crypto_rregister(sc->sc_cid, talitos_read_random, sc); -+#endif -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { -+ printk(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { -+ printk(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { -+ printk(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ printk(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printk("\n"); -+ return 0; -+ -+out: -+#ifndef CONFIG_PPC_MERGE -+ talitos_remove(pdev); -+#endif -+ return -ENOMEM; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_remove(struct of_device *ofdev) -+#else -+static int talitos_remove(struct platform_device *pdev) -+#endif -+{ -+#ifdef CONFIG_PPC_MERGE -+ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); -+#else -+ struct talitos_softc *sc = platform_get_drvdata(pdev); -+#endif -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_chnfifo) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ if (sc->sc_chnfifo[i]) -+ kfree(sc->sc_chnfifo[i]); -+ kfree(sc->sc_chnfifo); -+ } -+ if (sc->sc_chnlastalg) -+ kfree(sc->sc_chnlastalg); -+ if (sc->sc_chnfifolock) -+ kfree(sc->sc_chnfifolock); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_base_addr) -+ iounmap((void *) sc->sc_base_addr); -+ kfree(sc); -+ return 0; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static struct of_device_id talitos_match[] = { -+ { -+ .type = "crypto", -+ .compatible = "talitos", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, talitos_match); -+ -+static struct of_platform_driver talitos_driver = { -+ .name = DRV_NAME, -+ .match_table = talitos_match, -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+}; -+ -+static int __init talitos_init(void) -+{ -+ return of_register_platform_driver(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ of_unregister_platform_driver(&talitos_driver); -+} -+#else -+/* Structure for a platform device driver */ -+static struct platform_driver talitos_driver = { -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+ .driver = { -+ .name = "fsl-sec2", -+ } -+}; -+ -+static int __init talitos_init(void) -+{ -+ return platform_driver_register(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ platform_driver_unregister(&talitos_driver); -+} -+#endif -+ -+module_init(talitos_init); -+module_exit(talitos_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("kim.phillips@freescale.com"); -+MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); -diff --git a/crypto/ocf/talitos/talitos_dev.h b/crypto/ocf/talitos/talitos_dev.h -new file mode 100644 -index 0000000..86bb57c ---- /dev/null -+++ b/crypto/ocf/talitos/talitos_dev.h -@@ -0,0 +1,277 @@ -+/* -+ * Freescale SEC (talitos) device dependent data structures -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ */ -+ -+/* device ID register values */ -+#define TALITOS_ID_SEC_2_0 0x40 -+#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ -+ -+/* -+ * following num_channels, channel-fifo-depth, exec-unit-mask, and -+ * descriptor-types-mask are for forward-compatibility with openfirmware -+ * flat device trees -+ */ -+ -+/* -+ * num_channels : the number of channels available in each SEC version. -+ */ -+ -+/* n.b. this driver requires these values be a power of 2 */ -+#define TALITOS_NCHANNELS_SEC_1_0 4 -+#define TALITOS_NCHANNELS_SEC_1_2 1 -+#define TALITOS_NCHANNELS_SEC_2_0 4 -+#define TALITOS_NCHANNELS_SEC_2_01 4 -+#define TALITOS_NCHANNELS_SEC_2_1 4 -+#define TALITOS_NCHANNELS_SEC_2_4 4 -+ -+/* -+ * channel-fifo-depth : The number of descriptor -+ * pointers a channel fetch fifo can hold. -+ */ -+#define TALITOS_CHFIFOLEN_SEC_1_0 1 -+#define TALITOS_CHFIFOLEN_SEC_1_2 1 -+#define TALITOS_CHFIFOLEN_SEC_2_0 24 -+#define TALITOS_CHFIFOLEN_SEC_2_01 24 -+#define TALITOS_CHFIFOLEN_SEC_2_1 24 -+#define TALITOS_CHFIFOLEN_SEC_2_4 24 -+ -+/* -+ * exec-unit-mask : The bitmask representing what Execution Units (EUs) -+ * are available. EU information should be encoded following the SEC's -+ * EU_SEL0 bitfield documentation, i.e. as follows: -+ * -+ * bit 31 = set if SEC permits no-EU selection (should be always set) -+ * bit 30 = set if SEC has the ARC4 EU (AFEU) -+ * bit 29 = set if SEC has the des/3des EU (DEU) -+ * bit 28 = set if SEC has the message digest EU (MDEU) -+ * bit 27 = set if SEC has the random number generator EU (RNG) -+ * bit 26 = set if SEC has the public key EU (PKEU) -+ * bit 25 = set if SEC has the aes EU (AESU) -+ * bit 24 = set if SEC has the Kasumi EU (KEU) -+ * -+ */ -+#define TALITOS_HAS_EU_NONE (1<<0) -+#define TALITOS_HAS_EU_AFEU (1<<1) -+#define TALITOS_HAS_EU_DEU (1<<2) -+#define TALITOS_HAS_EU_MDEU (1<<3) -+#define TALITOS_HAS_EU_RNG (1<<4) -+#define TALITOS_HAS_EU_PKEU (1<<5) -+#define TALITOS_HAS_EU_AESU (1<<6) -+#define TALITOS_HAS_EU_KEU (1<<7) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_EUS_SEC_1_0 0x7f -+#define TALITOS_HAS_EUS_SEC_1_2 0x4d -+#define TALITOS_HAS_EUS_SEC_2_0 0x7f -+#define TALITOS_HAS_EUS_SEC_2_01 0x7f -+#define TALITOS_HAS_EUS_SEC_2_1 0xff -+#define TALITOS_HAS_EUS_SEC_2_4 0x7f -+ -+/* -+ * descriptor-types-mask : The bitmask representing what descriptors -+ * are available. Descriptor type information should be encoded -+ * following the SEC's Descriptor Header Dword DESC_TYPE field -+ * documentation, i.e. as follows: -+ * -+ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type -+ * bit 1 = set if SEC supports the ipsec_esp descriptor type -+ * bit 2 = set if SEC supports the common_nonsnoop desc. type -+ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type -+ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type -+ * bit 5 = set if SEC supports the srtp descriptor type -+ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type -+ * bit 7 = set if SEC supports the pkeu_assemble descriptor type -+ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type -+ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type -+ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type -+ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type -+ * -+ * ..and so on and so forth. -+ */ -+#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) -+#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) -+#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf -+#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf -+ -+/* -+ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register -+ */ -+ -+/* global register offset addresses */ -+#define TALITOS_ID 0x1020 -+#define TALITOS_ID_HI 0x1024 -+#define TALITOS_MCR 0x1030 /* master control register */ -+#define TALITOS_MCR_HI 0x1038 /* master control register */ -+#define TALITOS_MCR_SWR 0x1 -+#define TALITOS_IMR 0x1008 /* interrupt mask register */ -+#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ -+#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ -+#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ -+#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ -+#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ -+#define TALITOS_ISR 0x1010 /* interrupt status register */ -+#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ -+#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ -+#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ -+#define TALITOS_ICR 0x1018 /* interrupt clear register */ -+#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ -+ -+/* channel register address stride */ -+#define TALITOS_CH_OFFSET 0x100 -+ -+/* channel register offset addresses and bits */ -+#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ -+#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ -+#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ -+#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ -+#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ -+#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ -+#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel -+ * Descriptor Buffer (debug) */ -+ -+/* execution unit register offset addresses and bits */ -+#define TALITOS_DEUSR 0x2028 /* DEU status register */ -+#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ -+#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ -+#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ -+#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ -+#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ -+#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ -+#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ -+#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ -+#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ -+#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ -+#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ -+#define TALITOS_RNGSR 0xa028 /* RNG status register */ -+#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ -+#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ -+#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ -+#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ -+#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ -+#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ -+#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ -+#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ -+#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ -+ -+/* descriptor pointer entry */ -+struct talitos_desc_ptr { -+ u16 len; /* length */ -+ u8 extent; /* jump (to s/g link table) and extent */ -+ u8 res; /* reserved */ -+ u32 ptr; /* pointer */ -+}; -+ -+/* descriptor */ -+struct talitos_desc { -+ u32 hdr; /* header */ -+ u32 res; /* reserved */ -+ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ -+}; -+ -+/* talitos descriptor header (hdr) bits */ -+ -+/* primary execution unit select */ -+#define TALITOS_SEL0_AFEU 0x10000000 -+#define TALITOS_SEL0_DEU 0x20000000 -+#define TALITOS_SEL0_MDEU 0x30000000 -+#define TALITOS_SEL0_RNG 0x40000000 -+#define TALITOS_SEL0_PKEU 0x50000000 -+#define TALITOS_SEL0_AESU 0x60000000 -+ -+/* primary execution unit mode (MODE0) and derivatives */ -+#define TALITOS_MODE0_AESU_CBC 0x00200000 -+#define TALITOS_MODE0_AESU_ENC 0x00100000 -+#define TALITOS_MODE0_DEU_CBC 0x00400000 -+#define TALITOS_MODE0_DEU_3DES 0x00200000 -+#define TALITOS_MODE0_DEU_ENC 0x00100000 -+#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ -+#define TALITOS_MODE0_MDEU_HMAC 0x00800000 -+#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ -+#define TALITOS_MODE0_MDEU_MD5 0x00200000 -+#define TALITOS_MODE0_MDEU_SHA256 0x00100000 -+#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE0_MDEU_MD5_HMAC \ -+ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) -+ -+/* secondary execution unit select (SEL1) */ -+/* it's MDEU or nothing */ -+#define TALITOS_SEL1_MDEU 0x00030000 -+ -+/* secondary execution unit mode (MODE1) and derivatives */ -+#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ -+#define TALITOS_MODE1_MDEU_HMAC 0x00000800 -+#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ -+#define TALITOS_MODE1_MDEU_MD5 0x00000200 -+#define TALITOS_MODE1_MDEU_SHA256 0x00000100 -+#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE1_MDEU_MD5_HMAC \ -+ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) -+ -+/* direction of overall data flow (DIR) */ -+#define TALITOS_DIR_OUTBOUND 0x00000000 -+#define TALITOS_DIR_INBOUND 0x00000002 -+ -+/* done notification (DN) */ -+#define TALITOS_DONE_NOTIFY 0x00000001 -+ -+/* descriptor types */ -+/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ -+#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) -+#define TD_TYPE_IPSEC_ESP (1 << 3) -+#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) -+#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) -+ -+#define TALITOS_HDR_DONE_BITS 0xff000000 -+ -+#define DPRINTF(a...) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_cdev) : "talitos"); \ -+ printk(a); \ -+ } \ -+ } while (0) -diff --git a/crypto/ocf/talitos/talitos_soft.h b/crypto/ocf/talitos/talitos_soft.h -new file mode 100644 -index 0000000..79efdbd ---- /dev/null -+++ b/crypto/ocf/talitos/talitos_soft.h -@@ -0,0 +1,77 @@ -+/* -+ * Freescale SEC data structures for integration with ocf-linux -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ * paired descriptor and associated crypto operation -+ */ -+struct desc_cryptop_pair { -+ struct talitos_desc cf_desc; /* descriptor ptr */ -+ struct cryptop *cf_crp; /* cryptop ptr */ -+}; -+ -+/* -+ * Holds data specific to a single talitos device. -+ */ -+struct talitos_softc { -+ softc_device_decl sc_cdev; -+ struct platform_device *sc_dev; /* device backpointer */ -+ ocf_iomem_t sc_base_addr; -+ int sc_irq; -+ int sc_num; /* if we have multiple chips */ -+ int32_t sc_cid; /* crypto tag */ -+ u64 sc_chiprev; /* major/minor chip revision */ -+ int sc_nsessions; -+ struct talitos_session *sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ int sc_chfifo_len; /* channel fetch fifo len */ -+ int sc_exec_units; /* execution units mask */ -+ int sc_desc_types; /* descriptor types mask */ -+ /* -+ * mutual exclusion for intra-channel resources, e.g. fetch fifos -+ * the last entry is a meta-channel lock used by the channel scheduler -+ */ -+ spinlock_t *sc_chnfifolock; -+ /* sc_chnlastalgo contains last algorithm for that channel */ -+ int *sc_chnlastalg; -+ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ -+ struct desc_cryptop_pair **sc_chnfifo; -+}; -+ -+struct talitos_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_hmac[5]; /* hmac inner state */ -+ u_int32_t ses_hmac_len; /* hmac length */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ -+}; -+ -+#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) -+#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -diff --git a/crypto/ocf/uio.h b/crypto/ocf/uio.h -new file mode 100644 -index 0000000..03a6249 ---- /dev/null -+++ b/crypto/ocf/uio.h -@@ -0,0 +1,54 @@ -+#ifndef _OCF_UIO_H_ -+#define _OCF_UIO_H_ -+ -+#include -+ -+/* -+ * The linux uio.h doesn't have all we need. To be fully api compatible -+ * with the BSD cryptodev, we need to keep this around. Perhaps this can -+ * be moved back into the linux/uio.h -+ * -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+struct uio { -+ struct iovec *uio_iov; -+ int uio_iovcnt; -+ off_t uio_offset; -+ int uio_resid; -+#if 0 -+ enum uio_seg uio_segflg; -+ enum uio_rw uio_rw; -+ struct thread *uio_td; -+#endif -+}; -+ -+#endif -diff --git a/drivers/char/random.c b/drivers/char/random.c -index 8258982..6509c94 100644 ---- a/drivers/char/random.c -+++ b/drivers/char/random.c -@@ -129,6 +129,9 @@ - * unsigned int value); - * void add_interrupt_randomness(int irq); - * -+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+ * int random_input_wait(void); -+ * - * add_input_randomness() uses the input layer interrupt timing, as well as - * the event type information from the hardware. - * -@@ -140,6 +143,13 @@ - * a better measure, since the timing of the disk interrupts are more - * unpredictable. - * -+ * random_input_words() just provides a raw block of entropy to the input -+ * pool, such as from a hardware entropy generator. -+ * -+ * random_input_wait() suspends the caller until such time as the -+ * entropy pool falls below the write threshold, and returns a count of how -+ * much entropy (in bits) is needed to sustain the pool. -+ * - * All of these routines try to estimate how many bits of randomness a - * particular randomness source. They do this by keeping track of the - * first and second order deltas of the event timings. -@@ -714,6 +724,61 @@ void add_disk_randomness(struct gendisk *disk) - } - #endif - -+/* -+ * random_input_words - add bulk entropy to pool -+ * -+ * @buf: buffer to add -+ * @wordcount: number of __u32 words to add -+ * @ent_count: total amount of entropy (in bits) to credit -+ * -+ * this provides bulk input of entropy to the input pool -+ * -+ */ -+void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+{ -+ mix_pool_bytes(&input_pool, buf, wordcount*4); -+ -+ credit_entropy_bits(&input_pool, ent_count); -+ -+ DEBUG_ENT("crediting %d bits => %d\n", -+ ent_count, input_pool.entropy_count); -+ /* -+ * Wake up waiting processes if we have enough -+ * entropy. -+ */ -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ wake_up_interruptible(&random_read_wait); -+} -+EXPORT_SYMBOL(random_input_words); -+ -+/* -+ * random_input_wait - wait until random needs entropy -+ * -+ * this function sleeps until the /dev/random subsystem actually -+ * needs more entropy, and then return the amount of entropy -+ * that it would be nice to have added to the system. -+ */ -+int random_input_wait(void) -+{ -+ int count; -+ -+ wait_event_interruptible(random_write_wait, -+ input_pool.entropy_count < random_write_wakeup_thresh); -+ -+ count = random_write_wakeup_thresh - input_pool.entropy_count; -+ -+ /* likely we got woken up due to a signal */ -+ if (count <= 0) count = random_read_wakeup_thresh; -+ -+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", -+ count, -+ input_pool.entropy_count, random_write_wakeup_thresh); -+ -+ return count; -+} -+EXPORT_SYMBOL(random_input_wait); -+ -+ - #define EXTRACT_SIZE 10 - - /********************************************************************* -diff --git a/fs/fcntl.c b/fs/fcntl.c -index 2cf93ec..1b6d2bb 100644 ---- a/fs/fcntl.c -+++ b/fs/fcntl.c -@@ -141,6 +141,7 @@ SYSCALL_DEFINE1(dup, unsigned int, fildes) - } - return ret; - } -+EXPORT_SYMBOL(sys_dup); - - #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) - -diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h -index adaf3c1..e961a9a 100644 ---- a/include/linux/miscdevice.h -+++ b/include/linux/miscdevice.h -@@ -12,6 +12,7 @@ - #define APOLLO_MOUSE_MINOR 7 - #define PC110PAD_MINOR 9 - /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ -+#define CRYPTODEV_MINOR 70 /* /dev/crypto */ - #define WATCHDOG_MINOR 130 /* Watchdog timer */ - #define TEMP_MINOR 131 /* Temperature Sensor */ - #define RTC_MINOR 135 -diff --git a/include/linux/random.h b/include/linux/random.h -index 25d02fe..b59ec10 100644 ---- a/include/linux/random.h -+++ b/include/linux/random.h -@@ -9,6 +9,7 @@ - - #include - #include -+#include /* for __u32 in user space */ - #include - - /* ioctl()'s for the random number generator */ -@@ -34,6 +35,30 @@ - /* Clear the entropy pool and associated counters. (Superuser only.) */ - #define RNDCLEARPOOL _IO( 'R', 0x06 ) - -+#ifdef CONFIG_FIPS_RNG -+ -+/* Size of seed value - equal to AES blocksize */ -+#define AES_BLOCK_SIZE_BYTES 16 -+#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES -+/* Size of AES key */ -+#define KEY_SIZE_BYTES 16 -+ -+/* ioctl() structure used by FIPS 140-2 Tests */ -+struct rand_fips_test { -+ unsigned char key[KEY_SIZE_BYTES]; /* Input */ -+ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char result[SEED_SIZE_BYTES]; /* Output */ -+}; -+ -+/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ -+#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) -+ -+/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ -+#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) -+ -+#endif /* #ifdef CONFIG_FIPS_RNG */ -+ - struct rand_pool_info { - int entropy_count; - int buf_size; -@@ -50,6 +75,10 @@ extern void add_input_randomness(unsigned int type, unsigned int code, - unsigned int value); - extern void add_interrupt_randomness(int irq); - -+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); -+extern int random_input_wait(void); -+#define HAS_RANDOM_INPUT_WAIT 1 -+ - extern void get_random_bytes(void *buf, int nbytes); - void generate_random_uuid(unsigned char uuid_out[16]); - -diff --git a/kernel/pid.c b/kernel/pid.c -index d3f722d..e041b52 100644 ---- a/kernel/pid.c -+++ b/kernel/pid.c -@@ -387,6 +387,7 @@ struct task_struct *find_task_by_vpid(pid_t vnr) - { - return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); - } -+EXPORT_SYMBOL(find_task_by_vpid); - - struct pid *get_task_pid(struct task_struct *task, enum pid_type type) - { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-Revert-omap3-beagle-Fix-compile-time-errors.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-Revert-omap3-beagle-Fix-compile-time-errors.patch deleted file mode 100644 index abcf45b6..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-Revert-omap3-beagle-Fix-compile-time-errors.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 09b6266a567b22e07200973312ffb8f43e7f7d43 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Fri, 30 Apr 2010 11:12:24 +0200 -Subject: [PATCH 01/45] Revert "omap3: beagle: Fix compile-time errors" - -This commit clashes with the other beagle patches we apply on top - -This reverts commit da5b291cba631d303cb137fa6a620c494d828197. ---- - arch/arm/mach-omap2/board-omap3beagle.c | 34 ++---------------------------- - 1 files changed, 3 insertions(+), 31 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index c5da58e..330fb25 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -56,22 +56,6 @@ - - #define NAND_BLOCK_SIZE SZ_128K - --#ifdef CONFIG_PM --static struct omap_opp * _omap35x_mpu_rate_table = omap35x_mpu_rate_table; --static struct omap_opp * _omap37x_mpu_rate_table = omap37x_mpu_rate_table; --static struct omap_opp * _omap35x_dsp_rate_table = omap35x_dsp_rate_table; --static struct omap_opp * _omap37x_dsp_rate_table = omap37x_dsp_rate_table; --static struct omap_opp * _omap35x_l3_rate_table = omap35x_l3_rate_table; --static struct omap_opp * _omap37x_l3_rate_table = omap37x_l3_rate_table; --#else /* CONFIG_PM */ --static struct omap_opp * _omap35x_mpu_rate_table = NULL; --static struct omap_opp * _omap37x_mpu_rate_table = NULL; --static struct omap_opp * _omap35x_dsp_rate_table = NULL; --static struct omap_opp * _omap37x_dsp_rate_table = NULL; --static struct omap_opp * _omap35x_l3_rate_table = NULL; --static struct omap_opp * _omap37x_l3_rate_table = NULL; --#endif /* CONFIG_PM */ -- - static struct mtd_partition omap3beagle_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { -@@ -377,21 +361,9 @@ static void __init omap3_beagle_init_irq(void) - { - omap_board_config = omap3_beagle_config; - omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); -- -- if (cpu_is_omap3630()) { -- omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- mt46h32m32lf6_sdrc_params, -- _omap37x_mpu_rate_table, -- _omap37x_dsp_rate_table, -- _omap37x_l3_rate_table); -- } else { -- omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- mt46h32m32lf6_sdrc_params, -- _omap35x_mpu_rate_table, -- _omap35x_dsp_rate_table, -- _omap35x_l3_rate_table); -- } -- -+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -+ mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table, -+ omap3_dsp_rate_table, omap3_l3_rate_table); - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-cgroupfs-create-sys-fs-cgroup-to-mount-cgroupfs-on.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-cgroupfs-create-sys-fs-cgroup-to-mount-cgroupfs-on.patch deleted file mode 100644 index 37d5fb90..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0001-cgroupfs-create-sys-fs-cgroup-to-mount-cgroupfs-on.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 787c524fc478068d18eef72f43074b47722e50b0 Mon Sep 17 00:00:00 2001 -From: Greg KH -Date: Thu, 5 Aug 2010 13:53:35 -0700 -Subject: [PATCH] cgroupfs: create /sys/fs/cgroup to mount cgroupfs on - -We really shouldn't be asking userspace to create new root filesystems. -So follow along with all of the other in-kernel filesystems, and provide -a mount point in sysfs. - -For cgroupfs, this should be in /sys/fs/cgroup/ This change provides -that mount point when the cgroup filesystem is registered in the kernel. - -Acked-by: Paul Menage -Acked-by: Dhaval Giani -Cc: Li Zefan -Cc: Lennart Poettering -Cc: Kay Sievers -Signed-off-by: Greg Kroah-Hartman ---- - kernel/cgroup.c | 13 ++++++++++++- - 1 files changed, 12 insertions(+), 1 deletions(-) - -diff --git a/kernel/cgroup.c b/kernel/cgroup.c -index 0249f4b..db21dd8 100644 ---- a/kernel/cgroup.c -+++ b/kernel/cgroup.c -@@ -1472,6 +1472,8 @@ static struct file_system_type cgroup_fs_type = { - .kill_sb = cgroup_kill_sb, - }; - -+static struct kobject *cgroup_kobj; -+ - static inline struct cgroup *__d_cgrp(struct dentry *dentry) - { - return dentry->d_fsdata; -@@ -3283,9 +3285,18 @@ int __init cgroup_init(void) - hhead = css_set_hash(init_css_set.subsys); - hlist_add_head(&init_css_set.hlist, hhead); - BUG_ON(!init_root_id(&rootnode)); -+ -+ cgroup_kobj = kobject_create_and_add("cgroup", fs_kobj); -+ if (!cgroup_kobj) { -+ err = -ENOMEM; -+ goto out; -+ } -+ - err = register_filesystem(&cgroup_fs_type); -- if (err < 0) -+ if (err < 0) { -+ kobject_put(cgroup_kobj); - goto out; -+ } - - proc_create("cgroups", 0, NULL, &proc_cgroupstats_operations); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0002-OMAP3-craneboard-add-support-for-TinCanTools-Trainer.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0002-OMAP3-craneboard-add-support-for-TinCanTools-Trainer.patch deleted file mode 100644 index 4b1f1096..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0002-OMAP3-craneboard-add-support-for-TinCanTools-Trainer.patch +++ /dev/null @@ -1,55 +0,0 @@ -From ba5fd3ed4031a826309ab26045d27dbef88de418 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Wed, 19 Jan 2011 16:36:09 +0100 -Subject: [PATCH 2/2] OMAP3: craneboard: add support for TinCanTools Trainer expansion board - -Signed-off-by: Koen Kooi ---- - arch/arm/mach-omap2/board-am3517crane.c | 31 +++++++++++++++++++++++++++++++ - 1 files changed, 31 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c -index 300a79d..cbe2174 100644 ---- a/arch/arm/mach-omap2/board-am3517crane.c -+++ b/arch/arm/mach-omap2/board-am3517crane.c -@@ -747,6 +747,37 @@ static void __init am3517_crane_init(void) - am3517crane_flash_init(); - usb_musb_init(); - -+ if(!strcmp(expansionboard_name, "trainer")) -+ { -+ printk(KERN_INFO "Beagle expansionboard: exporting GPIOs 130-141,162 to userspace\n"); -+ gpio_request(130, "sysfs"); -+ gpio_export(130, 1); -+ gpio_request(131, "sysfs"); -+ gpio_export(131, 1); -+ gpio_request(132, "sysfs"); -+ gpio_export(132, 1); -+ gpio_request(133, "sysfs"); -+ gpio_export(133, 1); -+ gpio_request(134, "sysfs"); -+ gpio_export(134, 1); -+ gpio_request(135, "sysfs"); -+ gpio_export(135, 1); -+ gpio_request(136, "sysfs"); -+ gpio_export(136, 1); -+ gpio_request(137, "sysfs"); -+ gpio_export(137, 1); -+ gpio_request(138, "sysfs"); -+ gpio_export(138, 1); -+ gpio_request(139, "sysfs"); -+ gpio_export(139, 1); -+ gpio_request(140, "sysfs"); -+ gpio_export(140, 1); -+ gpio_request(141, "sysfs"); -+ gpio_export(141, 1); -+ gpio_request(162, "sysfs"); -+ gpio_export(162, 1); -+ } -+ - /* Configure GPIO for EHCI port */ - omap_mux_init_gpio(35, OMAP_PIN_OUTPUT); - gpio_request(35, "usb_ehci_enable"); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0002-board-omap3touchbook-make-it-build-against-TI-linux-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0002-board-omap3touchbook-make-it-build-against-TI-linux-.patch deleted file mode 100644 index c695b712..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0002-board-omap3touchbook-make-it-build-against-TI-linux-.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 5e84443afe149d9f503b63b1c87f23b807fe9e46 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sat, 30 Jan 2010 15:49:15 +0100 -Subject: [PATCH 02/45] board-omap3touchbook: make it build against TI linux-omap 2.6.32-PSP - ---- - arch/arm/mach-omap2/board-omap3touchbook.c | 11 +++++++++-- - 1 files changed, 9 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c -index fe3d22c..fc3e03c 100644 ---- a/arch/arm/mach-omap2/board-omap3touchbook.c -+++ b/arch/arm/mach-omap2/board-omap3touchbook.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -48,12 +49,18 @@ - #include - #include - #include -+#include -+#include - - #include "mux.h" - #include "mmc-twl4030.h" - -+#include "pm.h" -+#include "omap3-opp.h" -+ - #include - -+ - #define GPMC_CS0_BASE 0x60 - #define GPMC_CS_SIZE 0x30 - -@@ -78,7 +85,6 @@ static struct mtd_partition omap3touchbook_nand_partitions[] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 15 * NAND_BLOCK_SIZE, -- .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot Env", -@@ -440,7 +446,8 @@ static void __init omap3_touchbook_init_irq(void) - omap_board_config = omap3_touchbook_config; - omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- mt46h32m32lf6_sdrc_params); -+ mt46h32m32lf6_sdrc_params, omap35x_mpu_rate_table, -+ omap35x_dsp_rate_table, omap35x_l3_rate_table); - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0003-ARM-OMAP-add-support-for-TCT-Zippy-to-Beagle-board-f.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0003-ARM-OMAP-add-support-for-TCT-Zippy-to-Beagle-board-f.patch deleted file mode 100644 index 07ade0a5..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0003-ARM-OMAP-add-support-for-TCT-Zippy-to-Beagle-board-f.patch +++ /dev/null @@ -1,135 +0,0 @@ -From aeef52fa662c9a6d85b11474359fb9504fc1cf49 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Tue, 15 Dec 2009 15:34:29 -0800 -Subject: [PATCH 03/45] ARM: OMAP: add support for TCT Zippy to Beagle board file - -Signed-off-by: Steve Sakoman ---- - arch/arm/mach-omap2/board-omap3beagle.c | 74 +++++++++++++++++++++++++++++- - 1 files changed, 71 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 330fb25..ddfb9c0 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -56,6 +57,49 @@ - - #define NAND_BLOCK_SIZE SZ_128K - -+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) -+ -+#include -+#include -+ -+#define OMAP3BEAGLE_GPIO_ENC28J60_IRQ 157 -+ -+static struct omap2_mcspi_device_config enc28j60_spi_chip_info = { -+ .turbo_mode = 0, -+ .single_channel = 1, /* 0: slave, 1: master */ -+}; -+ -+static struct spi_board_info omap3beagle_spi_board_info[] __initdata = { -+ { -+ .modalias = "enc28j60", -+ .bus_num = 4, -+ .chip_select = 0, -+ .max_speed_hz = 20000000, -+ .controller_data = &enc28j60_spi_chip_info, -+ }, -+}; -+ -+static void __init omap3beagle_enc28j60_init(void) -+{ -+ if ((gpio_request(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, "ENC28J60_IRQ") == 0) && -+ (gpio_direction_input(OMAP3BEAGLE_GPIO_ENC28J60_IRQ) == 0)) { -+ gpio_export(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, 0); -+ omap3beagle_spi_board_info[0].irq = OMAP_GPIO_IRQ(OMAP3BEAGLE_GPIO_ENC28J60_IRQ); -+ set_irq_type(omap3beagle_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING); -+ } else { -+ printk(KERN_ERR "could not obtain gpio for ENC28J60_IRQ\n"); -+ return; -+ } -+ -+ spi_register_board_info(omap3beagle_spi_board_info, -+ ARRAY_SIZE(omap3beagle_spi_board_info)); -+} -+ -+#else -+static inline void __init omap3beagle_enc28j60_init(void) { return; } -+#endif -+ -+ - static struct mtd_partition omap3beagle_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { -@@ -118,6 +162,14 @@ static struct twl4030_hsmmc_info mmc[] = { - .wires = 8, - .gpio_wp = 29, - }, -+ { -+ .mmc = 2, -+ .wires = 4, -+ .gpio_wp = 141, -+ .gpio_cd = 162, -+ .transceiver = true, -+ .ocr_mask = 0x00100000, /* 3.3V */ -+ }, - {} /* Terminator */ - }; - -@@ -281,7 +333,7 @@ static struct twl4030_platform_data beagle_twldata = { - .vpll2 = &beagle_vpll2, - }; - --static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { -+static struct i2c_board_info __initdata beagle_i2c1_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, -@@ -290,10 +342,24 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { - }, - }; - -+#if defined(CONFIG_RTC_DRV_DS1307) || \ -+ defined(CONFIG_RTC_DRV_DS1307_MODULE) -+ -+static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { -+ { -+ I2C_BOARD_INFO("ds1307", 0x68), -+ }, -+}; -+#else -+static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = {}; -+#endif -+ - static int __init omap3_beagle_i2c_init(void) - { -- omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, -- ARRAY_SIZE(beagle_i2c_boardinfo)); -+ omap_register_i2c_bus(1, 2600, beagle_i2c1_boardinfo, -+ ARRAY_SIZE(beagle_i2c1_boardinfo)); -+ omap_register_i2c_bus(2, 400, beagle_i2c2_boardinfo, -+ ARRAY_SIZE(beagle_i2c2_boardinfo)); - /* Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, NULL, 0); -@@ -448,6 +514,8 @@ static void __init omap3_beagle_init(void) - /* REVISIT leave DVI powered down until it's needed ... */ - gpio_direction_output(170, true); - -+ omap3beagle_enc28j60_init(); -+ - usb_musb_init(); - usb_ehci_init(&ehci_pdata); - omap3beagle_flash_init(); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0004-ARM-OMAP-Make-beagle-u-boot-partition-writable.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0004-ARM-OMAP-Make-beagle-u-boot-partition-writable.patch deleted file mode 100644 index 46a46e77..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0004-ARM-OMAP-Make-beagle-u-boot-partition-writable.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 701bababc8f9e458e01bdb512199ce175110fe19 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 17 Dec 2009 12:40:24 -0800 -Subject: [PATCH 04/45] ARM: OMAP: Make beagle u-boot partition writable - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 1 - - 1 files changed, 0 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index ddfb9c0..9f72c7a 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -112,7 +112,6 @@ static struct mtd_partition omap3beagle_nand_partitions[] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 15 * NAND_BLOCK_SIZE, -- .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot Env", --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0005-board-omap3-beagle-add-DSS2-support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0005-board-omap3-beagle-add-DSS2-support.patch deleted file mode 100644 index e337a4f2..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0005-board-omap3-beagle-add-DSS2-support.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 818b8bbfb472de23b10aec58acd55eb31fafe0b9 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Wed, 10 Feb 2010 15:07:36 +0100 -Subject: [PATCH 05/45] board-omap3-beagle: add DSS2 support - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 130 ++++++++++++++++++++++++------- - 1 files changed, 103 insertions(+), 27 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 9f72c7a..3b7f6ec 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -40,6 +40,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -153,6 +154,105 @@ static struct platform_device omap3beagle_nand_device = { - .resource = &omap3beagle_nand_resource, - }; - -+/* DSS */ -+ -+static int beagle_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->reset_gpio != -1) -+ gpio_set_value(dssdev->reset_gpio, 1); -+ -+ return 0; -+} -+ -+static void beagle_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->reset_gpio != -1) -+ gpio_set_value(dssdev->reset_gpio, 0); -+} -+ -+static struct omap_dss_device beagle_dvi_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "dvi", -+ .driver_name = "generic_panel", -+ .phy.dpi.data_lines = 24, -+ .reset_gpio = 170, -+ .platform_enable = beagle_enable_dvi, -+ .platform_disable = beagle_disable_dvi, -+}; -+ -+static int beagle_panel_enable_tv(struct omap_dss_device *dssdev) -+{ -+#define ENABLE_VDAC_DEDICATED 0x03 -+#define ENABLE_VDAC_DEV_GRP 0x20 -+ -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ ENABLE_VDAC_DEDICATED, -+ TWL4030_VDAC_DEDICATED); -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP); -+ -+ return 0; -+} -+ -+static void beagle_panel_disable_tv(struct omap_dss_device *dssdev) -+{ -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00, -+ TWL4030_VDAC_DEDICATED); -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00, -+ TWL4030_VDAC_DEV_GRP); -+} -+ -+static struct omap_dss_device beagle_tv_device = { -+ .name = "tv", -+ .driver_name = "venc", -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -+ .platform_enable = beagle_panel_enable_tv, -+ .platform_disable = beagle_panel_disable_tv, -+}; -+ -+static struct omap_dss_device *beagle_dss_devices[] = { -+ &beagle_dvi_device, -+ &beagle_tv_device, -+}; -+ -+static struct omap_dss_board_info beagle_dss_data = { -+ .num_devices = ARRAY_SIZE(beagle_dss_devices), -+ .devices = beagle_dss_devices, -+ .default_device = &beagle_dvi_device, -+}; -+ -+static struct platform_device beagle_dss_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = &beagle_dss_data, -+ }, -+}; -+ -+static struct regulator_consumer_supply beagle_vdac_supply = { -+ .supply = "vdda_dac", -+ .dev = &beagle_dss_device.dev, -+}; -+ -+static struct regulator_consumer_supply beagle_vdvi_supply = { -+ .supply = "vdds_dsi", -+ .dev = &beagle_dss_device.dev, -+}; -+ -+static void __init beagle_display_init(void) -+{ -+ int r; -+ -+ r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset"); -+ if (r < 0) { -+ printk(KERN_ERR "Unable to get DVI reset GPIO\n"); -+ return; -+ } -+ -+ gpio_direction_output(beagle_dvi_device.reset_gpio, 0); -+} -+ - #include "sdram-micron-mt46h32m32lf-6.h" - - static struct twl4030_hsmmc_info mmc[] = { -@@ -172,15 +272,6 @@ static struct twl4030_hsmmc_info mmc[] = { - {} /* Terminator */ - }; - --static struct platform_device omap3_beagle_lcd_device = { -- .name = "omap3beagle_lcd", -- .id = -1, --}; -- --static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { -- .ctrl_name = "internal", --}; -- - static struct regulator_consumer_supply beagle_vmmc1_supply = { - .supply = "vmmc", - }; -@@ -236,16 +327,6 @@ static struct twl4030_gpio_platform_data beagle_gpio_data = { - .setup = beagle_twl_gpio_setup, - }; - --static struct regulator_consumer_supply beagle_vdac_supply = { -- .supply = "vdac", -- .dev = &omap3_beagle_lcd_device.dev, --}; -- --static struct regulator_consumer_supply beagle_vdvi_supply = { -- .supply = "vdvi", -- .dev = &omap3_beagle_lcd_device.dev, --}; -- - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ - static struct regulator_init_data beagle_vmmc1 = { - .constraints = { -@@ -418,14 +499,8 @@ static struct platform_device keys_gpio = { - }, - }; - --static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { -- { OMAP_TAG_LCD, &omap3_beagle_lcd_config }, --}; -- - static void __init omap3_beagle_init_irq(void) - { -- omap_board_config = omap3_beagle_config; -- omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table, - omap3_dsp_rate_table, omap3_l3_rate_table); -@@ -437,9 +512,9 @@ static void __init omap3_beagle_init_irq(void) - } - - static struct platform_device *omap3_beagle_devices[] __initdata = { -- &omap3_beagle_lcd_device, - &leds_gpio, - &keys_gpio, -+ &beagle_dss_device, - }; - - static void __init omap3beagle_flash_init(void) -@@ -522,8 +597,9 @@ static void __init omap3_beagle_init(void) - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); --} - -+ beagle_display_init(); -+} - static void __init omap3_beagle_map_io(void) - { - omap2_set_globals_343x(); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0006-board-omap3beagle-prepare-for-DM3730-based-Beagleboa.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0006-board-omap3beagle-prepare-for-DM3730-based-Beagleboa.patch deleted file mode 100644 index 2b326602..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0006-board-omap3beagle-prepare-for-DM3730-based-Beagleboa.patch +++ /dev/null @@ -1,103 +0,0 @@ -From e36c63f1fe13a60bdf6e9b3dd46ad969d6fe418d Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Wed, 27 Jan 2010 21:57:13 +0100 -Subject: [PATCH 06/45] board-omap3beagle: prepare for DM3730 based BeagleboardXM - -* OPP changes copy/pasted from board-omap3evm.c - * EHCI changes copy/pasted from Steve Kipisz' 2.6.33rcX work - * turn on power to camera on boot and add some comments ---- - arch/arm/mach-omap2/board-omap3beagle.c | 62 +++++++++++++++++++++++++++---- - 1 files changed, 54 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 3b7f6ec..429dacb 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -53,6 +53,23 @@ - #include "pm.h" - #include "omap3-opp.h" - -+#ifdef CONFIG_PM -+static struct omap_opp * _omap35x_mpu_rate_table = omap35x_mpu_rate_table; -+static struct omap_opp * _omap37x_mpu_rate_table = omap37x_mpu_rate_table; -+static struct omap_opp * _omap35x_dsp_rate_table = omap35x_dsp_rate_table; -+static struct omap_opp * _omap37x_dsp_rate_table = omap37x_dsp_rate_table; -+static struct omap_opp * _omap35x_l3_rate_table = omap35x_l3_rate_table; -+static struct omap_opp * _omap37x_l3_rate_table = omap37x_l3_rate_table; -+#else /* CONFIG_PM */ -+static struct omap_opp * _omap35x_mpu_rate_table = NULL; -+static struct omap_opp * _omap37x_mpu_rate_table = NULL; -+static struct omap_opp * _omap35x_dsp_rate_table = NULL; -+static struct omap_opp * _omap37x_dsp_rate_table = NULL; -+static struct omap_opp * _omap35x_l3_rate_table = NULL; -+static struct omap_opp * _omap37x_l3_rate_table = NULL; -+#endif /* CONFIG_PM */ -+ -+ - #define GPMC_CS0_BASE 0x60 - #define GPMC_CS_SIZE 0x30 - -@@ -303,12 +320,28 @@ static int beagle_twl_gpio_setup(struct device *dev, - * power switch and overcurrent detect - */ - -- gpio_request(gpio + 1, "EHCI_nOC"); -- gpio_direction_input(gpio + 1); -+ if (cpu_is_omap3630()) { -+ /* Power on DVI, Serial and PWR led */ -+ gpio_request(gpio + 1, "nDVI_PWR_EN"); -+ gpio_direction_output(gpio + 1, 0); -+ -+ /* Power on camera interface */ -+ gpio_request(gpio + 2, "CAM_EN"); -+ gpio_direction_output(gpio + 2, 1); -+ -+ /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ -+ gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); -+ } -+ else { -+ gpio_request(gpio + 1, "EHCI_nOC"); -+ gpio_direction_input(gpio + 1); -+ -+ /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ -+ gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); -+ } - -- /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ -- gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; -@@ -501,9 +534,22 @@ static struct platform_device keys_gpio = { - - static void __init omap3_beagle_init_irq(void) - { -- omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- mt46h32m32lf6_sdrc_params, omap3_mpu_rate_table, -- omap3_dsp_rate_table, omap3_l3_rate_table); -+ if (cpu_is_omap3630()) -+ { -+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -+ NULL, -+ _omap37x_mpu_rate_table, -+ _omap37x_dsp_rate_table, -+ _omap37x_l3_rate_table); -+ } -+ else -+ { -+ omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -+ NULL, -+ _omap35x_mpu_rate_table, -+ _omap35x_dsp_rate_table, -+ _omap35x_l3_rate_table); -+ } - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0007-ARM-OMAP-beagleboard-Add-infrastructure-to-do-fixups.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0007-ARM-OMAP-beagleboard-Add-infrastructure-to-do-fixups.patch deleted file mode 100644 index 86e6a709..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0007-ARM-OMAP-beagleboard-Add-infrastructure-to-do-fixups.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 25ae9895ed107a6fe9d9c4345f21bbdaee4ccde6 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Mon, 3 May 2010 14:41:29 +0200 -Subject: [PATCH 07/45] ARM: OMAP: beagleboard: Add infrastructure to do fixups based on expansionboard name passed by u-boot - -And add support for zippy2 ---- - arch/arm/mach-omap2/board-omap3beagle.c | 88 +++++++++++++++++++++++++++---- - 1 files changed, 78 insertions(+), 10 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 429dacb..ac96551 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -75,6 +75,8 @@ static struct omap_opp * _omap37x_l3_rate_table = NULL; - - #define NAND_BLOCK_SIZE SZ_128K - -+char expansionboard_name[16]; -+ - #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - - #include -@@ -87,7 +89,7 @@ static struct omap2_mcspi_device_config enc28j60_spi_chip_info = { - .single_channel = 1, /* 0: slave, 1: master */ - }; - --static struct spi_board_info omap3beagle_spi_board_info[] __initdata = { -+static struct spi_board_info omap3beagle_zippy_spi_board_info[] __initdata = { - { - .modalias = "enc28j60", - .bus_num = 4, -@@ -102,21 +104,62 @@ static void __init omap3beagle_enc28j60_init(void) - if ((gpio_request(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, "ENC28J60_IRQ") == 0) && - (gpio_direction_input(OMAP3BEAGLE_GPIO_ENC28J60_IRQ) == 0)) { - gpio_export(OMAP3BEAGLE_GPIO_ENC28J60_IRQ, 0); -- omap3beagle_spi_board_info[0].irq = OMAP_GPIO_IRQ(OMAP3BEAGLE_GPIO_ENC28J60_IRQ); -- set_irq_type(omap3beagle_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING); -+ omap3beagle_zippy_spi_board_info[0].irq = OMAP_GPIO_IRQ(OMAP3BEAGLE_GPIO_ENC28J60_IRQ); -+ set_irq_type(omap3beagle_zippy_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING); - } else { - printk(KERN_ERR "could not obtain gpio for ENC28J60_IRQ\n"); - return; - } - -- spi_register_board_info(omap3beagle_spi_board_info, -- ARRAY_SIZE(omap3beagle_spi_board_info)); -+ spi_register_board_info(omap3beagle_zippy_spi_board_info, -+ ARRAY_SIZE(omap3beagle_zippy_spi_board_info)); - } - - #else - static inline void __init omap3beagle_enc28j60_init(void) { return; } - #endif - -+#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE) -+ -+#include -+#include -+ -+#define OMAP3BEAGLE_GPIO_KS8851_IRQ 157 -+ -+static struct omap2_mcspi_device_config ks8851_spi_chip_info = { -+ .turbo_mode = 0, -+ .single_channel = 1, /* 0: slave, 1: master */ -+}; -+ -+static struct spi_board_info omap3beagle_zippy2_spi_board_info[] __initdata = { -+ { -+ .modalias = "ks8851", -+ .bus_num = 4, -+ .chip_select = 0, -+ .max_speed_hz = 36000000, -+ .controller_data = &ks8851_spi_chip_info, -+ }, -+}; -+ -+static void __init omap3beagle_ks8851_init(void) -+{ -+ if ((gpio_request(OMAP3BEAGLE_GPIO_KS8851_IRQ, "KS8851_IRQ") == 0) && -+ (gpio_direction_input(OMAP3BEAGLE_GPIO_KS8851_IRQ) == 0)) { -+ gpio_export(OMAP3BEAGLE_GPIO_KS8851_IRQ, 0); -+ omap3beagle_zippy2_spi_board_info[0].irq = OMAP_GPIO_IRQ(OMAP3BEAGLE_GPIO_KS8851_IRQ); -+ set_irq_type(omap3beagle_zippy2_spi_board_info[0].irq, IRQ_TYPE_EDGE_FALLING); -+ } else { -+ printk(KERN_ERR "could not obtain gpio for KS8851_IRQ\n"); -+ return; -+ } -+ -+ spi_register_board_info(omap3beagle_zippy2_spi_board_info, -+ ARRAY_SIZE(omap3beagle_zippy2_spi_board_info)); -+} -+ -+#else -+static inline void __init omap3beagle_ks8851_init(void) { return; } -+#endif - - static struct mtd_partition omap3beagle_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ -@@ -281,8 +324,6 @@ static struct twl4030_hsmmc_info mmc[] = { - { - .mmc = 2, - .wires = 4, -- .gpio_wp = 141, -- .gpio_cd = 162, - .transceiver = true, - .ocr_mask = 0x00100000, /* 3.3V */ - }, -@@ -601,7 +642,7 @@ static void __init omap3beagle_flash_init(void) - } - } - --static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -@@ -621,6 +662,15 @@ static struct omap_board_mux board_mux[] __initdata = { - #define board_mux NULL - #endif - -+static int __init expansionboard_setup(char *str) -+{ -+ if (!str) -+ return -EINVAL; -+ strncpy(expansionboard_name, str, 16); -+ printk(KERN_INFO "Beagle expansionboard: %s\n", expansionboard_name); -+ return 0; -+} -+ - static void __init omap3_beagle_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -@@ -634,8 +684,24 @@ static void __init omap3_beagle_init(void) - /* REVISIT leave DVI powered down until it's needed ... */ - gpio_direction_output(170, true); - -- omap3beagle_enc28j60_init(); -- -+ if(!strcmp(expansionboard_name, "zippy")) -+ { -+ printk(KERN_INFO "Beagle expansionboard: initializing enc28j60\n"); -+ omap3beagle_enc28j60_init(); -+ printk(KERN_INFO "Beagle expansionboard: assigning GPIO 141 and 162 to MMC1\n"); -+ mmc[1].gpio_wp = 141; -+ mmc[1].gpio_cd = 162; -+ } -+ -+ if(!strcmp(expansionboard_name, "zippy2")) -+ { -+ printk(KERN_INFO "Beagle expansionboard: initializing ks_8851\n"); -+ omap3beagle_ks8851_init(); -+ printk(KERN_INFO "Beagle expansionboard: assigning GPIO 141 and 162 to MMC1\n"); -+ mmc[1].gpio_wp = 141; -+ mmc[1].gpio_cd = 162; -+ } -+ - usb_musb_init(); - usb_ehci_init(&ehci_pdata); - omap3beagle_flash_init(); -@@ -652,6 +718,8 @@ static void __init omap3_beagle_map_io(void) - omap2_map_common_io(); - } - -+early_param("buddy", expansionboard_setup); -+ - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") - /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ - .phys_io = 0x48000000, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0008-ARM-OMAP-beagleboard-pre-export-GPIOs-to-userspace-w.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0008-ARM-OMAP-beagleboard-pre-export-GPIOs-to-userspace-w.patch deleted file mode 100644 index 88ca739d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0008-ARM-OMAP-beagleboard-pre-export-GPIOs-to-userspace-w.patch +++ /dev/null @@ -1,57 +0,0 @@ -From bf88487c59994b71cc57687915de0dc207a74b6b Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Mon, 3 May 2010 21:38:34 +0200 -Subject: [PATCH 08/45] ARM: OMAP: beagleboard: pre-export GPIOs to userspace when using a Tincantools trainerboard - -This really needs a for loop, patches welcome ---- - arch/arm/mach-omap2/board-omap3beagle.c | 33 ++++++++++++++++++++++++++++++- - 1 files changed, 32 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index ac96551..c9af202 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -701,7 +701,38 @@ static void __init omap3_beagle_init(void) - mmc[1].gpio_wp = 141; - mmc[1].gpio_cd = 162; - } -- -+ -+ if(!strcmp(expansionboard_name, "trainer")) -+ { -+ printk(KERN_INFO "Beagle expansionboard: exporting GPIOs 130-141,162 to userspace\n"); -+ gpio_request(130, "sysfs"); -+ gpio_export(130, 1); -+ gpio_request(131, "sysfs"); -+ gpio_export(131, 1); -+ gpio_request(132, "sysfs"); -+ gpio_export(132, 1); -+ gpio_request(133, "sysfs"); -+ gpio_export(133, 1); -+ gpio_request(134, "sysfs"); -+ gpio_export(134, 1); -+ gpio_request(135, "sysfs"); -+ gpio_export(135, 1); -+ gpio_request(136, "sysfs"); -+ gpio_export(136, 1); -+ gpio_request(137, "sysfs"); -+ gpio_export(137, 1); -+ gpio_request(138, "sysfs"); -+ gpio_export(138, 1); -+ gpio_request(139, "sysfs"); -+ gpio_export(139, 1); -+ gpio_request(140, "sysfs"); -+ gpio_export(140, 1); -+ gpio_request(141, "sysfs"); -+ gpio_export(141, 1); -+ gpio_request(162, "sysfs"); -+ gpio_export(162, 1); -+ } -+ - usb_musb_init(); - usb_ehci_init(&ehci_pdata); - omap3beagle_flash_init(); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0009-ARM-OMAP-beagleboard-initialize-ds1307-and-eeprom-on.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0009-ARM-OMAP-beagleboard-initialize-ds1307-and-eeprom-on.patch deleted file mode 100644 index 4079bcce..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0009-ARM-OMAP-beagleboard-initialize-ds1307-and-eeprom-on.patch +++ /dev/null @@ -1,76 +0,0 @@ -From f957bb53ba0c0056efd2c10d446ed9cfd6bd62ca Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Mon, 3 May 2010 22:31:34 +0200 -Subject: [PATCH 09/45] ARM: OMAP: beagleboard: initialize ds1307 and eeprom only for zippy and zippy2 - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 39 +++++++++++++++++++++++++++--- - 1 files changed, 35 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index c9af202..b3c8cb7 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -496,24 +496,55 @@ static struct i2c_board_info __initdata beagle_i2c1_boardinfo[] = { - }, - }; - -+ -+#if defined(CONFIG_EEPROM_AT24) || defined(CONFIG_EEPROM_AT24_MODULE) -+#include -+ -+static struct at24_platform_data m24c01 = { -+ .byte_len = SZ_1K / 8, -+ .page_size = 16, -+}; -+ - #if defined(CONFIG_RTC_DRV_DS1307) || \ - defined(CONFIG_RTC_DRV_DS1307_MODULE) - --static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { -+static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = { - { - I2C_BOARD_INFO("ds1307", 0x68), - }, -+ { -+ I2C_BOARD_INFO("24c01", 0x50), -+ .platform_data = &m24c01, -+ }, - }; - #else --static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = {}; -+static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = { -+ { -+ I2C_BOARD_INFO("24c01", 0x50), -+ .platform_data = &m24c01, -+ }, -+}; -+#endif -+#else -+static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = {}; - #endif - -+static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = {}; -+ - static int __init omap3_beagle_i2c_init(void) - { - omap_register_i2c_bus(1, 2600, beagle_i2c1_boardinfo, - ARRAY_SIZE(beagle_i2c1_boardinfo)); -- omap_register_i2c_bus(2, 400, beagle_i2c2_boardinfo, -- ARRAY_SIZE(beagle_i2c2_boardinfo)); -+ if(!strcmp(expansionboard_name, "zippy") || !strcmp(expansionboard_name, "zippy2")) -+ { -+ printk(KERN_INFO "Beagle expansionboard: registering i2c2 bus for zippy/zippy2\n"); -+ omap_register_i2c_bus(2, 400, beagle_zippy_i2c2_boardinfo, -+ ARRAY_SIZE(beagle_zippy_i2c2_boardinfo)); -+ } else -+ { -+ omap_register_i2c_bus(2, 400, beagle_i2c2_boardinfo, -+ ARRAY_SIZE(beagle_i2c2_boardinfo)); -+ } - /* Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, NULL, 0); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0010-ARM-OMAP-update-beagleboard-defconfig.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0010-ARM-OMAP-update-beagleboard-defconfig.patch deleted file mode 100644 index aea1ae2a..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0010-ARM-OMAP-update-beagleboard-defconfig.patch +++ /dev/null @@ -1,3323 +0,0 @@ -From b552461dec414a8e8705a226de2e6ef6d5931db9 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Tue, 27 Apr 2010 10:51:15 +0200 -Subject: [PATCH 10/45] ARM: OMAP: update beagleboard defconfig - ---- - arch/arm/configs/omap3_beagle_defconfig | 2514 +++++++++++++++++++++++++------ - 1 files changed, 2088 insertions(+), 426 deletions(-) - -diff --git a/arch/arm/configs/omap3_beagle_defconfig b/arch/arm/configs/omap3_beagle_defconfig -index 9cfae37..adb4f8c 100644 ---- a/arch/arm/configs/omap3_beagle_defconfig -+++ b/arch/arm/configs/omap3_beagle_defconfig -@@ -1,15 +1,13 @@ - # - # Automatically generated make config: don't edit --# Linux kernel version: 2.6.27-rc8 --# Wed Oct 1 17:14:22 2008 -+# Linux kernel version: 2.6.32 -+# Mon Apr 26 16:59:04 2010 - # - CONFIG_ARM=y - CONFIG_SYS_SUPPORTS_APM_EMULATION=y - CONFIG_GENERIC_GPIO=y - CONFIG_GENERIC_TIME=y - CONFIG_GENERIC_CLOCKEVENTS=y --CONFIG_MMU=y --# CONFIG_NO_IOPORT is not set - CONFIG_GENERIC_HARDIRQS=y - CONFIG_STACKTRACE_SUPPORT=y - CONFIG_HAVE_LATENCYTOP_SUPPORT=y -@@ -18,134 +16,183 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y - CONFIG_HARDIRQS_SW_RESEND=y - CONFIG_GENERIC_IRQ_PROBE=y - CONFIG_RWSEM_GENERIC_SPINLOCK=y --# CONFIG_ARCH_HAS_ILOG2_U32 is not set --# CONFIG_ARCH_HAS_ILOG2_U64 is not set -+CONFIG_ARCH_HAS_CPUFREQ=y - CONFIG_GENERIC_HWEIGHT=y - CONFIG_GENERIC_CALIBRATE_DELAY=y --CONFIG_ARCH_SUPPORTS_AOUT=y --CONFIG_ZONE_DMA=y - CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -+CONFIG_OPROFILE_ARMV7=y - CONFIG_VECTORS_BASE=0xffff0000 - CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+CONFIG_CONSTRUCTORS=y - - # - # General setup - # - CONFIG_EXPERIMENTAL=y - CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y - CONFIG_INIT_ENV_ARG_LIMIT=32 - CONFIG_LOCALVERSION="" --CONFIG_LOCALVERSION_AUTO=y -+# CONFIG_LOCALVERSION_AUTO is not set - CONFIG_SWAP=y - CONFIG_SYSVIPC=y - CONFIG_SYSVIPC_SYSCTL=y - # CONFIG_POSIX_MQUEUE is not set - CONFIG_BSD_PROCESS_ACCT=y - # CONFIG_BSD_PROCESS_ACCT_V3 is not set --# CONFIG_TASKSTATS is not set -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y - # CONFIG_AUDIT is not set --# CONFIG_IKCONFIG is not set --CONFIG_LOG_BUF_SHIFT=14 --# CONFIG_CGROUPS is not set -+ -+# -+# RCU Subsystem -+# -+CONFIG_TREE_RCU=y -+# CONFIG_TREE_PREEMPT_RCU is not set -+# CONFIG_TINY_RCU is not set -+# CONFIG_RCU_TRACE is not set -+CONFIG_RCU_FANOUT=32 -+# CONFIG_RCU_FANOUT_EXACT is not set -+# CONFIG_TREE_RCU_TRACE is not set -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_LOG_BUF_SHIFT=16 - CONFIG_GROUP_SCHED=y - CONFIG_FAIR_GROUP_SCHED=y - # CONFIG_RT_GROUP_SCHED is not set - CONFIG_USER_SCHED=y - # CONFIG_CGROUP_SCHED is not set --# CONFIG_SYSFS_DEPRECATED=y is not set --# CONFIG_SYSFS_DEPRECATED_V2=y is not set -+# CONFIG_CGROUPS is not set -+# CONFIG_SYSFS_DEPRECATED_V2 is not set - # CONFIG_RELAY is not set - # CONFIG_NAMESPACES is not set - CONFIG_BLK_DEV_INITRD=y - CONFIG_INITRAMFS_SOURCE="" -+CONFIG_RD_GZIP=y -+# CONFIG_RD_BZIP2 is not set -+# CONFIG_RD_LZMA is not set - CONFIG_CC_OPTIMIZE_FOR_SIZE=y - CONFIG_SYSCTL=y -+CONFIG_ANON_INODES=y - CONFIG_EMBEDDED=y - CONFIG_UID16=y - # CONFIG_SYSCTL_SYSCALL is not set - CONFIG_KALLSYMS=y - # CONFIG_KALLSYMS_ALL is not set --CONFIG_KALLSYMS_EXTRA_PASS=y -+# CONFIG_KALLSYMS_EXTRA_PASS is not set - CONFIG_HOTPLUG=y - CONFIG_PRINTK=y - CONFIG_BUG=y --CONFIG_ELF_CORE=y --CONFIG_COMPAT_BRK=y -+# CONFIG_ELF_CORE is not set - CONFIG_BASE_FULL=y - CONFIG_FUTEX=y --CONFIG_ANON_INODES=y - CONFIG_EPOLL=y - CONFIG_SIGNALFD=y - CONFIG_TIMERFD=y - CONFIG_EVENTFD=y - CONFIG_SHMEM=y -+CONFIG_AIO=y -+ -+# -+# Kernel Performance Events And Counters -+# - CONFIG_VM_EVENT_COUNTERS=y -+# CONFIG_COMPAT_BRK is not set - CONFIG_SLAB=y - # CONFIG_SLUB is not set - # CONFIG_SLOB is not set --# CONFIG_PROFILING is not set --# CONFIG_MARKERS is not set -+CONFIG_PROFILING=y -+CONFIG_TRACEPOINTS=y -+CONFIG_OPROFILE=y - CONFIG_HAVE_OPROFILE=y - # CONFIG_KPROBES is not set --# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set --# CONFIG_HAVE_IOREMAP_PROT is not set - CONFIG_HAVE_KPROBES=y - CONFIG_HAVE_KRETPROBES=y --# CONFIG_HAVE_ARCH_TRACEHOOK is not set --# CONFIG_HAVE_DMA_ATTRS is not set --# CONFIG_USE_GENERIC_SMP_HELPERS is not set - CONFIG_HAVE_CLK=y --CONFIG_PROC_PAGE_MONITOR=y -+ -+# -+# GCOV-based kernel profiling -+# -+# CONFIG_GCOV_KERNEL is not set -+CONFIG_SLOW_WORK=y -+# CONFIG_SLOW_WORK_DEBUG is not set - CONFIG_HAVE_GENERIC_DMA_COHERENT=y - CONFIG_SLABINFO=y - CONFIG_RT_MUTEXES=y --# CONFIG_TINY_SHMEM is not set - CONFIG_BASE_SMALL=0 - CONFIG_MODULES=y --# CONFIG_MODULE_FORCE_LOAD is not set -+CONFIG_MODULE_FORCE_LOAD=y - CONFIG_MODULE_UNLOAD=y --# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_MODULE_FORCE_UNLOAD=y - CONFIG_MODVERSIONS=y - CONFIG_MODULE_SRCVERSION_ALL=y --CONFIG_KMOD=y - CONFIG_BLOCK=y --# CONFIG_LBD is not set --# CONFIG_BLK_DEV_IO_TRACE is not set --# CONFIG_LSF is not set --# CONFIG_BLK_DEV_BSG is not set -+CONFIG_LBDAF=y -+CONFIG_BLK_DEV_BSG=y - # CONFIG_BLK_DEV_INTEGRITY is not set - - # - # IO Schedulers - # - CONFIG_IOSCHED_NOOP=y --CONFIG_IOSCHED_AS=y - CONFIG_IOSCHED_DEADLINE=y - CONFIG_IOSCHED_CFQ=y --CONFIG_DEFAULT_AS=y - # CONFIG_DEFAULT_DEADLINE is not set --# CONFIG_DEFAULT_CFQ is not set -+CONFIG_DEFAULT_CFQ=y - # CONFIG_DEFAULT_NOOP is not set --CONFIG_DEFAULT_IOSCHED="anticipatory" --CONFIG_CLASSIC_RCU=y -+CONFIG_DEFAULT_IOSCHED="cfq" -+# CONFIG_INLINE_SPIN_TRYLOCK is not set -+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -+# CONFIG_INLINE_SPIN_LOCK is not set -+# CONFIG_INLINE_SPIN_LOCK_BH is not set -+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -+# CONFIG_INLINE_SPIN_UNLOCK is not set -+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -+# CONFIG_INLINE_READ_TRYLOCK is not set -+# CONFIG_INLINE_READ_LOCK is not set -+# CONFIG_INLINE_READ_LOCK_BH is not set -+# CONFIG_INLINE_READ_LOCK_IRQ is not set -+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -+# CONFIG_INLINE_READ_UNLOCK is not set -+# CONFIG_INLINE_READ_UNLOCK_BH is not set -+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -+# CONFIG_INLINE_WRITE_TRYLOCK is not set -+# CONFIG_INLINE_WRITE_LOCK is not set -+# CONFIG_INLINE_WRITE_LOCK_BH is not set -+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -+# CONFIG_INLINE_WRITE_UNLOCK is not set -+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -+# CONFIG_MUTEX_SPIN_ON_OWNER is not set - CONFIG_FREEZER=y - - # - # System Type - # -+CONFIG_MMU=y - # CONFIG_ARCH_AAEC2000 is not set - # CONFIG_ARCH_INTEGRATOR is not set - # CONFIG_ARCH_REALVIEW is not set - # CONFIG_ARCH_VERSATILE is not set - # CONFIG_ARCH_AT91 is not set --# CONFIG_ARCH_CLPS7500 is not set - # CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_GEMINI is not set - # CONFIG_ARCH_EBSA110 is not set - # CONFIG_ARCH_EP93XX is not set - # CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_STMP3XXX is not set - # CONFIG_ARCH_NETX is not set - # CONFIG_ARCH_H720X is not set --# CONFIG_ARCH_IMX is not set -+# CONFIG_ARCH_NOMADIK is not set - # CONFIG_ARCH_IOP13XX is not set - # CONFIG_ARCH_IOP32X is not set - # CONFIG_ARCH_IOP33X is not set -@@ -153,23 +200,30 @@ CONFIG_FREEZER=y - # CONFIG_ARCH_IXP2000 is not set - # CONFIG_ARCH_IXP4XX is not set - # CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_DOVE is not set - # CONFIG_ARCH_KIRKWOOD is not set --# CONFIG_ARCH_KS8695 is not set --# CONFIG_ARCH_NS9XXX is not set - # CONFIG_ARCH_LOKI is not set - # CONFIG_ARCH_MV78XX0 is not set --# CONFIG_ARCH_MXC is not set - # CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_MMP is not set -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_NS9XXX is not set -+# CONFIG_ARCH_W90X900 is not set - # CONFIG_ARCH_PNX4008 is not set - # CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_MSM is not set - # CONFIG_ARCH_RPC is not set - # CONFIG_ARCH_SA1100 is not set - # CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_S3C64XX is not set -+# CONFIG_ARCH_S5PC1XX is not set - # CONFIG_ARCH_SHARK is not set - # CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_U300 is not set - # CONFIG_ARCH_DAVINCI is not set - CONFIG_ARCH_OMAP=y --# CONFIG_ARCH_MSM7X00A is not set -+# CONFIG_ARCH_BCMRING is not set -+# CONFIG_ARCH_U8500 is not set - - # - # TI OMAP Implementations -@@ -178,37 +232,55 @@ CONFIG_ARCH_OMAP_OTG=y - # CONFIG_ARCH_OMAP1 is not set - # CONFIG_ARCH_OMAP2 is not set - CONFIG_ARCH_OMAP3=y -+# CONFIG_ARCH_OMAP4 is not set - - # - # OMAP Feature Selections - # --# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set --# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set --# CONFIG_OMAP_RESET_CLOCKS is not set -+CONFIG_OMAP_SMARTREFLEX=y -+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -+CONFIG_OMAP_RESET_CLOCKS=y - # CONFIG_OMAP_MUX is not set --# CONFIG_OMAP_MCBSP is not set -+CONFIG_OMAP_MCBSP=y -+CONFIG_OMAP_MBOX_FWK=m -+CONFIG_OMAP_IOMMU=y - # CONFIG_OMAP_MPU_TIMER is not set - CONFIG_OMAP_32K_TIMER=y -+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -+# CONFIG_OMAP3_DEBOBS is not set - CONFIG_OMAP_32K_TIMER_HZ=128 - CONFIG_OMAP_DM_TIMER=y - # CONFIG_OMAP_LL_DEBUG_UART1 is not set - # CONFIG_OMAP_LL_DEBUG_UART2 is not set - CONFIG_OMAP_LL_DEBUG_UART3=y -+# CONFIG_OMAP_LL_DEBUG_NONE is not set -+# CONFIG_OMAP_PM_NONE is not set -+# CONFIG_OMAP_PM_NOOP is not set -+CONFIG_OMAP_PM_SRF=y - CONFIG_ARCH_OMAP34XX=y - CONFIG_ARCH_OMAP3430=y -+CONFIG_OMAP_PACKAGE_CBB=y - - # - # OMAP Board Type - # - CONFIG_MACH_OMAP3_BEAGLE=y -- --# --# Boot options --# -- --# --# Power management --# -+# CONFIG_MACH_OMAP_LDP is not set -+# CONFIG_MACH_OVERO is not set -+CONFIG_MACH_OMAP3EVM=y -+CONFIG_PMIC_TWL4030=y -+# CONFIG_MACH_OMAP3517EVM is not set -+# CONFIG_MACH_OMAP3_PANDORA is not set -+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -+# CONFIG_MACH_OMAP_3430SDP is not set -+# CONFIG_MACH_NOKIA_RX51 is not set -+# CONFIG_MACH_OMAP_ZOOM2 is not set -+# CONFIG_MACH_OMAP_ZOOM3 is not set -+# CONFIG_MACH_CM_T35 is not set -+# CONFIG_MACH_IGEP0020 is not set -+# CONFIG_MACH_OMAP_3630SDP is not set -+# CONFIG_OMAP3_EMU is not set -+# CONFIG_OMAP3_SDRC_AC_TIMING is not set - - # - # Processor Type -@@ -218,7 +290,7 @@ CONFIG_CPU_32v6K=y - CONFIG_CPU_V7=y - CONFIG_CPU_32v7=y - CONFIG_CPU_ABRT_EV7=y --CONFIG_CPU_PABRT_IFAR=y -+CONFIG_CPU_PABRT_V7=y - CONFIG_CPU_CACHE_V7=y - CONFIG_CPU_CACHE_VIPT=y - CONFIG_CPU_COPY_V6=y -@@ -231,12 +303,17 @@ CONFIG_CPU_CP15_MMU=y - # Processor Features - # - CONFIG_ARM_THUMB=y --# CONFIG_ARM_THUMBEE is not set -+CONFIG_ARM_THUMBEE=y - # CONFIG_CPU_ICACHE_DISABLE is not set - # CONFIG_CPU_DCACHE_DISABLE is not set - # CONFIG_CPU_BPREDICT_DISABLE is not set - CONFIG_HAS_TLS_REG=y --# CONFIG_OUTER_CACHE is not set -+CONFIG_ARM_L1_CACHE_SHIFT=6 -+CONFIG_USER_L2_PLE=y -+CONFIG_USER_PMON=y -+# CONFIG_ARM_ERRATA_430973 is not set -+# CONFIG_ARM_ERRATA_458693 is not set -+# CONFIG_ARM_ERRATA_460075 is not set - CONFIG_COMMON_CLKDEV=y - - # -@@ -257,42 +334,63 @@ CONFIG_VMSPLIT_3G=y - # CONFIG_VMSPLIT_2G is not set - # CONFIG_VMSPLIT_1G is not set - CONFIG_PAGE_OFFSET=0xC0000000 --# CONFIG_PREEMPT is not set -+# CONFIG_PREEMPT_NONE is not set -+# CONFIG_PREEMPT_VOLUNTARY is not set -+CONFIG_PREEMPT=y - CONFIG_HZ=128 -+# CONFIG_THUMB2_KERNEL is not set - CONFIG_AEABI=y --CONFIG_OABI_COMPAT=y --CONFIG_ARCH_FLATMEM_HAS_HOLES=y --# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set -+# CONFIG_OABI_COMPAT is not set -+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -+# CONFIG_HIGHMEM is not set - CONFIG_SELECT_MEMORY_MODEL=y - CONFIG_FLATMEM_MANUAL=y - # CONFIG_DISCONTIGMEM_MANUAL is not set - # CONFIG_SPARSEMEM_MANUAL is not set - CONFIG_FLATMEM=y - CONFIG_FLAT_NODE_MEM_MAP=y --# CONFIG_SPARSEMEM_STATIC is not set --# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set - CONFIG_PAGEFLAGS_EXTENDED=y - CONFIG_SPLIT_PTLOCK_CPUS=4 --# CONFIG_RESOURCES_64BIT is not set --CONFIG_ZONE_DMA_FLAG=1 --CONFIG_BOUNCE=y -+# CONFIG_PHYS_ADDR_T_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=0 - CONFIG_VIRT_TO_BUS=y --# CONFIG_LEDS is not set -+# CONFIG_KSM is not set -+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -+CONFIG_LEDS=y - CONFIG_ALIGNMENT_TRAP=y -+# CONFIG_UACCESS_WITH_MEMCPY is not set -+CONFIG_CPU_V7_SYSFS=y - - # - # Boot options - # - CONFIG_ZBOOT_ROM_TEXT=0x0 - CONFIG_ZBOOT_ROM_BSS=0x0 --CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" -+CONFIG_CMDLINE=" debug " - # CONFIG_XIP_KERNEL is not set --# CONFIG_KEXEC is not set -+CONFIG_KEXEC=y -+CONFIG_ATAGS_PROC=y - - # - # CPU Power Management - # --# CONFIG_CPU_FREQ is not set -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_TABLE=y -+CONFIG_CPU_FREQ_DEBUG=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y - # CONFIG_CPU_IDLE is not set - - # -@@ -302,29 +400,30 @@ CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.16 - # - # At least one emulation must be selected - # --CONFIG_FPE_NWFPE=y --# CONFIG_FPE_NWFPE_XP is not set --# CONFIG_FPE_FASTFPE is not set - CONFIG_VFP=y - CONFIG_VFPv3=y --# CONFIG_NEON is not set -+CONFIG_NEON=y - - # - # Userspace binary formats - # - CONFIG_BINFMT_ELF=y --# CONFIG_BINFMT_AOUT is not set -+CONFIG_HAVE_AOUT=y -+CONFIG_BINFMT_AOUT=m - CONFIG_BINFMT_MISC=y - - # - # Power management options - # - CONFIG_PM=y --# CONFIG_PM_DEBUG is not set -+CONFIG_PM_DEBUG=y -+# CONFIG_PM_VERBOSE is not set -+CONFIG_CAN_PM_TRACE=y - CONFIG_PM_SLEEP=y - CONFIG_SUSPEND=y - CONFIG_SUSPEND_FREEZER=y - # CONFIG_APM_EMULATION is not set -+CONFIG_PM_RUNTIME=y - CONFIG_ARCH_SUSPEND_POSSIBLE=y - CONFIG_NET=y - -@@ -332,13 +431,14 @@ CONFIG_NET=y - # Networking options - # - CONFIG_PACKET=y --# CONFIG_PACKET_MMAP is not set -+CONFIG_PACKET_MMAP=y - CONFIG_UNIX=y - CONFIG_XFRM=y - # CONFIG_XFRM_USER is not set - # CONFIG_XFRM_SUB_POLICY is not set - # CONFIG_XFRM_MIGRATE is not set - # CONFIG_XFRM_STATISTICS is not set -+CONFIG_XFRM_IPCOMP=m - CONFIG_NET_KEY=y - # CONFIG_NET_KEY_MIGRATE is not set - CONFIG_INET=y -@@ -349,63 +449,462 @@ CONFIG_IP_PNP=y - CONFIG_IP_PNP_DHCP=y - CONFIG_IP_PNP_BOOTP=y - CONFIG_IP_PNP_RARP=y --# CONFIG_NET_IPIP is not set --# CONFIG_NET_IPGRE is not set -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE=m - # CONFIG_ARPD is not set - # CONFIG_SYN_COOKIES is not set --# CONFIG_INET_AH is not set --# CONFIG_INET_ESP is not set --# CONFIG_INET_IPCOMP is not set --# CONFIG_INET_XFRM_TUNNEL is not set --# CONFIG_INET_TUNNEL is not set -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_TUNNEL=m -+CONFIG_INET_TUNNEL=m - CONFIG_INET_XFRM_MODE_TRANSPORT=y - CONFIG_INET_XFRM_MODE_TUNNEL=y - CONFIG_INET_XFRM_MODE_BEET=y --# CONFIG_INET_LRO is not set --CONFIG_INET_DIAG=y --CONFIG_INET_TCP_DIAG=y --# CONFIG_TCP_CONG_ADVANCED is not set -+CONFIG_INET_LRO=y -+CONFIG_INET_DIAG=m -+CONFIG_INET_TCP_DIAG=m -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_BIC=m - CONFIG_TCP_CONG_CUBIC=y -+CONFIG_TCP_CONG_WESTWOOD=m -+CONFIG_TCP_CONG_HTCP=m -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_VEGAS=m -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_YEAH=m -+CONFIG_TCP_CONG_ILLINOIS=m -+# CONFIG_DEFAULT_BIC is not set -+CONFIG_DEFAULT_CUBIC=y -+# CONFIG_DEFAULT_HTCP is not set -+# CONFIG_DEFAULT_VEGAS is not set -+# CONFIG_DEFAULT_WESTWOOD is not set -+# CONFIG_DEFAULT_RENO is not set - CONFIG_DEFAULT_TCP_CONG="cubic" - # CONFIG_TCP_MD5SIG is not set --# CONFIG_IPV6 is not set -+CONFIG_IPV6=m -+# CONFIG_IPV6_PRIVACY is not set -+# CONFIG_IPV6_ROUTER_PREF is not set -+# CONFIG_IPV6_OPTIMISTIC_DAD is not set -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=m -+CONFIG_INET6_XFRM_TUNNEL=m -+CONFIG_INET6_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_TRANSPORT=m -+CONFIG_INET6_XFRM_MODE_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_BEET=m -+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -+CONFIG_IPV6_SIT=m -+# CONFIG_IPV6_SIT_6RD is not set -+CONFIG_IPV6_NDISC_NODETYPE=y -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_SUBTREES=y -+CONFIG_IPV6_MROUTE=y -+# CONFIG_IPV6_PIMSM_V2 is not set - # CONFIG_NETWORK_SECMARK is not set --# CONFIG_NETFILTER is not set --# CONFIG_IP_DCCP is not set --# CONFIG_IP_SCTP is not set --# CONFIG_TIPC is not set --# CONFIG_ATM is not set --# CONFIG_BRIDGE is not set --# CONFIG_VLAN_8021Q is not set -+CONFIG_NETFILTER=y -+# CONFIG_NETFILTER_DEBUG is not set -+CONFIG_NETFILTER_ADVANCED=y -+CONFIG_BRIDGE_NETFILTER=y -+ -+# -+# Core Netfilter Configuration -+# -+CONFIG_NETFILTER_NETLINK=m -+CONFIG_NETFILTER_NETLINK_QUEUE=m -+CONFIG_NETFILTER_NETLINK_LOG=m -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CT_ACCT=y -+CONFIG_NF_CONNTRACK_MARK=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_GRE=m -+CONFIG_NF_CT_PROTO_SCTP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+# CONFIG_NETFILTER_TPROXY is not set -+CONFIG_NETFILTER_XTABLES=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -+CONFIG_NETFILTER_XT_TARGET_HL=m -+# CONFIG_NETFILTER_XT_TARGET_LED is not set -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -+CONFIG_NETFILTER_XT_TARGET_RATEEST=m -+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_HL=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -+CONFIG_NETFILTER_XT_MATCH_SCTP=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+# CONFIG_NETFILTER_XT_MATCH_OSF is not set -+CONFIG_IP_VS=m -+CONFIG_IP_VS_IPV6=y -+CONFIG_IP_VS_DEBUG=y -+CONFIG_IP_VS_TAB_BITS=12 -+ -+# -+# IPVS transport protocol load balancing support -+# -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_AH_ESP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+ -+# -+# IPVS scheduler -+# -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+ -+# -+# IPVS application helper -+# -+CONFIG_IP_VS_FTP=m -+ -+# -+# IP: Netfilter Configuration -+# -+CONFIG_NF_DEFRAG_IPV4=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_NF_CONNTRACK_PROC_COMPAT=y -+CONFIG_IP_NF_QUEUE=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_ADDRTYPE=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_TARGET_LOG=m -+CONFIG_IP_NF_TARGET_ULOG=m -+CONFIG_NF_NAT=m -+CONFIG_NF_NAT_NEEDED=y -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_NF_NAT_SNMP_BASIC=m -+CONFIG_NF_NAT_PROTO_DCCP=m -+CONFIG_NF_NAT_PROTO_GRE=m -+CONFIG_NF_NAT_PROTO_UDPLITE=m -+CONFIG_NF_NAT_PROTO_SCTP=m -+CONFIG_NF_NAT_FTP=m -+CONFIG_NF_NAT_IRC=m -+CONFIG_NF_NAT_TFTP=m -+CONFIG_NF_NAT_AMANDA=m -+CONFIG_NF_NAT_PPTP=m -+CONFIG_NF_NAT_H323=m -+CONFIG_NF_NAT_SIP=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+ -+# -+# IPv6: Netfilter Configuration -+# -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_IP6_NF_QUEUE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_TARGET_LOG=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+# CONFIG_BRIDGE_NF_EBTABLES is not set -+CONFIG_IP_DCCP=m -+CONFIG_INET_DCCP_DIAG=m -+ -+# -+# DCCP CCIDs Configuration (EXPERIMENTAL) -+# -+# CONFIG_IP_DCCP_CCID2_DEBUG is not set -+CONFIG_IP_DCCP_CCID3=y -+# CONFIG_IP_DCCP_CCID3_DEBUG is not set -+CONFIG_IP_DCCP_CCID3_RTO=100 -+CONFIG_IP_DCCP_TFRC_LIB=y -+ -+# -+# DCCP Kernel Hacking -+# -+# CONFIG_IP_DCCP_DEBUG is not set -+CONFIG_IP_SCTP=m -+# CONFIG_SCTP_DBG_MSG is not set -+# CONFIG_SCTP_DBG_OBJCNT is not set -+# CONFIG_SCTP_HMAC_NONE is not set -+# CONFIG_SCTP_HMAC_SHA1 is not set -+CONFIG_SCTP_HMAC_MD5=y -+# CONFIG_RDS is not set -+CONFIG_TIPC=m -+# CONFIG_TIPC_ADVANCED is not set -+# CONFIG_TIPC_DEBUG is not set -+CONFIG_ATM=m -+CONFIG_ATM_CLIP=m -+# CONFIG_ATM_CLIP_NO_ICMP is not set -+CONFIG_ATM_LANE=m -+CONFIG_ATM_MPOA=m -+CONFIG_ATM_BR2684=m -+# CONFIG_ATM_BR2684_IPFILTER is not set -+CONFIG_STP=m -+CONFIG_GARP=m -+CONFIG_BRIDGE=m -+# CONFIG_NET_DSA is not set -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y - # CONFIG_DECNET is not set -+CONFIG_LLC=m - # CONFIG_LLC2 is not set - # CONFIG_IPX is not set - # CONFIG_ATALK is not set - # CONFIG_X25 is not set - # CONFIG_LAPB is not set - # CONFIG_ECONET is not set --# CONFIG_WAN_ROUTER is not set --# CONFIG_NET_SCHED is not set -+CONFIG_WAN_ROUTER=m -+# CONFIG_PHONET is not set -+# CONFIG_IEEE802154 is not set -+CONFIG_NET_SCHED=y -+ -+# -+# Queueing/Scheduling -+# -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_ATM=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+ -+# -+# Classification -+# -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_ROUTE=y -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_PERF=y -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+# CONFIG_NET_EMATCH is not set -+# CONFIG_NET_CLS_ACT is not set -+CONFIG_NET_CLS_IND=y -+CONFIG_NET_SCH_FIFO=y -+# CONFIG_DCB is not set - - # - # Network testing - # - # CONFIG_NET_PKTGEN is not set -+# CONFIG_NET_DROP_MONITOR is not set - # CONFIG_HAMRADIO is not set --# CONFIG_CAN is not set --# CONFIG_IRDA is not set --# CONFIG_BT is not set --# CONFIG_AF_RXRPC is not set -- --# --# Wireless --# --# CONFIG_CFG80211 is not set --# CONFIG_WIRELESS_EXT is not set --# CONFIG_MAC80211 is not set --# CONFIG_IEEE80211 is not set --# CONFIG_RFKILL is not set --# CONFIG_NET_9P is not set -+CONFIG_CAN=m -+CONFIG_CAN_RAW=m -+CONFIG_CAN_BCM=m -+ -+# -+# CAN Device Drivers -+# -+CONFIG_CAN_VCAN=m -+# CONFIG_CAN_DEV is not set -+# CONFIG_CAN_DEBUG_DEVICES is not set -+CONFIG_IRDA=m -+ -+# -+# IrDA protocols -+# -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+ -+# -+# IrDA options -+# -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRDA_DEBUG=y -+ -+# -+# Infrared-port device drivers -+# -+ -+# -+# SIR device drivers -+# -+CONFIG_IRTTY_SIR=m -+ -+# -+# Dongle support -+# -+CONFIG_DONGLE=y -+CONFIG_ESI_DONGLE=m -+CONFIG_ACTISYS_DONGLE=m -+CONFIG_TEKRAM_DONGLE=m -+CONFIG_TOIM3232_DONGLE=m -+CONFIG_LITELINK_DONGLE=m -+CONFIG_MA600_DONGLE=m -+CONFIG_GIRBIL_DONGLE=m -+CONFIG_MCP2120_DONGLE=m -+CONFIG_OLD_BELKIN_DONGLE=m -+# CONFIG_ACT200L_DONGLE is not set -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+ -+# -+# FIR device drivers -+# -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_L2CAP=m -+CONFIG_BT_SCO=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+ -+# -+# Bluetooth device drivers -+# -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBTSDIO=m -+CONFIG_BT_HCIUART=m -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+# CONFIG_BT_HCIVHCI is not set -+# CONFIG_BT_MRVL is not set -+CONFIG_AF_RXRPC=m -+# CONFIG_AF_RXRPC_DEBUG is not set -+# CONFIG_RXKAD is not set -+CONFIG_FIB_RULES=y -+CONFIG_WIRELESS=y -+CONFIG_WIRELESS_EXT=y -+CONFIG_WEXT_CORE=y -+CONFIG_WEXT_PROC=y -+CONFIG_WEXT_SPY=y -+CONFIG_WEXT_PRIV=y -+CONFIG_CFG80211=m -+# CONFIG_NL80211_TESTMODE is not set -+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -+# CONFIG_CFG80211_REG_DEBUG is not set -+CONFIG_CFG80211_DEFAULT_PS=y -+# CONFIG_CFG80211_DEBUGFS is not set -+CONFIG_WIRELESS_OLD_REGULATORY=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_WIRELESS_EXT_SYSFS=y -+CONFIG_LIB80211=y -+CONFIG_LIB80211_CRYPT_WEP=m -+CONFIG_LIB80211_CRYPT_CCMP=m -+CONFIG_LIB80211_CRYPT_TKIP=m -+# CONFIG_LIB80211_DEBUG is not set -+CONFIG_MAC80211=m -+CONFIG_MAC80211_RC_PID=y -+# CONFIG_MAC80211_RC_MINSTREL is not set -+CONFIG_MAC80211_RC_DEFAULT_PID=y -+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -+CONFIG_MAC80211_RC_DEFAULT="pid" -+# CONFIG_MAC80211_MESH is not set -+CONFIG_MAC80211_LEDS=y -+# CONFIG_MAC80211_DEBUGFS is not set -+# CONFIG_MAC80211_DEBUG_MENU is not set -+CONFIG_WIMAX=m -+CONFIG_WIMAX_DEBUG_LEVEL=8 -+CONFIG_RFKILL=m -+CONFIG_RFKILL_LEDS=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_NET_9P=m -+# CONFIG_NET_9P_DEBUG is not set - - # - # Device Drivers -@@ -414,17 +913,22 @@ CONFIG_DEFAULT_TCP_CONG="cubic" - # - # Generic Driver Options - # --CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_UEVENT_HELPER_PATH="" -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y - CONFIG_STANDALONE=y - CONFIG_PREVENT_FIRMWARE_BUILD=y --# CONFIG_FW_LOADER is not set -+CONFIG_FW_LOADER=y -+CONFIG_FIRMWARE_IN_KERNEL=y -+CONFIG_EXTRA_FIRMWARE="" - # CONFIG_DEBUG_DRIVER is not set - # CONFIG_DEBUG_DEVRES is not set - # CONFIG_SYS_HYPERVISOR is not set - # CONFIG_CONNECTOR is not set - CONFIG_MTD=y - # CONFIG_MTD_DEBUG is not set --# CONFIG_MTD_CONCAT is not set -+# CONFIG_MTD_TESTS is not set -+CONFIG_MTD_CONCAT=y - CONFIG_MTD_PARTITIONS=y - # CONFIG_MTD_REDBOOT_PARTS is not set - # CONFIG_MTD_CMDLINE_PARTS is not set -@@ -472,6 +976,9 @@ CONFIG_MTD_CFI_I2=y - # - # Self-contained MTD device drivers - # -+# CONFIG_MTD_DATAFLASH is not set -+# CONFIG_MTD_M25P80 is not set -+# CONFIG_MTD_SST25L is not set - # CONFIG_MTD_SLRAM is not set - # CONFIG_MTD_PHRAM is not set - # CONFIG_MTD_MTDRAM is not set -@@ -487,38 +994,82 @@ CONFIG_MTD_NAND=y - # CONFIG_MTD_NAND_VERIFY_WRITE is not set - # CONFIG_MTD_NAND_ECC_SMC is not set - # CONFIG_MTD_NAND_MUSEUM_IDS is not set -+# CONFIG_MTD_NAND_GPIO is not set -+CONFIG_MTD_NAND_OMAP2=y -+CONFIG_MTD_NAND_OMAP_PREFETCH=y -+# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set - CONFIG_MTD_NAND_IDS=y - # CONFIG_MTD_NAND_DISKONCHIP is not set - # CONFIG_MTD_NAND_NANDSIM is not set --# CONFIG_MTD_NAND_PLATFORM is not set -+CONFIG_MTD_NAND_PLATFORM=y - # CONFIG_MTD_ALAUDA is not set - # CONFIG_MTD_ONENAND is not set - - # -+# LPDDR flash memory drivers -+# -+# CONFIG_MTD_LPDDR is not set -+ -+# - # UBI - Unsorted block images - # --# CONFIG_MTD_UBI is not set -+CONFIG_MTD_UBI=y -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_RESERVE=1 -+# CONFIG_MTD_UBI_GLUEBI is not set -+ -+# -+# UBI debugging options -+# -+# CONFIG_MTD_UBI_DEBUG is not set - # CONFIG_PARPORT is not set - CONFIG_BLK_DEV=y - # CONFIG_BLK_DEV_COW_COMMON is not set - CONFIG_BLK_DEV_LOOP=y --# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+ -+# -+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -+# - # CONFIG_BLK_DEV_NBD is not set - # CONFIG_BLK_DEV_UB is not set - CONFIG_BLK_DEV_RAM=y - CONFIG_BLK_DEV_RAM_COUNT=16 - CONFIG_BLK_DEV_RAM_SIZE=16384 - # CONFIG_BLK_DEV_XIP is not set --# CONFIG_CDROM_PKTCDVD is not set -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_CDROM_PKTCDVD_BUFFERS=8 -+# CONFIG_CDROM_PKTCDVD_WCACHE is not set - # CONFIG_ATA_OVER_ETH is not set --# CONFIG_MISC_DEVICES is not set -+# CONFIG_MG_DISK is not set -+CONFIG_MISC_DEVICES=y -+# CONFIG_AD525X_DPOT is not set -+# CONFIG_ICS932S401 is not set -+# CONFIG_ENCLOSURE_SERVICES is not set -+CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -+# CONFIG_ISL29003 is not set -+# CONFIG_DS1682 is not set -+# CONFIG_TI_DAC7512 is not set -+# CONFIG_C2PORT is not set -+ -+# -+# EEPROM support -+# -+# CONFIG_EEPROM_AT24 is not set -+# CONFIG_EEPROM_AT25 is not set -+# CONFIG_EEPROM_LEGACY is not set -+# CONFIG_EEPROM_MAX6875 is not set -+CONFIG_EEPROM_93CX6=y -+CONFIG_IWMC3200TOP=m -+# CONFIG_IWMC3200TOP_DEBUG is not set -+# CONFIG_IWMC3200TOP_DEBUGFS is not set - CONFIG_HAVE_IDE=y - # CONFIG_IDE is not set - - # - # SCSI device support - # --# CONFIG_RAID_ATTRS is not set -+CONFIG_RAID_ATTRS=m - CONFIG_SCSI=y - CONFIG_SCSI_DMA=y - # CONFIG_SCSI_TGT is not set -@@ -531,14 +1082,11 @@ CONFIG_SCSI_PROC_FS=y - CONFIG_BLK_DEV_SD=y - # CONFIG_CHR_DEV_ST is not set - # CONFIG_CHR_DEV_OSST is not set --# CONFIG_BLK_DEV_SR is not set --# CONFIG_CHR_DEV_SG is not set --# CONFIG_CHR_DEV_SCH is not set -- --# --# Some SCSI devices (e.g. CD jukebox) support multiple LUNs --# --# CONFIG_SCSI_MULTI_LUN is not set -+CONFIG_BLK_DEV_SR=y -+CONFIG_BLK_DEV_SR_VENDOR=y -+CONFIG_CHR_DEV_SG=y -+CONFIG_CHR_DEV_SCH=m -+CONFIG_SCSI_MULTI_LUN=y - # CONFIG_SCSI_CONSTANTS is not set - # CONFIG_SCSI_LOGGING is not set - # CONFIG_SCSI_SCAN_ASYNC is not set -@@ -549,78 +1097,277 @@ CONFIG_SCSI_WAIT_SCAN=m - # - # CONFIG_SCSI_SPI_ATTRS is not set - # CONFIG_SCSI_FC_ATTRS is not set --# CONFIG_SCSI_ISCSI_ATTRS is not set -+CONFIG_SCSI_ISCSI_ATTRS=m -+# CONFIG_SCSI_SAS_ATTRS is not set - # CONFIG_SCSI_SAS_LIBSAS is not set - # CONFIG_SCSI_SRP_ATTRS is not set - CONFIG_SCSI_LOWLEVEL=y --# CONFIG_ISCSI_TCP is not set -+CONFIG_ISCSI_TCP=m -+# CONFIG_LIBFC is not set -+# CONFIG_LIBFCOE is not set - # CONFIG_SCSI_DEBUG is not set - # CONFIG_SCSI_DH is not set -+# CONFIG_SCSI_OSD_INITIATOR is not set - # CONFIG_ATA is not set --# CONFIG_MD is not set -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_MD_LINEAR=m -+CONFIG_MD_RAID0=m -+CONFIG_MD_RAID1=m -+CONFIG_MD_RAID10=m -+CONFIG_MD_RAID456=m -+CONFIG_MD_RAID6_PQ=m -+# CONFIG_ASYNC_RAID6_TEST is not set -+CONFIG_MD_MULTIPATH=m -+CONFIG_MD_FAULTY=m -+CONFIG_BLK_DEV_DM=m -+# CONFIG_DM_DEBUG is not set -+CONFIG_DM_CRYPT=m -+CONFIG_DM_SNAPSHOT=m -+CONFIG_DM_MIRROR=m -+# CONFIG_DM_LOG_USERSPACE is not set -+CONFIG_DM_ZERO=m -+CONFIG_DM_MULTIPATH=m -+# CONFIG_DM_MULTIPATH_QL is not set -+# CONFIG_DM_MULTIPATH_ST is not set -+CONFIG_DM_DELAY=m -+# CONFIG_DM_UEVENT is not set - CONFIG_NETDEVICES=y --# CONFIG_DUMMY is not set --# CONFIG_BONDING is not set --# CONFIG_MACVLAN is not set --# CONFIG_EQUALIZER is not set --# CONFIG_TUN is not set --# CONFIG_VETH is not set --# CONFIG_NET_ETHERNET is not set -+CONFIG_DUMMY=m -+CONFIG_BONDING=m -+CONFIG_MACVLAN=m -+CONFIG_EQUALIZER=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_PHYLIB=y -+ -+# -+# MII PHY device drivers -+# -+# CONFIG_MARVELL_PHY is not set -+# CONFIG_DAVICOM_PHY is not set -+# CONFIG_QSEMI_PHY is not set -+# CONFIG_LXT_PHY is not set -+# CONFIG_CICADA_PHY is not set -+# CONFIG_VITESSE_PHY is not set -+# CONFIG_SMSC_PHY is not set -+# CONFIG_BROADCOM_PHY is not set -+# CONFIG_ICPLUS_PHY is not set -+# CONFIG_REALTEK_PHY is not set -+# CONFIG_NATIONAL_PHY is not set -+# CONFIG_STE10XP is not set -+# CONFIG_LSI_ET1011C_PHY is not set -+# CONFIG_FIXED_PHY is not set -+# CONFIG_MDIO_BITBANG is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_AX88796 is not set -+# CONFIG_SMC91X is not set -+# CONFIG_TI_DAVINCI_EMAC is not set -+# CONFIG_DM9000 is not set -+CONFIG_ENC28J60=y -+# CONFIG_ENC28J60_WRITEVERIFY is not set -+# CONFIG_ETHOC is not set -+CONFIG_SMC911X=y -+CONFIG_SMSC911X=y -+# CONFIG_DNET is not set -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -+# CONFIG_B44 is not set -+# CONFIG_KS8842 is not set -+CONFIG_KS8851=y -+# CONFIG_KS8851_MLL is not set - # CONFIG_NETDEV_1000 is not set - # CONFIG_NETDEV_10000 is not set -- --# --# Wireless LAN --# --# CONFIG_WLAN_PRE80211 is not set --# CONFIG_WLAN_80211 is not set --# CONFIG_IWLWIFI_LEDS is not set -+CONFIG_WLAN=y -+# CONFIG_LIBERTAS_THINFIRM is not set -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_RTL8187_LEDS=y -+# CONFIG_MAC80211_HWSIM is not set -+# CONFIG_ATH_COMMON is not set -+CONFIG_B43=m -+# CONFIG_B43_SDIO is not set -+CONFIG_B43_PHY_LP=y -+CONFIG_B43_LEDS=y -+CONFIG_B43_HWRNG=y -+# CONFIG_B43_DEBUG is not set -+# CONFIG_B43LEGACY is not set -+CONFIG_HOSTAP=m -+CONFIG_HOSTAP_FIRMWARE=y -+CONFIG_HOSTAP_FIRMWARE_NVRAM=y -+# CONFIG_IWM is not set -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+# CONFIG_LIBERTAS_SDIO is not set -+# CONFIG_LIBERTAS_SPI is not set -+# CONFIG_LIBERTAS_DEBUG is not set -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+# CONFIG_P54_SPI is not set -+CONFIG_P54_LEDS=y -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+# CONFIG_RT2800USB is not set -+CONFIG_RT2X00_LIB_USB=m -+CONFIG_RT2X00_LIB=m -+CONFIG_RT2X00_LIB_FIRMWARE=y -+CONFIG_RT2X00_LIB_CRYPTO=y -+CONFIG_RT2X00_LIB_LEDS=y -+# CONFIG_RT2X00_DEBUG is not set -+CONFIG_WL12XX=m -+CONFIG_WL1251=m -+CONFIG_WL1251_SPI=m -+CONFIG_WL1251_SDIO=m -+CONFIG_WL1271=m -+CONFIG_ZD1211RW=m -+# CONFIG_ZD1211RW_DEBUG is not set -+ -+# -+# WiMAX Wireless Broadband devices -+# -+CONFIG_WIMAX_I2400M=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_WIMAX_I2400M_SDIO=m -+CONFIG_WIMAX_IWMC3200_SDIO=y -+CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 - - # - # USB Network Adapters - # --# CONFIG_USB_CATC is not set --# CONFIG_USB_KAWETH is not set --# CONFIG_USB_PEGASUS is not set --# CONFIG_USB_RTL8150 is not set --# CONFIG_USB_USBNET is not set -+CONFIG_USB_CATC=y -+CONFIG_USB_KAWETH=y -+CONFIG_USB_PEGASUS=y -+CONFIG_USB_RTL8150=y -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=y -+CONFIG_USB_NET_CDCETHER=y -+CONFIG_USB_NET_CDC_EEM=y -+CONFIG_USB_NET_DM9601=y -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=y -+CONFIG_USB_NET_NET1080=y -+CONFIG_USB_NET_PLUSB=y -+CONFIG_USB_NET_MCS7830=y -+CONFIG_USB_NET_RNDIS_HOST=y -+CONFIG_USB_NET_CDC_SUBSET=y -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_BELKIN=y -+CONFIG_USB_ARMLINUX=y -+CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y -+CONFIG_USB_NET_ZAURUS=y -+CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m - # CONFIG_WAN is not set --# CONFIG_PPP is not set -+CONFIG_ATM_DRIVERS=y -+# CONFIG_ATM_DUMMY is not set -+# CONFIG_ATM_TCP is not set -+CONFIG_PPP=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_MPPE=m -+CONFIG_PPPOE=m -+# CONFIG_PPPOATM is not set -+CONFIG_PPPOL2TP=m - # CONFIG_SLIP is not set --# CONFIG_NETCONSOLE is not set --# CONFIG_NETPOLL is not set --# CONFIG_NET_POLL_CONTROLLER is not set -+CONFIG_SLHC=m -+CONFIG_NETCONSOLE=m -+CONFIG_NETCONSOLE_DYNAMIC=y -+CONFIG_NETPOLL=y -+CONFIG_NETPOLL_TRAP=y -+CONFIG_NET_POLL_CONTROLLER=y - # CONFIG_ISDN is not set -+# CONFIG_PHONE is not set - - # - # Input device support - # - CONFIG_INPUT=y --# CONFIG_INPUT_FF_MEMLESS is not set --# CONFIG_INPUT_POLLDEV is not set -+CONFIG_INPUT_FF_MEMLESS=y -+CONFIG_INPUT_POLLDEV=y -+# CONFIG_INPUT_SPARSEKMAP is not set - - # - # Userland interfaces - # --# CONFIG_INPUT_MOUSEDEV is not set -+CONFIG_INPUT_MOUSEDEV=y -+CONFIG_INPUT_MOUSEDEV_PSAUX=y -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 - # CONFIG_INPUT_JOYDEV is not set --# CONFIG_INPUT_EVDEV is not set -+CONFIG_INPUT_EVDEV=y - # CONFIG_INPUT_EVBUG is not set - - # - # Input Device Drivers - # --# CONFIG_INPUT_KEYBOARD is not set --# CONFIG_INPUT_MOUSE is not set -+CONFIG_INPUT_KEYBOARD=y -+# CONFIG_KEYBOARD_ADP5588 is not set -+# CONFIG_KEYBOARD_ATKBD is not set -+# CONFIG_QT2160 is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+CONFIG_KEYBOARD_GPIO=y -+# CONFIG_KEYBOARD_TCA6416 is not set -+# CONFIG_KEYBOARD_MATRIX is not set -+# CONFIG_KEYBOARD_LM8323 is not set -+# CONFIG_KEYBOARD_MAX7359 is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_OPENCORES is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_TWL4030 is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+CONFIG_INPUT_MOUSE=y -+CONFIG_MOUSE_PS2=y -+CONFIG_MOUSE_PS2_ALPS=y -+CONFIG_MOUSE_PS2_LOGIPS2PP=y -+CONFIG_MOUSE_PS2_SYNAPTICS=y -+CONFIG_MOUSE_PS2_TRACKPOINT=y -+# CONFIG_MOUSE_PS2_ELANTECH is not set -+# CONFIG_MOUSE_PS2_SENTELIC is not set -+# CONFIG_MOUSE_PS2_TOUCHKIT is not set -+# CONFIG_MOUSE_SERIAL is not set -+# CONFIG_MOUSE_APPLETOUCH is not set -+# CONFIG_MOUSE_BCM5974 is not set -+# CONFIG_MOUSE_VSXXXAA is not set -+# CONFIG_MOUSE_GPIO is not set -+# CONFIG_MOUSE_SYNAPTICS_I2C is not set - # CONFIG_INPUT_JOYSTICK is not set - # CONFIG_INPUT_TABLET is not set - # CONFIG_INPUT_TOUCHSCREEN is not set --# CONFIG_INPUT_MISC is not set -+CONFIG_INPUT_MISC=y -+# CONFIG_INPUT_ATI_REMOTE is not set -+# CONFIG_INPUT_ATI_REMOTE2 is not set -+# CONFIG_INPUT_KEYSPAN_REMOTE is not set -+# CONFIG_INPUT_POWERMATE is not set -+# CONFIG_INPUT_YEALINK is not set -+# CONFIG_INPUT_CM109 is not set -+CONFIG_INPUT_TWL4030_PWRBUTTON=y -+CONFIG_INPUT_UINPUT=y -+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - - # - # Hardware I/O ports - # --# CONFIG_SERIO is not set -+CONFIG_SERIO=y -+CONFIG_SERIO_SERPORT=y -+CONFIG_SERIO_LIBPS2=y -+# CONFIG_SERIO_RAW is not set -+# CONFIG_SERIO_ALTERA_PS2 is not set - # CONFIG_GAMEPORT is not set - - # -@@ -630,7 +1377,7 @@ CONFIG_VT=y - CONFIG_CONSOLE_TRANSLATIONS=y - CONFIG_VT_CONSOLE=y - CONFIG_HW_CONSOLE=y --# CONFIG_VT_HW_CONSOLE_BINDING is not set -+CONFIG_VT_HW_CONSOLE_BINDING=y - CONFIG_DEVKMEM=y - # CONFIG_SERIAL_NONSTANDARD is not set - -@@ -650,18 +1397,21 @@ CONFIG_SERIAL_8250_RSA=y - # - # Non-8250 serial port support - # -+# CONFIG_SERIAL_MAX3100 is not set - CONFIG_SERIAL_CORE=y - CONFIG_SERIAL_CORE_CONSOLE=y - CONFIG_UNIX98_PTYS=y -+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set - # CONFIG_LEGACY_PTYS is not set - # CONFIG_IPMI_HANDLER is not set - CONFIG_HW_RANDOM=y --# CONFIG_NVRAM is not set -+# CONFIG_HW_RANDOM_TIMERIOMEM is not set - # CONFIG_R3964 is not set - # CONFIG_RAW_DRIVER is not set - # CONFIG_TCG_TPM is not set - CONFIG_I2C=y - CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_COMPAT=y - CONFIG_I2C_CHARDEV=y - CONFIG_I2C_HELPER_AUTO=y - -@@ -672,6 +1422,7 @@ CONFIG_I2C_HELPER_AUTO=y - # - # I2C system bus drivers (mostly embedded / system-on-chip) - # -+# CONFIG_I2C_DESIGNWARE is not set - # CONFIG_I2C_GPIO is not set - # CONFIG_I2C_OCORES is not set - CONFIG_I2C_OMAP=y -@@ -693,26 +1444,41 @@ CONFIG_I2C_OMAP=y - # - # Miscellaneous I2C Chip support - # --# CONFIG_DS1682 is not set --# CONFIG_EEPROM_AT24 is not set --# CONFIG_EEPROM_LEGACY is not set --# CONFIG_SENSORS_PCF8574 is not set --# CONFIG_PCF8575 is not set --# CONFIG_SENSORS_PCA9539 is not set --# CONFIG_SENSORS_PCF8591 is not set --# CONFIG_ISP1301_OMAP is not set --# CONFIG_TPS65010 is not set --# CONFIG_SENSORS_MAX6875 is not set - # CONFIG_SENSORS_TSL2550 is not set - # CONFIG_I2C_DEBUG_CORE is not set - # CONFIG_I2C_DEBUG_ALGO is not set - # CONFIG_I2C_DEBUG_BUS is not set - # CONFIG_I2C_DEBUG_CHIP is not set --# CONFIG_SPI is not set -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+# CONFIG_SPI_BITBANG is not set -+# CONFIG_SPI_GPIO is not set -+CONFIG_SPI_OMAP24XX=y -+# CONFIG_SPI_XILINX is not set -+ -+# -+# SPI Protocol Masters -+# -+CONFIG_SPI_SPIDEV=y -+# CONFIG_SPI_TLE62X0 is not set -+ -+# -+# PPS support -+# -+# CONFIG_PPS is not set - CONFIG_ARCH_REQUIRE_GPIOLIB=y - CONFIG_GPIOLIB=y - # CONFIG_DEBUG_GPIO is not set --# CONFIG_GPIO_SYSFS is not set -+CONFIG_GPIO_SYSFS=y -+ -+# -+# Memory mapped GPIO expanders: -+# - - # - # I2C GPIO expanders: -@@ -729,49 +1495,469 @@ CONFIG_GPIO_TWL4030=y - # - # SPI GPIO expanders: - # -+# CONFIG_GPIO_MAX7301 is not set -+# CONFIG_GPIO_MCP23S08 is not set -+# CONFIG_GPIO_MC33880 is not set -+ -+# -+# AC97 GPIO expanders: -+# - # CONFIG_W1 is not set --# CONFIG_POWER_SUPPLY is not set --# CONFIG_HWMON is not set --# CONFIG_THERMAL is not set --# CONFIG_THERMAL_HWMON is not set --# CONFIG_WATCHDOG is not set -+CONFIG_POWER_SUPPLY=m -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+# CONFIG_PDA_POWER is not set -+# CONFIG_BATTERY_DS2760 is not set -+# CONFIG_BATTERY_DS2782 is not set -+# CONFIG_BATTERY_BQ27x00 is not set -+# CONFIG_BATTERY_MAX17040 is not set -+CONFIG_HWMON=y -+# CONFIG_HWMON_VID is not set -+# CONFIG_HWMON_DEBUG_CHIP is not set -+ -+# -+# Native drivers -+# -+# CONFIG_SENSORS_AD7414 is not set -+# CONFIG_SENSORS_AD7418 is not set -+# CONFIG_SENSORS_ADCXX is not set -+# CONFIG_SENSORS_ADM1021 is not set -+# CONFIG_SENSORS_ADM1025 is not set -+# CONFIG_SENSORS_ADM1026 is not set -+# CONFIG_SENSORS_ADM1029 is not set -+# CONFIG_SENSORS_ADM1031 is not set -+# CONFIG_SENSORS_ADM9240 is not set -+# CONFIG_SENSORS_ADT7462 is not set -+# CONFIG_SENSORS_ADT7470 is not set -+# CONFIG_SENSORS_ADT7473 is not set -+# CONFIG_SENSORS_ADT7475 is not set -+# CONFIG_SENSORS_ATXP1 is not set -+# CONFIG_SENSORS_DS1621 is not set -+# CONFIG_SENSORS_F71805F is not set -+# CONFIG_SENSORS_F71882FG is not set -+# CONFIG_SENSORS_F75375S is not set -+# CONFIG_SENSORS_G760A is not set -+# CONFIG_SENSORS_GL518SM is not set -+# CONFIG_SENSORS_GL520SM is not set -+# CONFIG_SENSORS_IT87 is not set -+# CONFIG_SENSORS_LM63 is not set -+# CONFIG_SENSORS_LM70 is not set -+# CONFIG_SENSORS_LM73 is not set -+# CONFIG_SENSORS_LM75 is not set -+# CONFIG_SENSORS_LM77 is not set -+# CONFIG_SENSORS_LM78 is not set -+# CONFIG_SENSORS_LM80 is not set -+# CONFIG_SENSORS_LM83 is not set -+# CONFIG_SENSORS_LM85 is not set -+# CONFIG_SENSORS_LM87 is not set -+# CONFIG_SENSORS_LM90 is not set -+# CONFIG_SENSORS_LM92 is not set -+# CONFIG_SENSORS_LM93 is not set -+# CONFIG_SENSORS_LTC4215 is not set -+# CONFIG_SENSORS_LTC4245 is not set -+# CONFIG_SENSORS_LM95241 is not set -+# CONFIG_SENSORS_MAX1111 is not set -+# CONFIG_SENSORS_MAX1619 is not set -+# CONFIG_SENSORS_MAX6650 is not set -+# CONFIG_SENSORS_PC87360 is not set -+# CONFIG_SENSORS_PC87427 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_SHT15 is not set -+# CONFIG_SENSORS_DME1737 is not set -+# CONFIG_SENSORS_SMSC47M1 is not set -+# CONFIG_SENSORS_SMSC47M192 is not set -+# CONFIG_SENSORS_SMSC47B397 is not set -+# CONFIG_SENSORS_ADS7828 is not set -+# CONFIG_SENSORS_THMC50 is not set -+# CONFIG_SENSORS_TMP401 is not set -+# CONFIG_SENSORS_TMP421 is not set -+# CONFIG_SENSORS_VT1211 is not set -+# CONFIG_SENSORS_W83781D is not set -+# CONFIG_SENSORS_W83791D is not set -+# CONFIG_SENSORS_W83792D is not set -+# CONFIG_SENSORS_W83793 is not set -+# CONFIG_SENSORS_W83L785TS is not set -+# CONFIG_SENSORS_W83L786NG is not set -+# CONFIG_SENSORS_W83627HF is not set -+# CONFIG_SENSORS_W83627EHF is not set -+# CONFIG_SENSORS_LIS3_SPI is not set -+CONFIG_THERMAL=y -+CONFIG_THERMAL_HWMON=y -+CONFIG_WATCHDOG=y -+CONFIG_WATCHDOG_NOWAYOUT=y -+ -+# -+# Watchdog Device Drivers -+# -+# CONFIG_SOFT_WATCHDOG is not set -+CONFIG_OMAP_WATCHDOG=y -+# CONFIG_TWL4030_WATCHDOG is not set -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_SSB_POSSIBLE=y - - # - # Sonics Silicon Backplane - # --CONFIG_SSB_POSSIBLE=y --# CONFIG_SSB is not set -+CONFIG_SSB=y -+CONFIG_SSB_SDIOHOST_POSSIBLE=y -+# CONFIG_SSB_SDIOHOST is not set -+# CONFIG_SSB_SILENT is not set -+# CONFIG_SSB_DEBUG is not set - - # - # Multifunction device drivers - # --# CONFIG_MFD_CORE is not set -+CONFIG_MFD_CORE=y - # CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set - # CONFIG_HTC_EGPIO is not set - # CONFIG_HTC_PASIC3 is not set -+# CONFIG_TPS65010 is not set - CONFIG_TWL4030_CORE=y --# CONFIG_UCB1400_CORE is not set -+CONFIG_TWL4030_POWER=y -+CONFIG_TWL4030_CODEC=y -+# CONFIG_TWL4030_MADC is not set - # CONFIG_MFD_TMIO is not set - # CONFIG_MFD_T7L66XB is not set - # CONFIG_MFD_TC6387XB is not set - # CONFIG_MFD_TC6393XB is not set -- --# --# Multimedia devices --# -+# CONFIG_PMIC_DA903X is not set -+# CONFIG_PMIC_ADP5520 is not set -+# CONFIG_MFD_WM8400 is not set -+# CONFIG_MFD_WM831X is not set -+# CONFIG_MFD_WM8350_I2C is not set -+# CONFIG_MFD_PCF50633 is not set -+# CONFIG_MFD_MC13783 is not set -+# CONFIG_AB3100_CORE is not set -+# CONFIG_EZX_PCAP is not set -+# CONFIG_MFD_88PM8607 is not set -+# CONFIG_AB4500_CORE is not set -+CONFIG_REGULATOR=y -+# CONFIG_REGULATOR_DEBUG is not set -+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -+# CONFIG_REGULATOR_BQ24022 is not set -+# CONFIG_REGULATOR_MAX1586 is not set -+CONFIG_REGULATOR_TWL4030=y -+# CONFIG_REGULATOR_LP3971 is not set -+# CONFIG_REGULATOR_TPS65023 is not set -+# CONFIG_REGULATOR_TPS6507X is not set -+CONFIG_MEDIA_SUPPORT=y - - # - # Multimedia core support - # --# CONFIG_VIDEO_DEV is not set --# CONFIG_DVB_CORE is not set --# CONFIG_VIDEO_MEDIA is not set -+CONFIG_VIDEO_DEV=y -+CONFIG_VIDEO_V4L2_COMMON=y -+CONFIG_VIDEO_ALLOW_V4L1=y -+CONFIG_VIDEO_V4L1_COMPAT=y -+CONFIG_DVB_CORE=m -+CONFIG_VIDEO_MEDIA=m - - # - # Multimedia drivers - # --CONFIG_DAB=y --# CONFIG_USB_DABUSB is not set -+CONFIG_MEDIA_ATTACH=y -+CONFIG_MEDIA_TUNER=m -+CONFIG_MEDIA_TUNER_CUSTOMISE=y -+CONFIG_MEDIA_TUNER_SIMPLE=m -+CONFIG_MEDIA_TUNER_TDA8290=m -+CONFIG_MEDIA_TUNER_TDA827X=m -+CONFIG_MEDIA_TUNER_TDA18271=m -+CONFIG_MEDIA_TUNER_TDA9887=m -+CONFIG_MEDIA_TUNER_TEA5761=m -+CONFIG_MEDIA_TUNER_TEA5767=m -+CONFIG_MEDIA_TUNER_MT20XX=m -+CONFIG_MEDIA_TUNER_MT2060=m -+CONFIG_MEDIA_TUNER_MT2266=m -+CONFIG_MEDIA_TUNER_MT2131=m -+CONFIG_MEDIA_TUNER_QT1010=m -+CONFIG_MEDIA_TUNER_XC2028=m -+CONFIG_MEDIA_TUNER_XC5000=m -+CONFIG_MEDIA_TUNER_MXL5005S=m -+CONFIG_MEDIA_TUNER_MXL5007T=m -+CONFIG_MEDIA_TUNER_MC44S803=m -+CONFIG_MEDIA_TUNER_MAX2165=m -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_V4L1=y -+CONFIG_VIDEOBUF_GEN=y -+CONFIG_VIDEOBUF_DMA_SG=y -+CONFIG_VIDEOBUF_VMALLOC=m -+CONFIG_VIDEOBUF_DMA_CONTIG=y -+CONFIG_VIDEOBUF_DVB=m -+CONFIG_VIDEO_IR=m -+CONFIG_VIDEO_TVEEPROM=m -+CONFIG_VIDEO_TUNER=m -+CONFIG_VIDEO_CAPTURE_DRIVERS=y -+# CONFIG_VIDEO_ADV_DEBUG is not set -+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -+CONFIG_VIDEO_IR_I2C=m -+ -+# -+# Encoders/decoders and other helper chips -+# -+ -+# -+# Audio decoders -+# -+# CONFIG_VIDEO_TVAUDIO is not set -+# CONFIG_VIDEO_TDA7432 is not set -+# CONFIG_VIDEO_TDA9840 is not set -+# CONFIG_VIDEO_TDA9875 is not set -+# CONFIG_VIDEO_TEA6415C is not set -+# CONFIG_VIDEO_TEA6420 is not set -+CONFIG_VIDEO_MSP3400=m -+# CONFIG_VIDEO_CS5345 is not set -+CONFIG_VIDEO_CS53L32A=m -+# CONFIG_VIDEO_M52790 is not set -+# CONFIG_VIDEO_TLV320AIC23B is not set -+CONFIG_VIDEO_WM8775=m -+# CONFIG_VIDEO_WM8739 is not set -+# CONFIG_VIDEO_VP27SMPX is not set -+ -+# -+# RDS decoders -+# -+# CONFIG_VIDEO_SAA6588 is not set -+ -+# -+# Video decoders -+# -+# CONFIG_VIDEO_ADV7180 is not set -+# CONFIG_VIDEO_BT819 is not set -+# CONFIG_VIDEO_BT856 is not set -+# CONFIG_VIDEO_BT866 is not set -+# CONFIG_VIDEO_KS0127 is not set -+# CONFIG_VIDEO_OV7670 is not set -+CONFIG_VIDEO_MT9V011=m -+# CONFIG_VIDEO_TCM825X is not set -+CONFIG_VIDEO_MT9P012=m -+# CONFIG_VIDEO_MT9T111 is not set -+# CONFIG_VIDEO_DW9710 is not set -+# CONFIG_VIDEO_OV3640 is not set -+# CONFIG_VIDEO_IMX046 is not set -+# CONFIG_VIDEO_LV8093 is not set -+# CONFIG_VIDEO_SAA7110 is not set -+CONFIG_VIDEO_SAA711X=m -+# CONFIG_VIDEO_SAA717X is not set -+# CONFIG_VIDEO_SAA7191 is not set -+# CONFIG_VIDEO_TVP514X is not set -+# CONFIG_VIDEO_TVP5150 is not set -+# CONFIG_VIDEO_VPX3220 is not set -+ -+# -+# Video and audio decoders -+# -+CONFIG_VIDEO_CX25840=m -+ -+# -+# MPEG video encoders -+# -+CONFIG_VIDEO_CX2341X=m -+ -+# -+# Video encoders -+# -+# CONFIG_VIDEO_SAA7127 is not set -+# CONFIG_VIDEO_SAA7185 is not set -+# CONFIG_VIDEO_ADV7170 is not set -+# CONFIG_VIDEO_ADV7175 is not set -+# CONFIG_VIDEO_THS7303 is not set -+# CONFIG_VIDEO_ADV7343 is not set -+ -+# -+# Video improvement chips -+# -+# CONFIG_VIDEO_UPD64031A is not set -+# CONFIG_VIDEO_UPD64083 is not set -+CONFIG_VIDEO_VIVI=m -+# CONFIG_VIDEO_CPIA is not set -+# CONFIG_VIDEO_CPIA2 is not set -+# CONFIG_VIDEO_SAA5246A is not set -+# CONFIG_VIDEO_SAA5249 is not set -+# CONFIG_VIDEO_AU0828 is not set -+CONFIG_TI_MEDIA=y -+CONFIG_VIDEO_VPSS_SYSTEM=y -+CONFIG_VIDEO_VPFE_CAPTURE=y -+# CONFIG_VIDEO_DM6446_CCDC is not set -+# CONFIG_VIDEO_DM355_CCDC is not set -+CONFIG_VIDEO_OMAP2_VOUT=y -+CONFIG_VIDEO_OMAP3=y -+CONFIG_VIDEO_OMAP3_ISP=y -+CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -+CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -+# CONFIG_SOC_CAMERA is not set -+CONFIG_V4L_USB_DRIVERS=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -+CONFIG_USB_GSPCA=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+# CONFIG_USB_GL860 is not set -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+# CONFIG_USB_GSPCA_JEILINJ is not set -+CONFIG_USB_GSPCA_MARS=m -+# CONFIG_USB_GSPCA_MR97310A is not set -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_PAC207=m -+# CONFIG_USB_GSPCA_PAC7302 is not set -+CONFIG_USB_GSPCA_PAC7311=m -+# CONFIG_USB_GSPCA_SN9C20X is not set -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+# CONFIG_USB_GSPCA_SQ905 is not set -+# CONFIG_USB_GSPCA_SQ905C is not set -+CONFIG_USB_GSPCA_STK014=m -+# CONFIG_USB_GSPCA_STV0680 is not set -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_PVRUSB2_SYSFS=y -+CONFIG_VIDEO_PVRUSB2_DVB=y -+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_VIDEO_CX231XX=m -+# CONFIG_VIDEO_CX231XX_ALSA is not set -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_USBVIDEO=m -+CONFIG_USB_VICAM=m -+CONFIG_USB_IBMCAM=m -+CONFIG_USB_KONICAWC=m -+CONFIG_USB_QUICKCAM_MESSENGER=m -+CONFIG_USB_ET61X251=m -+CONFIG_VIDEO_OVCAMCHIP=m -+CONFIG_USB_W9968CF=m -+CONFIG_USB_OV511=m -+CONFIG_USB_SE401=m -+CONFIG_USB_SN9C102=m -+CONFIG_USB_STV680=m -+CONFIG_USB_ZC0301=m -+CONFIG_USB_PWC=m -+# CONFIG_USB_PWC_DEBUG is not set -+CONFIG_USB_PWC_INPUT_EVDEV=y -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_RADIO_ADAPTERS=y -+# CONFIG_I2C_SI4713 is not set -+# CONFIG_RADIO_SI4713 is not set -+# CONFIG_USB_DSBR is not set -+# CONFIG_RADIO_SI470X is not set -+# CONFIG_USB_MR800 is not set -+# CONFIG_RADIO_TEA5764 is not set -+# CONFIG_RADIO_TEF6862 is not set -+CONFIG_DVB_MAX_ADAPTERS=8 -+CONFIG_DVB_DYNAMIC_MINORS=y -+CONFIG_DVB_CAPTURE_DRIVERS=y -+# CONFIG_TTPCI_EEPROM is not set -+ -+# -+# Supported USB Adapters -+# -+CONFIG_DVB_USB=m -+# CONFIG_DVB_USB_DEBUG is not set -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AF9015=m -+# CONFIG_DVB_USB_CE6230 is not set -+# CONFIG_DVB_USB_FRIIO is not set -+# CONFIG_DVB_USB_EC168 is not set -+# CONFIG_SMS_SIANO_MDTV is not set -+ -+# -+# Supported FlexCopII (B2C2) Adapters -+# -+CONFIG_DVB_B2C2_FLEXCOP=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set -+ -+# -+# Supported DVB Frontends -+# -+# CONFIG_DVB_FE_CUSTOMISE is not set -+CONFIG_DVB_CX24123=m -+CONFIG_DVB_MT312=m -+CONFIG_DVB_ZL10039=m -+CONFIG_DVB_S5H1420=m -+CONFIG_DVB_STV0288=m -+CONFIG_DVB_STB6000=m -+CONFIG_DVB_STV0299=m -+CONFIG_DVB_TDA10086=m -+CONFIG_DVB_TUNER_ITD1000=m -+CONFIG_DVB_TUNER_CX24113=m -+CONFIG_DVB_TDA826X=m -+CONFIG_DVB_CX24116=m -+CONFIG_DVB_SI21XX=m -+CONFIG_DVB_CX22702=m -+CONFIG_DVB_TDA1004X=m -+CONFIG_DVB_NXT6000=m -+CONFIG_DVB_MT352=m -+CONFIG_DVB_ZL10353=m -+CONFIG_DVB_DIB3000MB=m -+CONFIG_DVB_DIB3000MC=m -+CONFIG_DVB_DIB7000M=m -+CONFIG_DVB_DIB7000P=m -+CONFIG_DVB_TDA10048=m -+CONFIG_DVB_AF9013=m -+CONFIG_DVB_TDA10021=m -+CONFIG_DVB_TDA10023=m -+CONFIG_DVB_STV0297=m -+CONFIG_DVB_NXT200X=m -+CONFIG_DVB_BCM3510=m -+CONFIG_DVB_LGDT330X=m -+CONFIG_DVB_LGDT3305=m -+CONFIG_DVB_S5H1409=m -+CONFIG_DVB_S5H1411=m -+CONFIG_DVB_DIB8000=m -+CONFIG_DVB_PLL=m -+CONFIG_DVB_TUNER_DIB0070=m -+CONFIG_DVB_LNBP21=m -+CONFIG_DVB_ISL6421=m -+CONFIG_DVB_LGS8GL5=m -+# CONFIG_DAB is not set - - # - # Graphics support -@@ -781,6 +1967,7 @@ CONFIG_DAB=y - CONFIG_FB=y - # CONFIG_FIRMWARE_EDID is not set - # CONFIG_FB_DDC is not set -+# CONFIG_FB_BOOT_VESA_SUPPORT is not set - CONFIG_FB_CFB_FILLRECT=y - CONFIG_FB_CFB_COPYAREA=y - CONFIG_FB_CFB_IMAGEBLIT=y -@@ -793,24 +1980,57 @@ CONFIG_FB_CFB_IMAGEBLIT=y - # CONFIG_FB_SVGALIB is not set - # CONFIG_FB_MACMODES is not set - # CONFIG_FB_BACKLIGHT is not set --# CONFIG_FB_MODE_HELPERS is not set -+CONFIG_FB_MODE_HELPERS=y - # CONFIG_FB_TILEBLITTING is not set - - # - # Frame buffer hardware drivers - # - # CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_TMIO is not set - # CONFIG_FB_VIRTUAL is not set --CONFIG_FB_OMAP=y --# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set -+# CONFIG_FB_METRONOME is not set -+# CONFIG_FB_MB862XX is not set -+# CONFIG_FB_BROADSHEET is not set - # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set --CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2 -+CONFIG_OMAP2_VRAM=y -+CONFIG_OMAP2_VRFB=y -+CONFIG_OMAP2_DSS=y -+CONFIG_OMAP2_VRAM_SIZE=14 -+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -+# CONFIG_OMAP2_DSS_RFBI is not set -+CONFIG_OMAP2_DSS_VENC=y -+CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -+# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -+# CONFIG_OMAP2_DSS_SDI is not set -+CONFIG_OMAP2_DSS_DSI=y -+CONFIG_OMAP2_DSS_USE_DSI_PLL=y -+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -+CONFIG_FB_OMAP2=y -+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -+CONFIG_FB_OMAP2_NUM_FBS=3 -+ -+# -+# OMAP2/3 Display Device Drivers -+# -+CONFIG_PANEL_GENERIC=y -+# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -+CONFIG_PANEL_SHARP_LS037V7DW01=y -+# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -+# CONFIG_PANEL_TAAL is not set - # CONFIG_BACKLIGHT_LCD_SUPPORT is not set - - # - # Display device support - # --# CONFIG_DISPLAY_SUPPORT is not set -+CONFIG_DISPLAY_SUPPORT=y -+ -+# -+# Display hardware drivers -+# - - # - # Console display driver support -@@ -820,31 +2040,113 @@ CONFIG_DUMMY_CONSOLE=y - CONFIG_FRAMEBUFFER_CONSOLE=y - # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set - CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y --CONFIG_FONTS=y -+# CONFIG_FONTS is not set - CONFIG_FONT_8x8=y - CONFIG_FONT_8x16=y --# CONFIG_FONT_6x11 is not set --# CONFIG_FONT_7x14 is not set --# CONFIG_FONT_PEARL_8x8 is not set --# CONFIG_FONT_ACORN_8x8 is not set --# CONFIG_FONT_MINI_4x6 is not set --# CONFIG_FONT_SUN8x16 is not set --# CONFIG_FONT_SUN12x22 is not set --# CONFIG_FONT_10x18 is not set --# CONFIG_LOGO is not set -- --# --# Sound --# --# CONFIG_SOUND is not set --# CONFIG_HID_SUPPORT is not set -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_LOGO_LINUX_CLUT224=y -+CONFIG_SOUND=y -+CONFIG_SOUND_OSS_CORE=y -+CONFIG_SOUND_OSS_CORE_PRECLAIM=y -+CONFIG_SND=y -+CONFIG_SND_TIMER=y -+CONFIG_SND_PCM=y -+CONFIG_SND_HWDEP=y -+CONFIG_SND_RAWMIDI=y -+CONFIG_SND_JACK=y -+CONFIG_SND_SEQUENCER=m -+# CONFIG_SND_SEQ_DUMMY is not set -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=y -+CONFIG_SND_PCM_OSS=y -+CONFIG_SND_PCM_OSS_PLUGINS=y -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -+# CONFIG_SND_DYNAMIC_MINORS is not set -+CONFIG_SND_SUPPORT_OLD_API=y -+CONFIG_SND_VERBOSE_PROCFS=y -+# CONFIG_SND_VERBOSE_PRINTK is not set -+# CONFIG_SND_DEBUG is not set -+CONFIG_SND_RAWMIDI_SEQ=m -+# CONFIG_SND_OPL3_LIB_SEQ is not set -+# CONFIG_SND_OPL4_LIB_SEQ is not set -+# CONFIG_SND_SBAWE_SEQ is not set -+# CONFIG_SND_EMU10K1_SEQ is not set -+CONFIG_SND_DRIVERS=y -+# CONFIG_SND_DUMMY is not set -+# CONFIG_SND_VIRMIDI is not set -+# CONFIG_SND_MTPAV is not set -+# CONFIG_SND_SERIAL_U16550 is not set -+# CONFIG_SND_MPU401 is not set -+# CONFIG_SND_ARM is not set -+CONFIG_SND_SPI=y -+CONFIG_SND_USB=y -+CONFIG_SND_USB_AUDIO=y -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_SOC=y -+CONFIG_SND_OMAP_SOC=y -+CONFIG_SND_OMAP_SOC_MCBSP=y -+# CONFIG_SND_OMAP_SOC_OMAP3EVM is not set -+CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -+CONFIG_SND_SOC_I2C_AND_SPI=y -+# CONFIG_SND_SOC_ALL_CODECS is not set -+CONFIG_SND_SOC_TWL4030=y -+# CONFIG_SOUND_PRIME is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+# CONFIG_HIDRAW is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_HID_PID is not set -+# CONFIG_USB_HIDDEV is not set -+ -+# -+# Special HID drivers -+# -+CONFIG_HID_A4TECH=y -+CONFIG_HID_APPLE=y -+CONFIG_HID_BELKIN=y -+CONFIG_HID_CHERRY=y -+CONFIG_HID_CHICONY=y -+CONFIG_HID_CYPRESS=y -+# CONFIG_HID_DRAGONRISE is not set -+CONFIG_HID_EZKEY=y -+# CONFIG_HID_KYE is not set -+CONFIG_HID_GYRATION=y -+# CONFIG_HID_TWINHAN is not set -+# CONFIG_HID_KENSINGTON is not set -+CONFIG_HID_LOGITECH=y -+# CONFIG_LOGITECH_FF is not set -+# CONFIG_LOGIRUMBLEPAD2_FF is not set -+CONFIG_HID_MICROSOFT=y -+CONFIG_HID_MONTEREY=y -+CONFIG_HID_NTRIG=y -+CONFIG_HID_PANTHERLORD=y -+# CONFIG_PANTHERLORD_FF is not set -+CONFIG_HID_PETALYNX=y -+CONFIG_HID_SAMSUNG=y -+CONFIG_HID_SONY=y -+CONFIG_HID_SUNPLUS=y -+# CONFIG_HID_GREENASIA is not set -+# CONFIG_HID_SMARTJOYPLUS is not set -+CONFIG_HID_TOPSEED=y -+# CONFIG_HID_THRUSTMASTER is not set -+# CONFIG_HID_WACOM is not set -+# CONFIG_HID_ZEROPLUS is not set - CONFIG_USB_SUPPORT=y - CONFIG_USB_ARCH_HAS_HCD=y - CONFIG_USB_ARCH_HAS_OHCI=y - CONFIG_USB_ARCH_HAS_EHCI=y - CONFIG_USB=y - # CONFIG_USB_DEBUG is not set --# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - - # - # Miscellaneous USB options -@@ -857,18 +2159,25 @@ CONFIG_USB_OTG=y - # CONFIG_USB_OTG_WHITELIST is not set - # CONFIG_USB_OTG_BLACKLIST_HUB is not set - CONFIG_USB_MON=y -+# CONFIG_USB_WUSB is not set -+# CONFIG_USB_WUSB_CBAF is not set - - # - # USB Host Controller Drivers - # --CONFIG_USB_EHCI_HCD=y --CONFIG_USB_EHCI_ROOT_HUB_TT=y - # CONFIG_USB_C67X00_HCD is not set -+CONFIG_USB_EHCI_HCD=y -+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+# CONFIG_USB_OXU210HP_HCD is not set - # CONFIG_USB_ISP116X_HCD is not set - # CONFIG_USB_ISP1760_HCD is not set -+# CONFIG_USB_ISP1362_HCD is not set - # CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_U132_HCD is not set - # CONFIG_USB_SL811_HCD is not set - # CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_HWA_HCD is not set - CONFIG_USB_MUSB_HDRC=y - CONFIG_USB_MUSB_SOC=y - -@@ -882,24 +2191,39 @@ CONFIG_USB_GADGET_MUSB_HDRC=y - CONFIG_USB_MUSB_HDRC_HCD=y - # CONFIG_MUSB_PIO_ONLY is not set - CONFIG_USB_INVENTRA_DMA=y -+CONFIG_MUSB_USE_SYSTEM_DMA_RX=y - # CONFIG_USB_TI_CPPI_DMA is not set -+# CONFIG_USB_TI_CPPI41_DMA is not set - # CONFIG_USB_MUSB_DEBUG is not set - - # - # USB Device Class drivers - # --# CONFIG_USB_ACM is not set --# CONFIG_USB_PRINTER is not set --# CONFIG_USB_WDM is not set -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+CONFIG_USB_WDM=m -+CONFIG_USB_TMC=m - - # --# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' -+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may - # - - # --# may also be needed; see USB_STORAGE Help for more information -+# also be needed; see USB_STORAGE Help for more info - # --# CONFIG_USB_STORAGE is not set -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+# CONFIG_USB_STORAGE_DATAFAB is not set -+# CONFIG_USB_STORAGE_FREECOM is not set -+# CONFIG_USB_STORAGE_ISD200 is not set -+# CONFIG_USB_STORAGE_USBAT is not set -+# CONFIG_USB_STORAGE_SDDR09 is not set -+# CONFIG_USB_STORAGE_SDDR55 is not set -+# CONFIG_USB_STORAGE_JUMPSHOT is not set -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set - # CONFIG_USB_LIBUSUAL is not set - - # -@@ -911,92 +2235,200 @@ CONFIG_USB_INVENTRA_DMA=y - # - # USB port drivers - # --# CONFIG_USB_SERIAL is not set -+CONFIG_USB_SERIAL=m -+CONFIG_USB_EZUSB=y -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+# CONFIG_USB_SERIAL_CP210X is not set -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_FUNSOFT=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KEYSPAN_MPR=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19=y -+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_MOTOROLA=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+# CONFIG_USB_SERIAL_QUALCOMM is not set -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_HP4X=m -+CONFIG_USB_SERIAL_SAFE=m -+# CONFIG_USB_SERIAL_SAFE_PADDED is not set -+CONFIG_USB_SERIAL_SIEMENS_MPI=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+# CONFIG_USB_SERIAL_SYMBOL is not set -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_DEBUG=m - - # - # USB Miscellaneous drivers - # --# CONFIG_USB_EMI62 is not set --# CONFIG_USB_EMI26 is not set -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m - # CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_SEVSEG is not set - # CONFIG_USB_RIO500 is not set --# CONFIG_USB_LEGOTOWER is not set --# CONFIG_USB_LCD is not set --# CONFIG_USB_BERRY_CHARGE is not set --# CONFIG_USB_LED is not set --# CONFIG_USB_CYPRESS_CY7C63 is not set --# CONFIG_USB_CYTHERM is not set --# CONFIG_USB_PHIDGET is not set --# CONFIG_USB_IDMOUSE is not set --# CONFIG_USB_FTDI_ELAN is not set -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_BERRY_CHARGE=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m - # CONFIG_USB_APPLEDISPLAY is not set --# CONFIG_USB_LD is not set --# CONFIG_USB_TRANCEVIBRATOR is not set -+CONFIG_USB_SISUSBVGA=m -+CONFIG_USB_SISUSBVGA_CON=y -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m - # CONFIG_USB_IOWARRIOR is not set --# CONFIG_USB_TEST is not set -+CONFIG_USB_TEST=m - # CONFIG_USB_ISIGHTFW is not set -+CONFIG_USB_VST=m -+CONFIG_USB_ATM=m -+CONFIG_USB_SPEEDTOUCH=m -+CONFIG_USB_CXACRU=m -+CONFIG_USB_UEAGLEATM=m -+CONFIG_USB_XUSBATM=m - CONFIG_USB_GADGET=y - # CONFIG_USB_GADGET_DEBUG is not set - # CONFIG_USB_GADGET_DEBUG_FILES is not set -+CONFIG_USB_GADGET_DEBUG_FS=y -+CONFIG_USB_GADGET_VBUS_DRAW=2 - CONFIG_USB_GADGET_SELECTED=y --# CONFIG_USB_GADGET_AMD5536UDC is not set -+# CONFIG_USB_GADGET_AT91 is not set - # CONFIG_USB_GADGET_ATMEL_USBA is not set - # CONFIG_USB_GADGET_FSL_USB2 is not set --# CONFIG_USB_GADGET_NET2280 is not set --# CONFIG_USB_GADGET_PXA25X is not set --# CONFIG_USB_GADGET_M66592 is not set --# CONFIG_USB_M66592 is not set --# CONFIG_USB_GADGET_PXA27X is not set --# CONFIG_USB_GADGET_GOKU is not set - # CONFIG_USB_GADGET_LH7A40X is not set - # CONFIG_USB_GADGET_OMAP is not set -+# CONFIG_USB_GADGET_PXA25X is not set -+# CONFIG_USB_GADGET_R8A66597 is not set -+# CONFIG_USB_GADGET_PXA27X is not set -+# CONFIG_USB_GADGET_S3C_HSOTG is not set -+# CONFIG_USB_GADGET_IMX is not set - # CONFIG_USB_GADGET_S3C2410 is not set --# CONFIG_USB_GADGET_AT91 is not set -+# CONFIG_USB_GADGET_M66592 is not set -+# CONFIG_USB_GADGET_AMD5536UDC is not set -+# CONFIG_USB_GADGET_FSL_QE is not set -+# CONFIG_USB_GADGET_CI13XXX is not set -+# CONFIG_USB_GADGET_NET2280 is not set -+# CONFIG_USB_GADGET_GOKU is not set -+# CONFIG_USB_GADGET_LANGWELL is not set - # CONFIG_USB_GADGET_DUMMY_HCD is not set - CONFIG_USB_GADGET_DUALSPEED=y --# CONFIG_USB_ZERO is not set -+CONFIG_USB_ZERO=m -+CONFIG_USB_ZERO_HNPTEST=y -+# CONFIG_USB_AUDIO is not set - CONFIG_USB_ETH=m - CONFIG_USB_ETH_RNDIS=y --# CONFIG_USB_GADGETFS is not set --# CONFIG_USB_FILE_STORAGE is not set --# CONFIG_USB_G_SERIAL is not set --# CONFIG_USB_MIDI_GADGET is not set --# CONFIG_USB_G_PRINTER is not set --# CONFIG_USB_CDC_COMPOSITE is not set -+# CONFIG_USB_ETH_EEM is not set -+CONFIG_USB_GADGETFS=m -+CONFIG_USB_FILE_STORAGE=m -+# CONFIG_USB_FILE_STORAGE_TEST is not set -+# CONFIG_USB_MASS_STORAGE is not set -+CONFIG_USB_G_SERIAL=m -+CONFIG_USB_MIDI_GADGET=m -+CONFIG_USB_G_PRINTER=m -+CONFIG_USB_CDC_COMPOSITE=m -+# CONFIG_USB_G_MULTI is not set - - # - # OTG and related infrastructure - # - CONFIG_USB_OTG_UTILS=y --# CONFIG_USB_GPIO_VBUS is not set -+CONFIG_USB_GPIO_VBUS=y -+# CONFIG_ISP1301_OMAP is not set -+# CONFIG_USB_ULPI is not set - CONFIG_TWL4030_USB=y --# CONFIG_NOP_USB_XCEIV is not set -+CONFIG_NOP_USB_XCEIV=y - CONFIG_MMC=y - # CONFIG_MMC_DEBUG is not set --# CONFIG_MMC_UNSAFE_RESUME is not set -+CONFIG_MMC_UNSAFE_RESUME=y - - # --# MMC/SD Card Drivers -+# MMC/SD/SDIO Card Drivers - # - CONFIG_MMC_BLOCK=y - CONFIG_MMC_BLOCK_BOUNCE=y --# CONFIG_SDIO_UART is not set -+CONFIG_SDIO_UART=y - # CONFIG_MMC_TEST is not set - - # --# MMC/SD Host Controller Drivers -+# MMC/SD/SDIO Host Controller Drivers - # - # CONFIG_MMC_SDHCI is not set - # CONFIG_MMC_OMAP is not set - CONFIG_MMC_OMAP_HS=y -+# CONFIG_MMC_AT91 is not set -+# CONFIG_MMC_ATMELMCI is not set -+CONFIG_MMC_SPI=m - # CONFIG_MEMSTICK is not set -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+ -+# -+# LED drivers -+# -+# CONFIG_LEDS_PCA9532 is not set -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_GPIO_PLATFORM=y -+# CONFIG_LEDS_LP3944 is not set -+# CONFIG_LEDS_PCA955X is not set -+# CONFIG_LEDS_DAC124S085 is not set -+# CONFIG_LEDS_BD2802 is not set -+ -+# -+# LED Triggers -+# -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=m -+# CONFIG_LEDS_TRIGGER_GPIO is not set -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -+ -+# -+# iptables trigger is under Netfilter config (LED target) -+# - # CONFIG_ACCESSIBILITY is not set --# CONFIG_NEW_LEDS is not set - CONFIG_RTC_LIB=y --CONFIG_RTC_CLASS=y --CONFIG_RTC_HCTOSYS=y --CONFIG_RTC_HCTOSYS_DEVICE="rtc0" --# CONFIG_RTC_DEBUG is not set -+CONFIG_RTC_CLASS=m - - # - # RTC interfaces -@@ -1020,73 +2452,178 @@ CONFIG_RTC_INTF_DEV=y - # CONFIG_RTC_DRV_PCF8563 is not set - # CONFIG_RTC_DRV_PCF8583 is not set - # CONFIG_RTC_DRV_M41T80 is not set -+CONFIG_RTC_DRV_TWL4030=m - # CONFIG_RTC_DRV_S35390A is not set - # CONFIG_RTC_DRV_FM3130 is not set -+# CONFIG_RTC_DRV_RX8581 is not set -+# CONFIG_RTC_DRV_RX8025 is not set - - # - # SPI RTC drivers - # -+# CONFIG_RTC_DRV_M41T94 is not set -+# CONFIG_RTC_DRV_DS1305 is not set -+# CONFIG_RTC_DRV_DS1390 is not set -+# CONFIG_RTC_DRV_MAX6902 is not set -+# CONFIG_RTC_DRV_R9701 is not set -+# CONFIG_RTC_DRV_RS5C348 is not set -+# CONFIG_RTC_DRV_DS3234 is not set -+# CONFIG_RTC_DRV_PCF2123 is not set - - # - # Platform RTC drivers - # - # CONFIG_RTC_DRV_CMOS is not set -+# CONFIG_RTC_DRV_DS1286 is not set - # CONFIG_RTC_DRV_DS1511 is not set - # CONFIG_RTC_DRV_DS1553 is not set - # CONFIG_RTC_DRV_DS1742 is not set - # CONFIG_RTC_DRV_STK17TA8 is not set - # CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T35 is not set - # CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_MSM6242 is not set -+# CONFIG_RTC_DRV_BQ4802 is not set -+# CONFIG_RTC_DRV_RP5C01 is not set - # CONFIG_RTC_DRV_V3020 is not set - - # - # on-CPU RTC drivers - # - # CONFIG_DMADEVICES is not set -+# CONFIG_AUXDISPLAY is not set -+CONFIG_UIO=m -+CONFIG_UIO_PDRV=m -+CONFIG_UIO_PDRV_GENIRQ=m -+# CONFIG_UIO_SMX is not set -+# CONFIG_UIO_SERCOS3 is not set - - # --# Voltage and Current regulators -+# TI VLYNQ - # --CONFIG_REGULATOR=y --# CONFIG_REGULATOR_FIXED_VOLTAGE is not set --# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set --# CONFIG_REGULATOR_BQ24022 is not set --CONFIG_REGULATOR_TWL4030=y --# CONFIG_UIO is not set -+CONFIG_STAGING=y -+# CONFIG_STAGING_EXCLUDE_BUILD is not set -+# CONFIG_USB_IP_COMMON is not set -+CONFIG_W35UND=m -+# CONFIG_PRISM2_USB is not set -+CONFIG_ECHO=m -+CONFIG_OTUS=m -+# CONFIG_COMEDI is not set -+# CONFIG_ASUS_OLED is not set -+# CONFIG_INPUT_MIMIO is not set -+# CONFIG_TRANZPORT is not set -+ -+# -+# Qualcomm MSM Camera And Video -+# -+ -+# -+# Camera Sensor Selection -+# -+# CONFIG_INPUT_GPIO is not set -+# CONFIG_DST is not set -+# CONFIG_POHMELFS is not set -+# CONFIG_PLAN9AUTH is not set -+# CONFIG_LINE6_USB is not set -+# CONFIG_USB_SERIAL_QUATECH2 is not set -+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -+# CONFIG_VT6656 is not set -+# CONFIG_FB_UDL is not set -+ -+# -+# RAR Register Driver -+# -+# CONFIG_RAR_REGISTER is not set -+# CONFIG_IIO is not set -+# CONFIG_RAMZSWAP is not set -+# CONFIG_BATMAN_ADV is not set -+# CONFIG_STRIP is not set -+ -+# -+# CBUS support -+# -+# CONFIG_CBUS is not set - - # - # File systems - # -+CONFIG_FS_JOURNAL_INFO=y - CONFIG_EXT2_FS=y - # CONFIG_EXT2_FS_XATTR is not set - # CONFIG_EXT2_FS_XIP is not set - CONFIG_EXT3_FS=y -+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set - # CONFIG_EXT3_FS_XATTR is not set --# CONFIG_EXT4DEV_FS is not set -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_XATTR=y -+# CONFIG_EXT4_FS_POSIX_ACL is not set -+# CONFIG_EXT4_FS_SECURITY is not set -+# CONFIG_EXT4_DEBUG is not set - CONFIG_JBD=y --# CONFIG_REISERFS_FS is not set --# CONFIG_JFS_FS is not set --# CONFIG_FS_POSIX_ACL is not set --# CONFIG_XFS_FS is not set --# CONFIG_OCFS2_FS is not set -+# CONFIG_JBD_DEBUG is not set -+CONFIG_JBD2=y -+# CONFIG_JBD2_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+CONFIG_REISERFS_FS=m -+# CONFIG_REISERFS_CHECK is not set -+CONFIG_REISERFS_PROC_INFO=y -+CONFIG_REISERFS_FS_XATTR=y -+# CONFIG_REISERFS_FS_POSIX_ACL is not set -+# CONFIG_REISERFS_FS_SECURITY is not set -+CONFIG_JFS_FS=m -+# CONFIG_JFS_POSIX_ACL is not set -+# CONFIG_JFS_SECURITY is not set -+# CONFIG_JFS_DEBUG is not set -+# CONFIG_JFS_STATISTICS is not set -+CONFIG_FS_POSIX_ACL=y -+CONFIG_XFS_FS=m -+# CONFIG_XFS_QUOTA is not set -+# CONFIG_XFS_POSIX_ACL is not set -+# CONFIG_XFS_RT is not set -+# CONFIG_XFS_DEBUG is not set -+CONFIG_GFS2_FS=m -+# CONFIG_GFS2_FS_LOCKING_DLM is not set -+CONFIG_OCFS2_FS=m -+CONFIG_OCFS2_FS_O2CB=m -+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -+CONFIG_OCFS2_FS_STATS=y -+CONFIG_OCFS2_DEBUG_MASKLOG=y -+# CONFIG_OCFS2_DEBUG_FS is not set -+# CONFIG_OCFS2_FS_POSIX_ACL is not set -+CONFIG_BTRFS_FS=m -+# CONFIG_BTRFS_FS_POSIX_ACL is not set -+# CONFIG_NILFS2_FS is not set -+CONFIG_FILE_LOCKING=y -+CONFIG_FSNOTIFY=y - CONFIG_DNOTIFY=y - CONFIG_INOTIFY=y - CONFIG_INOTIFY_USER=y - CONFIG_QUOTA=y - # CONFIG_QUOTA_NETLINK_INTERFACE is not set - CONFIG_PRINT_QUOTA_WARNING=y -+CONFIG_QUOTA_TREE=y - # CONFIG_QFMT_V1 is not set - CONFIG_QFMT_V2=y - CONFIG_QUOTACTL=y - # CONFIG_AUTOFS_FS is not set --# CONFIG_AUTOFS4_FS is not set --# CONFIG_FUSE_FS is not set -+CONFIG_AUTOFS4_FS=m -+CONFIG_FUSE_FS=m -+# CONFIG_CUSE is not set -+CONFIG_GENERIC_ACL=y -+ -+# -+# Caches -+# -+# CONFIG_FSCACHE is not set - - # - # CD-ROM/DVD Filesystems - # --# CONFIG_ISO9660_FS is not set --# CONFIG_UDF_FS is not set -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y - - # - # DOS/FAT/NT Filesystems -@@ -1096,68 +2633,118 @@ CONFIG_MSDOS_FS=y - CONFIG_VFAT_FS=y - CONFIG_FAT_DEFAULT_CODEPAGE=437 - CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" --# CONFIG_NTFS_FS is not set -+CONFIG_NTFS_FS=m -+# CONFIG_NTFS_DEBUG is not set -+CONFIG_NTFS_RW=y - - # - # Pseudo filesystems - # - CONFIG_PROC_FS=y - CONFIG_PROC_SYSCTL=y -+CONFIG_PROC_PAGE_MONITOR=y - CONFIG_SYSFS=y - CONFIG_TMPFS=y --# CONFIG_TMPFS_POSIX_ACL is not set -+CONFIG_TMPFS_POSIX_ACL=y - # CONFIG_HUGETLB_PAGE is not set --# CONFIG_CONFIGFS_FS is not set -- --# --# Miscellaneous filesystems --# --# CONFIG_ADFS_FS is not set --# CONFIG_AFFS_FS is not set --# CONFIG_HFS_FS is not set --# CONFIG_HFSPLUS_FS is not set --# CONFIG_BEFS_FS is not set --# CONFIG_BFS_FS is not set --# CONFIG_EFS_FS is not set -+CONFIG_CONFIGFS_FS=m -+CONFIG_MISC_FILESYSTEMS=y -+CONFIG_ADFS_FS=m -+# CONFIG_ADFS_FS_RW is not set -+CONFIG_AFFS_FS=m -+# CONFIG_ECRYPT_FS is not set -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+CONFIG_BEFS_FS=m -+# CONFIG_BEFS_DEBUG is not set -+CONFIG_BFS_FS=m -+CONFIG_EFS_FS=m - CONFIG_JFFS2_FS=y - CONFIG_JFFS2_FS_DEBUG=0 - CONFIG_JFFS2_FS_WRITEBUFFER=y - # CONFIG_JFFS2_FS_WBUF_VERIFY is not set --# CONFIG_JFFS2_SUMMARY is not set --# CONFIG_JFFS2_FS_XATTR is not set --# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+CONFIG_JFFS2_FS_POSIX_ACL=y -+CONFIG_JFFS2_FS_SECURITY=y -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y - CONFIG_JFFS2_ZLIB=y --# CONFIG_JFFS2_LZO is not set -+CONFIG_JFFS2_LZO=y - CONFIG_JFFS2_RTIME=y --# CONFIG_JFFS2_RUBIN is not set --# CONFIG_CRAMFS is not set --# CONFIG_VXFS_FS is not set --# CONFIG_MINIX_FS is not set --# CONFIG_OMFS_FS is not set --# CONFIG_HPFS_FS is not set --# CONFIG_QNX4FS_FS is not set --# CONFIG_ROMFS_FS is not set --# CONFIG_SYSV_FS is not set --# CONFIG_UFS_FS is not set -+CONFIG_JFFS2_RUBIN=y -+# CONFIG_JFFS2_CMODE_NONE is not set -+# CONFIG_JFFS2_CMODE_PRIORITY is not set -+# CONFIG_JFFS2_CMODE_SIZE is not set -+CONFIG_JFFS2_CMODE_FAVOURLZO=y -+CONFIG_UBIFS_FS=y -+CONFIG_UBIFS_FS_XATTR=y -+CONFIG_UBIFS_FS_ADVANCED_COMPR=y -+CONFIG_UBIFS_FS_LZO=y -+CONFIG_UBIFS_FS_ZLIB=y -+# CONFIG_UBIFS_FS_DEBUG is not set -+CONFIG_CRAMFS=m -+CONFIG_SQUASHFS=y -+# CONFIG_SQUASHFS_EMBEDDED is not set -+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -+CONFIG_VXFS_FS=m -+CONFIG_MINIX_FS=m -+CONFIG_OMFS_FS=m -+CONFIG_HPFS_FS=m -+CONFIG_QNX4FS_FS=m -+CONFIG_ROMFS_FS=m -+CONFIG_ROMFS_BACKED_BY_BLOCK=y -+# CONFIG_ROMFS_BACKED_BY_MTD is not set -+# CONFIG_ROMFS_BACKED_BY_BOTH is not set -+CONFIG_ROMFS_ON_BLOCK=y -+CONFIG_SYSV_FS=m -+CONFIG_UFS_FS=m -+# CONFIG_UFS_FS_WRITE is not set -+# CONFIG_UFS_DEBUG is not set - CONFIG_NETWORK_FILESYSTEMS=y - CONFIG_NFS_FS=y - CONFIG_NFS_V3=y - # CONFIG_NFS_V3_ACL is not set - CONFIG_NFS_V4=y -+# CONFIG_NFS_V4_1 is not set - CONFIG_ROOT_NFS=y --# CONFIG_NFSD is not set -+CONFIG_NFSD=m -+CONFIG_NFSD_V2_ACL=y -+CONFIG_NFSD_V3=y -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y - CONFIG_LOCKD=y - CONFIG_LOCKD_V4=y -+CONFIG_EXPORTFS=m -+CONFIG_NFS_ACL_SUPPORT=m - CONFIG_NFS_COMMON=y - CONFIG_SUNRPC=y - CONFIG_SUNRPC_GSS=y - CONFIG_RPCSEC_GSS_KRB5=y - # CONFIG_RPCSEC_GSS_SPKM3 is not set --# CONFIG_SMB_FS is not set --# CONFIG_CIFS is not set --# CONFIG_NCP_FS is not set --# CONFIG_CODA_FS is not set --# CONFIG_AFS_FS is not set -+CONFIG_SMB_FS=m -+# CONFIG_SMB_NLS_DEFAULT is not set -+CONFIG_CIFS=m -+CONFIG_CIFS_STATS=y -+CONFIG_CIFS_STATS2=y -+# CONFIG_CIFS_WEAK_PW_HASH is not set -+# CONFIG_CIFS_UPCALL is not set -+# CONFIG_CIFS_XATTR is not set -+# CONFIG_CIFS_DEBUG2 is not set -+# CONFIG_CIFS_DFS_UPCALL is not set -+CONFIG_CIFS_EXPERIMENTAL=y -+CONFIG_NCP_FS=m -+# CONFIG_NCPFS_PACKET_SIGNING is not set -+# CONFIG_NCPFS_IOCTL_LOCKING is not set -+# CONFIG_NCPFS_STRONG is not set -+# CONFIG_NCPFS_NFS_NS is not set -+# CONFIG_NCPFS_OS2_NS is not set -+# CONFIG_NCPFS_SMALLDOS is not set -+# CONFIG_NCPFS_NLS is not set -+# CONFIG_NCPFS_EXTRAS is not set -+CONFIG_CODA_FS=m -+CONFIG_AFS_FS=m -+# CONFIG_AFS_DEBUG is not set -+CONFIG_9P_FS=m - - # - # Partition Types -@@ -1167,82 +2754,90 @@ CONFIG_PARTITION_ADVANCED=y - # CONFIG_OSF_PARTITION is not set - # CONFIG_AMIGA_PARTITION is not set - # CONFIG_ATARI_PARTITION is not set --# CONFIG_MAC_PARTITION is not set -+CONFIG_MAC_PARTITION=y - CONFIG_MSDOS_PARTITION=y --# CONFIG_BSD_DISKLABEL is not set --# CONFIG_MINIX_SUBPARTITION is not set --# CONFIG_SOLARIS_X86_PARTITION is not set -+CONFIG_BSD_DISKLABEL=y -+CONFIG_MINIX_SUBPARTITION=y -+CONFIG_SOLARIS_X86_PARTITION=y - # CONFIG_UNIXWARE_DISKLABEL is not set --# CONFIG_LDM_PARTITION is not set -+CONFIG_LDM_PARTITION=y -+CONFIG_LDM_DEBUG=y - # CONFIG_SGI_PARTITION is not set - # CONFIG_ULTRIX_PARTITION is not set - # CONFIG_SUN_PARTITION is not set - # CONFIG_KARMA_PARTITION is not set --# CONFIG_EFI_PARTITION is not set -+CONFIG_EFI_PARTITION=y - # CONFIG_SYSV68_PARTITION is not set - CONFIG_NLS=y - CONFIG_NLS_DEFAULT="iso8859-1" - CONFIG_NLS_CODEPAGE_437=y --# CONFIG_NLS_CODEPAGE_737 is not set --# CONFIG_NLS_CODEPAGE_775 is not set --# CONFIG_NLS_CODEPAGE_850 is not set --# CONFIG_NLS_CODEPAGE_852 is not set --# CONFIG_NLS_CODEPAGE_855 is not set --# CONFIG_NLS_CODEPAGE_857 is not set --# CONFIG_NLS_CODEPAGE_860 is not set --# CONFIG_NLS_CODEPAGE_861 is not set --# CONFIG_NLS_CODEPAGE_862 is not set --# CONFIG_NLS_CODEPAGE_863 is not set --# CONFIG_NLS_CODEPAGE_864 is not set --# CONFIG_NLS_CODEPAGE_865 is not set --# CONFIG_NLS_CODEPAGE_866 is not set --# CONFIG_NLS_CODEPAGE_869 is not set --# CONFIG_NLS_CODEPAGE_936 is not set --# CONFIG_NLS_CODEPAGE_950 is not set --# CONFIG_NLS_CODEPAGE_932 is not set --# CONFIG_NLS_CODEPAGE_949 is not set --# CONFIG_NLS_CODEPAGE_874 is not set --# CONFIG_NLS_ISO8859_8 is not set --# CONFIG_NLS_CODEPAGE_1250 is not set --# CONFIG_NLS_CODEPAGE_1251 is not set --# CONFIG_NLS_ASCII is not set -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=m - CONFIG_NLS_ISO8859_1=y --# CONFIG_NLS_ISO8859_2 is not set --# CONFIG_NLS_ISO8859_3 is not set --# CONFIG_NLS_ISO8859_4 is not set --# CONFIG_NLS_ISO8859_5 is not set --# CONFIG_NLS_ISO8859_6 is not set --# CONFIG_NLS_ISO8859_7 is not set --# CONFIG_NLS_ISO8859_9 is not set --# CONFIG_NLS_ISO8859_13 is not set --# CONFIG_NLS_ISO8859_14 is not set --# CONFIG_NLS_ISO8859_15 is not set --# CONFIG_NLS_KOI8_R is not set --# CONFIG_NLS_KOI8_U is not set --# CONFIG_NLS_UTF8 is not set --# CONFIG_DLM is not set -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_UTF8=y -+CONFIG_DLM=m -+# CONFIG_DLM_DEBUG is not set - - # - # Kernel hacking - # --# CONFIG_PRINTK_TIME is not set -+CONFIG_PRINTK_TIME=y - CONFIG_ENABLE_WARN_DEPRECATED=y - CONFIG_ENABLE_MUST_CHECK=y - CONFIG_FRAME_WARN=1024 - CONFIG_MAGIC_SYSRQ=y -+# CONFIG_STRIP_ASM_SYMS is not set - # CONFIG_UNUSED_SYMBOLS is not set --# CONFIG_DEBUG_FS is not set -+CONFIG_DEBUG_FS=y - # CONFIG_HEADERS_CHECK is not set - CONFIG_DEBUG_KERNEL=y - # CONFIG_DEBUG_SHIRQ is not set - CONFIG_DETECT_SOFTLOCKUP=y - # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set - CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -+CONFIG_DETECT_HUNG_TASK=y -+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 - CONFIG_SCHED_DEBUG=y --# CONFIG_SCHEDSTATS is not set --# CONFIG_TIMER_STATS is not set -+CONFIG_SCHEDSTATS=y -+CONFIG_TIMER_STATS=y - # CONFIG_DEBUG_OBJECTS is not set - # CONFIG_DEBUG_SLAB is not set -+# CONFIG_DEBUG_KMEMLEAK is not set -+CONFIG_DEBUG_PREEMPT=y - # CONFIG_DEBUG_RT_MUTEXES is not set - # CONFIG_RT_MUTEX_TESTER is not set - # CONFIG_DEBUG_SPINLOCK is not set -@@ -1252,137 +2847,204 @@ CONFIG_DEBUG_MUTEXES=y - # CONFIG_LOCK_STAT is not set - # CONFIG_DEBUG_SPINLOCK_SLEEP is not set - # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+CONFIG_STACKTRACE=y - # CONFIG_DEBUG_KOBJECT is not set - # CONFIG_DEBUG_BUGVERBOSE is not set --CONFIG_DEBUG_INFO=y -+# CONFIG_DEBUG_INFO is not set - # CONFIG_DEBUG_VM is not set - # CONFIG_DEBUG_WRITECOUNT is not set - # CONFIG_DEBUG_MEMORY_INIT is not set - # CONFIG_DEBUG_LIST is not set - # CONFIG_DEBUG_SG is not set --CONFIG_FRAME_POINTER=y -+# CONFIG_DEBUG_NOTIFIERS is not set -+# CONFIG_DEBUG_CREDENTIALS is not set - # CONFIG_BOOT_PRINTK_DELAY is not set - # CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_RCU_CPU_STALL_DETECTOR is not set - # CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set - # CONFIG_FAULT_INJECTION is not set - # CONFIG_LATENCYTOP is not set --CONFIG_HAVE_FTRACE=y --CONFIG_HAVE_DYNAMIC_FTRACE=y --# CONFIG_FTRACE is not set -+# CONFIG_SYSCTL_SYSCALL_CHECK is not set -+# CONFIG_PAGE_POISONING is not set -+CONFIG_NOP_TRACER=y -+CONFIG_HAVE_FUNCTION_TRACER=y -+CONFIG_RING_BUFFER=y -+CONFIG_EVENT_TRACING=y -+CONFIG_CONTEXT_SWITCH_TRACER=y -+CONFIG_RING_BUFFER_ALLOW_SWAP=y -+CONFIG_TRACING=y -+CONFIG_TRACING_SUPPORT=y -+CONFIG_FTRACE=y -+# CONFIG_FUNCTION_TRACER is not set - # CONFIG_IRQSOFF_TRACER is not set -+# CONFIG_PREEMPT_TRACER is not set - # CONFIG_SCHED_TRACER is not set --# CONFIG_CONTEXT_SWITCH_TRACER is not set -+# CONFIG_ENABLE_DEFAULT_TRACERS is not set -+# CONFIG_BOOT_TRACER is not set -+CONFIG_BRANCH_PROFILE_NONE=y -+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -+# CONFIG_PROFILE_ALL_BRANCHES is not set -+# CONFIG_STACK_TRACER is not set -+# CONFIG_KMEMTRACE is not set -+# CONFIG_WORKQUEUE_TRACER is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_RING_BUFFER_BENCHMARK is not set -+# CONFIG_DYNAMIC_DEBUG is not set - # CONFIG_SAMPLES is not set - CONFIG_HAVE_ARCH_KGDB=y - # CONFIG_KGDB is not set -+CONFIG_ARM_UNWIND=y - # CONFIG_DEBUG_USER is not set - # CONFIG_DEBUG_ERRORS is not set - # CONFIG_DEBUG_STACK_USAGE is not set - # CONFIG_DEBUG_LL is not set -+# CONFIG_OC_ETM is not set - - # - # Security options - # --# CONFIG_KEYS is not set -+CONFIG_KEYS=y -+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set - # CONFIG_SECURITY is not set --# CONFIG_SECURITY_FILE_CAPABILITIES is not set -+# CONFIG_SECURITYFS is not set -+# CONFIG_DEFAULT_SECURITY_SELINUX is not set -+# CONFIG_DEFAULT_SECURITY_SMACK is not set -+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -+CONFIG_DEFAULT_SECURITY_DAC=y -+CONFIG_DEFAULT_SECURITY="" -+CONFIG_XOR_BLOCKS=m -+CONFIG_ASYNC_CORE=m -+CONFIG_ASYNC_MEMCPY=m -+CONFIG_ASYNC_XOR=m -+CONFIG_ASYNC_PQ=m -+CONFIG_ASYNC_RAID6_RECOV=m - CONFIG_CRYPTO=y - - # - # Crypto core or helper - # -+CONFIG_CRYPTO_FIPS=y - CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_ALGAPI2=y -+CONFIG_CRYPTO_AEAD=m -+CONFIG_CRYPTO_AEAD2=y - CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_BLKCIPHER2=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_HASH2=y -+CONFIG_CRYPTO_RNG=m -+CONFIG_CRYPTO_RNG2=y -+CONFIG_CRYPTO_PCOMP=y - CONFIG_CRYPTO_MANAGER=y --# CONFIG_CRYPTO_GF128MUL is not set --# CONFIG_CRYPTO_NULL is not set --# CONFIG_CRYPTO_CRYPTD is not set --# CONFIG_CRYPTO_AUTHENC is not set --# CONFIG_CRYPTO_TEST is not set -+CONFIG_CRYPTO_MANAGER2=y -+CONFIG_CRYPTO_GF128MUL=m -+CONFIG_CRYPTO_NULL=m -+CONFIG_CRYPTO_WORKQUEUE=y -+CONFIG_CRYPTO_CRYPTD=m -+CONFIG_CRYPTO_AUTHENC=m -+CONFIG_CRYPTO_TEST=m - - # - # Authenticated Encryption with Associated Data - # --# CONFIG_CRYPTO_CCM is not set --# CONFIG_CRYPTO_GCM is not set --# CONFIG_CRYPTO_SEQIV is not set -+CONFIG_CRYPTO_CCM=m -+CONFIG_CRYPTO_GCM=m -+CONFIG_CRYPTO_SEQIV=m - - # - # Block modes - # - CONFIG_CRYPTO_CBC=y --# CONFIG_CRYPTO_CTR is not set --# CONFIG_CRYPTO_CTS is not set --CONFIG_CRYPTO_ECB=m --# CONFIG_CRYPTO_LRW is not set -+CONFIG_CRYPTO_CTR=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_ECB=y -+CONFIG_CRYPTO_LRW=m - CONFIG_CRYPTO_PCBC=m --# CONFIG_CRYPTO_XTS is not set -+CONFIG_CRYPTO_XTS=m - - # - # Hash modes - # --# CONFIG_CRYPTO_HMAC is not set --# CONFIG_CRYPTO_XCBC is not set -+CONFIG_CRYPTO_HMAC=m -+CONFIG_CRYPTO_XCBC=m -+# CONFIG_CRYPTO_VMAC is not set - - # - # Digest - # --# CONFIG_CRYPTO_CRC32C is not set --# CONFIG_CRYPTO_MD4 is not set -+CONFIG_CRYPTO_CRC32C=y -+CONFIG_CRYPTO_GHASH=m -+CONFIG_CRYPTO_MD4=m - CONFIG_CRYPTO_MD5=y --# CONFIG_CRYPTO_MICHAEL_MIC is not set --# CONFIG_CRYPTO_RMD128 is not set --# CONFIG_CRYPTO_RMD160 is not set --# CONFIG_CRYPTO_RMD256 is not set --# CONFIG_CRYPTO_RMD320 is not set --# CONFIG_CRYPTO_SHA1 is not set --# CONFIG_CRYPTO_SHA256 is not set --# CONFIG_CRYPTO_SHA512 is not set --# CONFIG_CRYPTO_TGR192 is not set --# CONFIG_CRYPTO_WP512 is not set -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA1=m -+CONFIG_CRYPTO_SHA256=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m - - # - # Ciphers - # --# CONFIG_CRYPTO_AES is not set --# CONFIG_CRYPTO_ANUBIS is not set --# CONFIG_CRYPTO_ARC4 is not set --# CONFIG_CRYPTO_BLOWFISH is not set --# CONFIG_CRYPTO_CAMELLIA is not set --# CONFIG_CRYPTO_CAST5 is not set --# CONFIG_CRYPTO_CAST6 is not set -+CONFIG_CRYPTO_AES=y -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_ARC4=y -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m - CONFIG_CRYPTO_DES=y --# CONFIG_CRYPTO_FCRYPT is not set --# CONFIG_CRYPTO_KHAZAD is not set --# CONFIG_CRYPTO_SALSA20 is not set --# CONFIG_CRYPTO_SEED is not set --# CONFIG_CRYPTO_SERPENT is not set --# CONFIG_CRYPTO_TEA is not set --# CONFIG_CRYPTO_TWOFISH is not set -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_SALSA20=m -+CONFIG_CRYPTO_SEED=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_TWOFISH_COMMON=m - - # - # Compression - # --# CONFIG_CRYPTO_DEFLATE is not set --# CONFIG_CRYPTO_LZO is not set -+CONFIG_CRYPTO_DEFLATE=y -+# CONFIG_CRYPTO_ZLIB is not set -+CONFIG_CRYPTO_LZO=y -+ -+# -+# Random Number Generation -+# -+CONFIG_CRYPTO_ANSI_CPRNG=m - CONFIG_CRYPTO_HW=y -+CONFIG_BINARY_PRINTF=y - - # - # Library routines - # - CONFIG_BITREVERSE=y --# CONFIG_GENERIC_FIND_FIRST_BIT is not set --# CONFIG_GENERIC_FIND_NEXT_BIT is not set -+CONFIG_GENERIC_FIND_LAST_BIT=y - CONFIG_CRC_CCITT=y --# CONFIG_CRC16 is not set --# CONFIG_CRC_T10DIF is not set --# CONFIG_CRC_ITU_T is not set -+CONFIG_CRC16=y -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC_ITU_T=y - CONFIG_CRC32=y --# CONFIG_CRC7 is not set -+CONFIG_CRC7=y - CONFIG_LIBCRC32C=y - CONFIG_ZLIB_INFLATE=y - CONFIG_ZLIB_DEFLATE=y --CONFIG_PLIST=y -+CONFIG_LZO_COMPRESS=y -+CONFIG_LZO_DECOMPRESS=y -+CONFIG_DECOMPRESS_GZIP=y -+CONFIG_TEXTSEARCH=y -+CONFIG_TEXTSEARCH_KMP=m -+CONFIG_TEXTSEARCH_BM=m -+CONFIG_TEXTSEARCH_FSM=m - CONFIG_HAS_IOMEM=y - CONFIG_HAS_IOPORT=y - CONFIG_HAS_DMA=y -+CONFIG_NLATTR=y --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0011-ASoC-enable-audio-capture-by-default-for-twl4030.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0011-ASoC-enable-audio-capture-by-default-for-twl4030.patch deleted file mode 100644 index e02a9ab1..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0011-ASoC-enable-audio-capture-by-default-for-twl4030.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 3cd85787199204da2faec4b4150302bf2228de48 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 17 Dec 2009 12:45:20 -0800 -Subject: [PATCH 11/45] ASoC: enable audio capture by default for twl4030 - ---- - sound/soc/codecs/twl4030.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c -index 74f0d65..53da465 100644 ---- a/sound/soc/codecs/twl4030.c -+++ b/sound/soc/codecs/twl4030.c -@@ -46,8 +46,8 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { - 0xc3, /* REG_OPTION (0x2) */ - 0x00, /* REG_UNKNOWN (0x3) */ - 0x00, /* REG_MICBIAS_CTL (0x4) */ -- 0x20, /* REG_ANAMICL (0x5) */ -- 0x00, /* REG_ANAMICR (0x6) */ -+ 0x34, /* REG_ANAMICL (0x5) */ -+ 0x14, /* REG_ANAMICR (0x6) */ - 0x00, /* REG_AVADC_CTL (0x7) */ - 0x00, /* REG_ADCMICSEL (0x8) */ - 0x00, /* REG_DIGMIXING (0x9) */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0012-MTD-NAND-omap2-proper-fix-for-subpage-read-ECC-error.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0012-MTD-NAND-omap2-proper-fix-for-subpage-read-ECC-error.patch deleted file mode 100644 index a8f3d8b4..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0012-MTD-NAND-omap2-proper-fix-for-subpage-read-ECC-error.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 7d8868d73fdd95eb928f54f881978590643e50cc Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 31 Dec 2009 07:05:02 -0800 -Subject: [PATCH 12/45] MTD: NAND: omap2: proper fix for subpage read ECC errors - ---- - drivers/mtd/nand/omap2.c | 11 +++++++---- - 1 files changed, 7 insertions(+), 4 deletions(-) - -diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c -index 08c193c..9b185b0 100644 ---- a/drivers/mtd/nand/omap2.c -+++ b/drivers/mtd/nand/omap2.c -@@ -295,11 +295,14 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) - u32 *p = (u32 *)buf; - - /* take care of subpage reads */ -- for (; len % 4 != 0; ) { -- *buf++ = __raw_readb(info->nand.IO_ADDR_R); -- len--; -+ if (len % 4) { -+ if (info->nand.options & NAND_BUSWIDTH_16) -+ omap_read_buf16(mtd, buf, len % 4); -+ else -+ omap_read_buf8(mtd, buf, len % 4); -+ p = (u32 *) (buf + len % 4); -+ len -= len % 4; - } -- p = (u32 *) buf; - - /* configure and start prefetch transfer */ - ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0013-OMAP3630-DSS2-Enable-Pre-Multiplied-Alpha-Support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0013-OMAP3630-DSS2-Enable-Pre-Multiplied-Alpha-Support.patch deleted file mode 100644 index 7f4954a9..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0013-OMAP3630-DSS2-Enable-Pre-Multiplied-Alpha-Support.patch +++ /dev/null @@ -1,44 +0,0 @@ -From af96930d2412b4af27407a48e262ce1bb2e32427 Mon Sep 17 00:00:00 2001 -From: Sudeep Basavaraj -Date: Tue, 5 Jan 2010 18:58:18 +0530 -Subject: [PATCH 13/45] OMAP3630:DSS2:Enable Pre-Multiplied Alpha Support - -Enables dss to process color formats with pre-mulitplied alpha values. -With this we can have alpha values defined for each pixel -and hence can have different blending values for each pixel. - -Signed-off-by: Sudeep Basavaraj -Signed-off-by: Kishore Y ---- - drivers/video/omap2/dss/dispc.c | 8 ++++++++ - 1 files changed, 8 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c -index f7acf87..c6d5fc5 100644 ---- a/drivers/video/omap2/dss/dispc.c -+++ b/drivers/video/omap2/dss/dispc.c -@@ -913,6 +913,11 @@ static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable) - dispc_write_reg(dispc_reg_att[plane], val); - } - -+static void _dispc_set_alpha_blend_attrs(enum omap_plane plane, bool enable) -+{ -+ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28); -+} -+ - void dispc_enable_replication(enum omap_plane plane, bool enable) - { - int bit; -@@ -1689,6 +1694,9 @@ static int _dispc_setup_plane(enum omap_plane plane, - - _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode); - -+ if (cpu_is_omap3630() && (plane != OMAP_DSS_VIDEO1)) -+ _dispc_set_alpha_blend_attrs(plane, 1); -+ - if (plane != OMAP_DSS_VIDEO1) - _dispc_setup_global_alpha(plane, global_alpha); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0014-DSS2-add-bootarg-for-selecting-svideo-or-composite-f.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0014-DSS2-add-bootarg-for-selecting-svideo-or-composite-f.patch deleted file mode 100644 index d9554e14..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0014-DSS2-add-bootarg-for-selecting-svideo-or-composite-f.patch +++ /dev/null @@ -1,75 +0,0 @@ -From ba26db491acb2d0ee6ef6e51756e843dfd56a125 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Tue, 19 Jan 2010 21:19:15 -0800 -Subject: [PATCH 14/45] DSS2: add bootarg for selecting svideo or composite for tv output - -also add pal-16 and ntsc-16 omapfb.mode settings for 16bpp ---- - drivers/video/omap2/dss/venc.c | 22 ++++++++++++++++++++++ - drivers/video/omap2/omapfb/omapfb-main.c | 10 +++++++++- - 2 files changed, 31 insertions(+), 1 deletions(-) - -diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c -index 8be116f..fbfc24b 100644 ---- a/drivers/video/omap2/dss/venc.c -+++ b/drivers/video/omap2/dss/venc.c -@@ -87,6 +87,11 @@ - #define VENC_OUTPUT_TEST 0xC8 - #define VENC_DAC_B__DAC_C 0xC8 - -+static char *tv_connection; -+ -+module_param_named(tvcable, tv_connection, charp, 0); -+MODULE_PARM_DESC(tvcable, "TV connection type (svideo, composite)"); -+ - struct venc_config { - u32 f_control; - u32 vidout_ctrl; -@@ -432,6 +437,23 @@ static int venc_panel_probe(struct omap_dss_device *dssdev) - { - dssdev->panel.timings = omap_dss_pal_timings; - -+ /* Allow the TV output to be overriden */ -+ if (tv_connection) { -+ if (strcmp(tv_connection, "svideo") == 0) { -+ printk(KERN_INFO -+ "omapdss: tv output is svideo.\n"); -+ dssdev->phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; -+ } else if (strcmp(tv_connection, "composite") == 0) { -+ printk(KERN_INFO -+ "omapdss: tv output is composite.\n"); -+ dssdev->phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; -+ } else { -+ printk(KERN_INFO -+ "omapdss: unsupported output type'%s'.\n", -+ tv_connection); -+ } -+ } -+ - return 0; - } - -diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c -index 7f47a34..0fe87e0 100644 ---- a/drivers/video/omap2/omapfb/omapfb-main.c -+++ b/drivers/video/omap2/omapfb/omapfb-main.c -@@ -1988,7 +1988,15 @@ static int omapfb_mode_to_timings(const char *mode_str, - int r; - - #ifdef CONFIG_OMAP2_DSS_VENC -- if (strcmp(mode_str, "pal") == 0) { -+ if (strcmp(mode_str, "pal-16") == 0) { -+ *timings = omap_dss_pal_timings; -+ *bpp = 16; -+ return 0; -+ } else if (strcmp(mode_str, "ntsc-16") == 0) { -+ *timings = omap_dss_ntsc_timings; -+ *bpp = 16; -+ return 0; -+ } else if (strcmp(mode_str, "pal") == 0) { - *timings = omap_dss_pal_timings; - *bpp = 0; - return 0; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0015-ISP-add-some-more-from-Leopard-imaging-patch.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0015-ISP-add-some-more-from-Leopard-imaging-patch.patch deleted file mode 100644 index f8030bbd..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0015-ISP-add-some-more-from-Leopard-imaging-patch.patch +++ /dev/null @@ -1,133 +0,0 @@ -From 739ec82561686ad0c5cc8befef3bcd74339d205e Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Thu, 11 Feb 2010 21:34:00 +0100 -Subject: [PATCH 15/45] ISP: add some more from Leopard imaging patch - ---- - drivers/media/video/isp/isppreview.c | 16 ++++++++- - include/media/v4l2-int-device.h | 58 ++++++++++++++++++++++++++++++++++ - 2 files changed, 72 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/video/isp/isppreview.c b/drivers/media/video/isp/isppreview.c -index 5494efc..85ee25d 100644 ---- a/drivers/media/video/isp/isppreview.c -+++ b/drivers/media/video/isp/isppreview.c -@@ -79,13 +79,26 @@ static struct ispprev_rgbtorgb flr_rgb2rgb = { - {0x0000, 0x0000, 0x0000} - }; - -+static struct ispprev_rgbtorgb unity_rgb2rgb = { -+ { /* RGB-RGB Matrix */ -+ {0x0100, 0x0000, 0x0000}, -+ {0x0000, 0x0100, 0x0000}, -+ {0x0000, 0x0000, 0x0100} -+ }, /* RGB Offset */ -+ {0x0000, 0x0000, 0x0000} -+}; -+ - /* Default values in Office Flourescent Light for RGB to YUV Conversion*/ - static struct ispprev_csc flr_prev_csc[] = { - { - { /* CSC Coef Matrix */ -- {66, 129, 25}, -+/* {66, 129, 25}, - {-38, -75, 112}, - {112, -94 , -18} -+*/ -+ {0x04C, 0x098, 0x01C}, -+ {0x3D4, 0x3AC, 0x080}, -+ {0x080, 0x39E, 0x3EC} - }, /* CSC Offset */ - {0x0, 0x0, 0x0} - }, -@@ -107,7 +120,6 @@ static struct ispprev_csc flr_prev_csc[] = { - } - }; - -- - /* Default values in Office Flourescent Light for CFA Gradient*/ - #define FLR_CFA_GRADTHRS_HORZ 0x28 - #define FLR_CFA_GRADTHRS_VERT 0x28 -diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h -index ed32d3f..ce415ec 100644 ---- a/include/media/v4l2-int-device.h -+++ b/include/media/v4l2-int-device.h -@@ -113,6 +113,8 @@ enum v4l2_if_type { - * on certain image sensors. - */ - V4L2_IF_TYPE_BT656, -+ V4L2_IF_TYPE_YCbCr, -+ V4L2_IF_TYPE_RAW, - }; - - enum v4l2_if_type_bt656_mode { -@@ -159,10 +161,66 @@ struct v4l2_if_type_bt656 { - u32 clock_curr; - }; - -+struct v4l2_if_type_ycbcr { -+ /* -+ * 0: Frame begins when vsync is high. -+ * 1: Frame begins when vsync changes from low to high. -+ */ -+ unsigned frame_start_on_rising_vs:1; -+ /* Use Bt synchronisation codes for sync correction. */ -+ unsigned bt_sync_correct:1; -+ /* Swap every two adjacent image data elements. */ -+ unsigned swap:1; -+ /* Inverted latch clock polarity from slave. */ -+ unsigned latch_clk_inv:1; -+ /* Hs polarity. 0 is active high, 1 active low. */ -+ unsigned nobt_hs_inv:1; -+ /* Vs polarity. 0 is active high, 1 active low. */ -+ unsigned nobt_vs_inv:1; -+ /* Minimum accepted bus clock for slave (in Hz). */ -+ u32 clock_min; -+ /* Maximum accepted bus clock for slave. */ -+ u32 clock_max; -+ /* -+ * Current wish of the slave. May only change in response to -+ * ioctls that affect image capture. -+ */ -+ u32 clock_curr; -+}; -+ -+struct v4l2_if_type_raw { -+ /* -+ * 0: Frame begins when vsync is high. -+ * 1: Frame begins when vsync changes from low to high. -+ */ -+ unsigned frame_start_on_rising_vs:1; -+ /* Use Bt synchronisation codes for sync correction. */ -+ unsigned bt_sync_correct:1; -+ /* Swap every two adjacent image data elements. */ -+ unsigned swap:1; -+ /* Inverted latch clock polarity from slave. */ -+ unsigned latch_clk_inv:1; -+ /* Hs polarity. 0 is active high, 1 active low. */ -+ unsigned nobt_hs_inv:1; -+ /* Vs polarity. 0 is active high, 1 active low. */ -+ unsigned nobt_vs_inv:1; -+ /* Minimum accepted bus clock for slave (in Hz). */ -+ u32 clock_min; -+ /* Maximum accepted bus clock for slave. */ -+ u32 clock_max; -+ /* -+ * Current wish of the slave. May only change in response to -+ * ioctls that affect image capture. -+ */ -+ u32 clock_curr; -+}; -+ - struct v4l2_ifparm { - enum v4l2_if_type if_type; - union { - struct v4l2_if_type_bt656 bt656; -+ struct v4l2_if_type_ycbcr ycbcr; -+ struct v4l2_if_type_raw raw; - } u; - }; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0016-ARM-OMAP-Overo-Add-support-for-second-ethernet-port.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0016-ARM-OMAP-Overo-Add-support-for-second-ethernet-port.patch deleted file mode 100644 index 4b9bd215..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0016-ARM-OMAP-Overo-Add-support-for-second-ethernet-port.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 1fc84dc95abaf51294efa10fe111d65bc0b08483 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Tue, 15 Dec 2009 14:59:42 -0800 -Subject: [PATCH 16/45] ARM: OMAP: Overo: Add support for second ethernet port - -Signed-off-by: Steve Sakoman ---- - arch/arm/mach-omap2/board-overo.c | 56 +++++++++++++++++++++++++++++++++++-- - 1 files changed, 53 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c -index e0aebc3..6204b8c 100644 ---- a/arch/arm/mach-omap2/board-overo.c -+++ b/arch/arm/mach-omap2/board-overo.c -@@ -63,6 +63,8 @@ - - #define OVERO_SMSC911X_CS 5 - #define OVERO_SMSC911X_GPIO 176 -+#define OVERO_SMSC911X2_CS 4 -+#define OVERO_SMSC911X2_GPIO 65 - - #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ - defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -@@ -137,6 +139,16 @@ static struct resource overo_smsc911x_resources[] = { - }, - }; - -+static struct resource overo_smsc911x2_resources[] = { -+ { -+ .name = "smsc911x2-memory", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, -+ }, -+}; -+ - static struct smsc911x_platform_config overo_smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, -@@ -146,7 +158,7 @@ static struct smsc911x_platform_config overo_smsc911x_config = { - - static struct platform_device overo_smsc911x_device = { - .name = "smsc911x", -- .id = -1, -+ .id = 0, - .num_resources = ARRAY_SIZE(overo_smsc911x_resources), - .resource = overo_smsc911x_resources, - .dev = { -@@ -154,9 +166,26 @@ static struct platform_device overo_smsc911x_device = { - }, - }; - -+static struct platform_device overo_smsc911x2_device = { -+ .name = "smsc911x", -+ .id = 1, -+ .num_resources = ARRAY_SIZE(overo_smsc911x2_resources), -+ .resource = overo_smsc911x2_resources, -+ .dev = { -+ .platform_data = &overo_smsc911x_config, -+ }, -+}; -+ -+static struct platform_device *smsc911x_devices[] = { -+ &overo_smsc911x_device, -+ &overo_smsc911x2_device, -+}; -+ - static inline void __init overo_init_smsc911x(void) - { -- unsigned long cs_mem_base; -+ unsigned long cs_mem_base, cs_mem_base2; -+ -+ /* set up first smsc911x chip */ - - if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) { - printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n"); -@@ -177,7 +206,28 @@ static inline void __init overo_init_smsc911x(void) - overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO); - overo_smsc911x_resources[1].end = 0; - -- platform_device_register(&overo_smsc911x_device); -+ /* set up second smsc911x chip */ -+ -+ if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) { -+ printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n"); -+ return; -+ } -+ -+ overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0; -+ overo_smsc911x2_resources[0].end = cs_mem_base2 + 0xff; -+ -+ if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) && -+ (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) { -+ gpio_export(OVERO_SMSC911X2_GPIO, 0); -+ } else { -+ printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n"); -+ return; -+ } -+ -+ overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO); -+ overo_smsc911x2_resources[1].end = 0; -+ -+ platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices)); - } - - #else --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0017-drivers-net-smsc911x-return-ENODEV-if-device-is-not-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0017-drivers-net-smsc911x-return-ENODEV-if-device-is-not-.patch deleted file mode 100644 index 40fbbff1..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0017-drivers-net-smsc911x-return-ENODEV-if-device-is-not-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From f6084470f7861f9cc05faec2a8f8825ec55f7022 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Tue, 15 Dec 2009 15:17:44 -0800 -Subject: [PATCH 17/45] drivers: net: smsc911x: return ENODEV if device is not found - -Signed-off-by: Steve Sakoman ---- - drivers/net/smsc911x.c | 4 +++- - 1 files changed, 3 insertions(+), 1 deletions(-) - -diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c -index 494cd91..2472cb0 100644 ---- a/drivers/net/smsc911x.c -+++ b/drivers/net/smsc911x.c -@@ -2021,8 +2021,10 @@ static int __devinit smsc911x_drv_probe(struct platform_device *pdev) - } - - retval = smsc911x_init(dev); -- if (retval < 0) -+ if (retval < 0) { -+ retval = -ENODEV; - goto out_unmap_io_3; -+ } - - /* configure irq polarity and type before connecting isr */ - if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0018-drivers-input-touchscreen-ads7846-return-ENODEV-if-d.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0018-drivers-input-touchscreen-ads7846-return-ENODEV-if-d.patch deleted file mode 100644 index 1ee7f324..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0018-drivers-input-touchscreen-ads7846-return-ENODEV-if-d.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 56f59d080226a7a6a033e7f20e8a41d1c327e5a1 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Tue, 15 Dec 2009 15:24:10 -0800 -Subject: [PATCH 18/45] drivers: input: touchscreen: ads7846: return ENODEV if device is not found - -Signed-off-by: Steve Sakoman ---- - drivers/input/touchscreen/ads7846.c | 13 ++++++++++--- - 1 files changed, 10 insertions(+), 3 deletions(-) - -diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c -index e53ac1f..45287ab 100644 ---- a/drivers/input/touchscreen/ads7846.c -+++ b/drivers/input/touchscreen/ads7846.c -@@ -1165,9 +1165,16 @@ static int __devinit ads7846_probe(struct spi_device *spi) - /* take a first sample, leaving nPENIRQ active and vREF off; avoid - * the touchscreen, in case it's not connected. - */ -- (void) ads7846_read12_ser(&spi->dev, -+ err = ads7846_read12_ser(&spi->dev, - READ_12BIT_SER(vaux) | ADS_PD10_ALL_ON); - -+ /* if sample is all 0's or all 1's then there is no device on spi */ -+ if ( (err == 0x000) || (err == 0xfff)) { -+ dev_info(&spi->dev, "no device detected, test read result was 0x%08X\n", err); -+ err = -ENODEV; -+ goto err_free_irq; -+ } -+ - err = sysfs_create_group(&spi->dev.kobj, &ads784x_attr_group); - if (err) - goto err_remove_hwmon; -@@ -1188,7 +1195,7 @@ static int __devinit ads7846_probe(struct spi_device *spi) - err_free_irq: - free_irq(spi->irq, ts); - err_free_gpio: -- if (ts->gpio_pendown != -1) -+ if (!ts->get_pendown_state && ts->gpio_pendown != -1) - gpio_free(ts->gpio_pendown); - err_cleanup_filter: - if (ts->filter_cleanup) -@@ -1216,7 +1223,7 @@ static int __devexit ads7846_remove(struct spi_device *spi) - /* suspend left the IRQ disabled */ - enable_irq(ts->spi->irq); - -- if (ts->gpio_pendown != -1) -+ if (!ts->get_pendown_state && ts->gpio_pendown != -1) - gpio_free(ts->gpio_pendown); - - if (ts->filter_cleanup) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0019-drivers-mfd-add-twl4030-madc-driver.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0019-drivers-mfd-add-twl4030-madc-driver.patch deleted file mode 100644 index 55c5e191..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0019-drivers-mfd-add-twl4030-madc-driver.patch +++ /dev/null @@ -1,601 +0,0 @@ -From b9270dc07b1b66cce33580bca6276c20f1bf68d2 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Wed, 19 Jan 2011 16:06:42 +0100 -Subject: [PATCH 19/45] drivers: mfd: add twl4030 madc driver - ---- - drivers/mfd/Kconfig | 21 ++ - drivers/mfd/Makefile | 1 + - drivers/mfd/twl4030-madc.c | 536 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 558 insertions(+), 0 deletions(-) - create mode 100644 drivers/mfd/twl4030-madc.c - -diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index 306b346..6221146 100644 ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -148,6 +148,27 @@ config TWL4030_CODEC - default n - - -+config TWL4030_MADC -+ tristate "TWL4030 MADC Driver" -+ depends on TWL4030_CORE -+ help -+ The TWL4030 Monitoring ADC driver enables the host -+ processor to monitor analog signals using analog-to-digital -+ conversions on the input source. TWL4030 MADC provides the -+ following features: -+ - Single 10-bit ADC with successive approximation register (SAR) conversion; -+ - Analog multiplexer for 16 inputs; -+ - Seven (of the 16) inputs are freely available; -+ - Battery voltage monitoring; -+ - Concurrent conversion request management; -+ - Interrupt signal to Primary Interrupt Handler; -+ - Averaging feature; -+ - Selective enable/disable of the averaging feature. -+ -+ Say 'y' here to statically link this module into the kernel or 'm' -+ to build it as a dinamically loadable module. The module will be -+ called twl4030-madc.ko -+ - config MFD_TMIO - bool - default n -diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile -index 85dc3a7..44350e7 100644 ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -29,6 +29,7 @@ obj-$(CONFIG_MENELAUS) += menelaus.o - obj-$(CONFIG_TWL4030_CORE) += twl-core.o twl4030-irq.o twl6030-irq.o - obj-$(CONFIG_TWL4030_POWER) += twl4030-power.o - obj-$(CONFIG_TWL4030_CODEC) += twl4030-codec.o -+obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o - - obj-$(CONFIG_TPS65910_CORE) += tps65910-core.o - -diff --git a/drivers/mfd/twl4030-madc.c b/drivers/mfd/twl4030-madc.c -new file mode 100644 -index 0000000..7d83ab8 ---- /dev/null -+++ b/drivers/mfd/twl4030-madc.c -@@ -0,0 +1,536 @@ -+/* -+ * TWL4030 MADC module driver -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Mikko Ylinen -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA -+ * 02110-1301 USA -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define TWL4030_MADC_PFX "twl4030-madc: " -+ -+struct twl4030_madc_data { -+ struct device *dev; -+ struct mutex lock; -+ struct work_struct ws; -+ struct twl4030_madc_request requests[TWL4030_MADC_NUM_METHODS]; -+ int imr; -+ int isr; -+}; -+ -+static struct twl4030_madc_data *the_madc; -+ -+static -+const struct twl4030_madc_conversion_method twl4030_conversion_methods[] = { -+ [TWL4030_MADC_RT] = { -+ .sel = TWL4030_MADC_RTSELECT_LSB, -+ .avg = TWL4030_MADC_RTAVERAGE_LSB, -+ .rbase = TWL4030_MADC_RTCH0_LSB, -+ }, -+ [TWL4030_MADC_SW1] = { -+ .sel = TWL4030_MADC_SW1SELECT_LSB, -+ .avg = TWL4030_MADC_SW1AVERAGE_LSB, -+ .rbase = TWL4030_MADC_GPCH0_LSB, -+ .ctrl = TWL4030_MADC_CTRL_SW1, -+ }, -+ [TWL4030_MADC_SW2] = { -+ .sel = TWL4030_MADC_SW2SELECT_LSB, -+ .avg = TWL4030_MADC_SW2AVERAGE_LSB, -+ .rbase = TWL4030_MADC_GPCH0_LSB, -+ .ctrl = TWL4030_MADC_CTRL_SW2, -+ }, -+}; -+ -+static int twl4030_madc_read(struct twl4030_madc_data *madc, u8 reg) -+{ -+ int ret; -+ u8 val; -+ -+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_MADC, &val, reg); -+ if (ret) { -+ dev_dbg(madc->dev, "unable to read register 0x%X\n", reg); -+ return ret; -+ } -+ -+ return val; -+} -+ -+static void twl4030_madc_write(struct twl4030_madc_data *madc, u8 reg, u8 val) -+{ -+ int ret; -+ -+ ret = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, val, reg); -+ if (ret) -+ dev_err(madc->dev, "unable to write register 0x%X\n", reg); -+} -+ -+static int twl4030_madc_channel_raw_read(struct twl4030_madc_data *madc, u8 reg) -+{ -+ u8 msb, lsb; -+ -+ /* For each ADC channel, we have MSB and LSB register pair. MSB address -+ * is always LSB address+1. reg parameter is the addr of LSB register */ -+ msb = twl4030_madc_read(madc, reg + 1); -+ lsb = twl4030_madc_read(madc, reg); -+ -+ return (int)(((msb << 8) | lsb) >> 6); -+} -+ -+static int twl4030_madc_read_channels(struct twl4030_madc_data *madc, -+ u8 reg_base, u16 channels, int *buf) -+{ -+ int count = 0; -+ u8 reg, i; -+ -+ if (unlikely(!buf)) -+ return 0; -+ -+ for (i = 0; i < TWL4030_MADC_MAX_CHANNELS; i++) { -+ if (channels & (1<imr); -+ val &= ~(1 << id); -+ twl4030_madc_write(madc, madc->imr, val); -+} -+ -+static void twl4030_madc_disable_irq(struct twl4030_madc_data *madc, int id) -+{ -+ u8 val; -+ -+ val = twl4030_madc_read(madc, madc->imr); -+ val |= (1 << id); -+ twl4030_madc_write(madc, madc->imr, val); -+} -+ -+static irqreturn_t twl4030_madc_irq_handler(int irq, void *_madc) -+{ -+ struct twl4030_madc_data *madc = _madc; -+ u8 isr_val, imr_val; -+ int i; -+ -+#ifdef CONFIG_LOCKDEP -+ /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which -+ * we don't want and can't tolerate. Although it might be -+ * friendlier not to borrow this thread context... -+ */ -+ local_irq_enable(); -+#endif -+ -+ /* Use COR to ack interrupts since we have no shared IRQs in ISRx */ -+ isr_val = twl4030_madc_read(madc, madc->isr); -+ imr_val = twl4030_madc_read(madc, madc->imr); -+ -+ isr_val &= ~imr_val; -+ -+ for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { -+ -+ if (!(isr_val & (1<requests[i].result_pending = 1; -+ } -+ -+ schedule_work(&madc->ws); -+ -+ return IRQ_HANDLED; -+} -+ -+static void twl4030_madc_work(struct work_struct *ws) -+{ -+ const struct twl4030_madc_conversion_method *method; -+ struct twl4030_madc_data *madc; -+ struct twl4030_madc_request *r; -+ int len, i; -+ -+ madc = container_of(ws, struct twl4030_madc_data, ws); -+ mutex_lock(&madc->lock); -+ -+ for (i = 0; i < TWL4030_MADC_NUM_METHODS; i++) { -+ -+ r = &madc->requests[i]; -+ -+ /* No pending results for this method, move to next one */ -+ if (!r->result_pending) -+ continue; -+ -+ method = &twl4030_conversion_methods[r->method]; -+ -+ /* Read results */ -+ len = twl4030_madc_read_channels(madc, method->rbase, -+ r->channels, r->rbuf); -+ -+ /* Return results to caller */ -+ if (r->func_cb != NULL) { -+ r->func_cb(len, r->channels, r->rbuf); -+ r->func_cb = NULL; -+ } -+ -+ /* Free request */ -+ r->result_pending = 0; -+ r->active = 0; -+ } -+ -+ mutex_unlock(&madc->lock); -+} -+ -+static int twl4030_madc_set_irq(struct twl4030_madc_data *madc, -+ struct twl4030_madc_request *req) -+{ -+ struct twl4030_madc_request *p; -+ -+ p = &madc->requests[req->method]; -+ -+ memcpy(p, req, sizeof *req); -+ -+ twl4030_madc_enable_irq(madc, req->method); -+ -+ return 0; -+} -+ -+static inline void twl4030_madc_start_conversion(struct twl4030_madc_data *madc, -+ int conv_method) -+{ -+ const struct twl4030_madc_conversion_method *method; -+ -+ method = &twl4030_conversion_methods[conv_method]; -+ -+ switch (conv_method) { -+ case TWL4030_MADC_SW1: -+ case TWL4030_MADC_SW2: -+ twl4030_madc_write(madc, method->ctrl, TWL4030_MADC_SW_START); -+ break; -+ case TWL4030_MADC_RT: -+ default: -+ break; -+ } -+} -+ -+static int twl4030_madc_wait_conversion_ready( -+ struct twl4030_madc_data *madc, -+ unsigned int timeout_ms, u8 status_reg) -+{ -+ unsigned long timeout; -+ -+ timeout = jiffies + msecs_to_jiffies(timeout_ms); -+ do { -+ u8 reg; -+ -+ reg = twl4030_madc_read(madc, status_reg); -+ if (!(reg & TWL4030_MADC_BUSY) && (reg & TWL4030_MADC_EOC_SW)) -+ return 0; -+ } while (!time_after(jiffies, timeout)); -+ -+ return -EAGAIN; -+} -+ -+int twl4030_madc_conversion(struct twl4030_madc_request *req) -+{ -+ const struct twl4030_madc_conversion_method *method; -+ u8 ch_msb, ch_lsb; -+ int ret; -+ -+ if (unlikely(!req)) -+ return -EINVAL; -+ -+ mutex_lock(&the_madc->lock); -+ -+ /* Do we have a conversion request ongoing */ -+ if (the_madc->requests[req->method].active) { -+ ret = -EBUSY; -+ goto out; -+ } -+ -+ ch_msb = (req->channels >> 8) & 0xff; -+ ch_lsb = req->channels & 0xff; -+ -+ method = &twl4030_conversion_methods[req->method]; -+ -+ /* Select channels to be converted */ -+ twl4030_madc_write(the_madc, method->sel + 1, ch_msb); -+ twl4030_madc_write(the_madc, method->sel, ch_lsb); -+ -+ /* Select averaging for all channels if do_avg is set */ -+ if (req->do_avg) { -+ twl4030_madc_write(the_madc, method->avg + 1, ch_msb); -+ twl4030_madc_write(the_madc, method->avg, ch_lsb); -+ } -+ -+ if ((req->type == TWL4030_MADC_IRQ_ONESHOT) && (req->func_cb != NULL)) { -+ twl4030_madc_set_irq(the_madc, req); -+ twl4030_madc_start_conversion(the_madc, req->method); -+ the_madc->requests[req->method].active = 1; -+ ret = 0; -+ goto out; -+ } -+ -+ /* With RT method we should not be here anymore */ -+ if (req->method == TWL4030_MADC_RT) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ twl4030_madc_start_conversion(the_madc, req->method); -+ the_madc->requests[req->method].active = 1; -+ -+ /* Wait until conversion is ready (ctrl register returns EOC) */ -+ ret = twl4030_madc_wait_conversion_ready(the_madc, 5, method->ctrl); -+ if (ret) { -+ dev_dbg(the_madc->dev, "conversion timeout!\n"); -+ the_madc->requests[req->method].active = 0; -+ goto out; -+ } -+ -+ ret = twl4030_madc_read_channels(the_madc, method->rbase, req->channels, -+ req->rbuf); -+ -+ the_madc->requests[req->method].active = 0; -+ -+out: -+ mutex_unlock(&the_madc->lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL(twl4030_madc_conversion); -+ -+static int twl4030_madc_set_current_generator(struct twl4030_madc_data *madc, -+ int chan, int on) -+{ -+ int ret; -+ u8 regval; -+ -+ /* Current generator is only available for ADCIN0 and ADCIN1. NB: -+ * ADCIN1 current generator only works when AC or VBUS is present */ -+ if (chan > 1) -+ return EINVAL; -+ -+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ ®val, TWL4030_BCI_BCICTL1); -+ if (on) -+ regval |= (chan) ? TWL4030_BCI_ITHEN : TWL4030_BCI_TYPEN; -+ else -+ regval &= (chan) ? ~TWL4030_BCI_ITHEN : ~TWL4030_BCI_TYPEN; -+ ret = twl4030_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, -+ regval, TWL4030_BCI_BCICTL1); -+ -+ return ret; -+} -+ -+static int twl4030_madc_set_power(struct twl4030_madc_data *madc, int on) -+{ -+ u8 regval; -+ -+ regval = twl4030_madc_read(madc, TWL4030_MADC_CTRL1); -+ if (on) -+ regval |= TWL4030_MADC_MADCON; -+ else -+ regval &= ~TWL4030_MADC_MADCON; -+ twl4030_madc_write(madc, TWL4030_MADC_CTRL1, regval); -+ -+ return 0; -+} -+ -+static long twl4030_madc_ioctl(struct file *filp, unsigned int cmd, -+ unsigned long arg) -+{ -+ struct twl4030_madc_user_parms par; -+ int val, ret; -+ -+ ret = copy_from_user(&par, (void __user *) arg, sizeof(par)); -+ if (ret) { -+ dev_dbg(the_madc->dev, "copy_from_user: %d\n", ret); -+ return -EACCES; -+ } -+ -+ switch (cmd) { -+ case TWL4030_MADC_IOCX_ADC_RAW_READ: { -+ struct twl4030_madc_request req; -+ if (par.channel >= TWL4030_MADC_MAX_CHANNELS) -+ return -EINVAL; -+ -+ req.channels = (1 << par.channel); -+ req.do_avg = par.average; -+ req.method = TWL4030_MADC_SW1; -+ req.func_cb = NULL; -+ -+ val = twl4030_madc_conversion(&req); -+ if (val <= 0) { -+ par.status = -1; -+ } else { -+ par.status = 0; -+ par.result = (u16)req.rbuf[par.channel]; -+ } -+ break; -+ } -+ default: -+ return -EINVAL; -+ } -+ -+ ret = copy_to_user((void __user *) arg, &par, sizeof(par)); -+ if (ret) { -+ dev_dbg(the_madc->dev, "copy_to_user: %d\n", ret); -+ return -EACCES; -+ } -+ -+ return 0; -+} -+ -+static struct file_operations twl4030_madc_fileops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = twl4030_madc_ioctl -+}; -+ -+static struct miscdevice twl4030_madc_device = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "twl4030-madc", -+ .fops = &twl4030_madc_fileops -+}; -+ -+static int __init twl4030_madc_probe(struct platform_device *pdev) -+{ -+ struct twl4030_madc_data *madc; -+ struct twl4030_madc_platform_data *pdata = pdev->dev.platform_data; -+ int ret; -+ u8 regval; -+ -+ madc = kzalloc(sizeof *madc, GFP_KERNEL); -+ if (!madc) -+ return -ENOMEM; -+ -+ if (!pdata) { -+ dev_dbg(&pdev->dev, "platform_data not available\n"); -+ ret = -EINVAL; -+ goto err_pdata; -+ } -+ -+ madc->imr = (pdata->irq_line == 1) ? TWL4030_MADC_IMR1 : TWL4030_MADC_IMR2; -+ madc->isr = (pdata->irq_line == 1) ? TWL4030_MADC_ISR1 : TWL4030_MADC_ISR2; -+ -+ ret = misc_register(&twl4030_madc_device); -+ if (ret) { -+ dev_dbg(&pdev->dev, "could not register misc_device\n"); -+ goto err_misc; -+ } -+ twl4030_madc_set_power(madc, 1); -+ twl4030_madc_set_current_generator(madc, 0, 1); -+ -+ /* Enable ADCIN3 through 6 */ -+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_USB, -+ ®val, TWL4030_USB_CARKIT_ANA_CTRL); -+ -+ regval |= TWL4030_USB_SEL_MADC_MCPC; -+ -+ ret = twl4030_i2c_write_u8(TWL4030_MODULE_USB, -+ regval, TWL4030_USB_CARKIT_ANA_CTRL); -+ -+ -+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ ®val, TWL4030_BCI_BCICTL1); -+ -+ regval |= TWL4030_BCI_MESBAT; -+ -+ ret = twl4030_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, -+ regval, TWL4030_BCI_BCICTL1); -+ -+ ret = request_irq(platform_get_irq(pdev, 0), twl4030_madc_irq_handler, -+ 0, "twl4030_madc", madc); -+ if (ret) { -+ dev_dbg(&pdev->dev, "could not request irq\n"); -+ goto err_irq; -+ } -+ -+ platform_set_drvdata(pdev, madc); -+ mutex_init(&madc->lock); -+ INIT_WORK(&madc->ws, twl4030_madc_work); -+ -+ the_madc = madc; -+ -+ return 0; -+ -+err_irq: -+ misc_deregister(&twl4030_madc_device); -+ -+err_misc: -+err_pdata: -+ kfree(madc); -+ -+ return ret; -+} -+ -+static int __exit twl4030_madc_remove(struct platform_device *pdev) -+{ -+ struct twl4030_madc_data *madc = platform_get_drvdata(pdev); -+ -+ twl4030_madc_set_power(madc, 0); -+ twl4030_madc_set_current_generator(madc, 0, 0); -+ free_irq(platform_get_irq(pdev, 0), madc); -+ cancel_work_sync(&madc->ws); -+ misc_deregister(&twl4030_madc_device); -+ -+ return 0; -+} -+ -+static struct platform_driver twl4030_madc_driver = { -+ .probe = twl4030_madc_probe, -+ .remove = __exit_p(twl4030_madc_remove), -+ .driver = { -+ .name = "twl4030_madc", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init twl4030_madc_init(void) -+{ -+ return platform_driver_register(&twl4030_madc_driver); -+} -+module_init(twl4030_madc_init); -+ -+static void __exit twl4030_madc_exit(void) -+{ -+ platform_driver_unregister(&twl4030_madc_driver); -+} -+module_exit(twl4030_madc_exit); -+ -+MODULE_ALIAS("platform:twl4030-madc"); -+MODULE_AUTHOR("Nokia Corporation"); -+MODULE_DESCRIPTION("twl4030 ADC driver"); -+MODULE_LICENSE("GPL"); -+ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0020-ARM-OMAP-Add-missing-twl4030-madc-header-file.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0020-ARM-OMAP-Add-missing-twl4030-madc-header-file.patch deleted file mode 100644 index 0e1bdaf7..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0020-ARM-OMAP-Add-missing-twl4030-madc-header-file.patch +++ /dev/null @@ -1,149 +0,0 @@ -From b13ea241d699a10e3f5347a90bc3d31329f3601d Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 17 Dec 2009 15:54:58 -0800 -Subject: [PATCH 20/45] ARM: OMAP: Add missing twl4030 madc header file - ---- - include/linux/i2c/twl4030-madc.h | 130 ++++++++++++++++++++++++++++++++++++++ - 1 files changed, 130 insertions(+), 0 deletions(-) - create mode 100644 include/linux/i2c/twl4030-madc.h - -diff --git a/include/linux/i2c/twl4030-madc.h b/include/linux/i2c/twl4030-madc.h -new file mode 100644 -index 0000000..341a665 ---- /dev/null -+++ b/include/linux/i2c/twl4030-madc.h -@@ -0,0 +1,130 @@ -+/* -+ * include/linux/i2c/twl4030-madc.h -+ * -+ * TWL4030 MADC module driver header -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Mikko Ylinen -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA -+ * 02110-1301 USA -+ * -+ */ -+ -+#ifndef _TWL4030_MADC_H -+#define _TWL4030_MADC_H -+ -+struct twl4030_madc_conversion_method { -+ u8 sel; -+ u8 avg; -+ u8 rbase; -+ u8 ctrl; -+}; -+ -+#define TWL4030_MADC_MAX_CHANNELS 16 -+ -+struct twl4030_madc_request { -+ u16 channels; -+ u16 do_avg; -+ u16 method; -+ u16 type; -+ int active; -+ int result_pending; -+ int rbuf[TWL4030_MADC_MAX_CHANNELS]; -+ void (*func_cb)(int len, int channels, int *buf); -+}; -+ -+enum conversion_methods { -+ TWL4030_MADC_RT, -+ TWL4030_MADC_SW1, -+ TWL4030_MADC_SW2, -+ TWL4030_MADC_NUM_METHODS -+}; -+ -+enum sample_type { -+ TWL4030_MADC_WAIT, -+ TWL4030_MADC_IRQ_ONESHOT, -+ TWL4030_MADC_IRQ_REARM -+}; -+ -+#define TWL4030_MADC_CTRL1 0x00 -+#define TWL4030_MADC_CTRL2 0x01 -+ -+#define TWL4030_MADC_RTSELECT_LSB 0x02 -+#define TWL4030_MADC_SW1SELECT_LSB 0x06 -+#define TWL4030_MADC_SW2SELECT_LSB 0x0A -+ -+#define TWL4030_MADC_RTAVERAGE_LSB 0x04 -+#define TWL4030_MADC_SW1AVERAGE_LSB 0x08 -+#define TWL4030_MADC_SW2AVERAGE_LSB 0x0C -+ -+#define TWL4030_MADC_CTRL_SW1 0x12 -+#define TWL4030_MADC_CTRL_SW2 0x13 -+ -+#define TWL4030_MADC_RTCH0_LSB 0x17 -+#define TWL4030_MADC_GPCH0_LSB 0x37 -+ -+#define TWL4030_MADC_MADCON (1<<0) /* MADC power on */ -+#define TWL4030_MADC_BUSY (1<<0) /* MADC busy */ -+#define TWL4030_MADC_EOC_SW (1<<1) /* MADC conversion completion */ -+#define TWL4030_MADC_SW_START (1<<5) /* MADC SWx start conversion */ -+ -+#define TWL4030_MADC_ADCIN0 (1<<0) -+#define TWL4030_MADC_ADCIN1 (1<<1) -+#define TWL4030_MADC_ADCIN2 (1<<2) -+#define TWL4030_MADC_ADCIN3 (1<<3) -+#define TWL4030_MADC_ADCIN4 (1<<4) -+#define TWL4030_MADC_ADCIN5 (1<<5) -+#define TWL4030_MADC_ADCIN6 (1<<6) -+#define TWL4030_MADC_ADCIN7 (1<<7) -+#define TWL4030_MADC_ADCIN8 (1<<8) -+#define TWL4030_MADC_ADCIN9 (1<<9) -+#define TWL4030_MADC_ADCIN10 (1<<10) -+#define TWL4030_MADC_ADCIN11 (1<<11) -+#define TWL4030_MADC_ADCIN12 (1<<12) -+#define TWL4030_MADC_ADCIN13 (1<<13) -+#define TWL4030_MADC_ADCIN14 (1<<14) -+#define TWL4030_MADC_ADCIN15 (1<<15) -+ -+/* Fixed channels */ -+#define TWL4030_MADC_BTEMP TWL4030_MADC_ADCIN1 -+#define TWL4030_MADC_VBUS TWL4030_MADC_ADCIN8 -+#define TWL4030_MADC_VBKB TWL4030_MADC_ADCIN9 -+#define TWL4030_MADC_ICHG TWL4030_MADC_ADCIN10 -+#define TWL4030_MADC_VCHG TWL4030_MADC_ADCIN11 -+#define TWL4030_MADC_VBAT TWL4030_MADC_ADCIN12 -+ -+/* BCI related - XXX To be moved elsewhere */ -+#define TWL4030_BCI_BCICTL1 0x23 -+#define TWL4030_BCI_MESBAT (1<<1) -+#define TWL4030_BCI_TYPEN (1<<4) -+#define TWL4030_BCI_ITHEN (1<<3) -+ -+/* USB related - XXX To be moved elsewhere */ -+#define TWL4030_USB_CARKIT_ANA_CTRL 0xBB -+#define TWL4030_USB_SEL_MADC_MCPC (1<<3) -+ -+#define TWL4030_MADC_IOC_MAGIC '`' -+#define TWL4030_MADC_IOCX_ADC_RAW_READ _IO(TWL4030_MADC_IOC_MAGIC, 0) -+ -+struct twl4030_madc_user_parms { -+ int channel; -+ int average; -+ int status; -+ u16 result; -+}; -+ -+int twl4030_madc_conversion(struct twl4030_madc_request *conv); -+ -+#endif --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0021-ARM-OMAP-Add-twl4030-madc-support-to-Overo.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0021-ARM-OMAP-Add-twl4030-madc-support-to-Overo.patch deleted file mode 100644 index e1515e16..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0021-ARM-OMAP-Add-twl4030-madc-support-to-Overo.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 6b34060f2a665d94e953a7a9b3d66a79e1736cd6 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 17 Dec 2009 14:27:15 -0800 -Subject: [PATCH 21/45] ARM: OMAP: Add twl4030 madc support to Overo - ---- - arch/arm/mach-omap2/board-overo.c | 5 +++++ - 1 files changed, 5 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c -index 6204b8c..9c76588 100644 ---- a/arch/arm/mach-omap2/board-overo.c -+++ b/arch/arm/mach-omap2/board-overo.c -@@ -390,10 +390,15 @@ static struct twl4030_codec_data overo_codec_data = { - - /* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ - -+static struct twl4030_madc_platform_data overo_madc_data = { -+ .irq_line = 1, -+}; -+ - static struct twl4030_platform_data overo_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - .gpio = &overo_gpio_data, -+ .madc = &overo_madc_data, - .usb = &overo_usb_data, - .codec = &overo_codec_data, - .vmmc1 = &overo_vmmc1, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0022-ARM-OMAP-Add-twl4030-madc-support-to-Beagle.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0022-ARM-OMAP-Add-twl4030-madc-support-to-Beagle.patch deleted file mode 100644 index 48e777ba..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0022-ARM-OMAP-Add-twl4030-madc-support-to-Beagle.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 04101f4527b88fbd540fc89f2a8af06d26030fd1 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 17 Dec 2009 14:32:36 -0800 -Subject: [PATCH 22/45] ARM: OMAP: Add twl4030 madc support to Beagle - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 5 +++++ - 1 files changed, 5 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index b3c8cb7..dd830b1 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -473,6 +473,10 @@ static struct twl4030_codec_data beagle_codec_data = { - .audio = &beagle_audio_data, - }; - -+static struct twl4030_madc_platform_data beagle_madc_data = { -+ .irq_line = 1, -+}; -+ - static struct twl4030_platform_data beagle_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, -@@ -481,6 +485,7 @@ static struct twl4030_platform_data beagle_twldata = { - .usb = &beagle_usb_data, - .gpio = &beagle_gpio_data, - .codec = &beagle_codec_data, -+ .madc = &beagle_madc_data, - .vmmc1 = &beagle_vmmc1, - .vsim = &beagle_vsim, - .vdac = &beagle_vdac, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0023-netdev-rt73usb-add-vendor-device-ID-for-Ceiva-Wirele.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0023-netdev-rt73usb-add-vendor-device-ID-for-Ceiva-Wirele.patch deleted file mode 100644 index e5ba1d1d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0023-netdev-rt73usb-add-vendor-device-ID-for-Ceiva-Wirele.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 6c58da582504f23256ec656a03706a1df438f291 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Tue, 19 Jan 2010 20:00:46 -0800 -Subject: [PATCH 23/45] netdev: rt73usb - add vendor/device ID for Ceiva Wireless PartNo 81726-00702 - ---- - drivers/net/wireless/rt2x00/rt73usb.c | 2 ++ - 1 files changed, 2 insertions(+), 0 deletions(-) - -diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c -index ced3b6a..719ac0a 100644 ---- a/drivers/net/wireless/rt2x00/rt73usb.c -+++ b/drivers/net/wireless/rt2x00/rt73usb.c -@@ -2357,6 +2357,8 @@ static struct usb_device_id rt73usb_device_table[] = { - { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, - { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) }, - { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) }, -+ /* Ceiva Wireless PartNo 81726-00702 */ -+ { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) }, - /* CNet */ - { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, - { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0024-mmc-don-t-display-single-block-read-console-messages.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0024-mmc-don-t-display-single-block-read-console-messages.patch deleted file mode 100644 index 4b4e54fa..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0024-mmc-don-t-display-single-block-read-console-messages.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b17b11c0f8d56f868da267641486b62e1a44790b Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Mon, 4 Jan 2010 19:20:25 -0800 -Subject: [PATCH 24/45] mmc: don't display single block read console messages - -mmc: don't display single block read console messages ---- - drivers/mmc/card/block.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c -index 85f0e8c..05492e9 100644 ---- a/drivers/mmc/card/block.c -+++ b/drivers/mmc/card/block.c -@@ -338,8 +338,8 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) - if (brq.cmd.error || brq.data.error || brq.stop.error) { - if (brq.data.blocks > 1 && rq_data_dir(req) == READ) { - /* Redo read one sector at a time */ -- printk(KERN_WARNING "%s: retrying using single " -- "block read\n", req->rq_disk->disk_name); -+ /* printk(KERN_WARNING "%s: retrying using single " -+ "block read\n", req->rq_disk->disk_name); */ - disable_multi = 1; - continue; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0025-ARM-OMAP2-mmc-twl4030-move-clock-input-selection-pri.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0025-ARM-OMAP2-mmc-twl4030-move-clock-input-selection-pri.patch deleted file mode 100644 index 78666fb4..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0025-ARM-OMAP2-mmc-twl4030-move-clock-input-selection-pri.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 297f577635fe0182e596112c33b213fd22b4efa7 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Sun, 24 Jan 2010 09:33:56 -0800 -Subject: [PATCH 25/45] ARM: OMAP2: mmc-twl4030: move clock input selection prior to vcc test - -otherwise it is not executed on systems that use non-twl regulators ---- - arch/arm/mach-omap2/mmc-twl4030.c | 16 ++++++++-------- - 1 files changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c -index 0c3c72d..dbdafb9 100644 ---- a/arch/arm/mach-omap2/mmc-twl4030.c -+++ b/arch/arm/mach-omap2/mmc-twl4030.c -@@ -302,6 +302,14 @@ static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int v - if (c == NULL) - return -ENODEV; - -+ if (mmc->slots[0].internal_clock) { -+ u32 reg; -+ -+ reg = omap_ctrl_readl(control_devconf1_offset); -+ reg |= OMAP2_MMCSDIO2ADPCLKISEL; -+ omap_ctrl_writel(reg, control_devconf1_offset); -+ } -+ - /* If we don't see a Vcc regulator, assume it's a fixed - * voltage always-on regulator. - */ -@@ -322,14 +330,6 @@ static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int v - * chips/cards need an interface voltage rail too. - */ - if (power_on) { -- /* only MMC2 supports a CLKIN */ -- if (mmc->slots[0].internal_clock) { -- u32 reg; -- -- reg = omap_ctrl_readl(control_devconf1_offset); -- reg |= OMAP2_MMCSDIO2ADPCLKISEL; -- omap_ctrl_writel(reg, control_devconf1_offset); -- } - ret = mmc_regulator_set_ocr(c->vcc, vdd); - /* enable interface voltage rail, if needed */ - if (ret == 0 && c->vcc_aux) { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0026-board-overo-add-PM-code-and-sync-with-http-www.sakom.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0026-board-overo-add-PM-code-and-sync-with-http-www.sakom.patch deleted file mode 100644 index 53bfbe0d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0026-board-overo-add-PM-code-and-sync-with-http-www.sakom.patch +++ /dev/null @@ -1,373 +0,0 @@ -From 1f91f7f6dea0268e23d5e3e78b6c8dc5ed245313 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sun, 14 Feb 2010 12:52:02 +0100 -Subject: [PATCH 26/45] board-overo: add PM code and sync with http://www.sakoman.com/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=shortlog;h=refs/heads/omap3-2.6.32 - ---- - arch/arm/mach-omap2/board-overo.c | 274 ++++++++++++++++++++++++++++++++----- - 1 files changed, 242 insertions(+), 32 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c -index 9c76588..2595f81 100644 ---- a/arch/arm/mach-omap2/board-overo.c -+++ b/arch/arm/mach-omap2/board-overo.c -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -40,16 +41,24 @@ - - #include - #include -+#include - #include - #include - #include - #include -+#include - #include -- --#include "mux.h" -+#include -+#include -+ - #include "sdram-micron-mt46h32m32lf-6.h" - #include "mmc-twl4030.h" - -+#include "mux.h" -+ -+#include "pm.h" -+#include "omap3-opp.h" -+ - #define OVERO_GPIO_BT_XGATE 15 - #define OVERO_GPIO_W2W_NRESET 16 - #define OVERO_GPIO_PENDOWN 114 -@@ -95,18 +104,6 @@ static struct ads7846_platform_data ads7846_config = { - .keep_vref_on = 1, - }; - --static struct spi_board_info overo_spi_board_info[] __initdata = { -- { -- .modalias = "ads7846", -- .bus_num = 1, -- .chip_select = 0, -- .max_speed_hz = 1500000, -- .controller_data = &ads7846_mcspi_config, -- .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), -- .platform_data = &ads7846_config, -- } --}; -- - static void __init overo_ads7846_init(void) - { - if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) && -@@ -116,9 +113,6 @@ static void __init overo_ads7846_init(void) - printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n"); - return; - } -- -- spi_register_board_info(overo_spi_board_info, -- ARRAY_SIZE(overo_spi_board_info)); - } - - #else -@@ -234,6 +228,169 @@ static inline void __init overo_init_smsc911x(void) - static inline void __init overo_init_smsc911x(void) { return; } - #endif - -+/* DSS */ -+static int lcd_enabled; -+static int dvi_enabled; -+ -+#define OVERO_GPIO_LCD_EN 144 -+#define OVERO_GPIO_LCD_BL 145 -+ -+static void __init overo_display_init(void) -+{ -+ if ((gpio_request(OVERO_GPIO_LCD_EN, "OVERO_GPIO_LCD_EN") == 0) && -+ (gpio_direction_output(OVERO_GPIO_LCD_EN, 1) == 0)) -+ gpio_export(OVERO_GPIO_LCD_EN, 0); -+ else -+ printk(KERN_ERR "could not obtain gpio for " -+ "OVERO_GPIO_LCD_EN\n"); -+ -+ if ((gpio_request(OVERO_GPIO_LCD_BL, "OVERO_GPIO_LCD_BL") == 0) && -+ (gpio_direction_output(OVERO_GPIO_LCD_BL, 1) == 0)) -+ gpio_export(OVERO_GPIO_LCD_BL, 0); -+ else -+ printk(KERN_ERR "could not obtain gpio for " -+ "OVERO_GPIO_LCD_BL\n"); -+} -+ -+static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (lcd_enabled) { -+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); -+ return -EINVAL; -+ } -+ dvi_enabled = 1; -+ -+ return 0; -+} -+ -+static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ dvi_enabled = 0; -+} -+ -+static struct omap_dss_device overo_dvi_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "dvi", -+ .driver_name = "generic_panel", -+ .phy.dpi.data_lines = 24, -+ .platform_enable = overo_panel_enable_dvi, -+ .platform_disable = overo_panel_disable_dvi, -+}; -+ -+static int overo_panel_enable_tv(struct omap_dss_device *dssdev) -+{ -+#define ENABLE_VDAC_DEDICATED 0x03 -+#define ENABLE_VDAC_DEV_GRP 0x20 -+ -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ ENABLE_VDAC_DEDICATED, -+ TWL4030_VDAC_DEDICATED); -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP); -+ -+ return 0; -+} -+ -+static void overo_panel_disable_tv(struct omap_dss_device *dssdev) -+{ -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00, -+ TWL4030_VDAC_DEDICATED); -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00, -+ TWL4030_VDAC_DEV_GRP); -+} -+ -+static struct omap_dss_device overo_tv_device = { -+ .name = "tv", -+ .driver_name = "venc", -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -+ .platform_enable = overo_panel_enable_tv, -+ .platform_disable = overo_panel_disable_tv, -+}; -+ -+static int overo_panel_enable_lcd(struct omap_dss_device *dssdev) -+{ -+ if (dvi_enabled) { -+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); -+ return -EINVAL; -+ } -+ -+ gpio_set_value(OVERO_GPIO_LCD_EN, 1); -+ gpio_set_value(OVERO_GPIO_LCD_BL, 1); -+ lcd_enabled = 1; -+ return 0; -+} -+ -+static void overo_panel_disable_lcd(struct omap_dss_device *dssdev) -+{ -+ gpio_set_value(OVERO_GPIO_LCD_EN, 0); -+ gpio_set_value(OVERO_GPIO_LCD_BL, 0); -+ lcd_enabled = 0; -+} -+ -+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ -+ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -+static struct omap_dss_device overo_lcd35_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "lcd35", -+ .driver_name = "lgphilips_lb035q02_panel", -+ .phy.dpi.data_lines = 24, -+ .panel.recommended_bpp = 16, -+ .platform_enable = overo_panel_enable_lcd, -+ .platform_disable = overo_panel_disable_lcd, -+}; -+#endif -+ -+#if defined(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) || \ -+ defined(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C_MODULE) -+static struct omap_dss_device overo_lcd43_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "lcd43", -+ .driver_name = "samsung_lte_panel", -+ .phy.dpi.data_lines = 24, -+ .panel.recommended_bpp = 16, -+ .platform_enable = overo_panel_enable_lcd, -+ .platform_disable = overo_panel_disable_lcd, -+}; -+#endif -+ -+static struct omap_dss_device *overo_dss_devices[] = { -+ &overo_dvi_device, -+ &overo_tv_device, -+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ -+ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -+ &overo_lcd35_device, -+#endif -+#if defined(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) || \ -+ defined(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C_MODULE) -+ &overo_lcd43_device, -+#endif -+}; -+ -+static struct omap_dss_board_info overo_dss_data = { -+ .num_devices = ARRAY_SIZE(overo_dss_devices), -+ .devices = overo_dss_devices, -+ .default_device = &overo_dvi_device, -+}; -+ -+static struct platform_device overo_dss_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = &overo_dss_data, -+ }, -+}; -+ -+static struct regulator_consumer_supply overo_vdda_dac_supply = { -+ .supply = "vdda_dac", -+ .dev = &overo_dss_device.dev, -+}; -+ -+static struct regulator_consumer_supply overo_vdds_dsi_supply = { -+ .supply = "vdds_dsi", -+ .dev = &overo_dss_device.dev, -+}; -+ - static struct mtd_partition overo_nand_partitions[] = { - { - .name = "xloader", -@@ -379,6 +536,37 @@ static struct regulator_init_data overo_vmmc1 = { - .consumer_supplies = &overo_vmmc1_supply, - }; - -+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ -+static struct regulator_init_data overo_vdac = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &overo_vdda_dac_supply, -+}; -+ -+/* VPLL2 for digital video outputs */ -+static struct regulator_init_data overo_vpll2 = { -+ .constraints = { -+ .name = "VDVI", -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &overo_vdds_dsi_supply, -+}; -+ -+/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ -+ - static struct twl4030_codec_audio_data overo_audio_data = { - .audio_mclk = 26000000, - }; -@@ -402,6 +590,8 @@ static struct twl4030_platform_data overo_twldata = { - .usb = &overo_usb_data, - .codec = &overo_codec_data, - .vmmc1 = &overo_vmmc1, -+ .vdac = &overo_vdac, -+ .vpll2 = &overo_vpll2, - }; - - static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { -@@ -422,31 +612,50 @@ static int __init overo_i2c_init(void) - return 0; - } - --static struct platform_device overo_lcd_device = { -- .name = "overo_lcd", -- .id = -1, --}; -- --static struct omap_lcd_config overo_lcd_config __initdata = { -- .ctrl_name = "internal", -+static struct spi_board_info overo_spi_board_info[] __initdata = { -+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ -+ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -+ { -+ .modalias = "ads7846", -+ .bus_num = 1, -+ .chip_select = 0, -+ .max_speed_hz = 1500000, -+ .controller_data = &ads7846_mcspi_config, -+ .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), -+ .platform_data = &ads7846_config, -+ }, -+#endif -+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ -+ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -+ { -+ .modalias = "lgphilips_lb035q02_panel-spi", -+ .bus_num = 1, -+ .chip_select = 1, -+ .max_speed_hz = 500000, -+ .mode = SPI_MODE_3, -+ }, -+#endif - }; - --static struct omap_board_config_kernel overo_config[] __initdata = { -- { OMAP_TAG_LCD, &overo_lcd_config }, --}; -+static int __init overo_spi_init(void) -+{ -+ overo_ads7846_init(); -+ spi_register_board_info(overo_spi_board_info, -+ ARRAY_SIZE(overo_spi_board_info)); -+ return 0; -+} - - static void __init overo_init_irq(void) - { -- omap_board_config = overo_config; -- omap_board_config_size = ARRAY_SIZE(overo_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- mt46h32m32lf6_sdrc_params, NULL, NULL, NULL); -+ NULL, omap35x_mpu_rate_table, -+ omap35x_dsp_rate_table, omap35x_l3_rate_table); - omap_init_irq(); - omap_gpio_init(); - } - - static struct platform_device *overo_devices[] __initdata = { -- &overo_lcd_device, -+ &overo_dss_device, - }; - - static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -@@ -477,8 +686,9 @@ static void __init overo_init(void) - overo_flash_init(); - usb_musb_init(); - usb_ehci_init(&ehci_pdata); -- overo_ads7846_init(); -+ overo_spi_init(); - overo_init_smsc911x(); -+ overo_display_init(); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0027-twl4030-madc-adjust-for-twl4030-twl-api-changes.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0027-twl4030-madc-adjust-for-twl4030-twl-api-changes.patch deleted file mode 100644 index 1f8fb069..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0027-twl4030-madc-adjust-for-twl4030-twl-api-changes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From e102ffa8fcc1586ed7d4c1390b7b2c7d7d359c40 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Mon, 15 Feb 2010 14:20:51 +0100 -Subject: [PATCH 27/45] twl4030-madc: adjust for twl4030 -> twl api changes - ---- - drivers/mfd/twl4030-madc.c | 18 +++++++++--------- - 1 files changed, 9 insertions(+), 9 deletions(-) - -diff --git a/drivers/mfd/twl4030-madc.c b/drivers/mfd/twl4030-madc.c -index 7d83ab8..de6bdcd 100644 ---- a/drivers/mfd/twl4030-madc.c -+++ b/drivers/mfd/twl4030-madc.c -@@ -29,7 +29,7 @@ - #include - #include - #include --#include -+#include - #include - - #include -@@ -73,7 +73,7 @@ static int twl4030_madc_read(struct twl4030_madc_data *madc, u8 reg) - int ret; - u8 val; - -- ret = twl4030_i2c_read_u8(TWL4030_MODULE_MADC, &val, reg); -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &val, reg); - if (ret) { - dev_dbg(madc->dev, "unable to read register 0x%X\n", reg); - return ret; -@@ -86,7 +86,7 @@ static void twl4030_madc_write(struct twl4030_madc_data *madc, u8 reg, u8 val) - { - int ret; - -- ret = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, val, reg); -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, val, reg); - if (ret) - dev_err(madc->dev, "unable to write register 0x%X\n", reg); - } -@@ -342,13 +342,13 @@ static int twl4030_madc_set_current_generator(struct twl4030_madc_data *madc, - if (chan > 1) - return EINVAL; - -- ret = twl4030_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, - ®val, TWL4030_BCI_BCICTL1); - if (on) - regval |= (chan) ? TWL4030_BCI_ITHEN : TWL4030_BCI_TYPEN; - else - regval &= (chan) ? ~TWL4030_BCI_ITHEN : ~TWL4030_BCI_TYPEN; -- ret = twl4030_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, - regval, TWL4030_BCI_BCICTL1); - - return ret; -@@ -453,21 +453,21 @@ static int __init twl4030_madc_probe(struct platform_device *pdev) - twl4030_madc_set_current_generator(madc, 0, 1); - - /* Enable ADCIN3 through 6 */ -- ret = twl4030_i2c_read_u8(TWL4030_MODULE_USB, -+ ret = twl_i2c_read_u8(TWL4030_MODULE_USB, - ®val, TWL4030_USB_CARKIT_ANA_CTRL); - - regval |= TWL4030_USB_SEL_MADC_MCPC; - -- ret = twl4030_i2c_write_u8(TWL4030_MODULE_USB, -+ ret = twl_i2c_write_u8(TWL4030_MODULE_USB, - regval, TWL4030_USB_CARKIT_ANA_CTRL); - - -- ret = twl4030_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, - ®val, TWL4030_BCI_BCICTL1); - - regval |= TWL4030_BCI_MESBAT; - -- ret = twl4030_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, - regval, TWL4030_BCI_BCICTL1); - - ret = request_irq(platform_get_irq(pdev, 0), twl4030_madc_irq_handler, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0028-OMAP-DSS2-Re-add-support-for-Samsung-lte430wq-f0c-pa.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0028-OMAP-DSS2-Re-add-support-for-Samsung-lte430wq-f0c-pa.patch deleted file mode 100644 index 58f4701a..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0028-OMAP-DSS2-Re-add-support-for-Samsung-lte430wq-f0c-pa.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 5e227dbb55a40c616cca8a2345a159310c729897 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Mon, 15 Feb 2010 14:38:00 +0100 -Subject: [PATCH 28/45] OMAP: DSS2: (Re)add support for Samsung lte430wq-f0c panel - ---- - drivers/video/omap2/displays/Kconfig | 6 + - drivers/video/omap2/displays/Makefile | 1 + - .../omap2/displays/panel-samsung-lte430wq-f0c.c | 113 ++++++++++++++++++++ - 3 files changed, 120 insertions(+), 0 deletions(-) - create mode 100644 drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c - -diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig -index 4ce47dd..4229a28 100644 ---- a/drivers/video/omap2/displays/Kconfig -+++ b/drivers/video/omap2/displays/Kconfig -@@ -7,6 +7,12 @@ config PANEL_GENERIC - Generic panel driver. - Used for DVI output for Beagle and OMAP3 SDP. - -+config PANEL_SAMSUNG_LTE430WQ_F0C -+ tristate "Samsung LTE430WQ-F0C LCD Panel" -+ depends on OMAP2_DSS -+ help -+ LCD Panel used on Overo Palo43 -+ - config PANEL_SHARP_LS037V7DW01 - tristate "Sharp LS037V7DW01 LCD Panel" - depends on OMAP2_DSS -diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile -index 8f3d0ad..9317445 100644 ---- a/drivers/video/omap2/displays/Makefile -+++ b/drivers/video/omap2/displays/Makefile -@@ -1,4 +1,5 @@ - obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o -+obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o - obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o - obj-$(CONFIG_PANEL_SHARP_LQ043T1DG01) += panel-sharp-lq043t1dg01.o - -diff --git a/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c -new file mode 100644 -index 0000000..3f0477e ---- /dev/null -+++ b/drivers/video/omap2/displays/panel-samsung-lte430wq-f0c.c -@@ -0,0 +1,113 @@ -+/* -+ * LCD panel driver for Samsung LTE430WQ-F0C -+ * -+ * Author: Steve Sakoman -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include -+#include -+ -+#include -+ -+static struct omap_video_timings samsung_lte_timings = { -+ .x_res = 480, -+ .y_res = 272, -+ -+ .pixel_clock = 9200, -+ -+ .hsw = 41, -+ .hfp = 8, -+ .hbp = 45-41, -+ -+ .vsw = 10, -+ .vfp = 4, -+ .vbp = 12-10, -+}; -+ -+static int samsung_lte_panel_probe(struct omap_dss_device *dssdev) -+{ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS; -+ dssdev->panel.timings = samsung_lte_timings; -+ -+ return 0; -+} -+ -+static void samsung_lte_panel_remove(struct omap_dss_device *dssdev) -+{ -+} -+ -+static int samsung_lte_panel_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ /* wait couple of vsyncs until enabling the LCD */ -+ msleep(50); -+ -+ if (dssdev->platform_enable) -+ r = dssdev->platform_enable(dssdev); -+ -+ return r; -+} -+ -+static void samsung_lte_panel_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ /* wait at least 5 vsyncs after disabling the LCD */ -+ -+ msleep(100); -+} -+ -+static int samsung_lte_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ samsung_lte_panel_disable(dssdev); -+ return 0; -+} -+ -+static int samsung_lte_panel_resume(struct omap_dss_device *dssdev) -+{ -+ return samsung_lte_panel_enable(dssdev); -+} -+ -+static struct omap_dss_driver samsung_lte_driver = { -+ .probe = samsung_lte_panel_probe, -+ .remove = samsung_lte_panel_remove, -+ -+ .enable = samsung_lte_panel_enable, -+ .disable = samsung_lte_panel_disable, -+ .suspend = samsung_lte_panel_suspend, -+ .resume = samsung_lte_panel_resume, -+ -+ .driver = { -+ .name = "samsung_lte_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init samsung_lte_panel_drv_init(void) -+{ -+ return omap_dss_register_driver(&samsung_lte_driver); -+} -+ -+static void __exit samsung_lte_panel_drv_exit(void) -+{ -+ omap_dss_unregister_driver(&samsung_lte_driver); -+} -+ -+module_init(samsung_lte_panel_drv_init); -+module_exit(samsung_lte_panel_drv_exit); -+MODULE_LICENSE("GPL"); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0029-OMAP-DSS2-Add-support-for-LG-Philips-LB035Q02-panel.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0029-OMAP-DSS2-Add-support-for-LG-Philips-LB035Q02-panel.patch deleted file mode 100644 index 4f24fdd9..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0029-OMAP-DSS2-Add-support-for-LG-Philips-LB035Q02-panel.patch +++ /dev/null @@ -1,254 +0,0 @@ -From e960b2c16c24198a669a7c49e6282333faa74a3e Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 17 Dec 2009 15:05:30 -0800 -Subject: [PATCH 29/45] OMAP: DSS2: Add support for LG Philips LB035Q02 panel - ---- - drivers/video/omap2/displays/Kconfig | 6 + - drivers/video/omap2/displays/Makefile | 1 + - .../omap2/displays/panel-lgphilips-lb035q02.c | 206 ++++++++++++++++++++ - 3 files changed, 213 insertions(+), 0 deletions(-) - create mode 100644 drivers/video/omap2/displays/panel-lgphilips-lb035q02.c - -diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig -index 4229a28..875250a 100644 ---- a/drivers/video/omap2/displays/Kconfig -+++ b/drivers/video/omap2/displays/Kconfig -@@ -7,6 +7,12 @@ config PANEL_GENERIC - Generic panel driver. - Used for DVI output for Beagle and OMAP3 SDP. - -+config PANEL_LGPHILIPS_LB035Q02 -+ tristate "LG.Philips LB035Q02 LCD Panel" -+ depends on OMAP2_DSS -+ help -+ LCD Panel used on Overo Palo35 -+ - config PANEL_SAMSUNG_LTE430WQ_F0C - tristate "Samsung LTE430WQ-F0C LCD Panel" - depends on OMAP2_DSS -diff --git a/drivers/video/omap2/displays/Makefile b/drivers/video/omap2/displays/Makefile -index 9317445..f8e6c52 100644 ---- a/drivers/video/omap2/displays/Makefile -+++ b/drivers/video/omap2/displays/Makefile -@@ -1,4 +1,5 @@ - obj-$(CONFIG_PANEL_GENERIC) += panel-generic.o -+obj-$(CONFIG_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o - obj-$(CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C) += panel-samsung-lte430wq-f0c.o - obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o - obj-$(CONFIG_PANEL_SHARP_LQ043T1DG01) += panel-sharp-lq043t1dg01.o -diff --git a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c -new file mode 100644 -index 0000000..22dc865 ---- /dev/null -+++ b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c -@@ -0,0 +1,206 @@ -+/* -+ * LCD panel driver for LG.Philips LB035Q02 -+ * -+ * Author: Steve Sakoman -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+static struct spi_device *spidev; -+ -+static struct omap_video_timings lb035q02_timings = { -+ .x_res = 320, -+ .y_res = 240, -+ -+ .pixel_clock = 6500, -+ -+ .hsw = 2, -+ .hfp = 20, -+ .hbp = 68, -+ -+ .vsw = 2, -+ .vfp = 4, -+ .vbp = 18, -+}; -+ -+static int lb035q02_panel_probe(struct omap_dss_device *dssdev) -+{ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS; -+ dssdev->panel.timings = lb035q02_timings; -+ -+ return 0; -+} -+ -+static void lb035q02_panel_remove(struct omap_dss_device *dssdev) -+{ -+} -+ -+static int lb035q02_write_reg(u8 reg, u16 val) -+{ -+ struct spi_message msg; -+ struct spi_transfer index_xfer = { -+ .len = 3, -+ .cs_change = 1, -+ }; -+ struct spi_transfer value_xfer = { -+ .len = 3, -+ }; -+ u8 buffer[16]; -+ -+ spi_message_init(&msg); -+ -+ /* register index */ -+ buffer[0] = 0x70; -+ buffer[1] = 0x00; -+ buffer[2] = reg & 0x7f; -+ index_xfer.tx_buf = buffer; -+ spi_message_add_tail(&index_xfer, &msg); -+ -+ /* register value */ -+ buffer[4] = 0x72; -+ buffer[5] = val >> 8; -+ buffer[6] = val; -+ value_xfer.tx_buf = buffer + 4; -+ spi_message_add_tail(&value_xfer, &msg); -+ -+ return spi_sync(spidev, &msg); -+} -+ -+static int lb035q02_panel_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ pr_info("lgphilips_lb035q02: panel_enable: 0x%08x\n", spidev); -+ /* wait couple of vsyncs until enabling the LCD */ -+ msleep(50); -+ -+ if (dssdev->platform_enable) -+ r = dssdev->platform_enable(dssdev); -+ -+ /* Panel init sequence from page 28 of the spec */ -+ lb035q02_write_reg(0x01, 0x6300); -+ lb035q02_write_reg(0x02, 0x0200); -+ lb035q02_write_reg(0x03, 0x0177); -+ lb035q02_write_reg(0x04, 0x04c7); -+ lb035q02_write_reg(0x05, 0xffc0); -+ lb035q02_write_reg(0x06, 0xe806); -+ lb035q02_write_reg(0x0a, 0x4008); -+ lb035q02_write_reg(0x0b, 0x0000); -+ lb035q02_write_reg(0x0d, 0x0030); -+ lb035q02_write_reg(0x0e, 0x2800); -+ lb035q02_write_reg(0x0f, 0x0000); -+ lb035q02_write_reg(0x16, 0x9f80); -+ lb035q02_write_reg(0x17, 0x0a0f); -+ lb035q02_write_reg(0x1e, 0x00c1); -+ lb035q02_write_reg(0x30, 0x0300); -+ lb035q02_write_reg(0x31, 0x0007); -+ lb035q02_write_reg(0x32, 0x0000); -+ lb035q02_write_reg(0x33, 0x0000); -+ lb035q02_write_reg(0x34, 0x0707); -+ lb035q02_write_reg(0x35, 0x0004); -+ lb035q02_write_reg(0x36, 0x0302); -+ lb035q02_write_reg(0x37, 0x0202); -+ lb035q02_write_reg(0x3a, 0x0a0d); -+ lb035q02_write_reg(0x3b, 0x0806); -+ -+ return r; -+} -+ -+static void lb035q02_panel_disable(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ /* wait at least 5 vsyncs after disabling the LCD */ -+ -+ msleep(100); -+} -+ -+static int lb035q02_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ pr_info("lgphilips_lb035q02: panel_suspend\n"); -+ lb035q02_panel_disable(dssdev); -+ return 0; -+} -+ -+static int lb035q02_panel_resume(struct omap_dss_device *dssdev) -+{ -+ pr_info("lgphilips_lb035q02: panel_resume\n"); -+ return lb035q02_panel_enable(dssdev); -+} -+ -+static struct omap_dss_driver lb035q02_driver = { -+ .probe = lb035q02_panel_probe, -+ .remove = lb035q02_panel_remove, -+ -+ .enable = lb035q02_panel_enable, -+ .disable = lb035q02_panel_disable, -+ .suspend = lb035q02_panel_suspend, -+ .resume = lb035q02_panel_resume, -+ -+ .driver = { -+ .name = "lgphilips_lb035q02_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __devinit lb035q02_panel_spi_probe(struct spi_device *spi) -+{ -+ spidev = spi; -+ return 0; -+} -+ -+static int __devexit lb035q02_panel_spi_remove(struct spi_device *spi) -+{ -+ return 0; -+} -+ -+static struct spi_driver lb035q02_spi_driver = { -+ .driver = { -+ .name = "lgphilips_lb035q02_panel-spi", -+ .owner = THIS_MODULE, -+ }, -+ .probe = lb035q02_panel_spi_probe, -+ .remove = __devexit_p (lb035q02_panel_spi_remove), -+}; -+ -+static int __init lb035q02_panel_drv_init(void) -+{ -+ int ret; -+ ret = spi_register_driver(&lb035q02_spi_driver); -+ if (ret != 0) -+ pr_err("lgphilips_lb035q02: Unable to register SPI driver: %d\n", ret); -+ -+ ret = omap_dss_register_driver(&lb035q02_driver); -+ if (ret != 0) -+ pr_err("lgphilips_lb035q02: Unable to register panel driver: %d\n", ret); -+ -+ return ret; -+} -+ -+static void __exit lb035q02_panel_drv_exit(void) -+{ -+ spi_unregister_driver(&lb035q02_spi_driver); -+ omap_dss_unregister_driver(&lb035q02_driver); -+} -+ -+module_init(lb035q02_panel_drv_init); -+module_exit(lb035q02_panel_drv_exit); -+MODULE_LICENSE("GPL"); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0030-Fix-for-bus-width-which-improves-SD-card-s-peformanc.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0030-Fix-for-bus-width-which-improves-SD-card-s-peformanc.patch deleted file mode 100644 index 306389e7..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0030-Fix-for-bus-width-which-improves-SD-card-s-peformanc.patch +++ /dev/null @@ -1,32 +0,0 @@ -From ed355dc59a30638b914152d52752d5e0ca06ecbd Mon Sep 17 00:00:00 2001 -From: Kishore Kadiyala -Date: Wed, 17 Feb 2010 19:34:47 +0530 -Subject: [PATCH 30/45] Fix for bus width which improves SD card's peformance. - -This patch fixes bus width which improves peformance for SD cards. -OMAP-MMC controller's can support maximum bus width of '8'. -when bus width is mentioned as "8" in controller data,the SD -stack will check whether bus width is "4" and if not it will -set bus width to "1" and there by degrading peformance. - -Signed-off-by: Kishore Kadiyala ---- - drivers/mmc/host/omap_hsmmc.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c -index fa94580..9646a75 100644 ---- a/drivers/mmc/host/omap_hsmmc.c -+++ b/drivers/mmc/host/omap_hsmmc.c -@@ -1776,7 +1776,7 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev) - MMC_CAP_WAIT_WHILE_BUSY; - - if (mmc_slot(host).wires >= 8) -- mmc->caps |= MMC_CAP_8_BIT_DATA; -+ mmc->caps |= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA); - else if (mmc_slot(host).wires >= 4) - mmc->caps |= MMC_CAP_4_BIT_DATA; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0031-ARM-VFP-add-support-to-sync-the-VFP-state-of-the-cur.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0031-ARM-VFP-add-support-to-sync-the-VFP-state-of-the-cur.patch deleted file mode 100644 index 28d9f376..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0031-ARM-VFP-add-support-to-sync-the-VFP-state-of-the-cur.patch +++ /dev/null @@ -1,109 +0,0 @@ -From b366c2810c736d8d544cf261f3354eebaf5e5655 Mon Sep 17 00:00:00 2001 -From: Imre Deak -Date: Thu, 4 Feb 2010 21:38:02 +0200 -Subject: [PATCH 31/45] ARM: VFP: add support to sync the VFP state of the current thread - -ARM: VFP: add support to sync the VFP state of the current thread - -So far vfp_sync_state worked only for threads other than the current -one. This worked for tracing other threads, but not for PTRACE_TRACEME. -Syncing for the current thread will also be needed by an upcoming patch -adding support for VFP context save / restore around signal handlers. - -For SMP we need get_cpu now, since we have to protect the FPEXC -register, other than this things remained the same for threads other -than the current. - -Signed-off-by: Imre Deak -Signed-off-by: Bryan Wu ---- - arch/arm/vfp/vfpmodule.c | 46 +++++++++++++++++++++++++++++++--------------- - 1 files changed, 31 insertions(+), 15 deletions(-) - -diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c -index aed05bc..f28f45b 100644 ---- a/arch/arm/vfp/vfpmodule.c -+++ b/arch/arm/vfp/vfpmodule.c -@@ -423,12 +423,19 @@ static inline void vfp_pm_init(void) { } - #endif /* CONFIG_PM */ - - /* -- * Synchronise the hardware VFP state of a thread other than current with the -- * saved one. This function is used by the ptrace mechanism. -+ * Synchronise the hardware VFP state of a thread with the saved one. -+ * This function is used by the ptrace mechanism and the signal handler path. - */ --#ifdef CONFIG_SMP - void vfp_sync_state(struct thread_info *thread) - { -+ unsigned int cpu = get_cpu(); -+ u32 fpexc = fmrx(FPEXC); -+ int vfp_enabled; -+ int self; -+ -+ vfp_enabled = fpexc & FPEXC_EN; -+ self = thread == current_thread_info(); -+#ifdef CONFIG_SMP - /* - * On SMP systems, the VFP state is automatically saved at every - * context switch. We mark the thread VFP state as belonging to a -@@ -436,18 +443,22 @@ void vfp_sync_state(struct thread_info *thread) - * needed. - */ - thread->vfpstate.hard.cpu = NR_CPUS; --} --#else --void vfp_sync_state(struct thread_info *thread) --{ -- unsigned int cpu = get_cpu(); -- u32 fpexc = fmrx(FPEXC); -- - /* -- * If VFP is enabled, the previous state was already saved and -- * last_VFP_context updated. -+ * Only the current thread's saved VFP context can be out-of-date. -+ * For others there is nothing else to do, since we already ensured -+ * force loading above. - */ -- if (fpexc & FPEXC_EN) -+ if (!self) -+ goto out; -+#endif -+ /* -+ * If the VFP is enabled only the current thread's saved VFP -+ * context can get out-of-date. For other threads the context -+ * was updated when the current thread started to use the VFP. -+ * This also means that the context will be reloaded next time -+ * the thread uses the VFP, so no need to enforce it. -+ */ -+ if (vfp_enabled && !self) - goto out; - - if (!last_VFP_context[cpu]) -@@ -456,8 +467,14 @@ void vfp_sync_state(struct thread_info *thread) - /* - * Save the last VFP state on this CPU. - */ -- fmxr(FPEXC, fpexc | FPEXC_EN); -+ if (!vfp_enabled) -+ fmxr(FPEXC, fpexc | FPEXC_EN); - vfp_save_state(last_VFP_context[cpu], fpexc); -+ /* -+ * Disable VFP in case it was enabled so that the force reload -+ * can happen. -+ */ -+ fpexc &= ~FPEXC_EN; - fmxr(FPEXC, fpexc); - - /* -@@ -469,7 +486,6 @@ void vfp_sync_state(struct thread_info *thread) - out: - put_cpu(); - } --#endif - - #include - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0032-ARM-VFP-preserve-the-HW-context-when-calling-signal-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0032-ARM-VFP-preserve-the-HW-context-when-calling-signal-.patch deleted file mode 100644 index f2571306..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0032-ARM-VFP-preserve-the-HW-context-when-calling-signal-.patch +++ /dev/null @@ -1,211 +0,0 @@ -From 1be18045f852e78bf78d2042a5210c53d830f81b Mon Sep 17 00:00:00 2001 -From: Imre Deak -Date: Thu, 4 Feb 2010 21:38:30 +0200 -Subject: [PATCH 32/45] ARM: VFP: preserve the HW context when calling signal handlers - -ARM: VFP: preserve the HW context when calling signal handlers - -Signal handlers can use floating point, so prevent them to corrupt -the main thread's VFP context. So far there were two signal stack -frame formats defined based on the VFP implementation, but the user -struct used for ptrace covers all posibilities, so use it for the -signal stack too. This patch extends the user struct and leaves -its magic number the same, in the hope that user space code does -not depend on its size and can parse the original regs w/o -problems. - -Support to save / restore the exception registers was added by -Will Deacon. - -Signed-off-by: Imre Deak -Signed-off-by: Will Deacon -Signed-off-by: Bryan Wu ---- - arch/arm/include/asm/ucontext.h | 19 +++----- - arch/arm/include/asm/user.h | 3 + - arch/arm/kernel/signal.c | 91 +++++++++++++++++++++++++++++++++++++-- - 3 files changed, 97 insertions(+), 16 deletions(-) - -diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h -index bf65e9f..1c3236b 100644 ---- a/arch/arm/include/asm/ucontext.h -+++ b/arch/arm/include/asm/ucontext.h -@@ -59,23 +59,18 @@ struct iwmmxt_sigframe { - #endif /* CONFIG_IWMMXT */ - - #ifdef CONFIG_VFP --#if __LINUX_ARM_ARCH__ < 6 --/* For ARM pre-v6, we use fstmiax and fldmiax. This adds one extra -- * word after the registers, and a word of padding at the end for -- * alignment. */ - #define VFP_MAGIC 0x56465001 --#define VFP_STORAGE_SIZE 152 --#else --#define VFP_MAGIC 0x56465002 --#define VFP_STORAGE_SIZE 144 --#endif - - struct vfp_sigframe - { - unsigned long magic; - unsigned long size; -- union vfp_state storage; --}; -+ struct user_vfp ufp; -+} __attribute__((__aligned__(8))); -+ -+/* 8 byte for magic and size, 272 byte for ufp */ -+#define VFP_STORAGE_SIZE sizeof(struct vfp_sigframe) -+ - #endif /* CONFIG_VFP */ - - /* -@@ -91,7 +86,7 @@ struct aux_sigframe { - #ifdef CONFIG_IWMMXT - struct iwmmxt_sigframe iwmmxt; - #endif --#if 0 && defined CONFIG_VFP /* Not yet saved. */ -+#ifdef CONFIG_VFP - struct vfp_sigframe vfp; - #endif - /* Something that isn't a valid magic number for any coprocessor. */ -diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h -index df95e05..ea7e44d 100644 ---- a/arch/arm/include/asm/user.h -+++ b/arch/arm/include/asm/user.h -@@ -88,6 +88,9 @@ struct user{ - struct user_vfp { - unsigned long long fpregs[32]; - unsigned long fpscr; -+ unsigned long fpexc; -+ unsigned long fpinst; -+ unsigned long fpinst2; - }; - - #endif /* _ARM_USER_H */ -diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c -index e7714f3..6a36851 100644 ---- a/arch/arm/kernel/signal.c -+++ b/arch/arm/kernel/signal.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - - #include "ptrace.h" - #include "signal.h" -@@ -175,6 +176,88 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame) - - #endif - -+#ifdef CONFIG_VFP -+ -+static int preserve_vfp_context(struct vfp_sigframe __user *frame) -+{ -+ struct thread_info *thread = current_thread_info(); -+ struct vfp_hard_struct *h = &thread->vfpstate.hard; -+ const unsigned long magic = VFP_MAGIC; -+ const unsigned long size = VFP_STORAGE_SIZE; -+ int err = 0; -+ -+ vfp_sync_state(thread); -+ __put_user_error(magic, &frame->magic, err); -+ __put_user_error(size, &frame->size, err); -+ -+ /* -+ * Copy the floating point registers. There can be unused -+ * registers see asm/hwcap.h for details. -+ */ -+ err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs, -+ sizeof(h->fpregs)); -+ /* -+ * Copy the status and control register. -+ */ -+ __put_user_error(h->fpscr, &frame->ufp.fpscr, err); -+ -+ /* -+ * Copy the exception registers. -+ */ -+ __put_user_error(h->fpexc, &frame->ufp.fpexc, err); -+ __put_user_error(h->fpinst, &frame->ufp.fpinst, err); -+ __put_user_error(h->fpinst2, &frame->ufp.fpinst2, err); -+ -+ return err ? -EFAULT : 0; -+} -+ -+static int restore_vfp_context(struct vfp_sigframe __user *frame) -+{ -+ struct thread_info *thread = current_thread_info(); -+ struct vfp_hard_struct *h = &thread->vfpstate.hard; -+ unsigned long magic; -+ unsigned long size; -+ unsigned long fpexc; -+ int err = 0; -+ -+ vfp_sync_state(thread); -+ __get_user_error(magic, &frame->magic, err); -+ __get_user_error(size, &frame->size, err); -+ -+ if (err) -+ return -EFAULT; -+ if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE) -+ return -EINVAL; -+ -+ /* -+ * Copy the floating point registers. There can be unused -+ * registers see asm/hwcap.h for details. -+ */ -+ err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs, -+ sizeof(h->fpregs)); -+ /* -+ * Copy the status and control register. -+ */ -+ __get_user_error(h->fpscr, &frame->ufp.fpscr, err); -+ -+ /* -+ * Sanitise and restore the exception registers. -+ */ -+ __get_user_error(fpexc, &frame->ufp.fpexc, err); -+ /* Ensure the VFP is enabled. */ -+ fpexc |= FPEXC_EN; -+ /* Ensure FPINST2 is invalid and the exception flag is cleared. */ -+ fpexc &= ~(FPEXC_EX | FPEXC_FP2V); -+ h->fpexc = fpexc; -+ -+ __get_user_error(h->fpinst, &frame->ufp.fpinst, err); -+ __get_user_error(h->fpinst2, &frame->ufp.fpinst2, err); -+ -+ return err ? -EFAULT : 0; -+} -+ -+#endif -+ - /* - * Do a signal return; undo the signal stack. These are aligned to 64-bit. - */ -@@ -233,8 +316,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf) - err |= restore_iwmmxt_context(&aux->iwmmxt); - #endif - #ifdef CONFIG_VFP --// if (err == 0) --// err |= vfp_restore_state(&sf->aux.vfp); -+ if (err == 0) -+ err |= restore_vfp_context(&aux->vfp); - #endif - - return err; -@@ -348,8 +431,8 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set) - err |= preserve_iwmmxt_context(&aux->iwmmxt); - #endif - #ifdef CONFIG_VFP --// if (err == 0) --// err |= vfp_save_state(&sf->aux.vfp); -+ if (err == 0) -+ err |= preserve_vfp_context(&aux->vfp); - #endif - __put_user_error(0, &aux->end_magic, err); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0033-Switch-SGX-clocks-to-200MHz-on-DM37xx-OMAP36xx.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0033-Switch-SGX-clocks-to-200MHz-on-DM37xx-OMAP36xx.patch deleted file mode 100644 index 5711d393..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0033-Switch-SGX-clocks-to-200MHz-on-DM37xx-OMAP36xx.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 754249937d4ea60207bd85d172240840caa8fa2c Mon Sep 17 00:00:00 2001 -From: Prabindh Sundareson -Date: Wed, 3 Mar 2010 15:45:35 +0100 -Subject: [PATCH 33/45] Switch SGX clocks to 200MHz on DM37xx/OMAP36xx - ---- - arch/arm/mach-omap2/clock34xx_data.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c -index e3c752f..89e2f61 100644 ---- a/arch/arm/mach-omap2/clock34xx_data.c -+++ b/arch/arm/mach-omap2/clock34xx_data.c -@@ -3325,8 +3325,8 @@ static struct omap_clk omap3xxx_clks[] = { - CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), - CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), - CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), -- CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), -- CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), -+ CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517 | CK_36XX), -+ CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517 | CK_36XX), - CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), - CLK(NULL, "modem_fck", &modem_fck, CK_343X), - CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0034-modedb.c-add-proper-720p60-mode.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0034-modedb.c-add-proper-720p60-mode.patch deleted file mode 100644 index e7d4b25c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0034-modedb.c-add-proper-720p60-mode.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 48fe0d059d9bd5a8486309db26c7780fe3044626 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Mon, 8 Mar 2010 14:38:31 +0100 -Subject: [PATCH 34/45] modedb.c: add proper 720p60 mode - ---- - drivers/video/modedb.c | 4 ++++ - 1 files changed, 4 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c -index b32fa2a..f017d57 100644 ---- a/drivers/video/modedb.c -+++ b/drivers/video/modedb.c -@@ -44,6 +44,10 @@ static const struct fb_videomode modedb[] = { - NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, - 0, FB_VMODE_NONINTERLACED - }, { -+ /* 1280x720 @ 60 Hz, 45 kHz hsync, CEA 681-E Format 4 */ -+ "hd720", 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5, -+ 0, FB_VMODE_NONINTERLACED -+ }, { - /* 800x600 @ 56 Hz, 35.15 kHz hsync */ - NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, - 0, FB_VMODE_NONINTERLACED --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0035-RTC-add-support-for-backup-battery-recharge.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0035-RTC-add-support-for-backup-battery-recharge.patch deleted file mode 100644 index 6daabafa..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0035-RTC-add-support-for-backup-battery-recharge.patch +++ /dev/null @@ -1,55 +0,0 @@ -From eade32775fc8fc3c25c9bdace1828fe649a31e0a Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Thu, 4 Feb 2010 12:26:22 -0800 -Subject: [PATCH 35/45] RTC: add support for backup battery recharge - ---- - drivers/rtc/rtc-twl.c | 25 +++++++++++++++++++++++++ - 1 files changed, 25 insertions(+), 0 deletions(-) - -diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c -index c6a83a2..2329b5b 100644 ---- a/drivers/rtc/rtc-twl.c -+++ b/drivers/rtc/rtc-twl.c -@@ -30,6 +30,23 @@ - - #include - -+/* -+ * PM_RECEIVER block register offsets (use TWL4030_MODULE_PM_RECEIVER) -+ */ -+#define REG_BB_CFG 0x12 -+ -+/* PM_RECEIVER BB_CFG bitfields */ -+#define BIT_PM_RECEIVER_BB_CFG_BBCHEN 0x10 -+#define BIT_PM_RECEIVER_BB_CFG_BBSEL 0x0C -+#define BIT_PM_RECEIVER_BB_CFG_BBSEL_2V5 0x00 -+#define BIT_PM_RECEIVER_BB_CFG_BBSEL_3V0 0x04 -+#define BIT_PM_RECEIVER_BB_CFG_BBSEL_3V1 0x08 -+#define BIT_PM_RECEIVER_BB_CFG_BBSEL_3v2 0x0c -+#define BIT_PM_RECEIVER_BB_CFG_BBISEL 0x03 -+#define BIT_PM_RECEIVER_BB_CFG_BBISEL_25UA 0x00 -+#define BIT_PM_RECEIVER_BB_CFG_BBISEL_150UA 0x01 -+#define BIT_PM_RECEIVER_BB_CFG_BBISEL_500UA 0x02 -+#define BIT_PM_RECEIVER_BB_CFG_BBISEL_1MA 0x03 - - /* - * RTC block register offsets (use TWL_MODULE_RTC) -@@ -508,6 +525,14 @@ static int __devinit twl_rtc_probe(struct platform_device *pdev) - if (ret < 0) - goto out2; - -+ /* enable backup battery charging */ -+ /* use a conservative 25uA @ 3.1V */ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ BIT_PM_RECEIVER_BB_CFG_BBCHEN | -+ BIT_PM_RECEIVER_BB_CFG_BBSEL_3V1 | -+ BIT_PM_RECEIVER_BB_CFG_BBISEL_25UA, -+ REG_BB_CFG); -+ - return ret; - - out2: --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0036-ARM-Add-prompt-for-CONFIG_ALIGNMENT_TRAP.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0036-ARM-Add-prompt-for-CONFIG_ALIGNMENT_TRAP.patch deleted file mode 100644 index 2505f428..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0036-ARM-Add-prompt-for-CONFIG_ALIGNMENT_TRAP.patch +++ /dev/null @@ -1,29 +0,0 @@ -From f4902a8ee1bbc739a60dcd970705c5665e98691f Mon Sep 17 00:00:00 2001 -From: Mans Rullgard -Date: Mon, 13 Oct 2008 20:32:16 +0100 -Subject: [PATCH 36/45] ARM: Add prompt for CONFIG_ALIGNMENT_TRAP - -This adds a prompt text for CONFIG_ALIGNMENT_TRAP, thus making it -visible in make *config. - -Signed-off-by: Mans Rullgard ---- - arch/arm/Kconfig | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 88f628b..f5ded3c 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1224,7 +1224,7 @@ config LEDS_CPU - will overrule the CPU usage LED. - - config ALIGNMENT_TRAP -- bool -+ bool "Enable alignment trap" - depends on CPU_CP15_MMU - default y if !ARCH_EBSA110 - help --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0037-ARM-Print-warning-on-alignment-trap-in-kernel-mode.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0037-ARM-Print-warning-on-alignment-trap-in-kernel-mode.patch deleted file mode 100644 index 9594edd2..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0037-ARM-Print-warning-on-alignment-trap-in-kernel-mode.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 310ec494b3c860e657290648821dbc98da9fff90 Mon Sep 17 00:00:00 2001 -From: Mans Rullgard -Date: Sat, 28 Mar 2009 13:21:55 +0000 -Subject: [PATCH 37/45] ARM: Print warning on alignment trap in kernel mode - -Signed-off-by: Mans Rullgard ---- - arch/arm/mm/alignment.c | 7 +++++++ - 1 files changed, 7 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c -index b270d62..5e9014b 100644 ---- a/arch/arm/mm/alignment.c -+++ b/arch/arm/mm/alignment.c -@@ -756,6 +756,13 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs) - - ai_sys += 1; - -+ printk("Alignment trap in kernel: %s (%d) PC=0x%08lx Instr=0x%0*lx " -+ "Address=0x%08lx FSR 0x%03x\n", current->comm, -+ task_pid_nr(current), instrptr, -+ thumb_mode(regs) ? 4 : 8, -+ thumb_mode(regs) ? tinstr : instr, -+ addr, fsr); -+ - fixup: - - regs->ARM_pc += isize; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0038-ARM-Expose-some-CPU-control-registers-via-sysfs.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0038-ARM-Expose-some-CPU-control-registers-via-sysfs.patch deleted file mode 100644 index 0b19cb70..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0038-ARM-Expose-some-CPU-control-registers-via-sysfs.patch +++ /dev/null @@ -1,202 +0,0 @@ -From 9eeb533964f73b661d23f7b145b96aa5d247e950 Mon Sep 17 00:00:00 2001 -From: Mans Rullgard -Date: Tue, 10 Nov 2009 00:39:21 +0000 -Subject: [PATCH 38/45] ARM: Expose some CPU control registers via sysfs - -This creates sysfs files under /sys/devices/system/cpu/cpuN -exposing the values of the control register, auxiliary control -register, and L2 cache auxiliary control register. Writing to -the files allows setting the value of bits which are safe to -change at any time. - -Signed-off-by: Mans Rullgard ---- - arch/arm/Kconfig | 5 ++ - arch/arm/kernel/Makefile | 1 + - arch/arm/kernel/sysfs_v7.c | 146 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 152 insertions(+), 0 deletions(-) - create mode 100644 arch/arm/kernel/sysfs_v7.c - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index f5ded3c..2d370da 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1252,6 +1252,11 @@ config UACCESS_WITH_MEMCPY - However, if the CPU data cache is using a write-allocate mode, - this option is unlikely to provide any performance gain. - -+config CPU_V7_SYSFS -+ bool -+ depends on CPU_V7 && SYSFS -+ default y -+ - endmenu - - menu "Boot options" -diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile -index dd00f74..ee20134 100644 ---- a/arch/arm/kernel/Makefile -+++ b/arch/arm/kernel/Makefile -@@ -38,6 +38,7 @@ obj-$(CONFIG_ARM_THUMBEE) += thumbee.o - obj-$(CONFIG_KGDB) += kgdb.o - obj-$(CONFIG_ARM_UNWIND) += unwind.o - obj-$(CONFIG_HAVE_TCM) += tcm.o -+obj-$(CONFIG_CPU_V7_SYSFS) += sysfs_v7.o - - obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o - AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 -diff --git a/arch/arm/kernel/sysfs_v7.c b/arch/arm/kernel/sysfs_v7.c -new file mode 100644 -index 0000000..c05bf5f ---- /dev/null -+++ b/arch/arm/kernel/sysfs_v7.c -@@ -0,0 +1,146 @@ -+/* -+ * linux/arch/arm/kernel/sysfs.c -+ * -+ * Copyright (C) 2008 Mans Rullgard -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#define SETBITS(val, bits, new) \ -+ do { \ -+ val &= ~bits; \ -+ val |= new & bits; \ -+ } while (0) -+ -+#define SHOW_REG(name, opc1, crn, crm, opc2) \ -+static ssize_t name##_show(struct sys_device *dev, \ -+ struct sysdev_attribute *attr, \ -+ char *buf) \ -+{ \ -+ unsigned val; \ -+ asm ("mrc p15,"#opc1", %0,"#crn","#crm","#opc2 : "=r"(val)); \ -+ return snprintf(buf, PAGE_SIZE, "%08x\n", val); \ -+} -+ -+#define STORE_REG(name, opc1, crn, crm, opc2, bits) \ -+static ssize_t name##_store(struct sys_device *dev, \ -+ struct sysdev_attribute *attr, \ -+ const char *buf, size_t size) \ -+{ \ -+ char *end; \ -+ unsigned new = simple_strtoul(buf, &end, 0); \ -+ unsigned val; \ -+ \ -+ if (end == buf) \ -+ return -EINVAL; \ -+ \ -+ asm ("mrc p15,"#opc1", %0,"#crn","#crm","#opc2 : "=r"(val)); \ -+ SETBITS(val, bits, new); \ -+ asm ("mcr p15,"#opc1", %0,"#crn","#crm","#opc2 :: "r"(val)); \ -+ \ -+ return end - buf; \ -+} -+ -+#define RD_REG(name, opc1, crn, crm, opc2) \ -+ SHOW_REG(name, opc1, crn, crm, opc2) \ -+ static SYSDEV_ATTR(name, S_IRUGO|S_IWUSR, name##_show, NULL) -+ -+#define RDWR_REG(name, opc1, crn, crm, opc2, bits) \ -+ SHOW_REG(name, opc1, crn, crm, opc2) \ -+ STORE_REG(name, opc1, crn, crm, opc2, bits) \ -+ static SYSDEV_ATTR(name, S_IRUGO|S_IWUSR, name##_show, name##_store) -+ -+RDWR_REG(control, 0, c1, c0, 0, 0x802); -+ -+SHOW_REG(aux_ctl, 0, c1, c0, 1) -+ -+#ifdef CONFIG_ARCH_OMAP34XX -+static ssize_t aux_ctl_store(struct sys_device *dev, -+ struct sysdev_attribute *attr, -+ const char *buf, size_t size) -+{ -+ char *end; -+ unsigned new = simple_strtoul(buf, &end, 0); -+ unsigned val; -+ -+ if (end == buf) -+ return -EINVAL; -+ -+ asm ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val)); -+ SETBITS(val, 0xff8, new); -+ val &= ~2; -+ asm ("mov r0, %0 \n\t" -+ "mov r12, #3 \n\t" -+ "smc #0 \n\t" -+ :: "r"(val) : "r0", "r12"); -+ -+ return end - buf; -+} -+#define AUX_WR S_IWUSR -+#else -+#define aux_ctl_store NULL -+#define AUX_WR 0 -+#endif -+ -+static SYSDEV_ATTR(aux_control, S_IRUGO|AUX_WR, aux_ctl_show, aux_ctl_store); -+ -+SHOW_REG(l2_aux_ctl, 1, c9, c0, 2) -+ -+#ifdef CONFIG_ARCH_OMAP34XX -+static ssize_t l2_aux_ctl_store(struct sys_device *dev, -+ struct sysdev_attribute *attr, -+ const char *buf, size_t size) -+{ -+ char *end; -+ unsigned new = simple_strtoul(buf, &end, 0); -+ unsigned val; -+ -+ if (end == buf) -+ return -EINVAL; -+ -+ asm ("mrc p15, 1, %0, c9, c0, 2" : "=r"(val)); -+ SETBITS(val, 0xbc00000, new); -+ asm ("mov r0, %0 \n\t" -+ "mov r12, #2 \n\t" -+ "smc #0 \n\t" -+ :: "r"(val) : "r0", "r12"); -+ -+ return end - buf; -+} -+#define L2AUX_WR S_IWUSR -+#else -+#define l2_aux_ctl_store NULL -+#define L2AUX_WR 0 -+#endif -+ -+static SYSDEV_ATTR(l2_aux_control, S_IRUGO|L2AUX_WR, -+ l2_aux_ctl_show, l2_aux_ctl_store); -+ -+#define REG_ATTR(sysdev, name) \ -+ do { \ -+ int err = sysfs_create_file(&sysdev->kobj, &name.attr); \ -+ WARN_ON(err != 0); \ -+ } while (0) -+ -+static int __init cpu_sysfs_init(void) -+{ -+ struct sys_device *sysdev; -+ int cpu; -+ -+ for_each_possible_cpu(cpu) { -+ sysdev = get_cpu_sysdev(cpu); -+ REG_ATTR(sysdev, attr_control); -+ REG_ATTR(sysdev, attr_aux_control); -+ REG_ATTR(sysdev, attr_l2_aux_control); -+ } -+ -+ return 0; -+} -+device_initcall(cpu_sysfs_init); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0039-ARM-Add-option-to-allow-userspace-PLE-access.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0039-ARM-Add-option-to-allow-userspace-PLE-access.patch deleted file mode 100644 index f72c477f..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0039-ARM-Add-option-to-allow-userspace-PLE-access.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 2f716593e3f11859bf98c997183c47587c2dba76 Mon Sep 17 00:00:00 2001 -From: Mans Rullgard -Date: Tue, 10 Nov 2009 00:41:54 +0000 -Subject: [PATCH 39/45] ARM: Add option to allow userspace PLE access - -This adds a Kconfig option to allow userspace to access the L2 preload -engine (PLE) found in Cortex-A8. - -Signed-off-by: Mans Rullgard ---- - arch/arm/kernel/head.S | 4 ++++ - arch/arm/mm/Kconfig | 8 ++++++++ - 2 files changed, 12 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S -index eb62bf9..659ec9e 100644 ---- a/arch/arm/kernel/head.S -+++ b/arch/arm/kernel/head.S -@@ -172,6 +172,10 @@ __enable_mmu: - #ifdef CONFIG_CPU_ICACHE_DISABLE - bic r0, r0, #CR_I - #endif -+#ifdef CONFIG_USER_L2_PLE -+ mov r5, #3 -+ mcr p15, 0, r5, c11, c1, 0 -+#endif - mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ - domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ -diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig -index dd4698c..564ff7d 100644 ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -785,3 +785,11 @@ config ARM_L1_CACHE_SHIFT - int - default 6 if ARCH_OMAP3 || ARCH_S5PC1XX - default 5 -+ -+config USER_L2_PLE -+ bool "Enable userspace access to the L2 PLE" -+ depends on CPU_V7 -+ default n -+ help -+ Enable userspace access to the L2 preload engine (PLE) available -+ in Cortex-A series ARM processors. --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch deleted file mode 100644 index 5cecd3fa..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch +++ /dev/null @@ -1,49 +0,0 @@ -From dd1e35157bfd32303aaf87b1ec3f85d8dd1c0014 Mon Sep 17 00:00:00 2001 -From: Mans Rullgard -Date: Tue, 10 Nov 2009 00:52:56 +0000 -Subject: [PATCH 40/45] ARM: Add option to allow userspace access to performance counters - -This adds an option to allow userspace access to the performance monitor -registers of the Cortex-A8. - -Signed-off-by: Mans Rullgard ---- - arch/arm/mm/Kconfig | 7 +++++++ - arch/arm/mm/proc-v7.S | 6 ++++++ - 2 files changed, 13 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig -index 564ff7d..fda2e68 100644 ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -793,3 +793,10 @@ config USER_L2_PLE - help - Enable userspace access to the L2 preload engine (PLE) available - in Cortex-A series ARM processors. -+ -+config USER_PMON -+ bool "Enable userspace access to performance counters" -+ depends on CPU_V7 -+ default n -+ help -+ Enable userpsace access to the performance monitor registers. -diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S -index 3a28521..fec926a 100644 ---- a/arch/arm/mm/proc-v7.S -+++ b/arch/arm/mm/proc-v7.S -@@ -270,6 +270,12 @@ __v7_setup: - mcr p15, 0, r5, c10, c2, 0 @ write PRRR - mcr p15, 0, r6, c10, c2, 1 @ write NMRR - #endif -+ -+#ifdef CONFIG_USER_PMON -+ mov r0, #1 -+ mcr p15, 0, r0, c9, c14, 0 -+#endif -+ - adr r5, v7_crval - ldmia r5, {r5, r6} - #ifdef CONFIG_CPU_ENDIAN_BE8 --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0041-ARM-Expose-some-PMON-registers-through-sysfs.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0041-ARM-Expose-some-PMON-registers-through-sysfs.patch deleted file mode 100644 index c5ee454c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0041-ARM-Expose-some-PMON-registers-through-sysfs.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 13fdb12b3744ca0eaf00d5339919b17ce933c6d5 Mon Sep 17 00:00:00 2001 -From: Mans Rullgard -Date: Sat, 28 Mar 2009 13:05:02 +0000 -Subject: [PATCH 41/45] ARM: Expose some PMON registers through sysfs - ---- - arch/arm/kernel/sysfs_v7.c | 11 +++++++++++ - 1 files changed, 11 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/kernel/sysfs_v7.c b/arch/arm/kernel/sysfs_v7.c -index c05bf5f..5ed32fb 100644 ---- a/arch/arm/kernel/sysfs_v7.c -+++ b/arch/arm/kernel/sysfs_v7.c -@@ -123,6 +123,12 @@ static ssize_t l2_aux_ctl_store(struct sys_device *dev, - static SYSDEV_ATTR(l2_aux_control, S_IRUGO|L2AUX_WR, - l2_aux_ctl_show, l2_aux_ctl_store); - -+RDWR_REG(pmon_pmnc, 0, c9, c12, 0, 0x3f) -+RDWR_REG(pmon_cntens, 0, c9, c12, 1, 0x8000000f) -+RDWR_REG(pmon_cntenc, 0, c9, c12, 2, 0x8000000f) -+RDWR_REG(pmon_ccnt, 0, c9, c13, 0, 0xffffffff) -+RDWR_REG(pmon_useren, 0, c9, c14, 0, 1) -+ - #define REG_ATTR(sysdev, name) \ - do { \ - int err = sysfs_create_file(&sysdev->kobj, &name.attr); \ -@@ -139,6 +145,11 @@ static int __init cpu_sysfs_init(void) - REG_ATTR(sysdev, attr_control); - REG_ATTR(sysdev, attr_aux_control); - REG_ATTR(sysdev, attr_l2_aux_control); -+ REG_ATTR(sysdev, attr_pmon_pmnc); -+ REG_ATTR(sysdev, attr_pmon_cntens); -+ REG_ATTR(sysdev, attr_pmon_cntenc); -+ REG_ATTR(sysdev, attr_pmon_ccnt); -+ REG_ATTR(sysdev, attr_pmon_useren); - } - - return 0; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0042-musb-allow-host-io-without-gadget-module.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0042-musb-allow-host-io-without-gadget-module.patch deleted file mode 100644 index 65c12c8e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0042-musb-allow-host-io-without-gadget-module.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 97283f52ea7fbb9b611a65d031c997e4ae44d465 Mon Sep 17 00:00:00 2001 -From: Ajay Kumar Gupta -Date: Wed, 14 Apr 2010 16:08:37 +0530 -Subject: [PATCH 42/45] musb: allow host io without gadget module - -Signed-off-by: Ajay Kumar Gupta ---- - drivers/usb/musb/musb_core.c | 14 +++++++++----- - drivers/usb/musb/musb_gadget.c | 26 -------------------------- - 2 files changed, 9 insertions(+), 31 deletions(-) - -diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c -index 71ec7e8..9988553 100644 ---- a/drivers/usb/musb/musb_core.c -+++ b/drivers/usb/musb/musb_core.c -@@ -2101,10 +2101,12 @@ bad_config: - * (We expect the ID pin to be forcibly grounded!!) - * Otherwise, wait till the gadget driver hooks up. - */ -- if (!is_otg_enabled(musb) && is_host_enabled(musb)) { -- MUSB_HST_MODE(musb); -- musb->xceiv->default_a = 1; -- musb->xceiv->state = OTG_STATE_A_IDLE; -+ if (is_host_enabled(musb)) { -+ if (!is_otg_enabled(musb)) { -+ MUSB_HST_MODE(musb); -+ musb->xceiv->default_a = 1; -+ musb->xceiv->state = OTG_STATE_A_IDLE; -+ } - - status = usb_add_hcd(musb_to_hcd(musb), -1, 0); - -@@ -2115,7 +2117,9 @@ bad_config: - & MUSB_DEVCTL_BDEVICE - ? 'B' : 'A')); - -- } else /* peripheral is enabled */ { -+ } -+ /* peripheral is enabled */ -+ if (is_peripheral_enabled(musb)) { - MUSB_DEV_MODE(musb); - musb->xceiv->default_a = 0; - musb->xceiv->state = OTG_STATE_B_IDLE; -diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c -index 454f6db..d0d1cee 100644 ---- a/drivers/usb/musb/musb_gadget.c -+++ b/drivers/usb/musb/musb_gadget.c -@@ -1768,24 +1768,6 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) - otg_set_peripheral(musb->xceiv, &musb->g); - - spin_unlock_irqrestore(&musb->lock, flags); -- -- if (is_otg_enabled(musb)) { -- DBG(3, "OTG startup...\n"); -- -- /* REVISIT: funcall to other code, which also -- * handles power budgeting ... this way also -- * ensures HdrcStart is indirectly called. -- */ -- retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); -- if (retval < 0) { -- DBG(1, "add_hcd failed, %d\n", retval); -- spin_lock_irqsave(&musb->lock, flags); -- otg_set_peripheral(musb->xceiv, NULL); -- musb->gadget_driver = NULL; -- musb->g.dev.driver = NULL; -- spin_unlock_irqrestore(&musb->lock, flags); -- } -- } - } - - return retval; -@@ -1881,14 +1863,6 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) - retval = -EINVAL; - spin_unlock_irqrestore(&musb->lock, flags); - -- if (is_otg_enabled(musb) && retval == 0) { -- usb_remove_hcd(musb_to_hcd(musb)); -- /* FIXME we need to be able to register another -- * gadget driver here and have everything work; -- * that currently misbehaves. -- */ -- } -- - return retval; - } - EXPORT_SYMBOL(usb_gadget_unregister_driver); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0043-MTD-silence-ecc-errors-on-mtdblock0.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0043-MTD-silence-ecc-errors-on-mtdblock0.patch deleted file mode 100644 index b80e3d62..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0043-MTD-silence-ecc-errors-on-mtdblock0.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 2379628bcd6c08e472020c78019ce8ea3fce3027 Mon Sep 17 00:00:00 2001 -From: Steve Sakoman -Date: Mon, 26 Apr 2010 11:17:26 -0700 -Subject: [PATCH 43/45] MTD: silence ecc errors on mtdblock0 - -mtdblock0 is the x-load partition, which uses hw ecc -this confuses linux, which uses sw ecc -this patch silences ecc error messages when linux peeks into mtdblock0 -* not for upstream submission * ---- - block/blk-core.c | 3 ++- - drivers/mtd/nand/nand_ecc.c | 2 +- - fs/buffer.c | 3 ++- - 3 files changed, 5 insertions(+), 3 deletions(-) - -diff --git a/block/blk-core.c b/block/blk-core.c -index 718897e..c526fde 100644 ---- a/block/blk-core.c -+++ b/block/blk-core.c -@@ -1970,7 +1970,8 @@ bool blk_update_request(struct request *req, int error, unsigned int nr_bytes) - req->errors = 0; - - if (error && (blk_fs_request(req) && !(req->cmd_flags & REQ_QUIET))) { -- printk(KERN_ERR "end_request: I/O error, dev %s, sector %llu\n", -+ if (req->rq_disk && (strcmp(req->rq_disk->disk_name, "mtdblock0") != 0)) -+ printk(KERN_ERR "end_request: I/O error, dev %s, sector %llu\n", - req->rq_disk ? req->rq_disk->disk_name : "?", - (unsigned long long)blk_rq_pos(req)); - } -diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c -index 92320a6..2b86b6d 100644 ---- a/drivers/mtd/nand/nand_ecc.c -+++ b/drivers/mtd/nand/nand_ecc.c -@@ -492,7 +492,7 @@ int __nand_correct_data(unsigned char *buf, - if ((bitsperbyte[b0] + bitsperbyte[b1] + bitsperbyte[b2]) == 1) - return 1; /* error in ecc data; no action needed */ - -- printk(KERN_ERR "uncorrectable error : "); -+// printk(KERN_ERR "uncorrectable error : "); - return -1; - } - EXPORT_SYMBOL(__nand_correct_data); -diff --git a/fs/buffer.c b/fs/buffer.c -index 6fa5302..27b3103 100644 ---- a/fs/buffer.c -+++ b/fs/buffer.c -@@ -114,7 +114,8 @@ static int quiet_error(struct buffer_head *bh) - static void buffer_io_error(struct buffer_head *bh) - { - char b[BDEVNAME_SIZE]; -- printk(KERN_ERR "Buffer I/O error on device %s, logical block %Lu\n", -+ if (strcmp(bdevname(bh->b_bdev, b), "mtdblock0") != 0) -+ printk(KERN_ERR "Buffer I/O error on device %s, logical block %Lu\n", - bdevname(bh->b_bdev, b), - (unsigned long long)bh->b_blocknr); - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0044-ARM-OMAP-beagle-every-known-beagle-except-revB-uses-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0044-ARM-OMAP-beagle-every-known-beagle-except-revB-uses-.patch deleted file mode 100644 index 5656c356..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0044-ARM-OMAP-beagle-every-known-beagle-except-revB-uses-.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 71886bfebaf13c74a55f11264096286a554e5a3d Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Thu, 13 May 2010 21:43:08 +0200 -Subject: [PATCH 44/45] ARM: OMAP: beagle: every known beagle (except revB) uses 2 chipselects so don't use NULL for the second chipselect timings - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index dd830b1..078e026 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -614,7 +614,7 @@ static void __init omap3_beagle_init_irq(void) - if (cpu_is_omap3630()) - { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- NULL, -+ mt46h32m32lf6_sdrc_params, - _omap37x_mpu_rate_table, - _omap37x_dsp_rate_table, - _omap37x_l3_rate_table); -@@ -622,7 +622,7 @@ static void __init omap3_beagle_init_irq(void) - else - { - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, -- NULL, -+ mt46h32m32lf6_sdrc_params, - _omap35x_mpu_rate_table, - _omap35x_dsp_rate_table, - _omap35x_l3_rate_table); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0045-ARM-OMAP-beagle-add-support-for-beagleFPGA-expansion.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0045-ARM-OMAP-beagle-add-support-for-beagleFPGA-expansion.patch deleted file mode 100644 index 2a48a301..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0045-ARM-OMAP-beagle-add-support-for-beagleFPGA-expansion.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 1ebb6f864a831fc8efebe4a7a9f65d07fa31466a Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sat, 15 May 2010 21:47:32 +0200 -Subject: [PATCH 45/45] ARM: OMAP: beagle: add support for beagleFPGA expansionboard: http://members.cox.net/ebrombaugh1/embedded/beagle/beagle_fpga.html - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 26 ++++++++++++++++++++++++++ - 1 files changed, 26 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 078e026..b313350 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -47,6 +48,7 @@ - #include - #include - #include -+#include - - #include "mux.h" - #include "mmc-twl4030.h" -@@ -609,6 +611,24 @@ static struct platform_device keys_gpio = { - }, - }; - -+static struct spi_board_info beaglefpga_mcspi_board_info[] = { -+ // spi 4.0 -+ { -+ .modalias = "spidev", -+ .max_speed_hz = 48000000, //48 Mbps -+ .bus_num = 4, -+ .chip_select = 0, -+ .mode = SPI_MODE_1, -+ }, -+}; -+ -+static void __init beaglefpga_init_spi(void) -+{ -+ /* hook the spi ports to the spidev driver */ -+ spi_register_board_info(beaglefpga_mcspi_board_info, -+ ARRAY_SIZE(beaglefpga_mcspi_board_info)); -+} -+ - static void __init omap3_beagle_init_irq(void) - { - if (cpu_is_omap3630()) -@@ -769,6 +789,12 @@ static void __init omap3_beagle_init(void) - gpio_export(162, 1); - } - -+ if(!strcmp(expansionboard_name, "beaglefpga")) -+ { -+ printk(KERN_INFO "Beagle expansionboard: Using McSPI for SPI\n"); -+ beaglefpga_init_spi(); -+ } -+ - usb_musb_init(); - usb_ehci_init(&ehci_pdata); - omap3beagle_flash_init(); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0046-attemp-to-fix-serial-console-corruption-during-cpuid.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0046-attemp-to-fix-serial-console-corruption-during-cpuid.patch deleted file mode 100644 index 11f52262..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0046-attemp-to-fix-serial-console-corruption-during-cpuid.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b0c673e40d40428a9bd05101d15d773cd4f4720c Mon Sep 17 00:00:00 2001 -From: Ranjith Lohithakshan -Date: Sat, 22 May 2010 18:32:24 +0200 -Subject: [PATCH 46/48] attemp to fix serial console corruption during cpuidle - ---- - arch/arm/mach-omap2/cpuidle34xx.c | 6 +++++- - 1 files changed, 5 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c -index f8aea56..35d1c3e 100644 ---- a/arch/arm/mach-omap2/cpuidle34xx.c -+++ b/arch/arm/mach-omap2/cpuidle34xx.c -@@ -60,7 +60,7 @@ struct omap3_processor_cx { - - struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; - struct omap3_processor_cx current_cx_state; --struct powerdomain *mpu_pd, *core_pd; -+struct powerdomain *mpu_pd, *per_pd, *core_pd; - - /* - * The latencies/thresholds for various C states have -@@ -131,6 +131,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev, - local_fiq_disable(); - - pwrdm_set_next_pwrst(mpu_pd, mpu_state); -+ pwrdm_set_next_pwrst(per_pd, mpu_state); - pwrdm_set_next_pwrst(core_pd, core_state); - - if (omap_irq_pending() || need_resched()) -@@ -138,6 +139,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev, - - if (cx->type == OMAP3_STATE_C1) { - pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); -+ pwrdm_for_each_clkdm(per_pd, _cpuidle_deny_idle); - pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); - } - -@@ -146,6 +148,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev, - - if (cx->type == OMAP3_STATE_C1) { - pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); -+ pwrdm_for_each_clkdm(per_pd, _cpuidle_allow_idle); - pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); - } - -@@ -425,6 +428,7 @@ int __init omap3_idle_init(void) - struct cpuidle_device *dev; - - mpu_pd = pwrdm_lookup("mpu_pwrdm"); -+ per_pd = pwrdm_lookup("per_pwrdm"); - core_pd = pwrdm_lookup("core_pwrdm"); - - omap_init_power_states(); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0047-clock34xx-only-try-to-idle-IVA-subsys-when-CONFIG_PM.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0047-clock34xx-only-try-to-idle-IVA-subsys-when-CONFIG_PM.patch deleted file mode 100644 index 0db8bf7c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0047-clock34xx-only-try-to-idle-IVA-subsys-when-CONFIG_PM.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4d5f88fca430ca38a35e60683dc301e80046b05d Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sun, 23 May 2010 14:47:32 +0200 -Subject: [PATCH 47/48] clock34xx: only try to idle IVA subsys when CONFIG_PM is set - ---- - arch/arm/mach-omap2/clock34xx.c | 5 ++++- - 1 files changed, 4 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c -index 2bb7182..a323f9f 100644 ---- a/arch/arm/mach-omap2/clock34xx.c -+++ b/arch/arm/mach-omap2/clock34xx.c -@@ -407,7 +407,9 @@ void omap3_clk_lock_dpll5(void) - return; - } - -+#ifdef CONFIG_PM - extern void __init omap3_iva_idle(void); -+#endif - - /* - * Initialize IVA to a idle state. This is typically done by the -@@ -425,8 +427,9 @@ static void __init omap2_clk_iva_init_to_idle(void) - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); - -+#ifdef CONFIG_PM - omap3_iva_idle(); -- -+#endif - } - - /* REVISIT: Move this init stuff out into clock.c */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/0048-HACK-try-to-poweron-stuff-on-xM-rev-A.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/0048-HACK-try-to-poweron-stuff-on-xM-rev-A.patch deleted file mode 100644 index 19a235ac..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/0048-HACK-try-to-poweron-stuff-on-xM-rev-A.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 258a962bea2da43df6f70fd264a0e23b65669176 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Tue, 4 May 2010 17:04:27 +0200 -Subject: [PATCH 48/48] HACK: try to poweron stuff on xM rev A - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 14 +++++++------- - 1 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index b313350..7f0e241 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -237,7 +237,6 @@ static struct omap_dss_device beagle_dvi_device = { - .name = "dvi", - .driver_name = "generic_panel", - .phy.dpi.data_lines = 24, -- .reset_gpio = 170, - .platform_enable = beagle_enable_dvi, - .platform_disable = beagle_disable_dvi, - }; -@@ -364,6 +363,9 @@ static int beagle_twl_gpio_setup(struct device *dev, - */ - - if (cpu_is_omap3630()) { -+ /* DVI reset GPIO is different between revisions */ -+ beagle_dvi_device.reset_gpio = 129; -+ - /* Power on DVI, Serial and PWR led */ - gpio_request(gpio + 1, "nDVI_PWR_EN"); - gpio_direction_output(gpio + 1, 0); -@@ -374,9 +376,12 @@ static int beagle_twl_gpio_setup(struct device *dev, - - /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ - gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); -+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - } - else { -+ /* DVI reset GPIO is different between revisions */ -+ beagle_dvi_device.reset_gpio = 170; -+ - gpio_request(gpio + 1, "EHCI_nOC"); - gpio_direction_input(gpio + 1); - -@@ -735,11 +740,6 @@ static void __init omap3_beagle_init(void) - ARRAY_SIZE(omap3_beagle_devices)); - omap_serial_init(); - -- omap_mux_init_gpio(170, OMAP_PIN_INPUT); -- gpio_request(170, "DVI_nPD"); -- /* REVISIT leave DVI powered down until it's needed ... */ -- gpio_direction_output(170, true); -- - if(!strcmp(expansionboard_name, "zippy")) - { - printk(KERN_INFO "Beagle expansionboard: initializing enc28j60\n"); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-crane/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-crane/defconfig deleted file mode 100644 index 52ec8601..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-crane/defconfig +++ /dev/null @@ -1,2139 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Fri Dec 24 10:51:48 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_INTEGRITY=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_PM_SRF is not set -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -CONFIG_MACH_CRANEBOARD=y -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_USER_L2_PLE=y -CONFIG_USER_PMON=y -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_458693=y -CONFIG_ARM_ERRATA_460075=y -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=y -CONFIG_CAN_RAW=y -CONFIG_CAN_BCM=y - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=y -CONFIG_CAN_DEV=y -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_TI_HECC=y -# CONFIG_CAN_SJA1000 is not set - -# -# CAN USB interfaces -# -# CONFIG_CAN_EMS_USB is not set -CONFIG_CAN_DEBUG_DEVICES=y -# CONFIG_IRDA is not set -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -# CONFIG_MAC80211_RC_PID is not set -CONFIG_MAC80211_RC_MINSTREL=y -# CONFIG_MAC80211_RC_DEFAULT_PID is not set -CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT="minstrel" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -# CONFIG_MTD_NAND_OMAP_PREFETCH is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -CONFIG_TI_DAVINCI_EMAC=y -# CONFIG_DM9000 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_AT76C50X_USB is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_RTL8187 is not set -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_HOSTAP is not set -# CONFIG_IWM is not set -# CONFIG_LIBERTAS is not set -# CONFIG_P54_COMMON is not set -# CONFIG_RT2X00 is not set -# CONFIG_WL12XX is not set -# CONFIG_ZD1211RW is not set - -# -# WiMAX Wireless Broadband devices -# -# CONFIG_WIMAX_I2400M_USB is not set -# CONFIG_WIMAX_I2400M_SDIO is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -CONFIG_USB_USBNET=y -# CONFIG_USB_NET_AX8817X is not set -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_HSO is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -CONFIG_TPS65910_CORE=y -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_MFD_88PM8607 is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_DMA_SG=m -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=m -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -CONFIG_VIDEO_IR_I2C=m -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_SAA711X=m -CONFIG_VIDEO_TVP5150=m -CONFIG_VIDEO_CX25840=m -CONFIG_VIDEO_CX2341X=m -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=m -CONFIG_VIDEO_VPSS_SYSTEM=m -CONFIG_VIDEO_VPFE_CAPTURE=m -CONFIG_VIDEO_DM6446_CCDC=m -CONFIG_VIDEO_DM355_CCDC=m -CONFIG_VIDEO_OMAP2_VOUT=m -# CONFIG_VIDEO_OMAP3 is not set -# CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER is not set -# CONFIG_VIDEO_OMAP34XX_ISP_RESIZER is not set -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SN9C20X_EVDEV=y -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -# CONFIG_VIDEO_EM28XX_ALSA is not set -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -# CONFIG_VIDEO_CX231XX_ALSA is not set -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -# CONFIG_RADIO_ADAPTERS is not set -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_FRIIO=m -CONFIG_DVB_USB_EC168=m -CONFIG_SMS_SIANO_MDTV=m - -# -# Siano module components -# -# CONFIG_SMS_USB_DRV is not set -# CONFIG_SMS_SDIO_DRV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_EC100=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_LGS8GL5=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=4 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -# CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO is not set -CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE=y -# CONFIG_OMAP2_DSS_SDI is not set -# CONFIG_OMAP2_DSS_DSI is not set -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=1 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -# CONFIG_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_LOGO is not set -CONFIG_SOUND=m -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_HWDEP=m -CONFIG_SND_RAWMIDI=m -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -CONFIG_SND_DUMMY=m -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -CONFIG_SND_ARM=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_CAIAQ=m -# CONFIG_SND_USB_CAIAQ_INPUT is not set -CONFIG_SND_SOC=m -CONFIG_SND_OMAP_SOC=m -CONFIG_SND_SOC_I2C_AND_SPI=m -# CONFIG_SND_SOC_ALL_CODECS is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -# CONFIG_USB_TI_CPPI_DMA is not set -CONFIG_USB_TI_CPPI41_DMA=y -CONFIG_USB_MUSB_DEBUG=y - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TPS65910=y -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -# CONFIG_W35UND is not set -# CONFIG_ECHO is not set -# CONFIG_OTUS is not set -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -# CONFIG_RAMZSWAP is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_STRIP is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_EARLY_PRINTK is not set -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=m -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-evm/configs/stock b/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-evm/configs/stock deleted file mode 100644 index 83353e46..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-evm/configs/stock +++ /dev/null @@ -1,2151 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Wed Jul 20 08:54:46 2011 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_INTEGRITY=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_PM_SRF is not set -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -CONFIG_MACH_OMAP3517EVM=y -# CONFIG_MACH_CRANEBOARD is not set -CONFIG_PMIC_TPS65023=y -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_USER_L2_PLE is not set -# CONFIG_USER_PMON is not set -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=y -CONFIG_CAN_RAW=y -CONFIG_CAN_BCM=y - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=y -CONFIG_CAN_DEV=y -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_TI_HECC=y -# CONFIG_CAN_SJA1000 is not set - -# -# CAN USB interfaces -# -# CONFIG_CAN_EMS_USB is not set -CONFIG_CAN_DEBUG_DEVICES=y -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -CONFIG_CONNECTOR=m -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -# CONFIG_MTD_NAND_OMAP_PREFETCH is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -CONFIG_ASYNC_RAID6_TEST=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_DELAY=m -CONFIG_DM_UEVENT=y -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -CONFIG_TI_DAVINCI_EMAC=y -# CONFIG_DM9000 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y -CONFIG_WLAN=y -# CONFIG_USB_ZD1201 is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -CONFIG_USB_USBNET=y -# CONFIG_USB_NET_AX8817X is not set -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -CONFIG_KEYBOARD_TCA6416=y -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -CONFIG_TOUCHSCREEN_TSC2004=y -# CONFIG_TOUCHSCREEN_W90X900 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -CONFIG_GPIO_PCA953X=y -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TPS65910_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_MFD_88PM8607 is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -CONFIG_REGULATOR_TPS65023=y -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_MT9V011 is not set -# CONFIG_VIDEO_MT9V113 is not set -# CONFIG_VIDEO_TCM825X is not set -# CONFIG_VIDEO_MT9P012 is not set -# CONFIG_VIDEO_MT9T112 is not set -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -CONFIG_VIDEO_TVP514X=y -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=y -CONFIG_VIDEO_VPFE_CAPTURE=y -CONFIG_VIDEO_DM6446_CCDC=y -# CONFIG_VIDEO_DM355_CCDC is not set -CONFIG_VIDEO_OMAP2_VOUT=y -# CONFIG_VIDEO_OMAP3 is not set -# CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER is not set -# CONFIG_VIDEO_OMAP34XX_ISP_RESIZER is not set -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SN9C20X_EVDEV=y -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -# CONFIG_RADIO_ADAPTERS is not set -CONFIG_DVB_MAX_ADAPTERS=8 -# CONFIG_DVB_DYNAMIC_MINORS is not set -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_FRIIO=m -CONFIG_DVB_USB_EC168=m -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -# CONFIG_DVB_B2C2_FLEXCOP is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_EC100=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DAB=y -CONFIG_USB_DABUSB=m - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_UVESA is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -# CONFIG_PANEL_SHARP_LS037V7DW01 is not set -CONFIG_PANEL_SHARP_LQ043T1DG01=y -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_LOGO is not set -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -CONFIG_SND_HRTIMER=m -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_AM3517EVM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TLV320AIC23=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -# CONFIG_USB_TI_CPPI_DMA is not set -CONFIG_USB_TI_CPPI41_DMA=y -CONFIG_USB_MUSB_DEBUG=y - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_S35390A=y -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_EARLY_PRINTK is not set -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y - -# -# OCF Configuration -# -# CONFIG_OCF_OCF is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-evm/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-evm/defconfig deleted file mode 100644 index 83353e46..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/am3517-evm/defconfig +++ /dev/null @@ -1,2151 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Wed Jul 20 08:54:46 2011 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_INTEGRITY=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_PM_SRF is not set -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -CONFIG_MACH_OMAP3517EVM=y -# CONFIG_MACH_CRANEBOARD is not set -CONFIG_PMIC_TPS65023=y -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_USER_L2_PLE is not set -# CONFIG_USER_PMON is not set -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug" -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=y -CONFIG_CAN_RAW=y -CONFIG_CAN_BCM=y - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=y -CONFIG_CAN_DEV=y -CONFIG_CAN_CALC_BITTIMING=y -CONFIG_CAN_TI_HECC=y -# CONFIG_CAN_SJA1000 is not set - -# -# CAN USB interfaces -# -# CONFIG_CAN_EMS_USB is not set -CONFIG_CAN_DEBUG_DEVICES=y -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -CONFIG_CONNECTOR=m -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -# CONFIG_MTD_NAND_OMAP_PREFETCH is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -CONFIG_ASYNC_RAID6_TEST=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_DELAY=m -CONFIG_DM_UEVENT=y -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -CONFIG_TI_DAVINCI_EMAC=y -# CONFIG_DM9000 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -CONFIG_NETDEV_1000=y -CONFIG_NETDEV_10000=y -CONFIG_WLAN=y -# CONFIG_USB_ZD1201 is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -CONFIG_USB_USBNET=y -# CONFIG_USB_NET_AX8817X is not set -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -CONFIG_KEYBOARD_TCA6416=y -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -CONFIG_TOUCHSCREEN_TSC2004=y -# CONFIG_TOUCHSCREEN_W90X900 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -CONFIG_GPIO_PCA953X=y -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TPS65910_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_MFD_88PM8607 is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_LP3971 is not set -CONFIG_REGULATOR_TPS65023=y -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_MT9V011 is not set -# CONFIG_VIDEO_MT9V113 is not set -# CONFIG_VIDEO_TCM825X is not set -# CONFIG_VIDEO_MT9P012 is not set -# CONFIG_VIDEO_MT9T112 is not set -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -CONFIG_VIDEO_TVP514X=y -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=y -CONFIG_VIDEO_VPFE_CAPTURE=y -CONFIG_VIDEO_DM6446_CCDC=y -# CONFIG_VIDEO_DM355_CCDC is not set -CONFIG_VIDEO_OMAP2_VOUT=y -# CONFIG_VIDEO_OMAP3 is not set -# CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER is not set -# CONFIG_VIDEO_OMAP34XX_ISP_RESIZER is not set -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SN9C20X_EVDEV=y -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -# CONFIG_RADIO_ADAPTERS is not set -CONFIG_DVB_MAX_ADAPTERS=8 -# CONFIG_DVB_DYNAMIC_MINORS is not set -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_FRIIO=m -CONFIG_DVB_USB_EC168=m -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -# CONFIG_DVB_B2C2_FLEXCOP is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_EC100=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DAB=y -CONFIG_USB_DABUSB=m - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_UVESA is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -# CONFIG_PANEL_SHARP_LS037V7DW01 is not set -CONFIG_PANEL_SHARP_LQ043T1DG01=y -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_LOGO is not set -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -CONFIG_SND_HRTIMER=m -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_AM3517EVM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TLV320AIC23=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -# CONFIG_USB_TI_CPPI_DMA is not set -CONFIG_USB_TI_CPPI41_DMA=y -CONFIG_USB_MUSB_DEBUG=y - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_S35390A=y -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_EARLY_PRINTK is not set -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y - -# -# OCF Configuration -# -# CONFIG_OCF_OCF is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/am37x-evm/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/am37x-evm/defconfig deleted file mode 100644 index 25781167..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/am37x-evm/defconfig +++ /dev/null @@ -1,2045 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Fri Jul 9 10:08:46 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=m -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_LL_DEBUG_UART1=y -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -# CONFIG_OMAP_LL_DEBUG_UART3 is not set -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_PM_SRF is not set -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -CONFIG_MACH_OMAP3EVM=y -CONFIG_PMIC_TWL4030=y -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_USER_L2_PLE is not set -# CONFIG_USER_PMON is not set -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_OMAP_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -# CONFIG_MTD_NAND_OMAP_PREFETCH is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -# CONFIG_MTD_ONENAND_GENERIC is not set -CONFIG_MTD_ONENAND_OMAP2=y -# CONFIG_MTD_ONENAND_OTP is not set -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -# CONFIG_MTD_ONENAND_SIM is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_USB_ZD1201 is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -CONFIG_USB_USBNET=y -# CONFIG_USB_NET_AX8817X is not set -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set -CONFIG_TWL4030_CODEC=y -# CONFIG_TWL4030_MADC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_MSP3400 is not set -# CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_WM8775 is not set -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_MT9V011 is not set -# CONFIG_VIDEO_TCM825X is not set -# CONFIG_VIDEO_MT9P012 is not set -# CONFIG_VIDEO_MT9T111 is not set -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -CONFIG_VIDEO_TVP514X=y -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -# CONFIG_VIDEO_CX25840 is not set - -# -# MPEG video encoders -# -# CONFIG_VIDEO_CX2341X is not set - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -CONFIG_TI_MEDIA=y -# CONFIG_VIDEO_VPSS_SYSTEM is not set -# CONFIG_VIDEO_VPFE_CAPTURE is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -# CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER is not set -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=y -# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set -# CONFIG_USB_GSPCA is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -# CONFIG_USB_PWC_INPUT_EVDEV is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=4 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=1 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_LOGO is not set -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -# CONFIG_SND_USB_CAIAQ is not set -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3EVM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -CONFIG_USB_MUSB_DEBUG=y - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -# CONFIG_TWL4030_USB is not set -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_EARLY_PRINTK is not set -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# OCF Configuration -# -CONFIG_OCF_OCF=y -CONFIG_OCF_RANDOMHARVEST=y -CONFIG_OCF_FIPS=y -CONFIG_OCF_CRYPTODEV=m -CONFIG_OCF_CRYPTOSOFT=m -# CONFIG_OCF_SAFE is not set -# CONFIG_OCF_IXP4XX is not set -# CONFIG_OCF_HIFN is not set -# CONFIG_OCF_HIFNHIPP is not set -# CONFIG_OCF_TALITOS is not set -# CONFIG_OCF_EP80579 is not set -# CONFIG_OCF_CRYPTOCTEON is not set -# CONFIG_OCF_KIRKWOOD is not set -# CONFIG_OCF_C7108 is not set -# CONFIG_OCF_OCFNULL is not set -# CONFIG_OCF_BENCH is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0001-omap-Beagle-revision-detection.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0001-omap-Beagle-revision-detection.patch deleted file mode 100644 index f29c9a6d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0001-omap-Beagle-revision-detection.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 325afc09116e11e28265b648ef33d8c0306c61f1 Mon Sep 17 00:00:00 2001 -From: Robert Nelson -Date: Thu, 23 Sep 2010 18:22:47 -0700 -Subject: [PATCH 01/10] omap: Beagle: revision detection - -Due to the omap3530 ES3.0 Silicon being used on both the -B5/B6 and C1/2/3 Beagle we can't use the cpu_is_omap34xx() -routines to differentiate the Beagle Boards. - -However gpio pins 171,172,173 where setup for this prupose, so -lets use them. - -Changes: -for older U-Boot's, use omap_mux_init_gpio() -keep Beagle Rev in board-omap3beagle.c -gpio_free on gpio request failure - -Tested on Beagle Revisions: B5, C2, C4, and xMA - -Signed-off-by: Robert Nelson -Acked-by: Jarkko Nikula -Signed-off-by: Tony Lindgren ---- - arch/arm/mach-omap2/board-omap3beagle.c | 88 +++++++++++++++++++++++++++++++ - 1 files changed, 88 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 2677b41..7ca2b3b 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -175,6 +175,93 @@ static void __init omap3beagle_ks8851_init(void) - static inline void __init omap3beagle_ks8851_init(void) { return; } - #endif - -+/* -+ * OMAP3 Beagle revision -+ * Run time detection of Beagle revision is done by reading GPIO. -+ * GPIO ID - -+ * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1 -+ * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0 -+ * C4 = GPIO173, GPIO172, GPIO171: 1 0 1 -+ * XM = GPIO173, GPIO172, GPIO171: 0 0 0 -+ */ -+enum { -+ OMAP3BEAGLE_BOARD_UNKN = 0, -+ OMAP3BEAGLE_BOARD_AXBX, -+ OMAP3BEAGLE_BOARD_C1_3, -+ OMAP3BEAGLE_BOARD_C4, -+ OMAP3BEAGLE_BOARD_XM, -+}; -+ -+static u8 omap3_beagle_version; -+ -+static u8 omap3_beagle_get_rev(void) -+{ -+ return omap3_beagle_version; -+} -+ -+static void __init omap3_beagle_init_rev(void) -+{ -+ int ret; -+ u16 beagle_rev = 0; -+ -+ omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP); -+ -+ ret = gpio_request(171, "rev_id_0"); -+ if (ret < 0) -+ goto fail0; -+ -+ ret = gpio_request(172, "rev_id_1"); -+ if (ret < 0) -+ goto fail1; -+ -+ ret = gpio_request(173, "rev_id_2"); -+ if (ret < 0) -+ goto fail2; -+ -+ gpio_direction_input(171); -+ gpio_direction_input(172); -+ gpio_direction_input(173); -+ -+ beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1) -+ | (gpio_get_value(173) << 2); -+ -+ switch (beagle_rev) { -+ case 7: -+ printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX; -+ break; -+ case 6: -+ printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3; -+ break; -+ case 5: -+ printk(KERN_INFO "OMAP3 Beagle Rev: C4\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; -+ break; -+ case 0: -+ printk(KERN_INFO "OMAP3 Beagle Rev: xM\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; -+ break; -+ default: -+ printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; -+ } -+ -+ return; -+ -+fail2: -+ gpio_free(172); -+fail1: -+ gpio_free(171); -+fail0: -+ printk(KERN_ERR "Unable to get revision detection GPIO pins\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; -+ -+ return; -+} -+ - static struct mtd_partition omap3beagle_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { -@@ -853,6 +940,7 @@ static int __init cameraboard_setup(char *str) - static void __init omap3_beagle_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ omap3_beagle_init_rev(); - omap3_beagle_i2c_init(); - - if (cpu_is_omap3630()) { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0002-omap-Beagle-only-Cx-boards-use-pin-23-for-write-prot.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0002-omap-Beagle-only-Cx-boards-use-pin-23-for-write-prot.patch deleted file mode 100644 index f8512867..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0002-omap-Beagle-only-Cx-boards-use-pin-23-for-write-prot.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 34d88746a9aa4aedb67e32579e559cbeb91de20f Mon Sep 17 00:00:00 2001 -From: Robert Nelson -Date: Thu, 23 Sep 2010 18:22:48 -0700 -Subject: [PATCH 02/10] omap: Beagle: only Cx boards use pin 23 for write protect - -system_rev comes from u-boot and is a constant 0x20, so -Bx boards also fall in this 'if' and will get setup with the -wrong gpio_wp pin. Switch to using the Beagle revision routine -to correcly set pin 23 only for C1/2/3 and C4 Boards. Bx boards -will then use the correct default pin setting. - -Signed-off-by: Robert Nelson -Acked-by: Jarkko Nikula -Signed-off-by: Tony Lindgren ---- - arch/arm/mach-omap2/board-omap3beagle.c | 3 ++- - 1 files changed, 2 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 7ca2b3b..beb877c 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -444,7 +444,8 @@ static struct gpio_led gpio_leds[]; - static int beagle_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) - { -- if (system_rev >= 0x20 && system_rev <= 0x34301000) { -+ if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || -+ (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { - omap_mux_init_gpio(23, OMAP_PIN_INPUT); - mmc[0].gpio_wp = 23; - } else { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0003-omap-Beagle-no-gpio_wp-pin-connection-on-xM.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0003-omap-Beagle-no-gpio_wp-pin-connection-on-xM.patch deleted file mode 100644 index d7d3fefe..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0003-omap-Beagle-no-gpio_wp-pin-connection-on-xM.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 037ef3add42d61dcd86438dc4b9378f154caa426 Mon Sep 17 00:00:00 2001 -From: Robert Nelson -Date: Thu, 23 Sep 2010 18:22:48 -0700 -Subject: [PATCH 03/10] omap: Beagle: no gpio_wp pin connection on xM - -The omap3630 based BeagleBoard xM uses a MicroSD card slot with -no write protection. - -Signed-off-by: Robert Nelson -Acked-by: Jarkko Nikula -Signed-off-by: Tony Lindgren ---- - arch/arm/mach-omap2/board-omap3beagle.c | 4 +++- - 1 files changed, 3 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index beb877c..247a426 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -444,7 +444,9 @@ static struct gpio_led gpio_leds[]; - static int beagle_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) - { -- if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || -+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { -+ mmc[0].gpio_wp = -EINVAL; -+ } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || - (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { - omap_mux_init_gpio(23, OMAP_PIN_INPUT); - mmc[0].gpio_wp = 23; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0004-omap3-beaglexm-fix-EHCI-power-up-GPIO-dir.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0004-omap3-beaglexm-fix-EHCI-power-up-GPIO-dir.patch deleted file mode 100644 index e646d3eb..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0004-omap3-beaglexm-fix-EHCI-power-up-GPIO-dir.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 62db06de896c221cfa2231a53a933d6b3e81d66d Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Tue, 11 Jan 2011 17:13:35 +0000 -Subject: [PATCH 04/10] omap3: beaglexm: fix EHCI power up GPIO dir - -EHCI enable power pin is inverted (active high) in comparison -to vanilla beagle which is active low. Handle this case conditionally. - -Without this fix, Beagle XM 4 port EHCI will not function and no -networking will be available - -[nm@ti.com: split up, added descriptive changelogs] -Signed-off-by: Nishanth Menon -Signed-off-by: Koen Kooi -Signed-off-by: Tony Lindgren ---- - arch/arm/mach-omap2/board-omap3beagle.c | 9 +++++++++ - 1 files changed, 9 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 247a426..7cfa2c8 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -487,6 +487,15 @@ static int beagle_twl_gpio_setup(struct device *dev, - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - } - -+ /* -+ * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active -+ * high / others active low) -+ */ -+ gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) -+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); -+ else -+ gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0005-omap3-beaglexm-fix-DVI-reset-GPIO.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0005-omap3-beaglexm-fix-DVI-reset-GPIO.patch deleted file mode 100644 index 6e6ab41b..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0005-omap3-beaglexm-fix-DVI-reset-GPIO.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 3d93d0b8974c867db70cb4a8681615113ac6113d Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Tue, 11 Jan 2011 17:13:36 +0000 -Subject: [PATCH 05/10] omap3: beaglexm: fix DVI reset GPIO - -GPIO reset line for Beagle XM is different from vanilla beagle -so we populate it as part of gpio update routine. - -This in part fixes the issue of display not functioning on beagle XM -platform. - -[nm@ti.com: split up, added descriptive changelogs] -Signed-off-by: Nishanth Menon -Signed-off-by: Koen Kooi -Signed-off-by: Tony Lindgren ---- - arch/arm/mach-omap2/board-omap3beagle.c | 8 +++++++- - 1 files changed, 7 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 7cfa2c8..939de5a 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -336,7 +336,7 @@ static struct omap_dss_device beagle_dvi_device = { - .name = "dvi", - .driver_name = "generic_panel", - .phy.dpi.data_lines = 24, -- .reset_gpio = 170, -+ .reset_gpio = -EINVAL, - .platform_enable = beagle_enable_dvi, - .platform_disable = beagle_disable_dvi, - }; -@@ -497,6 +497,12 @@ static int beagle_twl_gpio_setup(struct device *dev, - else - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - -+ /* DVI reset GPIO is different between beagle revisions */ -+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) -+ beagle_dvi_device.reset_gpio = 129; -+ else -+ beagle_dvi_device.reset_gpio = 170; -+ - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0006-omap3-beaglexm-fix-power-on-of-DVI.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0006-omap3-beaglexm-fix-power-on-of-DVI.patch deleted file mode 100644 index ba74284b..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0006-omap3-beaglexm-fix-power-on-of-DVI.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 7ad849e3d54d897614a74ad225392bd243e07d2e Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Wed, 12 Jan 2011 00:23:29 +0000 -Subject: [PATCH 06/10] omap3: beaglexm: fix power on of DVI - -TFP410 DVI chip is used to provide display out. -This chip is controlled by 2 lines: -LDO which supplies the power is controlled over gpio + 2 -and the enable of the chip itself is done over gpio + 1 -NOTE: the LDO is necessary for LED, serial blocks as well. - -gpio + 1 was used to sense USB overcurrent in vanilla beagle. - -Without this fix, the display would not function as the LDO -remains shut down. - -[nm@ti.com: split up, added descriptive changelogs] -Signed-off-by: Nishanth Menon -Signed-off-by: Koen Kooi -Signed-off-by: Tony Lindgren ---- - arch/arm/mach-omap2/board-omap3beagle.c | 40 +++++++++++++++++++++++++++++++ - 1 files changed, 40 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 939de5a..9880c5c 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -444,6 +444,8 @@ static struct gpio_led gpio_leds[]; - static int beagle_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) - { -+ int r; -+ - if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { - mmc[0].gpio_wp = -EINVAL; - } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || -@@ -465,6 +467,17 @@ static int beagle_twl_gpio_setup(struct device *dev, - * power switch and overcurrent detect - */ - -+ if (omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XM) { -+ r = gpio_request(gpio + 1, "EHCI_nOC"); -+ if (!r) { -+ r = gpio_direction_input(gpio + 1); -+ if (r) -+ gpio_free(gpio + 1); -+ } -+ if (r) -+ pr_err("%s: unable to configure EHCI_nOC\n", __func__); -+ } -+ - if (cpu_is_omap3630()) { - /* Power on DVI, Serial and PWR led */ - gpio_request(gpio + 1, "nDVI_PWR_EN"); -@@ -506,6 +519,33 @@ static int beagle_twl_gpio_setup(struct device *dev, - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; - -+ /* -+ * gpio + 1 on Xm controls the TFP410's enable line (active low) -+ * gpio + 2 control varies depending on the board rev as follows: -+ * P7/P8 revisions(prototype): Camera EN -+ * A2+ revisions (production): LDO (supplies DVI, serial, led blocks) -+ */ -+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { -+ r = gpio_request(gpio + 1, "nDVI_PWR_EN"); -+ if (!r) { -+ r = gpio_direction_output(gpio + 1, 0); -+ if (r) -+ gpio_free(gpio + 1); -+ } -+ if (r) -+ pr_err("%s: unable to configure nDVI_PWR_EN\n", -+ __func__); -+ r = gpio_request(gpio + 2, "DVI_LDO_EN"); -+ if (!r) { -+ r = gpio_direction_output(gpio + 2, 1); -+ if (r) -+ gpio_free(gpio + 2); -+ } -+ if (r) -+ pr_err("%s: unable to configure DVI_LDO_EN\n", -+ __func__); -+ } -+ - return 0; - } - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0007-beagleboard-hack-in-support-from-xM-rev-C.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0007-beagleboard-hack-in-support-from-xM-rev-C.patch deleted file mode 100644 index 0181f152..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0007-beagleboard-hack-in-support-from-xM-rev-C.patch +++ /dev/null @@ -1,61 +0,0 @@ -From b241e679f550f38062923eb7800a5c57a41fe95d Mon Sep 17 00:00:00 2001 -From: Jason Kridner -Date: Thu, 10 Mar 2011 13:15:38 +0100 -Subject: [PATCH 07/10] beagleboard: hack in support from xM rev C - -Based on patch by Koen Kooi ---- - arch/arm/mach-omap2/board-omap3beagle.c | 20 ++++++++++++++++---- - 1 files changed, 16 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 9880c5c..4bde54b 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -182,7 +182,9 @@ static inline void __init omap3beagle_ks8851_init(void) { return; } - * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1 - * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0 - * C4 = GPIO173, GPIO172, GPIO171: 1 0 1 -- * XM = GPIO173, GPIO172, GPIO171: 0 0 0 -+ * XMA = GPIO173, GPIO172, GPIO171: 0 0 0 -+ * XMB = GPIO173, GPIO172, GPIO171: 0 0 1 -+ * XMC = GPIO173, GPIO172, GPIO171: 0 1 0 - */ - enum { - OMAP3BEAGLE_BOARD_UNKN = 0, -@@ -190,6 +192,7 @@ enum { - OMAP3BEAGLE_BOARD_C1_3, - OMAP3BEAGLE_BOARD_C4, - OMAP3BEAGLE_BOARD_XM, -+ OMAP3BEAGLE_BOARD_XMC, - }; - - static u8 omap3_beagle_version; -@@ -241,12 +244,21 @@ static void __init omap3_beagle_init_rev(void) - omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; - break; - case 0: -- printk(KERN_INFO "OMAP3 Beagle Rev: xM\n"); -+ printk(KERN_INFO "OMAP3 Beagle Rev: xM A\n"); - omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; - break; -+ case 1: -+ printk(KERN_INFO "OMAP3 Beagle Rev: xM B\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; -+ break; -+ case 2: -+ printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n"); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC; -+ break; - default: -- printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); -- omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; -+ printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd, " -+ "assuming xM C or newer\n", beagle_rev); -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC; - } - - return; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0008-omap3-beagle-cleaned-up-board-revision-conditions.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0008-omap3-beagle-cleaned-up-board-revision-conditions.patch deleted file mode 100644 index 513a1019..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard-xmc/0008-omap3-beagle-cleaned-up-board-revision-conditions.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 8bd3ffb5755c49aaffecb20b9bd43f955ac26251 Mon Sep 17 00:00:00 2001 -From: Jason Kridner -Date: Wed, 16 Mar 2011 09:21:06 -0500 -Subject: [PATCH 08/10] omap3: beagle: cleaned up board revision conditions - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 70 ++++++++++++++----------------- - 1 files changed, 32 insertions(+), 38 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 4bde54b..664a9c6 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -191,7 +191,7 @@ enum { - OMAP3BEAGLE_BOARD_AXBX, - OMAP3BEAGLE_BOARD_C1_3, - OMAP3BEAGLE_BOARD_C4, -- OMAP3BEAGLE_BOARD_XM, -+ OMAP3BEAGLE_BOARD_XMAB, - OMAP3BEAGLE_BOARD_XMC, - }; - -@@ -245,11 +245,11 @@ static void __init omap3_beagle_init_rev(void) - break; - case 0: - printk(KERN_INFO "OMAP3 Beagle Rev: xM A\n"); -- omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XMAB; - break; - case 1: - printk(KERN_INFO "OMAP3 Beagle Rev: xM B\n"); -- omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; -+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XMAB; - break; - case 2: - printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n"); -@@ -458,13 +458,18 @@ static int beagle_twl_gpio_setup(struct device *dev, - { - int r; - -- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { -+ switch(omap3_beagle_get_rev()) -+ { -+ case OMAP3BEAGLE_BOARD_XMAB: -+ case OMAP3BEAGLE_BOARD_XMC: - mmc[0].gpio_wp = -EINVAL; -- } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || -- (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { -+ break; -+ case OMAP3BEAGLE_BOARD_C1_3: -+ case OMAP3BEAGLE_BOARD_C4: - omap_mux_init_gpio(23, OMAP_PIN_INPUT); - mmc[0].gpio_wp = 23; -- } else { -+ break; -+ default: - omap_mux_init_gpio(29, OMAP_PIN_INPUT); - } - /* gpio + 0 is "mmc0_cd" (input/IRQ) */ -@@ -479,7 +484,8 @@ static int beagle_twl_gpio_setup(struct device *dev, - * power switch and overcurrent detect - */ - -- if (omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XM) { -+ if ((omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XMAB) && -+ (omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XMC)) { - r = gpio_request(gpio + 1, "EHCI_nOC"); - if (!r) { - r = gpio_direction_input(gpio + 1); -@@ -490,54 +496,41 @@ static int beagle_twl_gpio_setup(struct device *dev, - pr_err("%s: unable to configure EHCI_nOC\n", __func__); - } - -- if (cpu_is_omap3630()) { -- /* Power on DVI, Serial and PWR led */ -- gpio_request(gpio + 1, "nDVI_PWR_EN"); -- gpio_direction_output(gpio + 1, 0); -- -- /* Power on camera interface */ -- gpio_request(gpio + 2, "CAM_EN"); -- gpio_direction_output(gpio + 2, 1); -- -- /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ -- gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); -- } -- else { -- gpio_request(gpio + 1, "EHCI_nOC"); -- gpio_direction_input(gpio + 1); -- -- /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ -- gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); -- } -- - /* -- * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active -+ * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, xM Ax/Bx active - * high / others active low) - */ - gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); -- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) -+ if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XMAB) - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); - else - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); - - /* DVI reset GPIO is different between beagle revisions */ -- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) -- beagle_dvi_device.reset_gpio = 129; -- else -+ switch(omap3_beagle_get_rev()) -+ { -+ case OMAP3BEAGLE_BOARD_AXBX: -+ case OMAP3BEAGLE_BOARD_C1_3: -+ case OMAP3BEAGLE_BOARD_C4: - beagle_dvi_device.reset_gpio = 170; -+ break; -+ case OMAP3BEAGLE_BOARD_XMAB: -+ case OMAP3BEAGLE_BOARD_XMC: -+ default: -+ beagle_dvi_device.reset_gpio = 129; -+ } - - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; - - /* -- * gpio + 1 on Xm controls the TFP410's enable line (active low) -+ * gpio + 1 on xM controls the TFP410's enable line (active low) - * gpio + 2 control varies depending on the board rev as follows: - * P7/P8 revisions(prototype): Camera EN - * A2+ revisions (production): LDO (supplies DVI, serial, led blocks) - */ -- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { -+ if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XMAB) || -+ (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XMC)) { - r = gpio_request(gpio + 1, "nDVI_PWR_EN"); - if (!r) { - r = gpio_direction_output(gpio + 1, 0); -@@ -1013,7 +1006,8 @@ static void __init omap3_beagle_init(void) - omap3_beagle_init_rev(); - omap3_beagle_i2c_init(); - -- if (cpu_is_omap3630()) { -+ if ((omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XMAB) && -+ (omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XMC)) { - gpio_buttons[0].gpio = 4; - } - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/configs/cpuidle b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/configs/cpuidle deleted file mode 100644 index 06e3879b..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/configs/cpuidle +++ /dev/null @@ -1,3053 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Thu Jul 22 14:16:08 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_SLOW_WORK_DEBUG is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_UNLOCK is not set -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_UNLOCK is not set -# CONFIG_INLINE_READ_UNLOCK_BH is not set -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_UNLOCK is not set -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MBOX_FWK=m -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -# CONFIG_OMAP_PM_NOOP is not set -CONFIG_OMAP_PM_SRF=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -CONFIG_MACH_OMAP3_BEAGLE=y -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_USER_L2_PLE=y -CONFIG_USER_PMON=y -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -CONFIG_CPU_FREQ_DEBUG=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -CONFIG_PM_RUNTIME=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -# CONFIG_DEFAULT_BIC is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -# CONFIG_IPV6_PIMSM_V2 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=m -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -# CONFIG_NETFILTER_TPROXY is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=m -# CONFIG_NETFILTER_XT_TARGET_LED is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_DCCP=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_UDPLITE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=y - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_RDS is not set -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_BRIDGE=m -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_IND=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -CONFIG_IRDA_ULTRA=y - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -CONFIG_IRDA_DEBUG=y - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -CONFIG_DONGLE=y -CONFIG_ESI_DONGLE=m -CONFIG_ACTISYS_DONGLE=m -CONFIG_TEKRAM_DONGLE=m -CONFIG_TOIM3232_DONGLE=m -CONFIG_LITELINK_DONGLE=m -CONFIG_MA600_DONGLE=m -CONFIG_GIRBIL_DONGLE=m -CONFIG_MCP2120_DONGLE=m -CONFIG_OLD_BELKIN_DONGLE=m -# CONFIG_ACT200L_DONGLE is not set -CONFIG_KINGSUN_DONGLE=m -CONFIG_KSDAZZLE_DONGLE=m -CONFIG_KS959_DONGLE=m - -# -# FIR device drivers -# -CONFIG_USB_IRDA=m -CONFIG_SIGMATEL_FIR=m -CONFIG_MCS_FIR=m -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_NET_9P=m -# CONFIG_NET_9P_DEBUG is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_AD525X_DPOT is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -# CONFIG_ISL29003 is not set -# CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -CONFIG_EEPROM_AT24=m -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y -CONFIG_IWMC3200TOP=m -# CONFIG_IWMC3200TOP_DEBUG is not set -# CONFIG_IWMC3200TOP_DEBUGFS is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -# CONFIG_DM_UEVENT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -CONFIG_ENC28J60=y -# CONFIG_ENC28J60_WRITEVERIFY is not set -# CONFIG_ETHOC is not set -CONFIG_SMC911X=y -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -CONFIG_KS8851=y -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -CONFIG_AT76C50X_USB=m -CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -CONFIG_B43=m -# CONFIG_B43_SDIO is not set -CONFIG_B43_PHY_LP=y -CONFIG_B43_LEDS=y -CONFIG_B43_HWRNG=y -# CONFIG_B43_DEBUG is not set -# CONFIG_B43LEGACY is not set -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -# CONFIG_IWM is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -# CONFIG_LIBERTAS_SDIO is not set -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_SPI is not set -CONFIG_P54_LEDS=y -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -# CONFIG_RT2800USB is not set -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -CONFIG_WL12XX=m -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL1271=m -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# WiMAX Wireless Broadband devices -# -CONFIG_WIMAX_I2400M=m -CONFIG_WIMAX_I2400M_USB=m -CONFIG_WIMAX_I2400M_SDIO=m -CONFIG_WIMAX_IWMC3200_SDIO=y -CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 - -# -# USB Network Adapters -# -CONFIG_USB_CATC=y -CONFIG_USB_KAWETH=y -CONFIG_USB_PEGASUS=y -CONFIG_USB_RTL8150=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -CONFIG_USB_NET_SMSC95XX=y -CONFIG_USB_NET_GL620A=y -CONFIG_USB_NET_NET1080=y -CONFIG_USB_NET_PLUSB=y -CONFIG_USB_NET_MCS7830=y -CONFIG_USB_NET_RNDIS_HOST=y -CONFIG_USB_NET_CDC_SUBSET=y -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=y -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -# CONFIG_WAN is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOATM is not set -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=m -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -CONFIG_SSB=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -# CONFIG_SSB_SDIOHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_CODEC=y -# CONFIG_TWL4030_MADC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_CUSTOMISE=y -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_MT9V113=m -# CONFIG_VIDEO_TCM825X is not set -CONFIG_VIDEO_MT9P012=m -CONFIG_VIDEO_MT9T112=m -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -# CONFIG_VIDEO_TVP514X is not set -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=y -CONFIG_VIDEO_VPFE_CAPTURE=y -# CONFIG_VIDEO_DM6446_CCDC is not set -# CONFIG_VIDEO_DM355_CCDC is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -# CONFIG_USB_GL860 is not set -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -# CONFIG_USB_GSPCA_JEILINJ is not set -CONFIG_USB_GSPCA_MARS=m -# CONFIG_USB_GSPCA_MR97310A is not set -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -# CONFIG_USB_GSPCA_PAC7302 is not set -CONFIG_USB_GSPCA_PAC7311=m -# CONFIG_USB_GSPCA_SN9C20X is not set -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -CONFIG_USB_GSPCA_STK014=m -# CONFIG_USB_GSPCA_STV0680 is not set -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -# CONFIG_VIDEO_CX231XX_ALSA is not set -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_TEF6862 is not set -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -# CONFIG_DVB_USB_CE6230 is not set -# CONFIG_DVB_USB_FRIIO is not set -# CONFIG_DVB_USB_EC168 is not set -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_LGS8GL5=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -CONFIG_HID_TOPSEED=y -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_U132_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -# CONFIG_USB_SERIAL_CP210X is not set -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m -CONFIG_USB_LED=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=m -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_VST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=480 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -CONFIG_USB_ZERO_HNPTEST=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -# CONFIG_USB_MASS_STORAGE is not set -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_GPIO_VBUS=y -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_TWL4030_USB=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_UNSAFE_RESUME=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=m - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=m -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=m -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -CONFIG_W35UND=m -# CONFIG_PRISM2_USB is not set -CONFIG_ECHO=m -CONFIG_OTUS=m -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -CONFIG_RTL8192SU=m -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -# CONFIG_RAMZSWAP is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_STRIP is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_JFS_FS=m -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=m -# CONFIG_GFS2_FS_LOCKING_DLM is not set -CONFIG_OCFS2_FS=m -CONFIG_OCFS2_FS_O2CB=m -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -# CONFIG_OCFS2_DEBUG_FS is not set -# CONFIG_OCFS2_FS_POSIX_ACL is not set -CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -# CONFIG_CUSE is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=m -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -# CONFIG_ECRYPT_FS is not set -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DFS_UPCALL is not set -CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_NCP_FS=m -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_9P_FS=m - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/configs/cpuidle-gether b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/configs/cpuidle-gether deleted file mode 100644 index 7261927e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/configs/cpuidle-gether +++ /dev/null @@ -1,3051 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Mon Jul 26 11:37:13 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_SLOW_WORK_DEBUG is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_UNLOCK is not set -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_UNLOCK is not set -# CONFIG_INLINE_READ_UNLOCK_BH is not set -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_UNLOCK is not set -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MBOX_FWK=m -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -# CONFIG_OMAP_PM_NOOP is not set -CONFIG_OMAP_PM_SRF=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -CONFIG_MACH_OMAP3_BEAGLE=y -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_USER_L2_PLE=y -CONFIG_USER_PMON=y -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -CONFIG_CPU_FREQ_DEBUG=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -CONFIG_PM_RUNTIME=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -# CONFIG_DEFAULT_BIC is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -# CONFIG_IPV6_PIMSM_V2 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=m -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -# CONFIG_NETFILTER_TPROXY is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=m -# CONFIG_NETFILTER_XT_TARGET_LED is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_DCCP=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_UDPLITE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=y - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_RDS is not set -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_BRIDGE=m -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_IND=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -CONFIG_IRDA_ULTRA=y - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -CONFIG_IRDA_DEBUG=y - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -CONFIG_DONGLE=y -CONFIG_ESI_DONGLE=m -CONFIG_ACTISYS_DONGLE=m -CONFIG_TEKRAM_DONGLE=m -CONFIG_TOIM3232_DONGLE=m -CONFIG_LITELINK_DONGLE=m -CONFIG_MA600_DONGLE=m -CONFIG_GIRBIL_DONGLE=m -CONFIG_MCP2120_DONGLE=m -CONFIG_OLD_BELKIN_DONGLE=m -# CONFIG_ACT200L_DONGLE is not set -CONFIG_KINGSUN_DONGLE=m -CONFIG_KSDAZZLE_DONGLE=m -CONFIG_KS959_DONGLE=m - -# -# FIR device drivers -# -CONFIG_USB_IRDA=m -CONFIG_SIGMATEL_FIR=m -CONFIG_MCS_FIR=m -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_NET_9P=m -# CONFIG_NET_9P_DEBUG is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_AD525X_DPOT is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -# CONFIG_ISL29003 is not set -# CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -CONFIG_EEPROM_AT24=m -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y -CONFIG_IWMC3200TOP=m -# CONFIG_IWMC3200TOP_DEBUG is not set -# CONFIG_IWMC3200TOP_DEBUGFS is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -# CONFIG_DM_UEVENT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -CONFIG_ENC28J60=y -# CONFIG_ENC28J60_WRITEVERIFY is not set -# CONFIG_ETHOC is not set -CONFIG_SMC911X=y -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -CONFIG_KS8851=y -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -CONFIG_AT76C50X_USB=m -CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -CONFIG_B43=m -# CONFIG_B43_SDIO is not set -CONFIG_B43_PHY_LP=y -CONFIG_B43_LEDS=y -CONFIG_B43_HWRNG=y -# CONFIG_B43_DEBUG is not set -# CONFIG_B43LEGACY is not set -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -# CONFIG_IWM is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -# CONFIG_LIBERTAS_SDIO is not set -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_SPI is not set -CONFIG_P54_LEDS=y -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -# CONFIG_RT2800USB is not set -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -CONFIG_WL12XX=m -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL1271=m -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# WiMAX Wireless Broadband devices -# -CONFIG_WIMAX_I2400M=m -CONFIG_WIMAX_I2400M_USB=m -CONFIG_WIMAX_I2400M_SDIO=m -CONFIG_WIMAX_IWMC3200_SDIO=y -CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 - -# -# USB Network Adapters -# -CONFIG_USB_CATC=y -CONFIG_USB_KAWETH=y -CONFIG_USB_PEGASUS=y -CONFIG_USB_RTL8150=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -CONFIG_USB_NET_SMSC95XX=y -CONFIG_USB_NET_GL620A=y -CONFIG_USB_NET_NET1080=y -CONFIG_USB_NET_PLUSB=y -CONFIG_USB_NET_MCS7830=y -CONFIG_USB_NET_RNDIS_HOST=y -CONFIG_USB_NET_CDC_SUBSET=y -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=y -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -# CONFIG_WAN is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOATM is not set -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=m -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -CONFIG_SSB=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -# CONFIG_SSB_SDIOHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_CODEC=y -# CONFIG_TWL4030_MADC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_CUSTOMISE=y -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_MT9V113=m -# CONFIG_VIDEO_TCM825X is not set -CONFIG_VIDEO_MT9P012=m -CONFIG_VIDEO_MT9T112=m -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -# CONFIG_VIDEO_TVP514X is not set -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=y -CONFIG_VIDEO_VPFE_CAPTURE=y -# CONFIG_VIDEO_DM6446_CCDC is not set -# CONFIG_VIDEO_DM355_CCDC is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -# CONFIG_USB_GL860 is not set -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -# CONFIG_USB_GSPCA_JEILINJ is not set -CONFIG_USB_GSPCA_MARS=m -# CONFIG_USB_GSPCA_MR97310A is not set -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -# CONFIG_USB_GSPCA_PAC7302 is not set -CONFIG_USB_GSPCA_PAC7311=m -# CONFIG_USB_GSPCA_SN9C20X is not set -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -CONFIG_USB_GSPCA_STK014=m -# CONFIG_USB_GSPCA_STV0680 is not set -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -# CONFIG_VIDEO_CX231XX_ALSA is not set -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_TEF6862 is not set -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -# CONFIG_DVB_USB_CE6230 is not set -# CONFIG_DVB_USB_FRIIO is not set -# CONFIG_DVB_USB_EC168 is not set -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_LGS8GL5=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -CONFIG_HID_TOPSEED=y -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_U132_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -# CONFIG_USB_SERIAL_CP210X is not set -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m -CONFIG_USB_LED=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=m -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_VST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=480 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_GPIO_VBUS=y -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_TWL4030_USB=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_UNSAFE_RESUME=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=m - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=m -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=m -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -CONFIG_W35UND=m -# CONFIG_PRISM2_USB is not set -CONFIG_ECHO=m -CONFIG_OTUS=m -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -CONFIG_RTL8192SU=m -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -# CONFIG_RAMZSWAP is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_STRIP is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_JFS_FS=m -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=m -# CONFIG_GFS2_FS_LOCKING_DLM is not set -CONFIG_OCFS2_FS=m -CONFIG_OCFS2_FS_O2CB=m -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -# CONFIG_OCFS2_DEBUG_FS is not set -# CONFIG_OCFS2_FS_POSIX_ACL is not set -CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -# CONFIG_CUSE is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=m -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -# CONFIG_ECRYPT_FS is not set -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DFS_UPCALL is not set -CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_NCP_FS=m -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_9P_FS=m - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/defconfig deleted file mode 100644 index 2abbd1a7..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/defconfig +++ /dev/null @@ -1,3071 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Sun May 1 17:33:44 2011 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_SLOW_WORK_DEBUG is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_UNLOCK is not set -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_UNLOCK is not set -# CONFIG_INLINE_READ_UNLOCK_BH is not set -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_UNLOCK is not set -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MBOX_FWK=m -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -# CONFIG_OMAP_PM_NOOP is not set -CONFIG_OMAP_PM_SRF=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -CONFIG_MACH_OMAP3_BEAGLE=y -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_CRANEBOARD is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_USER_L2_PLE=y -CONFIG_USER_PMON=y -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -CONFIG_CPU_FREQ_DEBUG=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -CONFIG_PM_RUNTIME=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -# CONFIG_DEFAULT_BIC is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -# CONFIG_IPV6_PIMSM_V2 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=m -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -# CONFIG_NETFILTER_TPROXY is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=m -# CONFIG_NETFILTER_XT_TARGET_LED is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_DCCP=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_UDPLITE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=y - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_RDS is not set -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_BRIDGE=m -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_IND=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -CONFIG_IRDA_ULTRA=y - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -CONFIG_IRDA_DEBUG=y - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -CONFIG_DONGLE=y -CONFIG_ESI_DONGLE=m -CONFIG_ACTISYS_DONGLE=m -CONFIG_TEKRAM_DONGLE=m -CONFIG_TOIM3232_DONGLE=m -CONFIG_LITELINK_DONGLE=m -CONFIG_MA600_DONGLE=m -CONFIG_GIRBIL_DONGLE=m -CONFIG_MCP2120_DONGLE=m -CONFIG_OLD_BELKIN_DONGLE=m -# CONFIG_ACT200L_DONGLE is not set -CONFIG_KINGSUN_DONGLE=m -CONFIG_KSDAZZLE_DONGLE=m -CONFIG_KS959_DONGLE=m - -# -# FIR device drivers -# -CONFIG_USB_IRDA=m -CONFIG_SIGMATEL_FIR=m -CONFIG_MCS_FIR=m -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_NET_9P=m -# CONFIG_NET_9P_DEBUG is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_AD525X_DPOT is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -# CONFIG_ISL29003 is not set -# CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -CONFIG_EEPROM_AT24=m -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y -CONFIG_IWMC3200TOP=m -# CONFIG_IWMC3200TOP_DEBUG is not set -# CONFIG_IWMC3200TOP_DEBUGFS is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -# CONFIG_DM_UEVENT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -CONFIG_ENC28J60=y -# CONFIG_ENC28J60_WRITEVERIFY is not set -# CONFIG_ETHOC is not set -CONFIG_SMC911X=y -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -CONFIG_KS8851=y -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -CONFIG_AT76C50X_USB=m -CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -CONFIG_B43=m -# CONFIG_B43_SDIO is not set -CONFIG_B43_PHY_LP=y -CONFIG_B43_LEDS=y -CONFIG_B43_HWRNG=y -# CONFIG_B43_DEBUG is not set -# CONFIG_B43LEGACY is not set -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -# CONFIG_IWM is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -# CONFIG_LIBERTAS_SDIO is not set -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_SPI is not set -CONFIG_P54_LEDS=y -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -# CONFIG_RT2800USB is not set -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -CONFIG_WL12XX=m -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL1271=m -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# WiMAX Wireless Broadband devices -# -CONFIG_WIMAX_I2400M=m -CONFIG_WIMAX_I2400M_USB=m -CONFIG_WIMAX_I2400M_SDIO=m -CONFIG_WIMAX_IWMC3200_SDIO=y -CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 - -# -# USB Network Adapters -# -CONFIG_USB_CATC=y -CONFIG_USB_KAWETH=y -CONFIG_USB_PEGASUS=y -CONFIG_USB_RTL8150=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -CONFIG_USB_NET_SMSC95XX=y -CONFIG_USB_NET_GL620A=y -CONFIG_USB_NET_NET1080=y -CONFIG_USB_NET_PLUSB=y -CONFIG_USB_NET_MCS7830=y -CONFIG_USB_NET_RNDIS_HOST=y -CONFIG_USB_NET_CDC_SUBSET=y -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=y -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -# CONFIG_WAN is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOATM is not set -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=m -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -CONFIG_SSB=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -# CONFIG_SSB_SDIOHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -# CONFIG_TPS65910_CORE is not set -CONFIG_TWL4030_CODEC=y -# CONFIG_TWL4030_MADC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_CUSTOMISE=y -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=y -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_MT9V113=m -# CONFIG_VIDEO_TCM825X is not set -CONFIG_VIDEO_MT9P012=m -CONFIG_VIDEO_MT9T112=m -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -# CONFIG_VIDEO_TVP514X is not set -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=y -CONFIG_VIDEO_VPFE_CAPTURE=y -# CONFIG_VIDEO_DM6446_CCDC is not set -# CONFIG_VIDEO_DM355_CCDC is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -CONFIG_SOC_CAMERA=y -# CONFIG_SOC_CAMERA_MT9M001 is not set -# CONFIG_SOC_CAMERA_MT9M111 is not set -CONFIG_SOC_CAMERA_MT9P031=m -# CONFIG_SOC_CAMERA_MT9T031 is not set -# CONFIG_SOC_CAMERA_MT9V022 is not set -# CONFIG_SOC_CAMERA_RJ54N1 is not set -# CONFIG_SOC_CAMERA_TW9910 is not set -# CONFIG_SOC_CAMERA_PLATFORM is not set -# CONFIG_SOC_CAMERA_OV772X is not set -# CONFIG_SOC_CAMERA_OV9640 is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -# CONFIG_USB_GL860 is not set -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -# CONFIG_USB_GSPCA_JEILINJ is not set -CONFIG_USB_GSPCA_MARS=m -# CONFIG_USB_GSPCA_MR97310A is not set -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -# CONFIG_USB_GSPCA_PAC7302 is not set -CONFIG_USB_GSPCA_PAC7311=m -# CONFIG_USB_GSPCA_SN9C20X is not set -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -CONFIG_USB_GSPCA_STK014=m -# CONFIG_USB_GSPCA_STV0680 is not set -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -# CONFIG_VIDEO_CX231XX_ALSA is not set -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_TEF6862 is not set -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -# CONFIG_DVB_USB_CE6230 is not set -# CONFIG_DVB_USB_FRIIO is not set -# CONFIG_DVB_USB_EC168 is not set -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_LGS8GL5=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -CONFIG_HID_TOPSEED=y -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_U132_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -# CONFIG_USB_SERIAL_CP210X is not set -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m -CONFIG_USB_LED=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=m -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_VST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=480 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -CONFIG_USB_ZERO_HNPTEST=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -# CONFIG_USB_MASS_STORAGE is not set -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_GPIO_VBUS=y -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_TWL4030_USB=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_UNSAFE_RESUME=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=m - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=m -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=m -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -CONFIG_W35UND=m -# CONFIG_PRISM2_USB is not set -CONFIG_ECHO=m -CONFIG_OTUS=m -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -CONFIG_RTL8192SU=m -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -# CONFIG_RAMZSWAP is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_STRIP is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_JFS_FS=m -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=m -# CONFIG_GFS2_FS_LOCKING_DLM is not set -CONFIG_OCFS2_FS=m -CONFIG_OCFS2_FS_O2CB=m -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -# CONFIG_OCFS2_DEBUG_FS is not set -# CONFIG_OCFS2_FS_POSIX_ACL is not set -CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -# CONFIG_CUSE is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=m -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -# CONFIG_ECRYPT_FS is not set -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DFS_UPCALL is not set -CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_NCP_FS=m -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_9P_FS=m - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_HW=y - -# -# OCF Configuration -# -# CONFIG_OCF_OCF is not set -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/logo_linux_clut224.ppm b/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/logo_linux_clut224.ppm deleted file mode 100644 index d29fc1c5..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/beagleboard/logo_linux_clut224.ppm +++ /dev/null @@ -1,73147 +0,0 @@ -P3 -# CREATOR: GIMP PNM Filter Version 1.1 -387 63 -255 -246 -97 -3 -246 -97 -3 -246 -97 -3 -246 -97 -3 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-0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 -214 -84 -0 diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0001-mt9t111-first-stab-at-merging-sensor-driver-based-on.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0001-mt9t111-first-stab-at-merging-sensor-driver-based-on.patch deleted file mode 100644 index bd4a7f88..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0001-mt9t111-first-stab-at-merging-sensor-driver-based-on.patch +++ /dev/null @@ -1,2394 +0,0 @@ -From 4e23fe54d7f8ecc1c927d225b1b74e6b00e22997 Mon Sep 17 00:00:00 2001 -From: OpenEmbedded User -Date: Tue, 9 Feb 2010 17:16:13 +0100 -Subject: [PATCH 01/75] mt9t111: first stab at merging sensor driver based on a patch by Leopard Imaging - ---- - drivers/media/video/Kconfig | 8 + - drivers/media/video/Makefile | 1 + - drivers/media/video/mt9t111.c | 883 ++++++++++++++++++++++++ - drivers/media/video/mt9t111_reg.h | 1364 +++++++++++++++++++++++++++++++++++++ - include/media/mt9t111.h | 79 +++ - 5 files changed, 2335 insertions(+), 0 deletions(-) - create mode 100644 drivers/media/video/mt9t111.c - create mode 100644 drivers/media/video/mt9t111_reg.h - create mode 100644 include/media/mt9t111.h - -diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig -index 41e39a7..f67ed46 100644 ---- a/drivers/media/video/Kconfig -+++ b/drivers/media/video/Kconfig -@@ -344,6 +344,14 @@ config VIDEO_MT9P012 - MT9P012 camera. It is currently working with the TI OMAP3 - camera controller. - -+config VIDEO_MT9T111 -+ tristate "Micron MT9T111 raw sensor driver (3MP)" -+ depends on I2C && VIDEO_V4L2 -+ ---help--- -+ This is a Video4Linux2 sensor-level driver for the Micron -+ MT9T111 camera. It is currently working with the TI OMAP3 -+ camera controller. -+ - config VIDEO_DW9710 - tristate "Lens driver for DW9710" - depends on I2C && VIDEO_V4L2 -diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile -index 88e8ec1..31688bf 100644 ---- a/drivers/media/video/Makefile -+++ b/drivers/media/video/Makefile -@@ -127,6 +127,7 @@ obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o - obj-y += isp/ - obj-$(CONFIG_VIDEO_OMAP3) += omap34xxcam.o - obj-$(CONFIG_VIDEO_MT9P012) += mt9p012.o -+obj-$(CONFIG_VIDEO_MT9T111) += mt9t111.o - obj-$(CONFIG_VIDEO_DW9710) += dw9710.o - obj-$(CONFIG_VIDEO_TPS61059) += tps61059.o - obj-$(CONFIG_VIDEO_OV3640) += ov3640.o -diff --git a/drivers/media/video/mt9t111.c b/drivers/media/video/mt9t111.c -new file mode 100644 -index 0000000..ecc5115 ---- /dev/null -+++ b/drivers/media/video/mt9t111.c -@@ -0,0 +1,883 @@ -+/* -+ * drivers/media/video/mt9t111.c -+ * -+ * mt9t111 sensor driver -+ * -+ * Copyright (C) 2009 Leopard Imaging -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include "mt9t111_reg.h" -+ -+#define USE_RAW // YCbCr mode does not work yet -+//#define COLOR_BAR // Create a Color bar test pattern, Blue, Green, Red, Grey -+ -+#define SENSOR_DETECTED 1 -+#define SENSOR_NOT_DETECTED 0 -+ -+static void mt9t111_loaddefault(struct i2c_client *client); -+ -+/* -+* as a place holder for further development -+*/ -+static void debug_dummy(char *in_msg) -+{ -+ -+} -+ -+/* list of image formats supported by mt9t111 sensor */ -+const static struct v4l2_fmtdesc mt9t111_formats[] = { -+#ifdef USE_RAW -+ { -+ .description = "RAW ", -+ .pixelformat = V4L2_PIX_FMT_SGRBG10, -+ }, -+#else -+ { -+ .description = "YUV 422 ", -+ .pixelformat = V4L2_PIX_FMT_YUYV, -+ }, -+#endif -+}; -+ -+#define NUM_CAPTURE_FORMATS ARRAY_SIZE(mt9t111_formats) -+ -+/* -+ * Array of image sizes supported by MT9T111. These must be ordered from -+ * smallest image size to largest. -+ */ -+const static struct capture_size mt9t111_sizes[] = { -+ { 640, 480 }, -+// { 2048, 1536} -+}; -+ -+#define NUM_CAPTURE_SIZE ARRAY_SIZE(mt9t111_sizes) -+ -+ -+const struct v4l2_fract mt9t111_frameintervals[] = { -+ { .numerator = 1, .denominator = 10 } -+}; -+ -+#define NUM_CAPTURE_FRAMEINTERVALS ARRAY_SIZE(mt9t111_frameintervals) -+ -+/** -+ * struct mt9t111_sensor - main structure for storage of sensor information -+ * @pdata: access functions and data for platform level information -+ * @v4l2_int_device: V4L2 device structure structure -+ * @i2c_client: iic client device structure -+ * @pix: V4L2 pixel format information structure -+ * @timeperframe: time per frame expressed as V4L fraction -+ * @scaler: -+ * @ver: mt9t111 chip version -+ * @fps: frames per second value -+ */ -+struct mt9t111_sensor { -+ const struct mt9t111_platform_data *pdata; -+ struct v4l2_int_device *v4l2_int_device; -+ struct i2c_client *i2c_client; -+ struct v4l2_pix_format pix; -+ struct v4l2_fract timeperframe; -+ int scaler; -+ int ver; -+ int fps; -+ int state; -+}; -+ -+static struct mt9t111_sensor mt9t111 = { -+ .timeperframe = { -+ .numerator = 1, -+ .denominator = 10, -+ }, -+ .state = SENSOR_NOT_DETECTED, -+}; -+ -+/** -+ * mt9t111_read_reg - Read a value from a register in an mt9t111 sensor device -+ * @client: i2c driver client structure -+ * @data_length: length of data to be read -+ * @reg: register address / offset -+ * @val: stores the value that gets read -+ * -+ * Read a value from a register in an mt9t111 sensor device. -+ * The value is returned in 'val'. -+ * Returns zero if successful, or non-zero otherwise. -+ */ -+static int -+mt9t111_read_reg(struct i2c_client *client, u16 reg, u16 *val) -+{ -+ struct i2c_msg msg[1]; -+ u8 data[4]; -+ int err; -+ -+ msg->addr = client->addr; -+ msg->flags = 0; -+ msg->len = 2; -+ msg->buf = data; -+ data[0] = (reg & 0xff00) >> 8; -+ data[1] = (reg & 0x00ff); -+ err = i2c_transfer(client->adapter, msg, 1); -+ if (err >= 0) { -+ msg->flags = I2C_M_RD; -+ msg->len = 2; /* 2 byte read */ -+ err = i2c_transfer(client->adapter, msg, 1); -+ if (err >= 0) { -+ *val = ((data[0] & 0x00ff) << 8) -+ | (data[1] & 0x00ff); -+ return 0; -+ } -+ } -+ return err; -+} -+ -+/** -+ * mt9t111_write_reg - Write a value to a register in an mt9t111 sensor device -+ * @client: i2c driver client structure -+ * @data_length: length of data to be read -+ * @reg: register address / offset -+ * @val: value to be written to specified register -+ * -+ * Write a value to a register in an mt9t111 sensor device. -+ * Returns zero if successful, or non-zero otherwise. -+ */ -+static int -+mt9t111_write_reg(struct i2c_client *client, u16 reg, u16 val) -+{ -+ struct i2c_msg msg[1]; -+ u8 data[20]; -+ int err; -+ -+ msg->addr = client->addr; -+ msg->flags = 0; -+ msg->len = 4; -+ msg->buf = data; -+ data[0] = (u8)((reg & 0xff00) >> 8); -+ data[1] = (u8)(reg & 0x00ff); -+ data[2] = (u8)((val & 0xff00) >> 8); -+ data[3] = (u8)(val & 0x00ff); -+ err = i2c_transfer(client->adapter, msg, 1); -+ -+ return err; -+} -+ -+/** -+ * mt9t111_write_regs - Write registers to an mt9t111 sensor device -+ * @client: i2c driver client structure -+ * @reg_in: pointer to registers to write -+ * @cnt: the number of registers -+ * -+ * Write registers . -+ * Returns zero if successful, or non-zero otherwise. -+ */ -+static int -+mt9t111_write_regs(struct i2c_client *client, mt9t111_regs *reg_in, int cnt) -+{ -+ int err = 0; -+ int i; -+ mt9t111_regs *reg = reg_in; -+ -+ for (i=0;idelay_time == 0) { -+ err |= mt9t111_write_reg(client, reg->addr, reg->data); -+ } else if (reg->addr != 0 || reg->data != 0) { -+ err |= mt9t111_write_reg(client, reg->addr, reg->data); -+ mdelay(reg->delay_time); -+ } else -+ mdelay(reg->delay_time); -+ -+ if (err < 0) { -+ dev_warn(&client->dev, "write reg error, addr = 0x%x, data = 0x%x \n", \ -+ reg->addr, reg->data); -+ return err; -+ } -+ reg++; -+ } -+ return err; -+} -+ -+/** -+ * mt9t111_detect - Detect if an mt9t111 is present, and if so which revision -+ * @client: pointer to the i2c client driver structure -+ * -+ * Detect if an mt9t111 is present -+ * Returns a negative error number if no device is detected, or the -+ * non-negative value of the version ID register if a device is detected. -+ */ -+static int -+mt9t111_detect(struct i2c_client *client) -+{ -+ u16 val; -+ -+ /* chip ID is at address 0 */ -+ if (mt9t111_read_reg(client, MT9T111_CHIP_ID, &val) < 0) -+ return -ENODEV; -+ dev_info(&client->dev, "model id detected 0x%x\n", val); -+ -+ if (val != MT9T111_CHIP_ID_VALUE) { -+ dev_warn(&client->dev, "model id mismatch received 0x%x expecting 0x%x\n", -+ val, MT9T111_CHIP_ID_VALUE); -+ -+ return -ENODEV; -+ } -+ -+ return 0; -+ -+} -+ -+/** -+ * mt9t111_configure - Configure the mt9t111 for the specified image mode -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Configure the mt9t111 for a specified image size, pixel format, and frame -+ * period. xclk is the frequency (in Hz) of the xclk input to the mt9t111. -+ * fper is the frame period (in seconds) expressed as a fraction. -+ * Returns zero if successful, or non-zero otherwise. -+ * The actual frame period is returned in fper. -+ */ -+static int mt9t111_configure(struct v4l2_int_device *s) -+{ -+ debug_dummy("debug_dummy -- to set imager mode"); -+ -+ return 0; -+} -+ -+/** -+ * ioctl_enum_framesizes - V4L2 sensor if handler for vidioc_int_enum_framesizes -+ * @s: pointer to standard V4L2 device structure -+ * @frms: pointer to standard V4L2 framesizes enumeration structure -+ * -+ * Returns possible framesizes depending on choosen pixel format -+ **/ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *frms) -+{ -+ int ifmt; -+ -+ for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) { -+ if (frms->pixel_format == mt9t111_formats[ifmt].pixelformat) -+ break; -+ } -+ /* Is requested pixelformat not found on sensor? */ -+ if (ifmt == NUM_CAPTURE_FORMATS) -+ return -EINVAL; -+ -+ /* Do we already reached all discrete framesizes? */ -+ if (frms->index >= NUM_CAPTURE_SIZE) -+ return -EINVAL; -+ -+ frms->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frms->discrete.width = mt9t111_sizes[frms->index].width; -+ frms->discrete.height = mt9t111_sizes[frms->index].height; -+ -+ return 0; -+ -+} -+ -+static int ioctl_enum_frameintervals(struct v4l2_int_device *s, -+ struct v4l2_frmivalenum *frmi) -+{ -+ int ifmt; -+ -+printk(KERN_INFO "entering ioctl_enum_frameintervals\n"); -+printk(KERN_INFO "index = %d, pixel_format = 0x%x, width = %d, height = %d\n", -+ frmi->index, frmi->pixel_format, frmi->width, frmi->height); -+printk(KERN_INFO "mt9t111 format = 0x%x\n", mt9t111_formats[0].pixelformat); -+ -+ if (frmi->index >= NUM_CAPTURE_FRAMEINTERVALS) -+ return -EINVAL; -+ -+ for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) { -+ if (frmi->pixel_format == mt9t111_formats[ifmt].pixelformat) -+ break; -+ } -+ /* Is requested pixelformat not found on sensor? */ -+ if (ifmt == NUM_CAPTURE_FORMATS) -+ return -EINVAL; -+ -+ frmi->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frmi->discrete.numerator = -+ mt9t111_frameintervals[frmi->index].numerator; -+ frmi->discrete.denominator = -+ mt9t111_frameintervals[frmi->index].denominator; -+ return 0; -+} -+ -+/** -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialize the sensor device (call mt9t111_configure()) -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ return 0; -+} -+ -+/** -+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the dev. at slave detach. The complement of ioctl_dev_init. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ return 0; -+} -+ -+/** -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. Returns 0 if -+ * mt9t111 device could be found, otherwise returns appropriate error. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ return 0; -+} -+ -+/** -+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num -+ * @s: pointer to standard V4L2 device structure -+ * @on: power state to which device is to be set -+ * -+ * Sets devices power state to requrested state, if possible. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) -+{ -+ struct mt9t111_sensor *sensor = s->priv; -+ struct i2c_client *c = sensor->i2c_client; -+ int rval; -+ -+ if ((on == V4L2_POWER_STANDBY) && (sensor->state == SENSOR_DETECTED)) -+ debug_dummy("debug_dummy -- put to standby\n"); -+ -+ if (on != V4L2_POWER_ON) -+ debug_dummy("debug_dummy -- stop master clock\n"); -+ else -+ debug_dummy("debug_dummy -- enable clock\n");; -+ -+ rval = sensor->pdata->power_set(on); -+ if (rval < 0) { -+ dev_err(&c->dev, "Unable to set the power state: " "mt9t111" -+ " sensor\n"); -+ //sensor->pdata->set_xclk(0); -+ return rval; -+ } -+ -+ if ((on == V4L2_POWER_ON) && (sensor->state == SENSOR_DETECTED)) -+ mt9t111_configure(s); -+ -+ if ((on == V4L2_POWER_ON) && (sensor->state == SENSOR_NOT_DETECTED)) { -+ rval = mt9t111_detect(c); -+ if (rval < 0) { -+ dev_err(&c->dev, "Unable to detect " "mt9t111" -+ " sensor\n"); -+ sensor->state = SENSOR_NOT_DETECTED; -+ return rval; -+ } -+ mt9t111_loaddefault(c); -+ sensor->state = SENSOR_DETECTED; -+ sensor->ver = rval; -+ pr_info("mt9t111" " chip version 0x%02x detected\n", -+ sensor->ver); -+ } -+ return 0; -+} -+ -+/** -+ * ioctl_g_priv - V4L2 sensor interface handler for vidioc_int_g_priv_num -+ * @s: pointer to standard V4L2 device structure -+ * @p: void pointer to hold sensor's private data address -+ * -+ * Returns device's (sensor's) private data area address in p parameter -+ */ -+static int ioctl_g_priv(struct v4l2_int_device *s, void *p) -+{ -+ struct mt9t111_sensor *sensor = s->priv; -+ -+ return sensor->pdata->priv_data_set(p); -+} -+ -+/** -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, -+ struct v4l2_streamparm *a) -+{ -+ //TODO: set paramters -+ debug_dummy("debug_dummy -- VIDIOC_S_PARM "); -+ return 0; -+} -+ -+/** -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, -+ struct v4l2_streamparm *a) -+{ -+ struct mt9t111_sensor *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ -+ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; -+ -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ cparm->capability = V4L2_CAP_TIMEPERFRAME; -+ cparm->timeperframe = sensor->timeperframe; -+ -+ return 0; -+} -+ -+/** -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ struct mt9t111_sensor *sensor = s->priv; -+ f->fmt.pix = sensor->pix; -+ -+ return 0; -+} -+ -+/** -+ * ioctl_try_fmt_cap - Implement the CAPTURE buffer VIDIOC_TRY_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 VIDIOC_TRY_FMT ioctl structure -+ * -+ * Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This -+ * ioctl is used to negotiate the image capture size and pixel format -+ * without actually making it take effect. -+ */ -+static int ioctl_try_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format *pix = &f->fmt.pix; -+ struct mt9t111_sensor *sensor = s->priv; -+ struct v4l2_pix_format *pix2 = &sensor->pix; -+ -+ pix->width = 640; -+ pix->height = 480; -+#ifdef USE_RAW -+ pix->pixelformat = V4L2_PIX_FMT_SGRBG10; -+ pix->bytesperline = pix->width; -+ pix->colorspace = V4L2_COLORSPACE_SRGB; -+#else -+ pix->pixelformat = V4L2_PIX_FMT_YUYV; -+ pix->bytesperline = pix->width * 2; -+ pix->colorspace = V4L2_COLORSPACE_JPEG; -+#endif -+ pix->field = V4L2_FIELD_NONE; -+ -+ pix->sizeimage = pix->bytesperline * pix->height; -+ pix->priv = 0; -+ *pix2 = *pix; -+ return 0; -+} -+ -+/** -+ * ioctl_s_fmt_cap - V4L2 sensor interface handler for VIDIOC_S_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 VIDIOC_S_FMT ioctl structure -+ * -+ * If the requested format is supported, configures the HW to use that -+ * format, returns error code if format not supported or HW can't be -+ * correctly configured. -+ */ -+static int ioctl_s_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ struct mt9t111_sensor *sensor = s->priv; -+ struct v4l2_pix_format *pix = &f->fmt.pix; -+ int rval; -+ -+ rval = ioctl_try_fmt_cap(s, f); -+ if (!rval) -+ sensor->pix = *pix; -+ -+ return rval; -+} -+ -+/** -+ * ioctl_enum_fmt_cap - Implement the CAPTURE buffer VIDIOC_ENUM_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: standard V4L2 VIDIOC_ENUM_FMT ioctl structure -+ * -+ * Implement the VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. -+ */ -+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ int index = fmt->index; -+ enum v4l2_buf_type type = fmt->type; -+ -+ memset(fmt, 0, sizeof(*fmt)); -+ fmt->index = index; -+ fmt->type = type; -+ -+ switch (fmt->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ if (index >= NUM_CAPTURE_FORMATS) -+ return -EINVAL; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ fmt->flags = mt9t111_formats[index].flags; -+ strlcpy(fmt->description, mt9t111_formats[index].description, -+ sizeof(fmt->description)); -+ fmt->pixelformat = mt9t111_formats[index].pixelformat; -+ -+ return 0; -+} -+ -+/** -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, -+ struct v4l2_control *vc) -+{ -+ debug_dummy("debug_dummy -- s ctrl\n"); -+ return 0; -+} -+ -+/** -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, -+ struct v4l2_control *vc) -+{ -+ debug_dummy("debug_dummy -- g ctrl\n"); -+ return 0; -+} -+ -+/** -+ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control information -+ * from the video_control[] array. Otherwise, returns -EINVAL if the -+ * control is not supported. -+ */ -+static int ioctl_queryctrl(struct v4l2_int_device *s, -+ struct v4l2_queryctrl *qc) -+{ -+ debug_dummy("debug_dummy -- query ctrl\n"); -+ return-EINVAL; -+} -+ -+/** -+ * ioctl_s_routing - V4L2 decoder interface handler for VIDIOC_S_INPUT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @index: number of the input -+ * -+ * If index is valid, selects the requested input. Otherwise, returns -EINVAL if -+ * the input is not supported or there is no active signal present in the -+ * selected input. -+ */ -+static int ioctl_s_routing(struct v4l2_int_device *s, -+ struct v4l2_routing *route) -+{ -+ return 0; -+} -+ -+/** -+ * ioctl_g_ifparm - V4L2 decoder interface handler for vidioc_int_g_ifparm_num -+ * @s: pointer to standard V4L2 device structure -+ * @p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure -+ * -+ * Gets slave interface parameters. -+ * Calculates the required xclk value to support the requested -+ * clock parameters in p. This value is returned in the p -+ * parameter. -+ */ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ struct mt9t111_sensor *sensor = s->priv; -+ int rval; -+ -+ if (p == NULL) -+ return -EINVAL; -+ -+ if (NULL == sensor->pdata->ifparm) -+ return -EINVAL; -+ -+ rval = sensor->pdata->ifparm(p); -+ if (rval) { -+ v4l_err(sensor->i2c_client, "g_ifparm.Err[%d]\n", rval); -+ return rval; -+ } -+ -+ p->u.ycbcr.clock_curr = 40*1000000; // temporal value -+ -+ return 0; -+} -+ -+ -+static struct v4l2_int_ioctl_desc mt9t111_ioctl_desc[] = { -+ { .num = vidioc_int_enum_framesizes_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_enum_framesizes }, -+ { .num = vidioc_int_enum_frameintervals_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_enum_frameintervals }, -+ { .num = vidioc_int_dev_init_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_dev_init }, -+ { .num = vidioc_int_dev_exit_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_dev_exit }, -+ { .num = vidioc_int_s_power_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_s_power }, -+ { .num = vidioc_int_g_priv_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_g_priv }, -+ {vidioc_int_g_ifparm_num, -+ .func = (v4l2_int_ioctl_func*) ioctl_g_ifparm}, -+ { .num = vidioc_int_init_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_init }, -+ { .num = vidioc_int_enum_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap }, -+ { .num = vidioc_int_try_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_try_fmt_cap }, -+ { .num = vidioc_int_g_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_g_fmt_cap }, -+ { .num = vidioc_int_s_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_s_fmt_cap }, -+ { .num = vidioc_int_g_parm_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_g_parm }, -+ { .num = vidioc_int_s_parm_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_s_parm }, -+ { .num = vidioc_int_queryctrl_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_queryctrl }, -+ { .num = vidioc_int_g_ctrl_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_g_ctrl }, -+ { .num = vidioc_int_s_ctrl_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_s_ctrl }, -+ {.num = vidioc_int_s_video_routing_num, -+ .func = (v4l2_int_ioctl_func *) ioctl_s_routing}, -+}; -+ -+static void mt9t111_refresh(struct i2c_client *client){ -+ int i; -+ unsigned short value; -+ // MCU_ADDRESS [SEQ_CMD] -- refresh -+ mt9t111_write_reg(client, 0x098E, 0x8400); -+ mt9t111_write_reg(client, 0x0990, 0x0006); -+ for (i=0;i<100;i++){ -+ mt9t111_write_reg(client, 0x098E, 0x8400); -+ mt9t111_read_reg(client,0x0990,&value); -+ if ( value == 0) -+ break; -+ mdelay(5); -+ } -+} -+ -+#ifdef COLOR_BAR -+static void mt9t111_color_bar(struct i2c_client *client) -+{ -+ mt9t111_write_reg(client, 0x3210, 0x01B0); // disable lens correction -+ -+ mt9t111_write_reg(client, 0x098E, 0x6003); -+ mt9t111_write_reg(client, 0x0990, 0x0100); -+ mt9t111_write_reg(client, 0x098E, 0x6025); -+ mt9t111_write_reg(client, 0x0990, 0x0003); -+} -+#endif -+ -+static void mt9t111_bayer_format(struct i2c_client *client) -+{ -+ mt9t111_write_regs(client, bayer_pattern_regs, sizeof(bayer_pattern_regs)/sizeof(mt9t111_regs)); -+} -+ -+static void mt9t111_enable_pll(struct i2c_client *client) -+{ -+ int i; -+ unsigned short value; -+ -+ mt9t111_write_regs(client, pll_regs1, sizeof(pll_regs1)/sizeof(mt9t111_regs)); -+ for (i=0;i<100;i++){ -+ mt9t111_read_reg(client,0x0014,&value); -+ if (( value & 0x8000) != 0) -+ break; -+ mdelay(2); -+ } -+ mt9t111_write_regs(client, pll_regs2, sizeof(pll_regs2)/sizeof(mt9t111_regs)); -+} -+ -+ -+static void mt9t111_loaddefault(struct i2c_client *client) -+{ -+ mt9t111_write_reg(client, 0x001A, 0x0219); -+ mt9t111_write_reg(client, 0x001A, 0x0218); -+ -+ mt9t111_enable_pll(client); -+ mt9t111_write_regs(client, def_regs1, sizeof(def_regs1)/sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, patch_rev6, sizeof(patch_rev6)/sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, def_regs2, sizeof(def_regs2)/sizeof(mt9t111_regs)); -+ -+#ifdef USE_RAW -+ mt9t111_bayer_format(client); -+#endif -+ -+#ifdef COLOR_BAR -+ mt9t111_color_bar(client); -+#endif -+ -+ mt9t111_refresh(client); -+} -+ -+static struct v4l2_int_slave mt9t111_slave = { -+ .ioctls = mt9t111_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(mt9t111_ioctl_desc), -+}; -+ -+static struct v4l2_int_device mt9t111_int_device = { -+ .module = THIS_MODULE, -+ .name = "mt9t111", -+ .priv = &mt9t111, -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &mt9t111_slave, -+ }, -+}; -+ -+/** -+ * mt9t111_probe - sensor driver i2c probe handler -+ * @client: i2c driver client device structure -+ * -+ * Register sensor as an i2c client device and V4L2 -+ * device. -+ */ -+static int -+mt9t111_probe(struct i2c_client *client, const struct i2c_device_id *id) -+{ -+ struct mt9t111_sensor *sensor = &mt9t111; -+ int err; -+ -+ if (i2c_get_clientdata(client)) -+ return -EBUSY; -+ -+ sensor->pdata = client->dev.platform_data; -+ -+ if (!sensor->pdata) { -+ dev_err(&client->dev, "no platform data?\n"); -+ return -ENODEV; -+ } -+ -+ sensor->v4l2_int_device = &mt9t111_int_device; -+ sensor->i2c_client = client; -+ -+ i2c_set_clientdata(client, sensor); -+ -+ sensor->pix.width = 640; -+ sensor->pix.height = 480; -+#ifdef USE_RAW -+ sensor->pix.pixelformat = V4L2_PIX_FMT_SGRBG10; -+#else -+ sensor->pix.pixelformat = V4L2_PIX_FMT_YUYV; -+#endif -+ err = v4l2_int_device_register(sensor->v4l2_int_device); -+ if (err) -+ i2c_set_clientdata(client, NULL); -+ return err; -+} -+ -+/** -+ * mt9t111_remove - sensor driver i2c remove handler -+ * @client: i2c driver client device structure -+ * -+ * Unregister sensor as an i2c client device and V4L2 -+ * device. Complement of mt9t111_probe(). -+ */ -+static int __exit -+mt9t111_remove(struct i2c_client *client) -+{ -+ struct mt9t111_sensor *sensor = i2c_get_clientdata(client); -+ -+ if (!client->adapter) -+ return -ENODEV; /* our client isn't attached */ -+ -+ v4l2_int_device_unregister(sensor->v4l2_int_device); -+ i2c_set_clientdata(client, NULL); -+ -+ return 0; -+} -+ -+static const struct i2c_device_id mt9t111_id[] = { -+ { "mt9t111", 0 }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(i2c, mt9t111_id); -+ -+static struct i2c_driver mt9t111sensor_i2c_driver = { -+ .driver = { -+ .name = "mt9t111", -+ .owner = THIS_MODULE, -+ }, -+ .probe = mt9t111_probe, -+ .remove = __exit_p(mt9t111_remove), -+ .id_table = mt9t111_id, -+}; -+ -+/** -+ * mt9t111sensor_init - sensor driver module_init handler -+ * -+ * Registers driver as an i2c client driver. Returns 0 on success, -+ * error code otherwise. -+ */ -+static int __init mt9t111sensor_init(void) -+{ -+printk(KERN_INFO "entering mt9t111sensor_init\n"); -+ return i2c_add_driver(&mt9t111sensor_i2c_driver); -+} -+module_init(mt9t111sensor_init); -+ -+/** -+ * mt9t111sensor_cleanup - sensor driver module_exit handler -+ * -+ * Unregisters/deletes driver as an i2c client driver. -+ * Complement of mt9t111sensor_init. -+ */ -+static void __exit mt9t111sensor_cleanup(void) -+{ -+ i2c_del_driver(&mt9t111sensor_i2c_driver); -+} -+module_exit(mt9t111sensor_cleanup); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("mt9t111 camera sensor driver"); -diff --git a/drivers/media/video/mt9t111_reg.h b/drivers/media/video/mt9t111_reg.h -new file mode 100644 -index 0000000..e012eeb ---- /dev/null -+++ b/drivers/media/video/mt9t111_reg.h -@@ -0,0 +1,1364 @@ -+/* -+ * drivers/media/video/mt9t111_reg.h -+ * -+ * mt9t111 sensor driver header file -+ * -+ * Copyright (C) 2009 Leopard Imaging -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#ifndef MT9T111_REG_H -+#define MT9T111_REG_H -+ -+/* register addr */ -+#define MT9T111_CHIP_ID (0x0000) -+ -+/* register value */ -+#define MT9T111_CHIP_ID_VALUE (0x2680) -+ -+typedef struct { -+ u16 delay_time; -+ u16 addr; -+ u16 data; -+} mt9t111_regs; -+ -+mt9t111_regs patch_rev6[] ={ -+ {0, 0x0982, 0x0}, -+ {0, 0x098A, 0xCE7}, -+ {0, 0x0990, 0x3C3C}, -+ {0, 0x0992, 0x3C3C}, -+ {0, 0x0994, 0x3C5F}, -+ {0, 0x0996, 0x4F30}, -+ {0, 0x0998, 0xED08}, -+ {0, 0x099a, 0xBD61}, -+ {0, 0x099c, 0xD5CE}, -+ {0, 0x099e, 0x4CD}, -+ {0, 0x098A, 0xCF7}, -+ {0, 0x0990, 0x1F17}, -+ {0, 0x0992, 0x211}, -+ {0, 0x0994, 0xCC33}, -+ {0, 0x0996, 0x2E30}, -+ {0, 0x0998, 0xED02}, -+ {0, 0x099a, 0xCCFF}, -+ {0, 0x099c, 0xFDED}, -+ {0, 0x099e, 0xCC}, -+ {0, 0x098A, 0xD07}, -+ {0, 0x0990, 0x2}, -+ {0, 0x0992, 0xBD70}, -+ {0, 0x0994, 0x6D18}, -+ {0, 0x0996, 0xDE1F}, -+ {0, 0x0998, 0x181F}, -+ {0, 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0x74A0}, -+ {0, 0x0990, 0x082E}, -+ {0, 0x3C52, 0x082E}, -+ {0, 0x098E, 0x488E}, -+ {0, 0x0990, 0x0020}, -+ {0, 0x098E, 0xECAC}, -+ {0, 0x0990, 0x0000} -+}; -+ -+mt9t111_regs def_regs2[] = { -+ {100, 0x0018, 0x0028}, -+ {0, 0x316C, 0x350F}, -+ {0, 0x098E, 0x6817}, -+ {0, 0x0990, 0x000C}, -+ {0, 0x0034, 0x0000} -+}; -+ -+mt9t111_regs pll_regs1[] = { -+ {0, 0x0014, 0x2425}, -+ {0, 0x0014, 0x2425}, -+ {0, 0x0014, 0x2145}, -+ {0, 0x0010, 0x0219}, -+ {0, 0x0012, 0x0090}, -+ {0, 0x002A, 0x79DD}, -+ {0, 0x0014, 0x2545}, -+ {0, 0x0014, 0x2547}, -+ {0, 0x0014, 0x3447}, -+ {0, 0x0014, 0x3047} -+}; -+ -+mt9t111_regs pll_regs2[] = { -+ {0, 0x0014, 0x3046}, -+ {0, 0x0022, 0x01E0}, -+ {0, 0x001E, 0x0707}, -+ {0, 0x3B84, 0x011D} -+}; -+ -+mt9t111_regs bayer_pattern_regs[] = { -+ {0, 0x098E, 0x6807}, -+ {0, 0x0990, 0x0100}, -+ {0, 0x098E, 0x6809}, -+ {0, 0x0990, 0x0000}, -+ {0, 0x098E, 0xE88E}, -+ {0, 0x0990, 0x0000}, -+ {0, 0x098E, 0x6C07}, -+ {0, 0x0990, 0x0100}, -+ {0, 0x098E, 0x6C09}, -+ {0, 0x0990, 0x0000}, -+ {0, 0x098E, 0xEC8E}, -+ {0, 0x0990, 0x0000} -+}; -+ -+#endif -diff --git a/include/media/mt9t111.h b/include/media/mt9t111.h -new file mode 100644 -index 0000000..7acbeed ---- /dev/null -+++ b/include/media/mt9t111.h -@@ -0,0 +1,79 @@ -+/* -+ * include/media/mt9t111.h -+ * -+ * mt9t111 sensor driver -+ * -+ * Copyright (C) 2009 Leopard Imaging -+ * -+ * This file is licensed under the terms of the GNU General Public License -+ * version 2. This program is licensed "as is" without any warranty of any -+ * kind, whether express or implied. -+ */ -+ -+#ifndef MT9T111_H -+#define MT9T111_H -+ -+/********************************* -+ * Defines and Macros and globals -+ ********************************/ -+ -+#ifdef TRUE -+#undef TRUE -+#endif -+ -+#ifdef FALSE -+#undef FALSE -+#endif -+ -+#define TRUE 1 -+#define FALSE 0 -+ -+#ifdef DEBUG -+#undef DEBUG -+#endif -+ -+#ifndef TYPES -+#define TYPES -+#endif -+ -+#define MT9T111_I2C_REGISTERED (1) -+#define MT9T111_I2C_UNREGISTERED (0) -+ -+/*i2c adress for MT9T111*/ -+#define MT9T111_I2C_ADDR (0x78 >>1) -+ -+#define MT9T111_CLK_MAX (75000000) /* 75MHz */ -+#define MT9T111_CLK_MIN (6000000) /* 6Mhz */ -+ -+#define MT9T111_I2C_CONFIG (1) -+#define I2C_ONE_BYTE_TRANSFER (1) -+#define I2C_TWO_BYTE_TRANSFER (2) -+#define I2C_THREE_BYTE_TRANSFER (3) -+#define I2C_FOUR_BYTE_TRANSFER (4) -+#define I2C_TXRX_DATA_MASK (0x00FF) -+#define I2C_TXRX_DATA_MASK_UPPER (0xFF00) -+#define I2C_TXRX_DATA_SHIFT (8) -+ -+struct mt9t111_platform_data { -+ char *master; -+ int (*power_set) (enum v4l2_power on); -+ int (*ifparm) (struct v4l2_ifparm *p); -+ int (*priv_data_set) (void *); -+ /* Interface control params */ -+ bool clk_polarity; -+ bool hs_polarity; -+ bool vs_polarity; -+}; -+ -+/** -+ * struct capture_size - image capture size information -+ * @width: image width in pixels -+ * @height: image height in pixels -+ */ -+struct capture_size { -+ unsigned long width; -+ unsigned long height; -+}; -+ -+#endif /*for ifndef MT9T111 */ -+ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0002-mt9t111-Fix-all-checkpatch-errors.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0002-mt9t111-Fix-all-checkpatch-errors.patch deleted file mode 100644 index 4fa44f00..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0002-mt9t111-Fix-all-checkpatch-errors.patch +++ /dev/null @@ -1,398 +0,0 @@ -From 5609c8fe642a0517bd151ad477fcd05d0abc7dc4 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 13:51:49 -0500 -Subject: [PATCH 02/75] mt9t111: Fix all checkpatch errors - -The code was plagued with checkpatch errors. Fix them! - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t111.c | 153 ++++++++++++++++++++----------------- - drivers/media/video/mt9t111_reg.h | 6 +- - include/media/mt9t111.h | 2 +- - 3 files changed, 87 insertions(+), 74 deletions(-) - -diff --git a/drivers/media/video/mt9t111.c b/drivers/media/video/mt9t111.c -index ecc5115..95e1508 100644 ---- a/drivers/media/video/mt9t111.c -+++ b/drivers/media/video/mt9t111.c -@@ -17,20 +17,21 @@ - #include - #include "mt9t111_reg.h" - --#define USE_RAW // YCbCr mode does not work yet --//#define COLOR_BAR // Create a Color bar test pattern, Blue, Green, Red, Grey -+/* YCbCr mode does not work yet */ -+#define USE_RAW -+/* Create a Color bar test pattern, Blue, Green, Red, Grey */ -+/* #define COLOR_BAR */ - - #define SENSOR_DETECTED 1 - #define SENSOR_NOT_DETECTED 0 - - static void mt9t111_loaddefault(struct i2c_client *client); - --/* --* as a place holder for further development --*/ -+/* -+ * as a place holder for further development -+ */ - static void debug_dummy(char *in_msg) - { -- - } - - /* list of image formats supported by mt9t111 sensor */ -@@ -55,8 +56,8 @@ const static struct v4l2_fmtdesc mt9t111_formats[] = { - * smallest image size to largest. - */ - const static struct capture_size mt9t111_sizes[] = { -- { 640, 480 }, --// { 2048, 1536} -+ { 640, 480 }, -+ /* { 2048, 1536} */ - }; - - #define NUM_CAPTURE_SIZE ARRAY_SIZE(mt9t111_sizes) -@@ -120,17 +121,17 @@ mt9t111_read_reg(struct i2c_client *client, u16 reg, u16 *val) - msg->addr = client->addr; - msg->flags = 0; - msg->len = 2; -- msg->buf = data; -+ msg->buf = data; - data[0] = (reg & 0xff00) >> 8; - data[1] = (reg & 0x00ff); - err = i2c_transfer(client->adapter, msg, 1); -- if (err >= 0) { -- msg->flags = I2C_M_RD; -- msg->len = 2; /* 2 byte read */ -- err = i2c_transfer(client->adapter, msg, 1); -- if (err >= 0) { -- *val = ((data[0] & 0x00ff) << 8) -- | (data[1] & 0x00ff); -+ if (err >= 0) { -+ msg->flags = I2C_M_RD; -+ msg->len = 2; /* 2 byte read */ -+ err = i2c_transfer(client->adapter, msg, 1); -+ if (err >= 0) { -+ *val = ((data[0] & 0x00ff) << 8) -+ | (data[1] & 0x00ff); - return 0; - } - } -@@ -159,7 +160,7 @@ mt9t111_write_reg(struct i2c_client *client, u16 reg, u16 val) - msg->len = 4; - msg->buf = data; - data[0] = (u8)((reg & 0xff00) >> 8); -- data[1] = (u8)(reg & 0x00ff); -+ data[1] = (u8)(reg & 0x00ff); - data[2] = (u8)((val & 0xff00) >> 8); - data[3] = (u8)(val & 0x00ff); - err = i2c_transfer(client->adapter, msg, 1); -@@ -171,7 +172,7 @@ mt9t111_write_reg(struct i2c_client *client, u16 reg, u16 val) - * mt9t111_write_regs - Write registers to an mt9t111 sensor device - * @client: i2c driver client structure - * @reg_in: pointer to registers to write -- * @cnt: the number of registers -+ * @cnt: the number of registers - * - * Write registers . - * Returns zero if successful, or non-zero otherwise. -@@ -182,19 +183,21 @@ mt9t111_write_regs(struct i2c_client *client, mt9t111_regs *reg_in, int cnt) - int err = 0; - int i; - mt9t111_regs *reg = reg_in; -- -- for (i=0;idelay_time == 0) { - err |= mt9t111_write_reg(client, reg->addr, reg->data); - } else if (reg->addr != 0 || reg->data != 0) { - err |= mt9t111_write_reg(client, reg->addr, reg->data); - mdelay(reg->delay_time); -- } else -+ } else { - mdelay(reg->delay_time); -- -+ } -+ - if (err < 0) { -- dev_warn(&client->dev, "write reg error, addr = 0x%x, data = 0x%x \n", \ -- reg->addr, reg->data); -+ dev_warn(&client->dev, "write reg error, addr = 0x%x," -+ " data = 0x%x \n", -+ reg->addr, reg->data); - return err; - } - reg++; -@@ -219,10 +222,11 @@ mt9t111_detect(struct i2c_client *client) - if (mt9t111_read_reg(client, MT9T111_CHIP_ID, &val) < 0) - return -ENODEV; - dev_info(&client->dev, "model id detected 0x%x\n", val); -- -+ - if (val != MT9T111_CHIP_ID_VALUE) { -- dev_warn(&client->dev, "model id mismatch received 0x%x expecting 0x%x\n", -- val, MT9T111_CHIP_ID_VALUE); -+ dev_warn(&client->dev, "model id mismatch received 0x%x" -+ " expecting 0x%x\n", -+ val, MT9T111_CHIP_ID_VALUE); - - return -ENODEV; - } -@@ -285,14 +289,17 @@ static int ioctl_enum_frameintervals(struct v4l2_int_device *s, - { - int ifmt; - --printk(KERN_INFO "entering ioctl_enum_frameintervals\n"); --printk(KERN_INFO "index = %d, pixel_format = 0x%x, width = %d, height = %d\n", -- frmi->index, frmi->pixel_format, frmi->width, frmi->height); --printk(KERN_INFO "mt9t111 format = 0x%x\n", mt9t111_formats[0].pixelformat); -+ printk(KERN_INFO "entering ioctl_enum_frameintervals\n"); -+ printk(KERN_INFO "index = %d, pixel_format = 0x%x," -+ " width = %d, height = %d\n", -+ frmi->index, frmi->pixel_format, -+ frmi->width, frmi->height); -+ printk(KERN_INFO "mt9t111 format = 0x%x\n", -+ mt9t111_formats[0].pixelformat); - - if (frmi->index >= NUM_CAPTURE_FRAMEINTERVALS) - return -EINVAL; -- -+ - for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) { - if (frmi->pixel_format == mt9t111_formats[ifmt].pixelformat) - break; -@@ -368,7 +375,7 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - if (rval < 0) { - dev_err(&c->dev, "Unable to set the power state: " "mt9t111" - " sensor\n"); -- //sensor->pdata->set_xclk(0); -+ /* sensor->pdata->set_xclk(0); */ - return rval; - } - -@@ -418,7 +425,7 @@ static int ioctl_g_priv(struct v4l2_int_device *s, void *p) - static int ioctl_s_parm(struct v4l2_int_device *s, - struct v4l2_streamparm *a) - { -- //TODO: set paramters -+ /* TODO: set paramters */ - debug_dummy("debug_dummy -- VIDIOC_S_PARM "); - return 0; - } -@@ -483,13 +490,13 @@ static int ioctl_try_fmt_cap(struct v4l2_int_device *s, - - pix->width = 640; - pix->height = 480; --#ifdef USE_RAW -+#ifdef USE_RAW - pix->pixelformat = V4L2_PIX_FMT_SGRBG10; -- pix->bytesperline = pix->width; -+ pix->bytesperline = pix->width; - pix->colorspace = V4L2_COLORSPACE_SRGB; - #else - pix->pixelformat = V4L2_PIX_FMT_YUYV; -- pix->bytesperline = pix->width * 2; -+ pix->bytesperline = pix->width * 2; - pix->colorspace = V4L2_COLORSPACE_JPEG; - #endif - pix->field = V4L2_FIELD_NONE; -@@ -585,7 +592,7 @@ static int ioctl_s_ctrl(struct v4l2_int_device *s, - static int ioctl_g_ctrl(struct v4l2_int_device *s, - struct v4l2_control *vc) - { -- debug_dummy("debug_dummy -- g ctrl\n"); -+ debug_dummy("debug_dummy -- g ctrl\n"); - return 0; - } - -@@ -601,8 +608,8 @@ static int ioctl_g_ctrl(struct v4l2_int_device *s, - static int ioctl_queryctrl(struct v4l2_int_device *s, - struct v4l2_queryctrl *qc) - { -- debug_dummy("debug_dummy -- query ctrl\n"); -- return-EINVAL; -+ debug_dummy("debug_dummy -- query ctrl\n"); -+ return -EINVAL; - } - - /** -@@ -647,12 +654,11 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) - return rval; - } - -- p->u.ycbcr.clock_curr = 40*1000000; // temporal value -+ p->u.ycbcr.clock_curr = 40 * 1000000; /* temporal value */ - - return 0; - } - -- - static struct v4l2_int_ioctl_desc mt9t111_ioctl_desc[] = { - { .num = vidioc_int_enum_framesizes_num, - .func = (v4l2_int_ioctl_func *)ioctl_enum_framesizes }, -@@ -666,8 +672,8 @@ static struct v4l2_int_ioctl_desc mt9t111_ioctl_desc[] = { - .func = (v4l2_int_ioctl_func *)ioctl_s_power }, - { .num = vidioc_int_g_priv_num, - .func = (v4l2_int_ioctl_func *)ioctl_g_priv }, -- {vidioc_int_g_ifparm_num, -- .func = (v4l2_int_ioctl_func*) ioctl_g_ifparm}, -+ { .num = vidioc_int_g_ifparm_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_g_ifparm }, - { .num = vidioc_int_init_num, - .func = (v4l2_int_ioctl_func *)ioctl_init }, - { .num = vidioc_int_enum_fmt_cap_num, -@@ -688,29 +694,30 @@ static struct v4l2_int_ioctl_desc mt9t111_ioctl_desc[] = { - .func = (v4l2_int_ioctl_func *)ioctl_g_ctrl }, - { .num = vidioc_int_s_ctrl_num, - .func = (v4l2_int_ioctl_func *)ioctl_s_ctrl }, -- {.num = vidioc_int_s_video_routing_num, -- .func = (v4l2_int_ioctl_func *) ioctl_s_routing}, -+ { .num = vidioc_int_s_video_routing_num, -+ .func = (v4l2_int_ioctl_func *)ioctl_s_routing }, - }; - --static void mt9t111_refresh(struct i2c_client *client){ -- int i; -- unsigned short value; -- // MCU_ADDRESS [SEQ_CMD] -- refresh -- mt9t111_write_reg(client, 0x098E, 0x8400); -- mt9t111_write_reg(client, 0x0990, 0x0006); -- for (i=0;i<100;i++){ -- mt9t111_write_reg(client, 0x098E, 0x8400); -- mt9t111_read_reg(client,0x0990,&value); -- if ( value == 0) -- break; -- mdelay(5); -+static void mt9t111_refresh(struct i2c_client *client) -+{ -+ int i; -+ unsigned short value; -+ /* MCU_ADDRESS [SEQ_CMD] -- refresh */ -+ mt9t111_write_reg(client, 0x098E, 0x8400); -+ mt9t111_write_reg(client, 0x0990, 0x0006); -+ for (i = 0; i < 100; i++) { -+ mt9t111_write_reg(client, 0x098E, 0x8400); -+ mt9t111_read_reg(client, 0x0990, &value); -+ if (value == 0) -+ break; -+ mdelay(5); - } - } - - #ifdef COLOR_BAR - static void mt9t111_color_bar(struct i2c_client *client) - { -- mt9t111_write_reg(client, 0x3210, 0x01B0); // disable lens correction -+ mt9t111_write_reg(client, 0x3210, 0x01B0); /* disable lens correction */ - - mt9t111_write_reg(client, 0x098E, 0x6003); - mt9t111_write_reg(client, 0x0990, 0x0100); -@@ -721,22 +728,25 @@ static void mt9t111_color_bar(struct i2c_client *client) - - static void mt9t111_bayer_format(struct i2c_client *client) - { -- mt9t111_write_regs(client, bayer_pattern_regs, sizeof(bayer_pattern_regs)/sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, bayer_pattern_regs, -+ sizeof(bayer_pattern_regs) / sizeof(mt9t111_regs)); - } - - static void mt9t111_enable_pll(struct i2c_client *client) - { - int i; -- unsigned short value; -+ unsigned short value; - -- mt9t111_write_regs(client, pll_regs1, sizeof(pll_regs1)/sizeof(mt9t111_regs)); -- for (i=0;i<100;i++){ -- mt9t111_read_reg(client,0x0014,&value); -- if (( value & 0x8000) != 0) -+ mt9t111_write_regs(client, pll_regs1, -+ sizeof(pll_regs1) / sizeof(mt9t111_regs)); -+ for (i = 0; i < 100; i++) { -+ mt9t111_read_reg(client, 0x0014, &value); -+ if ((value & 0x8000) != 0) - break; - mdelay(2); - } -- mt9t111_write_regs(client, pll_regs2, sizeof(pll_regs2)/sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, pll_regs2, -+ sizeof(pll_regs2) / sizeof(mt9t111_regs)); - } - - -@@ -746,9 +756,12 @@ static void mt9t111_loaddefault(struct i2c_client *client) - mt9t111_write_reg(client, 0x001A, 0x0218); - - mt9t111_enable_pll(client); -- mt9t111_write_regs(client, def_regs1, sizeof(def_regs1)/sizeof(mt9t111_regs)); -- mt9t111_write_regs(client, patch_rev6, sizeof(patch_rev6)/sizeof(mt9t111_regs)); -- mt9t111_write_regs(client, def_regs2, sizeof(def_regs2)/sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, def_regs1, -+ sizeof(def_regs1) / sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, patch_rev6, -+ sizeof(patch_rev6) / sizeof(mt9t111_regs)); -+ mt9t111_write_regs(client, def_regs2, -+ sizeof(def_regs2) / sizeof(mt9t111_regs)); - - #ifdef USE_RAW - mt9t111_bayer_format(client); -@@ -806,7 +819,7 @@ mt9t111_probe(struct i2c_client *client, const struct i2c_device_id *id) - - sensor->pix.width = 640; - sensor->pix.height = 480; --#ifdef USE_RAW -+#ifdef USE_RAW - sensor->pix.pixelformat = V4L2_PIX_FMT_SGRBG10; - #else - sensor->pix.pixelformat = V4L2_PIX_FMT_YUYV; -diff --git a/drivers/media/video/mt9t111_reg.h b/drivers/media/video/mt9t111_reg.h -index e012eeb..e226c37 100644 ---- a/drivers/media/video/mt9t111_reg.h -+++ b/drivers/media/video/mt9t111_reg.h -@@ -25,7 +25,7 @@ typedef struct { - u16 data; - } mt9t111_regs; - --mt9t111_regs patch_rev6[] ={ -+mt9t111_regs patch_rev6[] = { - {0, 0x0982, 0x0}, - {0, 0x098A, 0xCE7}, - {0, 0x0990, 0x3C3C}, -@@ -658,7 +658,7 @@ mt9t111_regs patch_rev6[] ={ - {100, 0x0990, 0x0004} - }; - --mt9t111_regs def_regs1[] ={ -+mt9t111_regs def_regs1[] = { - {0, 0x001A, 0x0218}, - {0, 0x001E, 0x0777}, - {0, 0x3084, 0x2409}, -@@ -1343,7 +1343,7 @@ mt9t111_regs pll_regs2[] = { - {0, 0x0014, 0x3046}, - {0, 0x0022, 0x01E0}, - {0, 0x001E, 0x0707}, -- {0, 0x3B84, 0x011D} -+ {0, 0x3B84, 0x011D} - }; - - mt9t111_regs bayer_pattern_regs[] = { -diff --git a/include/media/mt9t111.h b/include/media/mt9t111.h -index 7acbeed..0a5161a 100644 ---- a/include/media/mt9t111.h -+++ b/include/media/mt9t111.h -@@ -40,7 +40,7 @@ - #define MT9T111_I2C_UNREGISTERED (0) - - /*i2c adress for MT9T111*/ --#define MT9T111_I2C_ADDR (0x78 >>1) -+#define MT9T111_I2C_ADDR (0x78 >> 1) - - #define MT9T111_CLK_MAX (75000000) /* 75MHz */ - #define MT9T111_CLK_MIN (6000000) /* 6Mhz */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0003-mt9t111-Pass-v4l2_int_device-data.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0003-mt9t111-Pass-v4l2_int_device-data.patch deleted file mode 100644 index 0c6b90aa..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0003-mt9t111-Pass-v4l2_int_device-data.patch +++ /dev/null @@ -1,40 +0,0 @@ -From bb40914cf9e313d70385e647f956a55df15e717f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 16:17:56 -0500 -Subject: [PATCH 03/75] mt9t111: Pass v4l2_int_device data - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t111.c | 2 +- - include/media/mt9t111.h | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/video/mt9t111.c b/drivers/media/video/mt9t111.c -index 95e1508..6a7b2c0 100644 ---- a/drivers/media/video/mt9t111.c -+++ b/drivers/media/video/mt9t111.c -@@ -371,7 +371,7 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - else - debug_dummy("debug_dummy -- enable clock\n");; - -- rval = sensor->pdata->power_set(on); -+ rval = sensor->pdata->power_set(s, on); - if (rval < 0) { - dev_err(&c->dev, "Unable to set the power state: " "mt9t111" - " sensor\n"); -diff --git a/include/media/mt9t111.h b/include/media/mt9t111.h -index 0a5161a..aae3f99 100644 ---- a/include/media/mt9t111.h -+++ b/include/media/mt9t111.h -@@ -56,7 +56,7 @@ - - struct mt9t111_platform_data { - char *master; -- int (*power_set) (enum v4l2_power on); -+ int (*power_set) (struct v4l2_int_device *s, enum v4l2_power on); - int (*ifparm) (struct v4l2_ifparm *p); - int (*priv_data_set) (void *); - /* Interface control params */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0004-omap3beagle-Add-camera-support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0004-omap3beagle-Add-camera-support.patch deleted file mode 100644 index 511bd93c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0004-omap3beagle-Add-camera-support.patch +++ /dev/null @@ -1,352 +0,0 @@ -From 8b7b00860ac8c558c7156ff676655942027f7f53 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 16:15:58 -0500 -Subject: [PATCH 04/75] omap3beagle: Add camera support - -This is tested with the xM + Leopard imaging module camera, which -has a MT9T111. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/Makefile | 3 +- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 228 ++++++++++++++++++++++++ - arch/arm/mach-omap2/board-omap3beagle-camera.h | 41 +++++ - arch/arm/mach-omap2/board-omap3beagle.c | 25 +++ - 4 files changed, 296 insertions(+), 1 deletions(-) - create mode 100644 arch/arm/mach-omap2/board-omap3beagle-camera.c - create mode 100644 arch/arm/mach-omap2/board-omap3beagle-camera.h - -diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile -index 9042317..a49d436 100644 ---- a/arch/arm/mach-omap2/Makefile -+++ b/arch/arm/mach-omap2/Makefile -@@ -87,7 +87,8 @@ obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \ - mmc-twl4030.o - obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o - obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \ -- mmc-twl4030.o -+ mmc-twl4030.o \ -+ board-omap3beagle-camera.o - obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ - mmc-twl4030.o \ - board-ldp-camera.o -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -new file mode 100644 -index 0000000..e93437f ---- /dev/null -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -0,0 +1,228 @@ -+/* -+ * Driver for Leopard Module Board used in Beagleboard (xM) -+ * -+ * Copyright (C) 2010 Texas Instruments Inc -+ * Author: Sergio Aguirre -+ * -+ * Based on work done by: -+ * Vaibhav Hiremath -+ * Anuj Aggarwal -+ * Sivaraj R -+ * -+ * This package is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+ -+/* Include V4L2 ISP-Camera driver related header file */ -+#include <../drivers/media/video/omap34xxcam.h> -+#include <../drivers/media/video/isp/ispreg.h> -+ -+#include "mux.h" -+#include "board-omap3beagle-camera.h" -+ -+#define MODULE_NAME "omap3beaglelmb" -+ -+#define MT9T111_I2C_BUSNUM (2) -+ -+#define CAM_USE_XCLKA 1 -+ -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+static struct isp_interface_config mt9t111_if_config = { -+ .ccdc_par_ser = ISP_PARLL, -+ .dataline_shift = 0x0, -+ .hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE, -+ .strobe = 0x0, -+ .prestrobe = 0x0, -+ .shutter = 0x0, -+ .u.par.par_bridge = 0x1, -+ .u.par.par_clk_pol = 0x0, -+}; -+ -+static struct v4l2_ifparm mt9t111_ifparm_s = { -+#if 1 -+ .if_type = V4L2_IF_TYPE_RAW, -+ .u = { -+ .raw = { -+ .frame_start_on_rising_vs = 1, -+ .bt_sync_correct = 0, -+ .swap = 0, -+ .latch_clk_inv = 0, -+ .nobt_hs_inv = 0, /* active high */ -+ .nobt_vs_inv = 0, /* active high */ -+ .clock_min = MT9T111_CLK_MIN, -+ .clock_max = MT9T111_CLK_MAX, -+ }, -+ }, -+#else -+ .if_type = V4L2_IF_TYPE_YCbCr, -+ .u = { -+ .ycbcr = { -+ .frame_start_on_rising_vs = 1, -+ .bt_sync_correct = 0, -+ .swap = 0, -+ .latch_clk_inv = 0, -+ .nobt_hs_inv = 0, /* active high */ -+ .nobt_vs_inv = 0, /* active high */ -+ .clock_min = MT9T111_CLK_MIN, -+ .clock_max = MT9T111_CLK_MAX, -+ }, -+ }, -+#endif -+}; -+ -+/** -+ * @brief mt9t111_ifparm - Returns the mt9t111 interface parameters -+ * -+ * @param p - pointer to v4l2_ifparm structure -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9t111_ifparm(struct v4l2_ifparm *p) -+{ -+ if (p == NULL) -+ return -EINVAL; -+ -+ *p = mt9t111_ifparm_s; -+ return 0; -+} -+ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+static struct omap34xxcam_hw_config mt9t111_hwc = { -+ .dev_index = 0, -+ .dev_minor = 0, -+ .dev_type = OMAP34XXCAM_SLAVE_SENSOR, -+ .u.sensor.sensor_isp = 1, -+}; -+#endif -+ -+/** -+ * @brief mt9t111_set_prv_data - Returns mt9t111 omap34xx driver private data -+ * -+ * @param priv - pointer to omap34xxcam_hw_config structure -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9t111_set_prv_data(void *priv) -+{ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+ struct omap34xxcam_hw_config *hwc = priv; -+ -+ if (priv == NULL) -+ return -EINVAL; -+ -+ hwc->u.sensor = mt9t111_hwc.u.sensor; -+ hwc->dev_index = mt9t111_hwc.dev_index; -+ hwc->dev_minor = mt9t111_hwc.dev_minor; -+ hwc->dev_type = mt9t111_hwc.dev_type; -+ return 0; -+#else -+ return -EINVAL; -+#endif -+} -+ -+/** -+ * @brief mt9t111_power_set - Power-on or power-off TVP5146 device -+ * -+ * @param power - enum, Power on/off, resume/standby -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) -+{ -+ struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; -+ -+ switch (power) { -+ case V4L2_POWER_OFF: -+ isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); -+ break; -+ -+ case V4L2_POWER_STANDBY: -+ break; -+ -+ case V4L2_POWER_ON: -+ isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); -+ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+ isp_configure_interface(vdev->cam->isp, &mt9t111_if_config); -+#endif -+ break; -+ -+ default: -+ return -ENODEV; -+ break; -+ } -+ return 0; -+} -+ -+static struct mt9t111_platform_data mt9t111_pdata = { -+ .master = "omap34xxcam", -+ .power_set = mt9t111_power_set, -+ .priv_data_set = mt9t111_set_prv_data, -+ .ifparm = mt9t111_ifparm, -+ /* Some interface dependent params */ -+ .clk_polarity = 0, /* data clocked out on falling edge */ -+ .hs_polarity = 1, /* 0 - Active low, 1- Active high */ -+ .vs_polarity = 1, /* 0 - Active low, 1- Active high */ -+}; -+ -+static struct i2c_board_info __initdata mt9t111_i2c_board_info = { -+ I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), -+ .platform_data = &mt9t111_pdata, -+}; -+ -+#endif /* #ifdef CONFIG_VIDEO_MT9T111 */ -+ -+/** -+ * @brief omap3beaglelmb_init - module init function. Should be called before any -+ * client driver init call -+ * -+ * @return result of operation - 0 is success -+ */ -+int __init omap3beaglelmb_init(void) -+{ -+ int err; -+ -+ /* -+ * Register the I2C devices present in the board to the I2C -+ * framework. -+ * If more I2C devices are added, then each device information should -+ * be registered with I2C using i2c_register_board_info(). -+ */ -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+ err = i2c_register_board_info(MT9T111_I2C_BUSNUM, -+ &mt9t111_i2c_board_info, 1); -+ if (err) { -+ printk(KERN_ERR MODULE_NAME \ -+ ": MT9T111 I2C Board Registration failed \n"); -+ return err; -+ } -+#endif -+ printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); -+ -+ return 0; -+} -+arch_initcall(omap3beaglelmb_init); -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.h b/arch/arm/mach-omap2/board-omap3beagle-camera.h -new file mode 100644 -index 0000000..1026aeb ---- /dev/null -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.h -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (C) 2010 Texas Instruments Inc -+ * Author: Sergio Aguirre -+ * -+ * Based on work done by: -+ * Vaibhav Hiremath -+ * Anuj Aggarwal -+ * Sivaraj R -+ * -+ * This package is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef __BOARD_OMAP3BEAGLE_LMB_H_ -+#define __BOARD_OMAP3BEAGLE_LMB_H_ -+ -+/* mux id to enable/disable signal routing to different peripherals */ -+enum omap3beaglelmb_mux { -+ MUX_TVP5146 = 0, -+ MUX_CAMERA_SENSOR, -+ MUX_EXP_CAMERA_SENSOR, -+ NUM_MUX -+}; -+ -+/* enum to enable or disable mux */ -+enum config_mux { -+ DISABLE_MUX, -+ ENABLE_MUX -+}; -+ -+#endif /* __BOARD_OMAP3BEAGLE_LMB_H_ */ -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index b313350..d6b69a6 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -712,6 +712,31 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - - #ifdef CONFIG_OMAP_MUX - static struct omap_board_mux board_mux[] __initdata = { -+ /* Camera - Parallel Data */ -+ OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D10, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_D11, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ -+ /* Camera - HS/VS signals */ -+ OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), -+ -+ /* Camera - Reset GPIO 98 */ -+ OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), -+ -+ /* Camera - XCLK */ -+ OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), -+ - { .reg_offset = OMAP_MUX_TERMINATOR }, - }; - #else --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0005-TEMP-omap3beagle-camera-Add-defconfig.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0005-TEMP-omap3beagle-camera-Add-defconfig.patch deleted file mode 100644 index b14321ba..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0005-TEMP-omap3beagle-camera-Add-defconfig.patch +++ /dev/null @@ -1,3070 +0,0 @@ -From 754e3fe541b0784ed84282b95268fbb9c68d65c5 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 16:18:30 -0500 -Subject: [PATCH 05/75] TEMP: omap3beagle: camera: Add defconfig - -Signed-off-by: Sergio Aguirre ---- - arch/arm/configs/omap3_beagle_cam_defconfig | 3050 +++++++++++++++++++++++++++ - 1 files changed, 3050 insertions(+), 0 deletions(-) - create mode 100644 arch/arm/configs/omap3_beagle_cam_defconfig - -diff --git a/arch/arm/configs/omap3_beagle_cam_defconfig b/arch/arm/configs/omap3_beagle_cam_defconfig -new file mode 100644 -index 0000000..0ea8300 ---- /dev/null -+++ b/arch/arm/configs/omap3_beagle_cam_defconfig -@@ -0,0 +1,3050 @@ -+# -+# Automatically generated make config: don't edit -+# Linux kernel version: 2.6.32 -+# Fri Jun 11 14:25:23 2010 -+# -+CONFIG_ARM=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_GENERIC_GPIO=y -+CONFIG_GENERIC_TIME=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_GENERIC_HARDIRQS=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_HAVE_LATENCYTOP_SUPPORT=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_RWSEM_GENERIC_SPINLOCK=y -+CONFIG_ARCH_HAS_CPUFREQ=y -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -+CONFIG_OPROFILE_ARMV7=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+CONFIG_CONSTRUCTORS=y -+ -+# -+# General setup -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_BROKEN_ON_SMP=y -+CONFIG_LOCK_KERNEL=y -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_LOCALVERSION="" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+# CONFIG_POSIX_MQUEUE is not set -+CONFIG_BSD_PROCESS_ACCT=y -+# CONFIG_BSD_PROCESS_ACCT_V3 is not set -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+# CONFIG_AUDIT is not set -+ -+# -+# RCU Subsystem -+# -+CONFIG_TREE_RCU=y -+# CONFIG_TREE_PREEMPT_RCU is not set -+# CONFIG_TINY_RCU is not set -+# CONFIG_RCU_TRACE is not set -+CONFIG_RCU_FANOUT=32 -+# CONFIG_RCU_FANOUT_EXACT is not set -+# CONFIG_TREE_RCU_TRACE is not set -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_LOG_BUF_SHIFT=16 -+CONFIG_GROUP_SCHED=y -+CONFIG_FAIR_GROUP_SCHED=y -+# CONFIG_RT_GROUP_SCHED is not set -+CONFIG_USER_SCHED=y -+# CONFIG_CGROUP_SCHED is not set -+# CONFIG_CGROUPS is not set -+# CONFIG_SYSFS_DEPRECATED_V2 is not set -+# CONFIG_RELAY is not set -+# CONFIG_NAMESPACES is not set -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_RD_GZIP=y -+# CONFIG_RD_BZIP2 is not set -+# CONFIG_RD_LZMA is not set -+CONFIG_CC_OPTIMIZE_FOR_SIZE=y -+CONFIG_SYSCTL=y -+CONFIG_ANON_INODES=y -+CONFIG_EMBEDDED=y -+CONFIG_UID16=y -+# CONFIG_SYSCTL_SYSCALL is not set -+CONFIG_KALLSYMS=y -+# CONFIG_KALLSYMS_ALL is not set -+# CONFIG_KALLSYMS_EXTRA_PASS is not set -+CONFIG_HOTPLUG=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+# CONFIG_ELF_CORE is not set -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+CONFIG_SHMEM=y -+CONFIG_AIO=y -+ -+# -+# Kernel Performance Events And Counters -+# -+CONFIG_VM_EVENT_COUNTERS=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_SLAB=y -+# CONFIG_SLUB is not set -+# CONFIG_SLOB is not set -+CONFIG_PROFILING=y -+CONFIG_TRACEPOINTS=y -+CONFIG_OPROFILE=y -+CONFIG_HAVE_OPROFILE=y -+# CONFIG_KPROBES is not set -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+CONFIG_HAVE_CLK=y -+ -+# -+# GCOV-based kernel profiling -+# -+# CONFIG_GCOV_KERNEL is not set -+CONFIG_SLOW_WORK=y -+# CONFIG_SLOW_WORK_DEBUG is not set -+CONFIG_HAVE_GENERIC_DMA_COHERENT=y -+CONFIG_SLABINFO=y -+CONFIG_RT_MUTEXES=y -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_BLOCK=y -+CONFIG_LBDAF=y -+CONFIG_BLK_DEV_BSG=y -+# CONFIG_BLK_DEV_INTEGRITY is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+# CONFIG_DEFAULT_DEADLINE is not set -+CONFIG_DEFAULT_CFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="cfq" -+# CONFIG_INLINE_SPIN_TRYLOCK is not set -+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -+# CONFIG_INLINE_SPIN_LOCK is not set -+# CONFIG_INLINE_SPIN_LOCK_BH is not set -+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -+# CONFIG_INLINE_SPIN_UNLOCK is not set -+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -+# CONFIG_INLINE_READ_TRYLOCK is not set -+# CONFIG_INLINE_READ_LOCK is not set -+# CONFIG_INLINE_READ_LOCK_BH is not set -+# CONFIG_INLINE_READ_LOCK_IRQ is not set -+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -+# CONFIG_INLINE_READ_UNLOCK is not set -+# CONFIG_INLINE_READ_UNLOCK_BH is not set -+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -+# CONFIG_INLINE_WRITE_TRYLOCK is not set -+# CONFIG_INLINE_WRITE_LOCK is not set -+# CONFIG_INLINE_WRITE_LOCK_BH is not set -+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -+# CONFIG_INLINE_WRITE_UNLOCK is not set -+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -+# CONFIG_MUTEX_SPIN_ON_OWNER is not set -+CONFIG_FREEZER=y -+ -+# -+# System Type -+# -+CONFIG_MMU=y -+# CONFIG_ARCH_AAEC2000 is not set -+# CONFIG_ARCH_INTEGRATOR is not set -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_GEMINI is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_MXC is not set -+# CONFIG_ARCH_STMP3XXX is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_H720X is not set -+# CONFIG_ARCH_NOMADIK is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IXP23XX is not set -+# CONFIG_ARCH_IXP2000 is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_L7200 is not set -+# CONFIG_ARCH_DOVE is not set -+# CONFIG_ARCH_KIRKWOOD is not set -+# CONFIG_ARCH_LOKI is not set -+# CONFIG_ARCH_MV78XX0 is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_MMP is not set -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_NS9XXX is not set -+# CONFIG_ARCH_W90X900 is not set -+# CONFIG_ARCH_PNX4008 is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_MSM is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C2410 is not set -+# CONFIG_ARCH_S3C64XX is not set -+# CONFIG_ARCH_S5PC1XX is not set -+# CONFIG_ARCH_SHARK is not set -+# CONFIG_ARCH_LH7A40X is not set -+# CONFIG_ARCH_U300 is not set -+# CONFIG_ARCH_DAVINCI is not set -+CONFIG_ARCH_OMAP=y -+# CONFIG_ARCH_BCMRING is not set -+# CONFIG_ARCH_U8500 is not set -+ -+# -+# TI OMAP Implementations -+# -+CONFIG_ARCH_OMAP_OTG=y -+# CONFIG_ARCH_OMAP1 is not set -+# CONFIG_ARCH_OMAP2 is not set -+CONFIG_ARCH_OMAP3=y -+# CONFIG_ARCH_OMAP4 is not set -+ -+# -+# OMAP Feature Selections -+# -+CONFIG_OMAP_SMARTREFLEX=y -+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -+CONFIG_OMAP_RESET_CLOCKS=y -+# CONFIG_OMAP_MUX is not set -+CONFIG_OMAP_MCBSP=y -+CONFIG_OMAP_MBOX_FWK=m -+CONFIG_OMAP_IOMMU=y -+# CONFIG_OMAP_MPU_TIMER is not set -+CONFIG_OMAP_32K_TIMER=y -+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -+# CONFIG_OMAP3_DEBOBS is not set -+CONFIG_OMAP_32K_TIMER_HZ=128 -+CONFIG_OMAP_DM_TIMER=y -+# CONFIG_OMAP_LL_DEBUG_UART1 is not set -+# CONFIG_OMAP_LL_DEBUG_UART2 is not set -+CONFIG_OMAP_LL_DEBUG_UART3=y -+# CONFIG_OMAP_LL_DEBUG_NONE is not set -+# CONFIG_OMAP_PM_NONE is not set -+# CONFIG_OMAP_PM_NOOP is not set -+CONFIG_OMAP_PM_SRF=y -+CONFIG_ARCH_OMAP34XX=y -+CONFIG_ARCH_OMAP3430=y -+CONFIG_OMAP_PACKAGE_CBB=y -+ -+# -+# OMAP Board Type -+# -+CONFIG_MACH_OMAP3_BEAGLE=y -+# CONFIG_MACH_OMAP_LDP is not set -+# CONFIG_MACH_OVERO is not set -+CONFIG_MACH_OMAP3EVM=y -+CONFIG_PMIC_TWL4030=y -+# CONFIG_MACH_OMAP3517EVM is not set -+# CONFIG_MACH_OMAP3_PANDORA is not set -+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -+# CONFIG_MACH_OMAP_3430SDP is not set -+# CONFIG_MACH_NOKIA_RX51 is not set -+# CONFIG_MACH_OMAP_ZOOM2 is not set -+# CONFIG_MACH_OMAP_ZOOM3 is not set -+# CONFIG_MACH_CM_T35 is not set -+# CONFIG_MACH_IGEP0020 is not set -+# CONFIG_MACH_OMAP_3630SDP is not set -+# CONFIG_OMAP3_EMU is not set -+# CONFIG_OMAP3_SDRC_AC_TIMING is not set -+ -+# -+# Processor Type -+# -+CONFIG_CPU_32=y -+CONFIG_CPU_32v6K=y -+CONFIG_CPU_V7=y -+CONFIG_CPU_32v7=y -+CONFIG_CPU_ABRT_EV7=y -+CONFIG_CPU_PABRT_V7=y -+CONFIG_CPU_CACHE_V7=y -+CONFIG_CPU_CACHE_VIPT=y -+CONFIG_CPU_COPY_V6=y -+CONFIG_CPU_TLB_V7=y -+CONFIG_CPU_HAS_ASID=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+CONFIG_ARM_THUMB=y -+CONFIG_ARM_THUMBEE=y -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_DCACHE_DISABLE is not set -+# CONFIG_CPU_BPREDICT_DISABLE is not set -+CONFIG_HAS_TLS_REG=y -+CONFIG_ARM_L1_CACHE_SHIFT=6 -+CONFIG_USER_L2_PLE=y -+CONFIG_USER_PMON=y -+# CONFIG_ARM_ERRATA_430973 is not set -+# CONFIG_ARM_ERRATA_458693 is not set -+# CONFIG_ARM_ERRATA_460075 is not set -+CONFIG_COMMON_CLKDEV=y -+ -+# -+# Bus support -+# -+# CONFIG_PCI_SYSCALL is not set -+# CONFIG_ARCH_SUPPORTS_MSI is not set -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -+CONFIG_VMSPLIT_3G=y -+# CONFIG_VMSPLIT_2G is not set -+# CONFIG_VMSPLIT_1G is not set -+CONFIG_PAGE_OFFSET=0xC0000000 -+# CONFIG_PREEMPT_NONE is not set -+# CONFIG_PREEMPT_VOLUNTARY is not set -+CONFIG_PREEMPT=y -+CONFIG_HZ=128 -+# CONFIG_THUMB2_KERNEL is not set -+CONFIG_AEABI=y -+# CONFIG_OABI_COMPAT is not set -+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -+# CONFIG_HIGHMEM is not set -+CONFIG_SELECT_MEMORY_MODEL=y -+CONFIG_FLATMEM_MANUAL=y -+# CONFIG_DISCONTIGMEM_MANUAL is not set -+# CONFIG_SPARSEMEM_MANUAL is not set -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+CONFIG_PAGEFLAGS_EXTENDED=y -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+# CONFIG_PHYS_ADDR_T_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=0 -+CONFIG_VIRT_TO_BUS=y -+# CONFIG_KSM is not set -+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -+CONFIG_LEDS=y -+CONFIG_ALIGNMENT_TRAP=y -+# CONFIG_UACCESS_WITH_MEMCPY is not set -+CONFIG_CPU_V7_SYSFS=y -+ -+# -+# Boot options -+# -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE=" debug " -+# CONFIG_XIP_KERNEL is not set -+CONFIG_KEXEC=y -+CONFIG_ATAGS_PROC=y -+ -+# -+# CPU Power Management -+# -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_TABLE=y -+CONFIG_CPU_FREQ_DEBUG=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+# CONFIG_CPU_IDLE is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+CONFIG_VFP=y -+CONFIG_VFPv3=y -+CONFIG_NEON=y -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+CONFIG_HAVE_AOUT=y -+CONFIG_BINFMT_AOUT=m -+CONFIG_BINFMT_MISC=y -+ -+# -+# Power management options -+# -+CONFIG_PM=y -+CONFIG_PM_DEBUG=y -+# CONFIG_PM_VERBOSE is not set -+CONFIG_CAN_PM_TRACE=y -+CONFIG_PM_SLEEP=y -+CONFIG_SUSPEND=y -+CONFIG_SUSPEND_FREEZER=y -+# CONFIG_APM_EMULATION is not set -+CONFIG_PM_RUNTIME=y -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_MMAP=y -+CONFIG_UNIX=y -+CONFIG_XFRM=y -+# CONFIG_XFRM_USER is not set -+# CONFIG_XFRM_SUB_POLICY is not set -+# CONFIG_XFRM_MIGRATE is not set -+# CONFIG_XFRM_STATISTICS is not set -+CONFIG_XFRM_IPCOMP=m -+CONFIG_NET_KEY=y -+# CONFIG_NET_KEY_MIGRATE is not set -+CONFIG_INET=y -+# CONFIG_IP_MULTICAST is not set -+# CONFIG_IP_ADVANCED_ROUTER is not set -+CONFIG_IP_FIB_HASH=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+CONFIG_IP_PNP_RARP=y -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE=m -+# CONFIG_ARPD is not set -+# CONFIG_SYN_COOKIES is not set -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_TUNNEL=m -+CONFIG_INET_TUNNEL=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=y -+CONFIG_INET_XFRM_MODE_TUNNEL=y -+CONFIG_INET_XFRM_MODE_BEET=y -+CONFIG_INET_LRO=y -+CONFIG_INET_DIAG=m -+CONFIG_INET_TCP_DIAG=m -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_BIC=m -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_TCP_CONG_WESTWOOD=m -+CONFIG_TCP_CONG_HTCP=m -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_VEGAS=m -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_YEAH=m -+CONFIG_TCP_CONG_ILLINOIS=m -+# CONFIG_DEFAULT_BIC is not set -+CONFIG_DEFAULT_CUBIC=y -+# CONFIG_DEFAULT_HTCP is not set -+# CONFIG_DEFAULT_VEGAS is not set -+# CONFIG_DEFAULT_WESTWOOD is not set -+# CONFIG_DEFAULT_RENO is not set -+CONFIG_DEFAULT_TCP_CONG="cubic" -+# CONFIG_TCP_MD5SIG is not set -+CONFIG_IPV6=m -+# CONFIG_IPV6_PRIVACY is not set -+# CONFIG_IPV6_ROUTER_PREF is not set -+# CONFIG_IPV6_OPTIMISTIC_DAD is not set -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=m -+CONFIG_INET6_XFRM_TUNNEL=m -+CONFIG_INET6_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_TRANSPORT=m -+CONFIG_INET6_XFRM_MODE_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_BEET=m -+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -+CONFIG_IPV6_SIT=m -+# CONFIG_IPV6_SIT_6RD is not set -+CONFIG_IPV6_NDISC_NODETYPE=y -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_SUBTREES=y -+CONFIG_IPV6_MROUTE=y -+# CONFIG_IPV6_PIMSM_V2 is not set -+# CONFIG_NETWORK_SECMARK is not set -+CONFIG_NETFILTER=y -+# CONFIG_NETFILTER_DEBUG is not set -+CONFIG_NETFILTER_ADVANCED=y -+CONFIG_BRIDGE_NETFILTER=y -+ -+# -+# Core Netfilter Configuration -+# -+CONFIG_NETFILTER_NETLINK=m -+CONFIG_NETFILTER_NETLINK_QUEUE=m -+CONFIG_NETFILTER_NETLINK_LOG=m -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CT_ACCT=y -+CONFIG_NF_CONNTRACK_MARK=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_GRE=m -+CONFIG_NF_CT_PROTO_SCTP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+# CONFIG_NETFILTER_TPROXY is not set -+CONFIG_NETFILTER_XTABLES=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -+CONFIG_NETFILTER_XT_TARGET_HL=m -+# CONFIG_NETFILTER_XT_TARGET_LED is not set -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -+CONFIG_NETFILTER_XT_TARGET_RATEEST=m -+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_HL=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -+CONFIG_NETFILTER_XT_MATCH_SCTP=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+# CONFIG_NETFILTER_XT_MATCH_OSF is not set -+CONFIG_IP_VS=m -+CONFIG_IP_VS_IPV6=y -+CONFIG_IP_VS_DEBUG=y -+CONFIG_IP_VS_TAB_BITS=12 -+ -+# -+# IPVS transport protocol load balancing support -+# -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_AH_ESP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+ -+# -+# IPVS scheduler -+# -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+ -+# -+# IPVS application helper -+# -+CONFIG_IP_VS_FTP=m -+ -+# -+# IP: Netfilter Configuration -+# -+CONFIG_NF_DEFRAG_IPV4=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_NF_CONNTRACK_PROC_COMPAT=y -+CONFIG_IP_NF_QUEUE=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_ADDRTYPE=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_TARGET_LOG=m -+CONFIG_IP_NF_TARGET_ULOG=m -+CONFIG_NF_NAT=m -+CONFIG_NF_NAT_NEEDED=y -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_NF_NAT_SNMP_BASIC=m -+CONFIG_NF_NAT_PROTO_DCCP=m -+CONFIG_NF_NAT_PROTO_GRE=m -+CONFIG_NF_NAT_PROTO_UDPLITE=m -+CONFIG_NF_NAT_PROTO_SCTP=m -+CONFIG_NF_NAT_FTP=m -+CONFIG_NF_NAT_IRC=m -+CONFIG_NF_NAT_TFTP=m -+CONFIG_NF_NAT_AMANDA=m -+CONFIG_NF_NAT_PPTP=m -+CONFIG_NF_NAT_H323=m -+CONFIG_NF_NAT_SIP=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+ -+# -+# IPv6: Netfilter Configuration -+# -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_IP6_NF_QUEUE=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_TARGET_LOG=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+# CONFIG_BRIDGE_NF_EBTABLES is not set -+CONFIG_IP_DCCP=m -+CONFIG_INET_DCCP_DIAG=m -+ -+# -+# DCCP CCIDs Configuration (EXPERIMENTAL) -+# -+# CONFIG_IP_DCCP_CCID2_DEBUG is not set -+CONFIG_IP_DCCP_CCID3=y -+# CONFIG_IP_DCCP_CCID3_DEBUG is not set -+CONFIG_IP_DCCP_CCID3_RTO=100 -+CONFIG_IP_DCCP_TFRC_LIB=y -+ -+# -+# DCCP Kernel Hacking -+# -+# CONFIG_IP_DCCP_DEBUG is not set -+CONFIG_IP_SCTP=m -+# CONFIG_SCTP_DBG_MSG is not set -+# CONFIG_SCTP_DBG_OBJCNT is not set -+# CONFIG_SCTP_HMAC_NONE is not set -+# CONFIG_SCTP_HMAC_SHA1 is not set -+CONFIG_SCTP_HMAC_MD5=y -+# CONFIG_RDS is not set -+CONFIG_TIPC=m -+# CONFIG_TIPC_ADVANCED is not set -+# CONFIG_TIPC_DEBUG is not set -+CONFIG_ATM=m -+CONFIG_ATM_CLIP=m -+# CONFIG_ATM_CLIP_NO_ICMP is not set -+CONFIG_ATM_LANE=m -+CONFIG_ATM_MPOA=m -+CONFIG_ATM_BR2684=m -+# CONFIG_ATM_BR2684_IPFILTER is not set -+CONFIG_STP=m -+CONFIG_GARP=m -+CONFIG_BRIDGE=m -+# CONFIG_NET_DSA is not set -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+# CONFIG_DECNET is not set -+CONFIG_LLC=m -+# CONFIG_LLC2 is not set -+# CONFIG_IPX is not set -+# CONFIG_ATALK is not set -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+CONFIG_WAN_ROUTER=m -+# CONFIG_PHONET is not set -+# CONFIG_IEEE802154 is not set -+CONFIG_NET_SCHED=y -+ -+# -+# Queueing/Scheduling -+# -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_ATM=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+ -+# -+# Classification -+# -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_ROUTE=y -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_PERF=y -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+# CONFIG_NET_EMATCH is not set -+# CONFIG_NET_CLS_ACT is not set -+CONFIG_NET_CLS_IND=y -+CONFIG_NET_SCH_FIFO=y -+# CONFIG_DCB is not set -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_NET_DROP_MONITOR is not set -+# CONFIG_HAMRADIO is not set -+CONFIG_CAN=m -+CONFIG_CAN_RAW=m -+CONFIG_CAN_BCM=m -+ -+# -+# CAN Device Drivers -+# -+CONFIG_CAN_VCAN=m -+# CONFIG_CAN_DEV is not set -+# CONFIG_CAN_DEBUG_DEVICES is not set -+CONFIG_IRDA=m -+ -+# -+# IrDA protocols -+# -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+ -+# -+# IrDA options -+# -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRDA_DEBUG=y -+ -+# -+# Infrared-port device drivers -+# -+ -+# -+# SIR device drivers -+# -+CONFIG_IRTTY_SIR=m -+ -+# -+# Dongle support -+# -+CONFIG_DONGLE=y -+CONFIG_ESI_DONGLE=m -+CONFIG_ACTISYS_DONGLE=m -+CONFIG_TEKRAM_DONGLE=m -+CONFIG_TOIM3232_DONGLE=m -+CONFIG_LITELINK_DONGLE=m -+CONFIG_MA600_DONGLE=m -+CONFIG_GIRBIL_DONGLE=m -+CONFIG_MCP2120_DONGLE=m -+CONFIG_OLD_BELKIN_DONGLE=m -+# CONFIG_ACT200L_DONGLE is not set -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+ -+# -+# FIR device drivers -+# -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_L2CAP=m -+CONFIG_BT_SCO=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+ -+# -+# Bluetooth device drivers -+# -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBTSDIO=m -+CONFIG_BT_HCIUART=m -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+# CONFIG_BT_HCIVHCI is not set -+# CONFIG_BT_MRVL is not set -+CONFIG_AF_RXRPC=m -+# CONFIG_AF_RXRPC_DEBUG is not set -+# CONFIG_RXKAD is not set -+CONFIG_FIB_RULES=y -+CONFIG_WIRELESS=y -+CONFIG_WIRELESS_EXT=y -+CONFIG_WEXT_CORE=y -+CONFIG_WEXT_PROC=y -+CONFIG_WEXT_SPY=y -+CONFIG_WEXT_PRIV=y -+CONFIG_CFG80211=m -+# CONFIG_NL80211_TESTMODE is not set -+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -+# CONFIG_CFG80211_REG_DEBUG is not set -+CONFIG_CFG80211_DEFAULT_PS=y -+# CONFIG_CFG80211_DEBUGFS is not set -+CONFIG_WIRELESS_OLD_REGULATORY=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_WIRELESS_EXT_SYSFS=y -+CONFIG_LIB80211=y -+CONFIG_LIB80211_CRYPT_WEP=m -+CONFIG_LIB80211_CRYPT_CCMP=m -+CONFIG_LIB80211_CRYPT_TKIP=m -+# CONFIG_LIB80211_DEBUG is not set -+CONFIG_MAC80211=m -+CONFIG_MAC80211_RC_PID=y -+# CONFIG_MAC80211_RC_MINSTREL is not set -+CONFIG_MAC80211_RC_DEFAULT_PID=y -+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -+CONFIG_MAC80211_RC_DEFAULT="pid" -+# CONFIG_MAC80211_MESH is not set -+CONFIG_MAC80211_LEDS=y -+# CONFIG_MAC80211_DEBUGFS is not set -+# CONFIG_MAC80211_DEBUG_MENU is not set -+CONFIG_WIMAX=m -+CONFIG_WIMAX_DEBUG_LEVEL=8 -+CONFIG_RFKILL=m -+CONFIG_RFKILL_LEDS=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_NET_9P=m -+# CONFIG_NET_9P_DEBUG is not set -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER_PATH="" -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_STANDALONE=y -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+CONFIG_FW_LOADER=y -+CONFIG_FIRMWARE_IN_KERNEL=y -+CONFIG_EXTRA_FIRMWARE="" -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_CONNECTOR is not set -+CONFIG_MTD=y -+# CONFIG_MTD_DEBUG is not set -+# CONFIG_MTD_TESTS is not set -+CONFIG_MTD_CONCAT=y -+CONFIG_MTD_PARTITIONS=y -+# CONFIG_MTD_REDBOOT_PARTS is not set -+# CONFIG_MTD_CMDLINE_PARTS is not set -+# CONFIG_MTD_AFS_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_MTD_OOPS is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+# CONFIG_MTD_CFI is not set -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_DATAFLASH is not set -+# CONFIG_MTD_M25P80 is not set -+# CONFIG_MTD_SST25L is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOC2000 is not set -+# CONFIG_MTD_DOC2001 is not set -+# CONFIG_MTD_DOC2001PLUS is not set -+CONFIG_MTD_NAND=y -+# CONFIG_MTD_NAND_VERIFY_WRITE is not set -+# CONFIG_MTD_NAND_ECC_SMC is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+# CONFIG_MTD_NAND_GPIO is not set -+CONFIG_MTD_NAND_OMAP2=y -+CONFIG_MTD_NAND_OMAP_PREFETCH=y -+# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+CONFIG_MTD_NAND_PLATFORM=y -+# CONFIG_MTD_ALAUDA is not set -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# LPDDR flash memory drivers -+# -+# CONFIG_MTD_LPDDR is not set -+ -+# -+# UBI - Unsorted block images -+# -+CONFIG_MTD_UBI=y -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_RESERVE=1 -+# CONFIG_MTD_UBI_GLUEBI is not set -+ -+# -+# UBI debugging options -+# -+# CONFIG_MTD_UBI_DEBUG is not set -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+ -+# -+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -+# -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_UB is not set -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=16384 -+# CONFIG_BLK_DEV_XIP is not set -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_CDROM_PKTCDVD_BUFFERS=8 -+# CONFIG_CDROM_PKTCDVD_WCACHE is not set -+# CONFIG_ATA_OVER_ETH is not set -+# CONFIG_MG_DISK is not set -+CONFIG_MISC_DEVICES=y -+# CONFIG_AD525X_DPOT is not set -+# CONFIG_ICS932S401 is not set -+# CONFIG_ENCLOSURE_SERVICES is not set -+CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -+# CONFIG_ISL29003 is not set -+# CONFIG_DS1682 is not set -+# CONFIG_TI_DAC7512 is not set -+# CONFIG_C2PORT is not set -+ -+# -+# EEPROM support -+# -+# CONFIG_EEPROM_AT24 is not set -+# CONFIG_EEPROM_AT25 is not set -+# CONFIG_EEPROM_LEGACY is not set -+# CONFIG_EEPROM_MAX6875 is not set -+CONFIG_EEPROM_93CX6=y -+CONFIG_IWMC3200TOP=m -+# CONFIG_IWMC3200TOP_DEBUG is not set -+# CONFIG_IWMC3200TOP_DEBUGFS is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+CONFIG_RAID_ATTRS=m -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+# CONFIG_SCSI_TGT is not set -+# CONFIG_SCSI_NETLINK is not set -+CONFIG_SCSI_PROC_FS=y -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=y -+CONFIG_BLK_DEV_SR_VENDOR=y -+CONFIG_CHR_DEV_SG=y -+CONFIG_CHR_DEV_SCH=m -+CONFIG_SCSI_MULTI_LUN=y -+# CONFIG_SCSI_CONSTANTS is not set -+# CONFIG_SCSI_LOGGING is not set -+# CONFIG_SCSI_SCAN_ASYNC is not set -+CONFIG_SCSI_WAIT_SCAN=m -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+# CONFIG_SCSI_FC_ATTRS is not set -+CONFIG_SCSI_ISCSI_ATTRS=m -+# CONFIG_SCSI_SAS_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+CONFIG_SCSI_LOWLEVEL=y -+CONFIG_ISCSI_TCP=m -+# CONFIG_LIBFC is not set -+# CONFIG_LIBFCOE is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_DH is not set -+# CONFIG_SCSI_OSD_INITIATOR is not set -+# CONFIG_ATA is not set -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_MD_LINEAR=m -+CONFIG_MD_RAID0=m -+CONFIG_MD_RAID1=m -+CONFIG_MD_RAID10=m -+CONFIG_MD_RAID456=m -+CONFIG_MD_RAID6_PQ=m -+# CONFIG_ASYNC_RAID6_TEST is not set -+CONFIG_MD_MULTIPATH=m -+CONFIG_MD_FAULTY=m -+CONFIG_BLK_DEV_DM=m -+# CONFIG_DM_DEBUG is not set -+CONFIG_DM_CRYPT=m -+CONFIG_DM_SNAPSHOT=m -+CONFIG_DM_MIRROR=m -+# CONFIG_DM_LOG_USERSPACE is not set -+CONFIG_DM_ZERO=m -+CONFIG_DM_MULTIPATH=m -+# CONFIG_DM_MULTIPATH_QL is not set -+# CONFIG_DM_MULTIPATH_ST is not set -+CONFIG_DM_DELAY=m -+# CONFIG_DM_UEVENT is not set -+CONFIG_NETDEVICES=y -+CONFIG_DUMMY=m -+CONFIG_BONDING=m -+CONFIG_MACVLAN=m -+CONFIG_EQUALIZER=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_PHYLIB=y -+ -+# -+# MII PHY device drivers -+# -+# CONFIG_MARVELL_PHY is not set -+# CONFIG_DAVICOM_PHY is not set -+# CONFIG_QSEMI_PHY is not set -+# CONFIG_LXT_PHY is not set -+# CONFIG_CICADA_PHY is not set -+# CONFIG_VITESSE_PHY is not set -+# CONFIG_SMSC_PHY is not set -+# CONFIG_BROADCOM_PHY is not set -+# CONFIG_ICPLUS_PHY is not set -+# CONFIG_REALTEK_PHY is not set -+# CONFIG_NATIONAL_PHY is not set -+# CONFIG_STE10XP is not set -+# CONFIG_LSI_ET1011C_PHY is not set -+# CONFIG_FIXED_PHY is not set -+# CONFIG_MDIO_BITBANG is not set -+CONFIG_NET_ETHERNET=y -+CONFIG_MII=y -+# CONFIG_AX88796 is not set -+# CONFIG_SMC91X is not set -+# CONFIG_TI_DAVINCI_EMAC is not set -+# CONFIG_DM9000 is not set -+CONFIG_ENC28J60=y -+# CONFIG_ENC28J60_WRITEVERIFY is not set -+# CONFIG_ETHOC is not set -+CONFIG_SMC911X=y -+CONFIG_SMSC911X=y -+# CONFIG_DNET is not set -+# CONFIG_IBM_NEW_EMAC_ZMII is not set -+# CONFIG_IBM_NEW_EMAC_RGMII is not set -+# CONFIG_IBM_NEW_EMAC_TAH is not set -+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -+# CONFIG_B44 is not set -+# CONFIG_KS8842 is not set -+CONFIG_KS8851=y -+# CONFIG_KS8851_MLL is not set -+# CONFIG_NETDEV_1000 is not set -+# CONFIG_NETDEV_10000 is not set -+CONFIG_WLAN=y -+# CONFIG_LIBERTAS_THINFIRM is not set -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_RTL8187_LEDS=y -+# CONFIG_MAC80211_HWSIM is not set -+# CONFIG_ATH_COMMON is not set -+CONFIG_B43=m -+# CONFIG_B43_SDIO is not set -+CONFIG_B43_PHY_LP=y -+CONFIG_B43_LEDS=y -+CONFIG_B43_HWRNG=y -+# CONFIG_B43_DEBUG is not set -+# CONFIG_B43LEGACY is not set -+CONFIG_HOSTAP=m -+CONFIG_HOSTAP_FIRMWARE=y -+CONFIG_HOSTAP_FIRMWARE_NVRAM=y -+# CONFIG_IWM is not set -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+# CONFIG_LIBERTAS_SDIO is not set -+# CONFIG_LIBERTAS_SPI is not set -+# CONFIG_LIBERTAS_DEBUG is not set -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+# CONFIG_P54_SPI is not set -+CONFIG_P54_LEDS=y -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+# CONFIG_RT2800USB is not set -+CONFIG_RT2X00_LIB_USB=m -+CONFIG_RT2X00_LIB=m -+CONFIG_RT2X00_LIB_FIRMWARE=y -+CONFIG_RT2X00_LIB_CRYPTO=y -+CONFIG_RT2X00_LIB_LEDS=y -+# CONFIG_RT2X00_DEBUG is not set -+CONFIG_WL12XX=m -+CONFIG_WL1251=m -+CONFIG_WL1251_SPI=m -+CONFIG_WL1251_SDIO=m -+CONFIG_WL1271=m -+CONFIG_ZD1211RW=m -+# CONFIG_ZD1211RW_DEBUG is not set -+ -+# -+# WiMAX Wireless Broadband devices -+# -+CONFIG_WIMAX_I2400M=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_WIMAX_I2400M_SDIO=m -+CONFIG_WIMAX_IWMC3200_SDIO=y -+CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 -+ -+# -+# USB Network Adapters -+# -+CONFIG_USB_CATC=y -+CONFIG_USB_KAWETH=y -+CONFIG_USB_PEGASUS=y -+CONFIG_USB_RTL8150=y -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=y -+CONFIG_USB_NET_CDCETHER=y -+CONFIG_USB_NET_CDC_EEM=y -+CONFIG_USB_NET_DM9601=y -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=y -+CONFIG_USB_NET_NET1080=y -+CONFIG_USB_NET_PLUSB=y -+CONFIG_USB_NET_MCS7830=y -+CONFIG_USB_NET_RNDIS_HOST=y -+CONFIG_USB_NET_CDC_SUBSET=y -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_BELKIN=y -+CONFIG_USB_ARMLINUX=y -+CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y -+CONFIG_USB_NET_ZAURUS=y -+CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m -+# CONFIG_WAN is not set -+CONFIG_ATM_DRIVERS=y -+# CONFIG_ATM_DUMMY is not set -+# CONFIG_ATM_TCP is not set -+CONFIG_PPP=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_MPPE=m -+CONFIG_PPPOE=m -+# CONFIG_PPPOATM is not set -+CONFIG_PPPOL2TP=m -+# CONFIG_SLIP is not set -+CONFIG_SLHC=m -+CONFIG_NETCONSOLE=m -+CONFIG_NETCONSOLE_DYNAMIC=y -+CONFIG_NETPOLL=y -+CONFIG_NETPOLL_TRAP=y -+CONFIG_NET_POLL_CONTROLLER=y -+# CONFIG_ISDN is not set -+# CONFIG_PHONE is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+CONFIG_INPUT_FF_MEMLESS=y -+CONFIG_INPUT_POLLDEV=y -+# CONFIG_INPUT_SPARSEKMAP is not set -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+CONFIG_INPUT_MOUSEDEV_PSAUX=y -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+# CONFIG_INPUT_JOYDEV is not set -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+# CONFIG_KEYBOARD_ADP5588 is not set -+# CONFIG_KEYBOARD_ATKBD is not set -+# CONFIG_QT2160 is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+CONFIG_KEYBOARD_GPIO=y -+# CONFIG_KEYBOARD_TCA6416 is not set -+# CONFIG_KEYBOARD_MATRIX is not set -+# CONFIG_KEYBOARD_LM8323 is not set -+# CONFIG_KEYBOARD_MAX7359 is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_OPENCORES is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_TWL4030 is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+CONFIG_INPUT_MOUSE=y -+CONFIG_MOUSE_PS2=y -+CONFIG_MOUSE_PS2_ALPS=y -+CONFIG_MOUSE_PS2_LOGIPS2PP=y -+CONFIG_MOUSE_PS2_SYNAPTICS=y -+CONFIG_MOUSE_PS2_TRACKPOINT=y -+# CONFIG_MOUSE_PS2_ELANTECH is not set -+# CONFIG_MOUSE_PS2_SENTELIC is not set -+# CONFIG_MOUSE_PS2_TOUCHKIT is not set -+# CONFIG_MOUSE_SERIAL is not set -+# CONFIG_MOUSE_APPLETOUCH is not set -+# CONFIG_MOUSE_BCM5974 is not set -+# CONFIG_MOUSE_VSXXXAA is not set -+# CONFIG_MOUSE_GPIO is not set -+# CONFIG_MOUSE_SYNAPTICS_I2C is not set -+# CONFIG_INPUT_JOYSTICK is not set -+# CONFIG_INPUT_TABLET is not set -+# CONFIG_INPUT_TOUCHSCREEN is not set -+CONFIG_INPUT_MISC=y -+# CONFIG_INPUT_ATI_REMOTE is not set -+# CONFIG_INPUT_ATI_REMOTE2 is not set -+# CONFIG_INPUT_KEYSPAN_REMOTE is not set -+# CONFIG_INPUT_POWERMATE is not set -+# CONFIG_INPUT_YEALINK is not set -+# CONFIG_INPUT_CM109 is not set -+CONFIG_INPUT_TWL4030_PWRBUTTON=y -+CONFIG_INPUT_UINPUT=y -+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -+ -+# -+# Hardware I/O ports -+# -+CONFIG_SERIO=y -+CONFIG_SERIO_SERPORT=y -+CONFIG_SERIO_LIBPS2=y -+# CONFIG_SERIO_RAW is not set -+# CONFIG_SERIO_ALTERA_PS2 is not set -+# CONFIG_GAMEPORT is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_CONSOLE_TRANSLATIONS=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+CONFIG_VT_HW_CONSOLE_BINDING=y -+CONFIG_DEVKMEM=y -+# CONFIG_SERIAL_NONSTANDARD is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_NR_UARTS=32 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_MANY_PORTS=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DETECT_IRQ=y -+CONFIG_SERIAL_8250_RSA=y -+ -+# -+# Non-8250 serial port support -+# -+# CONFIG_SERIAL_MAX3100 is not set -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+CONFIG_UNIX98_PTYS=y -+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_HW_RANDOM=y -+# CONFIG_HW_RANDOM_TIMERIOMEM is not set -+# CONFIG_R3964 is not set -+# CONFIG_RAW_DRIVER is not set -+# CONFIG_TCG_TPM is not set -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_COMPAT=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_HELPER_AUTO=y -+ -+# -+# I2C Hardware Bus support -+# -+ -+# -+# I2C system bus drivers (mostly embedded / system-on-chip) -+# -+# CONFIG_I2C_DESIGNWARE is not set -+# CONFIG_I2C_GPIO is not set -+# CONFIG_I2C_OCORES is not set -+CONFIG_I2C_OMAP=y -+# CONFIG_I2C_SIMTEC is not set -+ -+# -+# External I2C/SMBus adapter drivers -+# -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_TINY_USB is not set -+ -+# -+# Other I2C/SMBus bus drivers -+# -+# CONFIG_I2C_PCA_PLATFORM is not set -+# CONFIG_I2C_STUB is not set -+ -+# -+# Miscellaneous I2C Chip support -+# -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_DEBUG_CHIP is not set -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+# CONFIG_SPI_BITBANG is not set -+# CONFIG_SPI_GPIO is not set -+CONFIG_SPI_OMAP24XX=y -+# CONFIG_SPI_XILINX is not set -+ -+# -+# SPI Protocol Masters -+# -+CONFIG_SPI_SPIDEV=y -+# CONFIG_SPI_TLE62X0 is not set -+ -+# -+# PPS support -+# -+# CONFIG_PPS is not set -+CONFIG_ARCH_REQUIRE_GPIOLIB=y -+CONFIG_GPIOLIB=y -+# CONFIG_DEBUG_GPIO is not set -+CONFIG_GPIO_SYSFS=y -+ -+# -+# Memory mapped GPIO expanders: -+# -+ -+# -+# I2C GPIO expanders: -+# -+# CONFIG_GPIO_MAX732X is not set -+# CONFIG_GPIO_PCA953X is not set -+# CONFIG_GPIO_PCF857X is not set -+CONFIG_GPIO_TWL4030=y -+ -+# -+# PCI GPIO expanders: -+# -+ -+# -+# SPI GPIO expanders: -+# -+# CONFIG_GPIO_MAX7301 is not set -+# CONFIG_GPIO_MCP23S08 is not set -+# CONFIG_GPIO_MC33880 is not set -+ -+# -+# AC97 GPIO expanders: -+# -+# CONFIG_W1 is not set -+CONFIG_POWER_SUPPLY=m -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+# CONFIG_PDA_POWER is not set -+# CONFIG_BATTERY_DS2760 is not set -+# CONFIG_BATTERY_DS2782 is not set -+# CONFIG_BATTERY_BQ27x00 is not set -+# CONFIG_BATTERY_MAX17040 is not set -+CONFIG_HWMON=y -+# CONFIG_HWMON_VID is not set -+# CONFIG_HWMON_DEBUG_CHIP is not set -+ -+# -+# Native drivers -+# -+# CONFIG_SENSORS_AD7414 is not set -+# CONFIG_SENSORS_AD7418 is not set -+# CONFIG_SENSORS_ADCXX is not set -+# CONFIG_SENSORS_ADM1021 is not set -+# CONFIG_SENSORS_ADM1025 is not set -+# CONFIG_SENSORS_ADM1026 is not set -+# CONFIG_SENSORS_ADM1029 is not set -+# CONFIG_SENSORS_ADM1031 is not set -+# CONFIG_SENSORS_ADM9240 is not set -+# CONFIG_SENSORS_ADT7462 is not set -+# CONFIG_SENSORS_ADT7470 is not set -+# CONFIG_SENSORS_ADT7473 is not set -+# CONFIG_SENSORS_ADT7475 is not set -+# CONFIG_SENSORS_ATXP1 is not set -+# CONFIG_SENSORS_DS1621 is not set -+# CONFIG_SENSORS_F71805F is not set -+# CONFIG_SENSORS_F71882FG is not set -+# CONFIG_SENSORS_F75375S is not set -+# CONFIG_SENSORS_G760A is not set -+# CONFIG_SENSORS_GL518SM is not set -+# CONFIG_SENSORS_GL520SM is not set -+# CONFIG_SENSORS_IT87 is not set -+# CONFIG_SENSORS_LM63 is not set -+# CONFIG_SENSORS_LM70 is not set -+# CONFIG_SENSORS_LM73 is not set -+# CONFIG_SENSORS_LM75 is not set -+# CONFIG_SENSORS_LM77 is not set -+# CONFIG_SENSORS_LM78 is not set -+# CONFIG_SENSORS_LM80 is not set -+# CONFIG_SENSORS_LM83 is not set -+# CONFIG_SENSORS_LM85 is not set -+# CONFIG_SENSORS_LM87 is not set -+# CONFIG_SENSORS_LM90 is not set -+# CONFIG_SENSORS_LM92 is not set -+# CONFIG_SENSORS_LM93 is not set -+# CONFIG_SENSORS_LTC4215 is not set -+# CONFIG_SENSORS_LTC4245 is not set -+# CONFIG_SENSORS_LM95241 is not set -+# CONFIG_SENSORS_MAX1111 is not set -+# CONFIG_SENSORS_MAX1619 is not set -+# CONFIG_SENSORS_MAX6650 is not set -+# CONFIG_SENSORS_PC87360 is not set -+# CONFIG_SENSORS_PC87427 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_SENSORS_SHT15 is not set -+# CONFIG_SENSORS_DME1737 is not set -+# CONFIG_SENSORS_SMSC47M1 is not set -+# CONFIG_SENSORS_SMSC47M192 is not set -+# CONFIG_SENSORS_SMSC47B397 is not set -+# CONFIG_SENSORS_ADS7828 is not set -+# CONFIG_SENSORS_THMC50 is not set -+# CONFIG_SENSORS_TMP401 is not set -+# CONFIG_SENSORS_TMP421 is not set -+# CONFIG_SENSORS_VT1211 is not set -+# CONFIG_SENSORS_W83781D is not set -+# CONFIG_SENSORS_W83791D is not set -+# CONFIG_SENSORS_W83792D is not set -+# CONFIG_SENSORS_W83793 is not set -+# CONFIG_SENSORS_W83L785TS is not set -+# CONFIG_SENSORS_W83L786NG is not set -+# CONFIG_SENSORS_W83627HF is not set -+# CONFIG_SENSORS_W83627EHF is not set -+# CONFIG_SENSORS_LIS3_SPI is not set -+CONFIG_THERMAL=y -+CONFIG_THERMAL_HWMON=y -+CONFIG_WATCHDOG=y -+CONFIG_WATCHDOG_NOWAYOUT=y -+ -+# -+# Watchdog Device Drivers -+# -+# CONFIG_SOFT_WATCHDOG is not set -+CONFIG_OMAP_WATCHDOG=y -+# CONFIG_TWL4030_WATCHDOG is not set -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_SSB_POSSIBLE=y -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB=y -+CONFIG_SSB_SDIOHOST_POSSIBLE=y -+# CONFIG_SSB_SDIOHOST is not set -+# CONFIG_SSB_SILENT is not set -+# CONFIG_SSB_DEBUG is not set -+ -+# -+# Multifunction device drivers -+# -+CONFIG_MFD_CORE=y -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_HTC_EGPIO is not set -+# CONFIG_HTC_PASIC3 is not set -+# CONFIG_TPS65010 is not set -+CONFIG_TWL4030_CORE=y -+CONFIG_TWL4030_POWER=y -+CONFIG_TWL4030_CODEC=y -+# CONFIG_TWL4030_MADC is not set -+# CONFIG_MFD_TMIO is not set -+# CONFIG_MFD_T7L66XB is not set -+# CONFIG_MFD_TC6387XB is not set -+# CONFIG_MFD_TC6393XB is not set -+# CONFIG_PMIC_DA903X is not set -+# CONFIG_PMIC_ADP5520 is not set -+# CONFIG_MFD_WM8400 is not set -+# CONFIG_MFD_WM831X is not set -+# CONFIG_MFD_WM8350_I2C is not set -+# CONFIG_MFD_PCF50633 is not set -+# CONFIG_MFD_MC13783 is not set -+# CONFIG_AB3100_CORE is not set -+# CONFIG_EZX_PCAP is not set -+# CONFIG_MFD_88PM8607 is not set -+# CONFIG_AB4500_CORE is not set -+CONFIG_REGULATOR=y -+# CONFIG_REGULATOR_DEBUG is not set -+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -+# CONFIG_REGULATOR_BQ24022 is not set -+# CONFIG_REGULATOR_MAX1586 is not set -+CONFIG_REGULATOR_TWL4030=y -+# CONFIG_REGULATOR_LP3971 is not set -+# CONFIG_REGULATOR_TPS65023 is not set -+# CONFIG_REGULATOR_TPS6507X is not set -+CONFIG_MEDIA_SUPPORT=y -+ -+# -+# Multimedia core support -+# -+CONFIG_VIDEO_DEV=y -+CONFIG_VIDEO_V4L2_COMMON=y -+CONFIG_VIDEO_ALLOW_V4L1=y -+CONFIG_VIDEO_V4L1_COMPAT=y -+CONFIG_DVB_CORE=m -+CONFIG_VIDEO_MEDIA=m -+ -+# -+# Multimedia drivers -+# -+CONFIG_MEDIA_ATTACH=y -+CONFIG_MEDIA_TUNER=m -+CONFIG_MEDIA_TUNER_CUSTOMISE=y -+CONFIG_MEDIA_TUNER_SIMPLE=m -+CONFIG_MEDIA_TUNER_TDA8290=m -+CONFIG_MEDIA_TUNER_TDA827X=m -+CONFIG_MEDIA_TUNER_TDA18271=m -+CONFIG_MEDIA_TUNER_TDA9887=m -+CONFIG_MEDIA_TUNER_TEA5761=m -+CONFIG_MEDIA_TUNER_TEA5767=m -+CONFIG_MEDIA_TUNER_MT20XX=m -+CONFIG_MEDIA_TUNER_MT2060=m -+CONFIG_MEDIA_TUNER_MT2266=m -+CONFIG_MEDIA_TUNER_MT2131=m -+CONFIG_MEDIA_TUNER_QT1010=m -+CONFIG_MEDIA_TUNER_XC2028=m -+CONFIG_MEDIA_TUNER_XC5000=m -+CONFIG_MEDIA_TUNER_MXL5005S=m -+CONFIG_MEDIA_TUNER_MXL5007T=m -+CONFIG_MEDIA_TUNER_MC44S803=m -+CONFIG_MEDIA_TUNER_MAX2165=m -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_V4L1=y -+CONFIG_VIDEOBUF_GEN=y -+CONFIG_VIDEOBUF_DMA_SG=y -+CONFIG_VIDEOBUF_VMALLOC=m -+CONFIG_VIDEOBUF_DMA_CONTIG=y -+CONFIG_VIDEOBUF_DVB=m -+CONFIG_VIDEO_IR=m -+CONFIG_VIDEO_TVEEPROM=m -+CONFIG_VIDEO_TUNER=m -+CONFIG_VIDEO_CAPTURE_DRIVERS=y -+# CONFIG_VIDEO_ADV_DEBUG is not set -+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -+CONFIG_VIDEO_IR_I2C=m -+ -+# -+# Encoders/decoders and other helper chips -+# -+ -+# -+# Audio decoders -+# -+# CONFIG_VIDEO_TVAUDIO is not set -+# CONFIG_VIDEO_TDA7432 is not set -+# CONFIG_VIDEO_TDA9840 is not set -+# CONFIG_VIDEO_TDA9875 is not set -+# CONFIG_VIDEO_TEA6415C is not set -+# CONFIG_VIDEO_TEA6420 is not set -+CONFIG_VIDEO_MSP3400=m -+# CONFIG_VIDEO_CS5345 is not set -+CONFIG_VIDEO_CS53L32A=m -+# CONFIG_VIDEO_M52790 is not set -+# CONFIG_VIDEO_TLV320AIC23B is not set -+CONFIG_VIDEO_WM8775=m -+# CONFIG_VIDEO_WM8739 is not set -+# CONFIG_VIDEO_VP27SMPX is not set -+ -+# -+# RDS decoders -+# -+# CONFIG_VIDEO_SAA6588 is not set -+ -+# -+# Video decoders -+# -+# CONFIG_VIDEO_ADV7180 is not set -+# CONFIG_VIDEO_BT819 is not set -+# CONFIG_VIDEO_BT856 is not set -+# CONFIG_VIDEO_BT866 is not set -+# CONFIG_VIDEO_KS0127 is not set -+# CONFIG_VIDEO_OV7670 is not set -+CONFIG_VIDEO_MT9V011=m -+# CONFIG_VIDEO_TCM825X is not set -+CONFIG_VIDEO_MT9P012=m -+CONFIG_VIDEO_MT9T111=y -+# CONFIG_VIDEO_DW9710 is not set -+# CONFIG_VIDEO_OV3640 is not set -+# CONFIG_VIDEO_IMX046 is not set -+# CONFIG_VIDEO_LV8093 is not set -+# CONFIG_VIDEO_SAA7110 is not set -+CONFIG_VIDEO_SAA711X=m -+# CONFIG_VIDEO_SAA717X is not set -+# CONFIG_VIDEO_SAA7191 is not set -+# CONFIG_VIDEO_TVP514X is not set -+# CONFIG_VIDEO_TVP5150 is not set -+# CONFIG_VIDEO_VPX3220 is not set -+ -+# -+# Video and audio decoders -+# -+CONFIG_VIDEO_CX25840=m -+ -+# -+# MPEG video encoders -+# -+CONFIG_VIDEO_CX2341X=m -+ -+# -+# Video encoders -+# -+# CONFIG_VIDEO_SAA7127 is not set -+# CONFIG_VIDEO_SAA7185 is not set -+# CONFIG_VIDEO_ADV7170 is not set -+# CONFIG_VIDEO_ADV7175 is not set -+# CONFIG_VIDEO_THS7303 is not set -+# CONFIG_VIDEO_ADV7343 is not set -+ -+# -+# Video improvement chips -+# -+# CONFIG_VIDEO_UPD64031A is not set -+# CONFIG_VIDEO_UPD64083 is not set -+CONFIG_VIDEO_VIVI=m -+# CONFIG_VIDEO_CPIA is not set -+# CONFIG_VIDEO_CPIA2 is not set -+# CONFIG_VIDEO_SAA5246A is not set -+# CONFIG_VIDEO_SAA5249 is not set -+# CONFIG_VIDEO_AU0828 is not set -+CONFIG_TI_MEDIA=y -+CONFIG_VIDEO_VPSS_SYSTEM=y -+CONFIG_VIDEO_VPFE_CAPTURE=y -+# CONFIG_VIDEO_DM6446_CCDC is not set -+# CONFIG_VIDEO_DM355_CCDC is not set -+CONFIG_VIDEO_OMAP2_VOUT=y -+CONFIG_VIDEO_OMAP3=y -+CONFIG_VIDEO_OMAP3_ISP=y -+CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -+CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -+# CONFIG_SOC_CAMERA is not set -+CONFIG_V4L_USB_DRIVERS=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -+CONFIG_USB_GSPCA=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+# CONFIG_USB_GL860 is not set -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+# CONFIG_USB_GSPCA_JEILINJ is not set -+CONFIG_USB_GSPCA_MARS=m -+# CONFIG_USB_GSPCA_MR97310A is not set -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_PAC207=m -+# CONFIG_USB_GSPCA_PAC7302 is not set -+CONFIG_USB_GSPCA_PAC7311=m -+# CONFIG_USB_GSPCA_SN9C20X is not set -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+# CONFIG_USB_GSPCA_SQ905 is not set -+# CONFIG_USB_GSPCA_SQ905C is not set -+CONFIG_USB_GSPCA_STK014=m -+# CONFIG_USB_GSPCA_STV0680 is not set -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_PVRUSB2_SYSFS=y -+CONFIG_VIDEO_PVRUSB2_DVB=y -+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_VIDEO_CX231XX=m -+# CONFIG_VIDEO_CX231XX_ALSA is not set -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_USBVIDEO=m -+CONFIG_USB_VICAM=m -+CONFIG_USB_IBMCAM=m -+CONFIG_USB_KONICAWC=m -+CONFIG_USB_QUICKCAM_MESSENGER=m -+CONFIG_USB_ET61X251=m -+CONFIG_VIDEO_OVCAMCHIP=m -+CONFIG_USB_W9968CF=m -+CONFIG_USB_OV511=m -+CONFIG_USB_SE401=m -+CONFIG_USB_SN9C102=m -+CONFIG_USB_STV680=m -+CONFIG_USB_ZC0301=m -+CONFIG_USB_PWC=m -+# CONFIG_USB_PWC_DEBUG is not set -+CONFIG_USB_PWC_INPUT_EVDEV=y -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_RADIO_ADAPTERS=y -+# CONFIG_I2C_SI4713 is not set -+# CONFIG_RADIO_SI4713 is not set -+# CONFIG_USB_DSBR is not set -+# CONFIG_RADIO_SI470X is not set -+# CONFIG_USB_MR800 is not set -+# CONFIG_RADIO_TEA5764 is not set -+# CONFIG_RADIO_TEF6862 is not set -+CONFIG_DVB_MAX_ADAPTERS=8 -+CONFIG_DVB_DYNAMIC_MINORS=y -+CONFIG_DVB_CAPTURE_DRIVERS=y -+# CONFIG_TTPCI_EEPROM is not set -+ -+# -+# Supported USB Adapters -+# -+CONFIG_DVB_USB=m -+# CONFIG_DVB_USB_DEBUG is not set -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AF9015=m -+# CONFIG_DVB_USB_CE6230 is not set -+# CONFIG_DVB_USB_FRIIO is not set -+# CONFIG_DVB_USB_EC168 is not set -+# CONFIG_SMS_SIANO_MDTV is not set -+ -+# -+# Supported FlexCopII (B2C2) Adapters -+# -+CONFIG_DVB_B2C2_FLEXCOP=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set -+ -+# -+# Supported DVB Frontends -+# -+# CONFIG_DVB_FE_CUSTOMISE is not set -+CONFIG_DVB_CX24123=m -+CONFIG_DVB_MT312=m -+CONFIG_DVB_ZL10039=m -+CONFIG_DVB_S5H1420=m -+CONFIG_DVB_STV0288=m -+CONFIG_DVB_STB6000=m -+CONFIG_DVB_STV0299=m -+CONFIG_DVB_TDA10086=m -+CONFIG_DVB_TUNER_ITD1000=m -+CONFIG_DVB_TUNER_CX24113=m -+CONFIG_DVB_TDA826X=m -+CONFIG_DVB_CX24116=m -+CONFIG_DVB_SI21XX=m -+CONFIG_DVB_CX22702=m -+CONFIG_DVB_TDA1004X=m -+CONFIG_DVB_NXT6000=m -+CONFIG_DVB_MT352=m -+CONFIG_DVB_ZL10353=m -+CONFIG_DVB_DIB3000MB=m -+CONFIG_DVB_DIB3000MC=m -+CONFIG_DVB_DIB7000M=m -+CONFIG_DVB_DIB7000P=m -+CONFIG_DVB_TDA10048=m -+CONFIG_DVB_AF9013=m -+CONFIG_DVB_TDA10021=m -+CONFIG_DVB_TDA10023=m -+CONFIG_DVB_STV0297=m -+CONFIG_DVB_NXT200X=m -+CONFIG_DVB_BCM3510=m -+CONFIG_DVB_LGDT330X=m -+CONFIG_DVB_LGDT3305=m -+CONFIG_DVB_S5H1409=m -+CONFIG_DVB_S5H1411=m -+CONFIG_DVB_DIB8000=m -+CONFIG_DVB_PLL=m -+CONFIG_DVB_TUNER_DIB0070=m -+CONFIG_DVB_LNBP21=m -+CONFIG_DVB_ISL6421=m -+CONFIG_DVB_LGS8GL5=m -+# CONFIG_DAB is not set -+ -+# -+# Graphics support -+# -+# CONFIG_VGASTATE is not set -+# CONFIG_VIDEO_OUTPUT_CONTROL is not set -+CONFIG_FB=y -+# CONFIG_FIRMWARE_EDID is not set -+# CONFIG_FB_DDC is not set -+# CONFIG_FB_BOOT_VESA_SUPPORT is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -+# CONFIG_FB_SYS_FILLRECT is not set -+# CONFIG_FB_SYS_COPYAREA is not set -+# CONFIG_FB_SYS_IMAGEBLIT is not set -+# CONFIG_FB_FOREIGN_ENDIAN is not set -+# CONFIG_FB_SYS_FOPS is not set -+# CONFIG_FB_SVGALIB is not set -+# CONFIG_FB_MACMODES is not set -+# CONFIG_FB_BACKLIGHT is not set -+CONFIG_FB_MODE_HELPERS=y -+# CONFIG_FB_TILEBLITTING is not set -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_TMIO is not set -+# CONFIG_FB_VIRTUAL is not set -+# CONFIG_FB_METRONOME is not set -+# CONFIG_FB_MB862XX is not set -+# CONFIG_FB_BROADSHEET is not set -+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -+CONFIG_OMAP2_VRAM=y -+CONFIG_OMAP2_VRFB=y -+CONFIG_OMAP2_DSS=y -+CONFIG_OMAP2_VRAM_SIZE=14 -+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -+# CONFIG_OMAP2_DSS_RFBI is not set -+CONFIG_OMAP2_DSS_VENC=y -+CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -+# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -+# CONFIG_OMAP2_DSS_SDI is not set -+CONFIG_OMAP2_DSS_DSI=y -+CONFIG_OMAP2_DSS_USE_DSI_PLL=y -+# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -+CONFIG_FB_OMAP2=y -+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -+# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -+CONFIG_FB_OMAP2_NUM_FBS=3 -+ -+# -+# OMAP2/3 Display Device Drivers -+# -+CONFIG_PANEL_GENERIC=y -+# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -+# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -+CONFIG_PANEL_SHARP_LS037V7DW01=y -+# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -+# CONFIG_PANEL_TAAL is not set -+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -+ -+# -+# Display device support -+# -+CONFIG_DISPLAY_SUPPORT=y -+ -+# -+# Display hardware drivers -+# -+ -+# -+# Console display driver support -+# -+# CONFIG_VGA_CONSOLE is not set -+CONFIG_DUMMY_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -+# CONFIG_FONTS is not set -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_LOGO_LINUX_CLUT224=y -+CONFIG_SOUND=y -+CONFIG_SOUND_OSS_CORE=y -+CONFIG_SOUND_OSS_CORE_PRECLAIM=y -+CONFIG_SND=y -+CONFIG_SND_TIMER=y -+CONFIG_SND_PCM=y -+CONFIG_SND_HWDEP=y -+CONFIG_SND_RAWMIDI=y -+CONFIG_SND_JACK=y -+CONFIG_SND_SEQUENCER=m -+# CONFIG_SND_SEQ_DUMMY is not set -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=y -+CONFIG_SND_PCM_OSS=y -+CONFIG_SND_PCM_OSS_PLUGINS=y -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -+# CONFIG_SND_DYNAMIC_MINORS is not set -+CONFIG_SND_SUPPORT_OLD_API=y -+CONFIG_SND_VERBOSE_PROCFS=y -+# CONFIG_SND_VERBOSE_PRINTK is not set -+# CONFIG_SND_DEBUG is not set -+CONFIG_SND_RAWMIDI_SEQ=m -+# CONFIG_SND_OPL3_LIB_SEQ is not set -+# CONFIG_SND_OPL4_LIB_SEQ is not set -+# CONFIG_SND_SBAWE_SEQ is not set -+# CONFIG_SND_EMU10K1_SEQ is not set -+CONFIG_SND_DRIVERS=y -+# CONFIG_SND_DUMMY is not set -+# CONFIG_SND_VIRMIDI is not set -+# CONFIG_SND_MTPAV is not set -+# CONFIG_SND_SERIAL_U16550 is not set -+# CONFIG_SND_MPU401 is not set -+# CONFIG_SND_ARM is not set -+CONFIG_SND_SPI=y -+CONFIG_SND_USB=y -+CONFIG_SND_USB_AUDIO=y -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_SOC=y -+CONFIG_SND_OMAP_SOC=y -+CONFIG_SND_OMAP_SOC_MCBSP=y -+# CONFIG_SND_OMAP_SOC_OMAP3EVM is not set -+CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE=y -+CONFIG_SND_SOC_I2C_AND_SPI=y -+# CONFIG_SND_SOC_ALL_CODECS is not set -+CONFIG_SND_SOC_TWL4030=y -+# CONFIG_SOUND_PRIME is not set -+CONFIG_HID_SUPPORT=y -+CONFIG_HID=y -+# CONFIG_HIDRAW is not set -+ -+# -+# USB Input Devices -+# -+CONFIG_USB_HID=y -+# CONFIG_HID_PID is not set -+# CONFIG_USB_HIDDEV is not set -+ -+# -+# Special HID drivers -+# -+CONFIG_HID_A4TECH=y -+CONFIG_HID_APPLE=y -+CONFIG_HID_BELKIN=y -+CONFIG_HID_CHERRY=y -+CONFIG_HID_CHICONY=y -+CONFIG_HID_CYPRESS=y -+# CONFIG_HID_DRAGONRISE is not set -+CONFIG_HID_EZKEY=y -+# CONFIG_HID_KYE is not set -+CONFIG_HID_GYRATION=y -+# CONFIG_HID_TWINHAN is not set -+# CONFIG_HID_KENSINGTON is not set -+CONFIG_HID_LOGITECH=y -+# CONFIG_LOGITECH_FF is not set -+# CONFIG_LOGIRUMBLEPAD2_FF is not set -+CONFIG_HID_MICROSOFT=y -+CONFIG_HID_MONTEREY=y -+CONFIG_HID_NTRIG=y -+CONFIG_HID_PANTHERLORD=y -+# CONFIG_PANTHERLORD_FF is not set -+CONFIG_HID_PETALYNX=y -+CONFIG_HID_SAMSUNG=y -+CONFIG_HID_SONY=y -+CONFIG_HID_SUNPLUS=y -+# CONFIG_HID_GREENASIA is not set -+# CONFIG_HID_SMARTJOYPLUS is not set -+CONFIG_HID_TOPSEED=y -+# CONFIG_HID_THRUSTMASTER is not set -+# CONFIG_HID_WACOM is not set -+# CONFIG_HID_ZEROPLUS is not set -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB_ARCH_HAS_OHCI=y -+CONFIG_USB_ARCH_HAS_EHCI=y -+CONFIG_USB=y -+# CONFIG_USB_DEBUG is not set -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEVICEFS=y -+CONFIG_USB_DEVICE_CLASS=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+CONFIG_USB_SUSPEND=y -+CONFIG_USB_OTG=y -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set -+CONFIG_USB_MON=y -+# CONFIG_USB_WUSB is not set -+# CONFIG_USB_WUSB_CBAF is not set -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+CONFIG_USB_EHCI_HCD=y -+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+# CONFIG_USB_OXU210HP_HCD is not set -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set -+# CONFIG_USB_ISP1362_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_U132_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_HWA_HCD is not set -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_MUSB_SOC=y -+ -+# -+# OMAP 343x high speed USB support -+# -+# CONFIG_USB_MUSB_HOST is not set -+# CONFIG_USB_MUSB_PERIPHERAL is not set -+CONFIG_USB_MUSB_OTG=y -+CONFIG_USB_GADGET_MUSB_HDRC=y -+CONFIG_USB_MUSB_HDRC_HCD=y -+# CONFIG_MUSB_PIO_ONLY is not set -+CONFIG_USB_INVENTRA_DMA=y -+CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -+# CONFIG_USB_TI_CPPI_DMA is not set -+# CONFIG_USB_TI_CPPI41_DMA is not set -+# CONFIG_USB_MUSB_DEBUG is not set -+ -+# -+# USB Device Class drivers -+# -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+CONFIG_USB_WDM=m -+CONFIG_USB_TMC=m -+ -+# -+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -+# -+ -+# -+# also be needed; see USB_STORAGE Help for more info -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+# CONFIG_USB_STORAGE_DATAFAB is not set -+# CONFIG_USB_STORAGE_FREECOM is not set -+# CONFIG_USB_STORAGE_ISD200 is not set -+# CONFIG_USB_STORAGE_USBAT is not set -+# CONFIG_USB_STORAGE_SDDR09 is not set -+# CONFIG_USB_STORAGE_SDDR55 is not set -+# CONFIG_USB_STORAGE_JUMPSHOT is not set -+# CONFIG_USB_STORAGE_ALAUDA is not set -+# CONFIG_USB_STORAGE_ONETOUCH is not set -+# CONFIG_USB_STORAGE_KARMA is not set -+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -+# CONFIG_USB_LIBUSUAL is not set -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+ -+# -+# USB port drivers -+# -+CONFIG_USB_SERIAL=m -+CONFIG_USB_EZUSB=y -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+# CONFIG_USB_SERIAL_CP210X is not set -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_FUNSOFT=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KEYSPAN_MPR=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19=y -+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_MOTOROLA=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+# CONFIG_USB_SERIAL_QUALCOMM is not set -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_HP4X=m -+CONFIG_USB_SERIAL_SAFE=m -+# CONFIG_USB_SERIAL_SAFE_PADDED is not set -+CONFIG_USB_SERIAL_SIEMENS_MPI=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+# CONFIG_USB_SERIAL_SYMBOL is not set -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_DEBUG=m -+ -+# -+# USB Miscellaneous drivers -+# -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+# CONFIG_USB_ADUTUX is not set -+# CONFIG_USB_SEVSEG is not set -+# CONFIG_USB_RIO500 is not set -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_BERRY_CHARGE=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m -+# CONFIG_USB_APPLEDISPLAY is not set -+CONFIG_USB_SISUSBVGA=m -+CONFIG_USB_SISUSBVGA_CON=y -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+# CONFIG_USB_IOWARRIOR is not set -+CONFIG_USB_TEST=m -+# CONFIG_USB_ISIGHTFW is not set -+CONFIG_USB_VST=m -+CONFIG_USB_ATM=m -+CONFIG_USB_SPEEDTOUCH=m -+CONFIG_USB_CXACRU=m -+CONFIG_USB_UEAGLEATM=m -+CONFIG_USB_XUSBATM=m -+CONFIG_USB_GADGET=y -+# CONFIG_USB_GADGET_DEBUG is not set -+# CONFIG_USB_GADGET_DEBUG_FILES is not set -+CONFIG_USB_GADGET_DEBUG_FS=y -+CONFIG_USB_GADGET_VBUS_DRAW=2 -+CONFIG_USB_GADGET_SELECTED=y -+# CONFIG_USB_GADGET_AT91 is not set -+# CONFIG_USB_GADGET_ATMEL_USBA is not set -+# CONFIG_USB_GADGET_FSL_USB2 is not set -+# CONFIG_USB_GADGET_LH7A40X is not set -+# CONFIG_USB_GADGET_OMAP is not set -+# CONFIG_USB_GADGET_PXA25X is not set -+# CONFIG_USB_GADGET_R8A66597 is not set -+# CONFIG_USB_GADGET_PXA27X is not set -+# CONFIG_USB_GADGET_S3C_HSOTG is not set -+# CONFIG_USB_GADGET_IMX is not set -+# CONFIG_USB_GADGET_S3C2410 is not set -+# CONFIG_USB_GADGET_M66592 is not set -+# CONFIG_USB_GADGET_AMD5536UDC is not set -+# CONFIG_USB_GADGET_FSL_QE is not set -+# CONFIG_USB_GADGET_CI13XXX is not set -+# CONFIG_USB_GADGET_NET2280 is not set -+# CONFIG_USB_GADGET_GOKU is not set -+# CONFIG_USB_GADGET_LANGWELL is not set -+# CONFIG_USB_GADGET_DUMMY_HCD is not set -+CONFIG_USB_GADGET_DUALSPEED=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_ZERO_HNPTEST=y -+# CONFIG_USB_AUDIO is not set -+CONFIG_USB_ETH=m -+CONFIG_USB_ETH_RNDIS=y -+# CONFIG_USB_ETH_EEM is not set -+CONFIG_USB_GADGETFS=m -+CONFIG_USB_FILE_STORAGE=m -+# CONFIG_USB_FILE_STORAGE_TEST is not set -+# CONFIG_USB_MASS_STORAGE is not set -+CONFIG_USB_G_SERIAL=m -+CONFIG_USB_MIDI_GADGET=m -+CONFIG_USB_G_PRINTER=m -+CONFIG_USB_CDC_COMPOSITE=m -+# CONFIG_USB_G_MULTI is not set -+ -+# -+# OTG and related infrastructure -+# -+CONFIG_USB_OTG_UTILS=y -+CONFIG_USB_GPIO_VBUS=y -+# CONFIG_ISP1301_OMAP is not set -+# CONFIG_USB_ULPI is not set -+CONFIG_TWL4030_USB=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_MMC=y -+# CONFIG_MMC_DEBUG is not set -+CONFIG_MMC_UNSAFE_RESUME=y -+ -+# -+# MMC/SD/SDIO Card Drivers -+# -+CONFIG_MMC_BLOCK=y -+CONFIG_MMC_BLOCK_BOUNCE=y -+CONFIG_SDIO_UART=y -+# CONFIG_MMC_TEST is not set -+ -+# -+# MMC/SD/SDIO Host Controller Drivers -+# -+# CONFIG_MMC_SDHCI is not set -+# CONFIG_MMC_OMAP is not set -+CONFIG_MMC_OMAP_HS=y -+# CONFIG_MMC_AT91 is not set -+# CONFIG_MMC_ATMELMCI is not set -+CONFIG_MMC_SPI=m -+# CONFIG_MEMSTICK is not set -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+ -+# -+# LED drivers -+# -+# CONFIG_LEDS_PCA9532 is not set -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_GPIO_PLATFORM=y -+# CONFIG_LEDS_LP3944 is not set -+# CONFIG_LEDS_PCA955X is not set -+# CONFIG_LEDS_DAC124S085 is not set -+# CONFIG_LEDS_BD2802 is not set -+ -+# -+# LED Triggers -+# -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=m -+# CONFIG_LEDS_TRIGGER_GPIO is not set -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -+ -+# -+# iptables trigger is under Netfilter config (LED target) -+# -+# CONFIG_ACCESSIBILITY is not set -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=m -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1374 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+# CONFIG_RTC_DRV_M41T80 is not set -+CONFIG_RTC_DRV_TWL4030=m -+# CONFIG_RTC_DRV_S35390A is not set -+# CONFIG_RTC_DRV_FM3130 is not set -+# CONFIG_RTC_DRV_RX8581 is not set -+# CONFIG_RTC_DRV_RX8025 is not set -+ -+# -+# SPI RTC drivers -+# -+# CONFIG_RTC_DRV_M41T94 is not set -+# CONFIG_RTC_DRV_DS1305 is not set -+# CONFIG_RTC_DRV_DS1390 is not set -+# CONFIG_RTC_DRV_MAX6902 is not set -+# CONFIG_RTC_DRV_R9701 is not set -+# CONFIG_RTC_DRV_RS5C348 is not set -+# CONFIG_RTC_DRV_DS3234 is not set -+# CONFIG_RTC_DRV_PCF2123 is not set -+ -+# -+# Platform RTC drivers -+# -+# CONFIG_RTC_DRV_CMOS is not set -+# CONFIG_RTC_DRV_DS1286 is not set -+# CONFIG_RTC_DRV_DS1511 is not set -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_STK17TA8 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T35 is not set -+# CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_MSM6242 is not set -+# CONFIG_RTC_DRV_BQ4802 is not set -+# CONFIG_RTC_DRV_RP5C01 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+# CONFIG_DMADEVICES is not set -+# CONFIG_AUXDISPLAY is not set -+CONFIG_UIO=m -+CONFIG_UIO_PDRV=m -+CONFIG_UIO_PDRV_GENIRQ=m -+# CONFIG_UIO_SMX is not set -+# CONFIG_UIO_SERCOS3 is not set -+ -+# -+# TI VLYNQ -+# -+CONFIG_STAGING=y -+# CONFIG_STAGING_EXCLUDE_BUILD is not set -+# CONFIG_USB_IP_COMMON is not set -+CONFIG_W35UND=m -+# CONFIG_PRISM2_USB is not set -+CONFIG_ECHO=m -+CONFIG_OTUS=m -+# CONFIG_COMEDI is not set -+# CONFIG_ASUS_OLED is not set -+# CONFIG_INPUT_MIMIO is not set -+# CONFIG_TRANZPORT is not set -+ -+# -+# Qualcomm MSM Camera And Video -+# -+ -+# -+# Camera Sensor Selection -+# -+# CONFIG_INPUT_GPIO is not set -+# CONFIG_DST is not set -+# CONFIG_POHMELFS is not set -+# CONFIG_PLAN9AUTH is not set -+# CONFIG_LINE6_USB is not set -+# CONFIG_USB_SERIAL_QUATECH2 is not set -+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -+# CONFIG_VT6656 is not set -+# CONFIG_FB_UDL is not set -+ -+# -+# RAR Register Driver -+# -+# CONFIG_RAR_REGISTER is not set -+# CONFIG_IIO is not set -+# CONFIG_RAMZSWAP is not set -+# CONFIG_BATMAN_ADV is not set -+# CONFIG_STRIP is not set -+ -+# -+# CBUS support -+# -+# CONFIG_CBUS is not set -+ -+# -+# File systems -+# -+CONFIG_FS_JOURNAL_INFO=y -+CONFIG_EXT2_FS=y -+# CONFIG_EXT2_FS_XATTR is not set -+# CONFIG_EXT2_FS_XIP is not set -+CONFIG_EXT3_FS=y -+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -+# CONFIG_EXT3_FS_XATTR is not set -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_XATTR=y -+# CONFIG_EXT4_FS_POSIX_ACL is not set -+# CONFIG_EXT4_FS_SECURITY is not set -+# CONFIG_EXT4_DEBUG is not set -+CONFIG_JBD=y -+# CONFIG_JBD_DEBUG is not set -+CONFIG_JBD2=y -+# CONFIG_JBD2_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+CONFIG_REISERFS_FS=m -+# CONFIG_REISERFS_CHECK is not set -+CONFIG_REISERFS_PROC_INFO=y -+CONFIG_REISERFS_FS_XATTR=y -+# CONFIG_REISERFS_FS_POSIX_ACL is not set -+# CONFIG_REISERFS_FS_SECURITY is not set -+CONFIG_JFS_FS=m -+# CONFIG_JFS_POSIX_ACL is not set -+# CONFIG_JFS_SECURITY is not set -+# CONFIG_JFS_DEBUG is not set -+# CONFIG_JFS_STATISTICS is not set -+CONFIG_FS_POSIX_ACL=y -+CONFIG_XFS_FS=m -+# CONFIG_XFS_QUOTA is not set -+# CONFIG_XFS_POSIX_ACL is not set -+# CONFIG_XFS_RT is not set -+# CONFIG_XFS_DEBUG is not set -+CONFIG_GFS2_FS=m -+# CONFIG_GFS2_FS_LOCKING_DLM is not set -+CONFIG_OCFS2_FS=m -+CONFIG_OCFS2_FS_O2CB=m -+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -+CONFIG_OCFS2_FS_STATS=y -+CONFIG_OCFS2_DEBUG_MASKLOG=y -+# CONFIG_OCFS2_DEBUG_FS is not set -+# CONFIG_OCFS2_FS_POSIX_ACL is not set -+CONFIG_BTRFS_FS=m -+# CONFIG_BTRFS_FS_POSIX_ACL is not set -+# CONFIG_NILFS2_FS is not set -+CONFIG_FILE_LOCKING=y -+CONFIG_FSNOTIFY=y -+CONFIG_DNOTIFY=y -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+CONFIG_QUOTA=y -+# CONFIG_QUOTA_NETLINK_INTERFACE is not set -+CONFIG_PRINT_QUOTA_WARNING=y -+CONFIG_QUOTA_TREE=y -+# CONFIG_QFMT_V1 is not set -+CONFIG_QFMT_V2=y -+CONFIG_QUOTACTL=y -+# CONFIG_AUTOFS_FS is not set -+CONFIG_AUTOFS4_FS=m -+CONFIG_FUSE_FS=m -+# CONFIG_CUSE is not set -+CONFIG_GENERIC_ACL=y -+ -+# -+# Caches -+# -+# CONFIG_FSCACHE is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+CONFIG_NTFS_FS=m -+# CONFIG_NTFS_DEBUG is not set -+CONFIG_NTFS_RW=y -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_PROC_PAGE_MONITOR=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+# CONFIG_HUGETLB_PAGE is not set -+CONFIG_CONFIGFS_FS=m -+CONFIG_MISC_FILESYSTEMS=y -+CONFIG_ADFS_FS=m -+# CONFIG_ADFS_FS_RW is not set -+CONFIG_AFFS_FS=m -+# CONFIG_ECRYPT_FS is not set -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+CONFIG_BEFS_FS=m -+# CONFIG_BEFS_DEBUG is not set -+CONFIG_BFS_FS=m -+CONFIG_EFS_FS=m -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+CONFIG_JFFS2_FS_POSIX_ACL=y -+CONFIG_JFFS2_FS_SECURITY=y -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y -+CONFIG_JFFS2_ZLIB=y -+CONFIG_JFFS2_LZO=y -+CONFIG_JFFS2_RTIME=y -+CONFIG_JFFS2_RUBIN=y -+# CONFIG_JFFS2_CMODE_NONE is not set -+# CONFIG_JFFS2_CMODE_PRIORITY is not set -+# CONFIG_JFFS2_CMODE_SIZE is not set -+CONFIG_JFFS2_CMODE_FAVOURLZO=y -+CONFIG_UBIFS_FS=y -+CONFIG_UBIFS_FS_XATTR=y -+CONFIG_UBIFS_FS_ADVANCED_COMPR=y -+CONFIG_UBIFS_FS_LZO=y -+CONFIG_UBIFS_FS_ZLIB=y -+# CONFIG_UBIFS_FS_DEBUG is not set -+CONFIG_CRAMFS=m -+CONFIG_SQUASHFS=y -+# CONFIG_SQUASHFS_EMBEDDED is not set -+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -+CONFIG_VXFS_FS=m -+CONFIG_MINIX_FS=m -+CONFIG_OMFS_FS=m -+CONFIG_HPFS_FS=m -+CONFIG_QNX4FS_FS=m -+CONFIG_ROMFS_FS=m -+CONFIG_ROMFS_BACKED_BY_BLOCK=y -+# CONFIG_ROMFS_BACKED_BY_MTD is not set -+# CONFIG_ROMFS_BACKED_BY_BOTH is not set -+CONFIG_ROMFS_ON_BLOCK=y -+CONFIG_SYSV_FS=m -+CONFIG_UFS_FS=m -+# CONFIG_UFS_FS_WRITE is not set -+# CONFIG_UFS_DEBUG is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+# CONFIG_NFS_V3_ACL is not set -+CONFIG_NFS_V4=y -+# CONFIG_NFS_V4_1 is not set -+CONFIG_ROOT_NFS=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V2_ACL=y -+CONFIG_NFSD_V3=y -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_EXPORTFS=m -+CONFIG_NFS_ACL_SUPPORT=m -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+CONFIG_SUNRPC_GSS=y -+CONFIG_RPCSEC_GSS_KRB5=y -+# CONFIG_RPCSEC_GSS_SPKM3 is not set -+CONFIG_SMB_FS=m -+# CONFIG_SMB_NLS_DEFAULT is not set -+CONFIG_CIFS=m -+CONFIG_CIFS_STATS=y -+CONFIG_CIFS_STATS2=y -+# CONFIG_CIFS_WEAK_PW_HASH is not set -+# CONFIG_CIFS_UPCALL is not set -+# CONFIG_CIFS_XATTR is not set -+# CONFIG_CIFS_DEBUG2 is not set -+# CONFIG_CIFS_DFS_UPCALL is not set -+CONFIG_CIFS_EXPERIMENTAL=y -+CONFIG_NCP_FS=m -+# CONFIG_NCPFS_PACKET_SIGNING is not set -+# CONFIG_NCPFS_IOCTL_LOCKING is not set -+# CONFIG_NCPFS_STRONG is not set -+# CONFIG_NCPFS_NFS_NS is not set -+# CONFIG_NCPFS_OS2_NS is not set -+# CONFIG_NCPFS_SMALLDOS is not set -+# CONFIG_NCPFS_NLS is not set -+# CONFIG_NCPFS_EXTRAS is not set -+CONFIG_CODA_FS=m -+CONFIG_AFS_FS=m -+# CONFIG_AFS_DEBUG is not set -+CONFIG_9P_FS=m -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+CONFIG_MAC_PARTITION=y -+CONFIG_MSDOS_PARTITION=y -+CONFIG_BSD_DISKLABEL=y -+CONFIG_MINIX_SUBPARTITION=y -+CONFIG_SOLARIS_X86_PARTITION=y -+# CONFIG_UNIXWARE_DISKLABEL is not set -+CONFIG_LDM_PARTITION=y -+CONFIG_LDM_DEBUG=y -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_SUN_PARTITION is not set -+# CONFIG_KARMA_PARTITION is not set -+CONFIG_EFI_PARTITION=y -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="iso8859-1" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=m -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_UTF8=y -+CONFIG_DLM=m -+# CONFIG_DLM_DEBUG is not set -+ -+# -+# Kernel hacking -+# -+CONFIG_PRINTK_TIME=y -+CONFIG_ENABLE_WARN_DEPRECATED=y -+CONFIG_ENABLE_MUST_CHECK=y -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_STRIP_ASM_SYMS is not set -+# CONFIG_UNUSED_SYMBOLS is not set -+CONFIG_DEBUG_FS=y -+# CONFIG_HEADERS_CHECK is not set -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_DETECT_SOFTLOCKUP=y -+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -+CONFIG_DETECT_HUNG_TASK=y -+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -+CONFIG_SCHED_DEBUG=y -+CONFIG_SCHEDSTATS=y -+CONFIG_TIMER_STATS=y -+# CONFIG_DEBUG_OBJECTS is not set -+# CONFIG_DEBUG_SLAB is not set -+# CONFIG_DEBUG_KMEMLEAK is not set -+CONFIG_DEBUG_PREEMPT=y -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+CONFIG_DEBUG_MUTEXES=y -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+CONFIG_STACKTRACE=y -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_DEBUG_INFO is not set -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_WRITECOUNT is not set -+# CONFIG_DEBUG_MEMORY_INIT is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_SG is not set -+# CONFIG_DEBUG_NOTIFIERS is not set -+# CONFIG_DEBUG_CREDENTIALS is not set -+# CONFIG_BOOT_PRINTK_DELAY is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_RCU_CPU_STALL_DETECTOR is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -+# CONFIG_FAULT_INJECTION is not set -+# CONFIG_LATENCYTOP is not set -+# CONFIG_SYSCTL_SYSCALL_CHECK is not set -+# CONFIG_PAGE_POISONING is not set -+CONFIG_NOP_TRACER=y -+CONFIG_HAVE_FUNCTION_TRACER=y -+CONFIG_RING_BUFFER=y -+CONFIG_EVENT_TRACING=y -+CONFIG_CONTEXT_SWITCH_TRACER=y -+CONFIG_RING_BUFFER_ALLOW_SWAP=y -+CONFIG_TRACING=y -+CONFIG_TRACING_SUPPORT=y -+CONFIG_FTRACE=y -+# CONFIG_FUNCTION_TRACER is not set -+# CONFIG_IRQSOFF_TRACER is not set -+# CONFIG_PREEMPT_TRACER is not set -+# CONFIG_SCHED_TRACER is not set -+# CONFIG_ENABLE_DEFAULT_TRACERS is not set -+# CONFIG_BOOT_TRACER is not set -+CONFIG_BRANCH_PROFILE_NONE=y -+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -+# CONFIG_PROFILE_ALL_BRANCHES is not set -+# CONFIG_STACK_TRACER is not set -+# CONFIG_KMEMTRACE is not set -+# CONFIG_WORKQUEUE_TRACER is not set -+# CONFIG_BLK_DEV_IO_TRACE is not set -+# CONFIG_RING_BUFFER_BENCHMARK is not set -+# CONFIG_DYNAMIC_DEBUG is not set -+# CONFIG_SAMPLES is not set -+CONFIG_HAVE_ARCH_KGDB=y -+# CONFIG_KGDB is not set -+CONFIG_ARM_UNWIND=y -+# CONFIG_DEBUG_USER is not set -+# CONFIG_DEBUG_ERRORS is not set -+# CONFIG_DEBUG_STACK_USAGE is not set -+# CONFIG_DEBUG_LL is not set -+# CONFIG_OC_ETM is not set -+ -+# -+# Security options -+# -+CONFIG_KEYS=y -+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITYFS is not set -+# CONFIG_DEFAULT_SECURITY_SELINUX is not set -+# CONFIG_DEFAULT_SECURITY_SMACK is not set -+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -+CONFIG_DEFAULT_SECURITY_DAC=y -+CONFIG_DEFAULT_SECURITY="" -+CONFIG_XOR_BLOCKS=m -+CONFIG_ASYNC_CORE=m -+CONFIG_ASYNC_MEMCPY=m -+CONFIG_ASYNC_XOR=m -+CONFIG_ASYNC_PQ=m -+CONFIG_ASYNC_RAID6_RECOV=m -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_FIPS=y -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_ALGAPI2=y -+CONFIG_CRYPTO_AEAD=m -+CONFIG_CRYPTO_AEAD2=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_BLKCIPHER2=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_HASH2=y -+CONFIG_CRYPTO_RNG=m -+CONFIG_CRYPTO_RNG2=y -+CONFIG_CRYPTO_PCOMP=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_MANAGER2=y -+CONFIG_CRYPTO_GF128MUL=m -+CONFIG_CRYPTO_NULL=m -+CONFIG_CRYPTO_WORKQUEUE=y -+CONFIG_CRYPTO_CRYPTD=m -+CONFIG_CRYPTO_AUTHENC=m -+CONFIG_CRYPTO_TEST=m -+ -+# -+# Authenticated Encryption with Associated Data -+# -+CONFIG_CRYPTO_CCM=m -+CONFIG_CRYPTO_GCM=m -+CONFIG_CRYPTO_SEQIV=m -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTR=m -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_ECB=y -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_PCBC=m -+CONFIG_CRYPTO_XTS=m -+ -+# -+# Hash modes -+# -+CONFIG_CRYPTO_HMAC=m -+CONFIG_CRYPTO_XCBC=m -+# CONFIG_CRYPTO_VMAC is not set -+ -+# -+# Digest -+# -+CONFIG_CRYPTO_CRC32C=y -+CONFIG_CRYPTO_GHASH=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA1=m -+CONFIG_CRYPTO_SHA256=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+ -+# -+# Ciphers -+# -+CONFIG_CRYPTO_AES=y -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_ARC4=y -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_SALSA20=m -+CONFIG_CRYPTO_SEED=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_TWOFISH_COMMON=m -+ -+# -+# Compression -+# -+CONFIG_CRYPTO_DEFLATE=y -+# CONFIG_CRYPTO_ZLIB is not set -+CONFIG_CRYPTO_LZO=y -+ -+# -+# Random Number Generation -+# -+CONFIG_CRYPTO_ANSI_CPRNG=m -+CONFIG_CRYPTO_HW=y -+CONFIG_BINARY_PRINTF=y -+ -+# -+# Library routines -+# -+CONFIG_BITREVERSE=y -+CONFIG_GENERIC_FIND_LAST_BIT=y -+CONFIG_CRC_CCITT=y -+CONFIG_CRC16=y -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC_ITU_T=y -+CONFIG_CRC32=y -+CONFIG_CRC7=y -+CONFIG_LIBCRC32C=y -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_LZO_COMPRESS=y -+CONFIG_LZO_DECOMPRESS=y -+CONFIG_DECOMPRESS_GZIP=y -+CONFIG_TEXTSEARCH=y -+CONFIG_TEXTSEARCH_KMP=m -+CONFIG_TEXTSEARCH_BM=m -+CONFIG_TEXTSEARCH_FSM=m -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT=y -+CONFIG_HAS_DMA=y -+CONFIG_NLATTR=y --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0006-omap3beagle-camera-Add-support-for-regulators.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0006-omap3beagle-camera-Add-support-for-regulators.patch deleted file mode 100644 index 1af46198..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0006-omap3beagle-camera-Add-support-for-regulators.patch +++ /dev/null @@ -1,238 +0,0 @@ -From a8bad5bfa652d2e35575f864da6192d41c85c818 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 16:50:39 -0500 -Subject: [PATCH 06/75] omap3beagle: camera: Add support for regulators - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 92 +++++++++++++++++++++--- - arch/arm/mach-omap2/board-omap3beagle.c | 53 ++++++++++++++ - 2 files changed, 135 insertions(+), 10 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index e93437f..af8581a 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -28,8 +28,9 @@ - #include - #include - #include --#include -+#include - #include -+#include - - #include - #include -@@ -50,6 +51,11 @@ - - #define CAM_USE_XCLKA 1 - -+static struct regulator *beagle_mt9t111_reg1; -+static struct regulator *beagle_mt9t111_reg2; -+ -+static struct device *beaglecam_dev; -+ - #if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) - static struct isp_interface_config mt9t111_if_config = { - .ccdc_par_ser = ISP_PARLL, -@@ -157,10 +163,13 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - - switch (power) { - case V4L2_POWER_OFF: -+ case V4L2_POWER_STANDBY: - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); -- break; - -- case V4L2_POWER_STANDBY: -+ if (regulator_is_enabled(beagle_mt9t111_reg1)) -+ regulator_disable(beagle_mt9t111_reg1); -+ if (regulator_is_enabled(beagle_mt9t111_reg2)) -+ regulator_disable(beagle_mt9t111_reg2); - break; - - case V4L2_POWER_ON: -@@ -169,6 +178,12 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - isp_configure_interface(vdev->cam->isp, &mt9t111_if_config); - #endif -+ -+ /* turn on analog power */ -+ regulator_enable(beagle_mt9t111_reg1); -+ regulator_enable(beagle_mt9t111_reg2); -+ udelay(100); -+ - break; - - default: -@@ -196,16 +211,22 @@ static struct i2c_board_info __initdata mt9t111_i2c_board_info = { - - #endif /* #ifdef CONFIG_VIDEO_MT9T111 */ - --/** -- * @brief omap3beaglelmb_init - module init function. Should be called before any -- * client driver init call -- * -- * @return result of operation - 0 is success -- */ --int __init omap3beaglelmb_init(void) -+ -+static int beagle_cam_probe(struct platform_device *pdev) - { - int err; - -+ beagle_mt9t111_reg1 = regulator_get(beaglecam_dev, "vaux3_1"); -+ if (IS_ERR(beagle_mt9t111_reg1)) { -+ dev_err(beaglecam_dev, "vaux3_1 regulator missing\n"); -+ return PTR_ERR(beagle_mt9t111_reg1); -+ } -+ beagle_mt9t111_reg2 = regulator_get(beaglecam_dev, "vaux4_1"); -+ if (IS_ERR(beagle_mt9t111_reg2)) { -+ dev_err(beaglecam_dev, "vaux4_1 regulator missing\n"); -+ regulator_put(beagle_mt9t111_reg1); -+ return PTR_ERR(beagle_mt9t111_reg2); -+ } - /* - * Register the I2C devices present in the board to the I2C - * framework. -@@ -221,8 +242,59 @@ int __init omap3beaglelmb_init(void) - return err; - } - #endif -+ -+ beaglecam_dev = &pdev->dev; -+ - printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); - - return 0; - } -+ -+static int beagle_cam_remove(struct platform_device *pdev) -+{ -+ if (regulator_is_enabled(beagle_mt9t111_reg1)) -+ regulator_disable(beagle_mt9t111_reg1); -+ regulator_put(beagle_mt9t111_reg1); -+ if (regulator_is_enabled(beagle_mt9t111_reg2)) -+ regulator_disable(beagle_mt9t111_reg2); -+ regulator_put(beagle_mt9t111_reg2); -+ -+ return 0; -+} -+ -+static int beagle_cam_suspend(struct device *dev) -+{ -+ return 0; -+} -+ -+static int beagle_cam_resume(struct device *dev) -+{ -+ return 0; -+} -+ -+static struct dev_pm_ops beagle_cam_pm_ops = { -+ .suspend = beagle_cam_suspend, -+ .resume = beagle_cam_resume, -+}; -+ -+static struct platform_driver beagle_cam_driver = { -+ .probe = beagle_cam_probe, -+ .remove = beagle_cam_remove, -+ .driver = { -+ .name = "beagle_cam", -+ .pm = &beagle_cam_pm_ops, -+ }, -+}; -+ -+/** -+ * @brief omap3beaglelmb_init - module init function. Should be called before any -+ * client driver init call -+ * -+ * @return result of operation - 0 is success -+ */ -+int __init omap3beaglelmb_init(void) -+{ -+ platform_driver_register(&beagle_cam_driver); -+ return 0; -+} - arch_initcall(omap3beaglelmb_init); -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index d6b69a6..aa16acd 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -403,6 +403,56 @@ static struct twl4030_gpio_platform_data beagle_gpio_data = { - .setup = beagle_twl_gpio_setup, - }; - -+ -+static struct platform_device beagle_cam_device = { -+ .name = "beagle_cam", -+ .id = -1, -+}; -+ -+static struct regulator_consumer_supply beagle_vaux3_supplies[] = { -+ { -+ .supply = "vaux3_1", -+ .dev = &beagle_cam_device.dev, -+ }, -+}; -+ -+static struct regulator_consumer_supply beagle_vaux4_supplies[] = { -+ { -+ .supply = "vaux4_1", -+ .dev = &beagle_cam_device.dev, -+ }, -+}; -+ -+/* VAUX3 for CAM_1V8 */ -+static struct regulator_init_data beagle_vaux3 = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .apply_uV = true, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(beagle_vaux3_supplies), -+ .consumer_supplies = beagle_vaux3_supplies, -+}; -+ -+/* VAUX4 for CAM_2V8 */ -+static struct regulator_init_data beagle_vaux4 = { -+ .constraints = { -+ .min_uV = 2800000, -+ .max_uV = 2800000, -+ .apply_uV = true, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(beagle_vaux4_supplies), -+ .consumer_supplies = beagle_vaux4_supplies, -+}; -+ - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ - static struct regulator_init_data beagle_vmmc1 = { - .constraints = { -@@ -492,6 +542,8 @@ static struct twl4030_platform_data beagle_twldata = { - .vsim = &beagle_vsim, - .vdac = &beagle_vdac, - .vpll2 = &beagle_vpll2, -+ .vaux3 = &beagle_vaux3, -+ .vaux4 = &beagle_vaux4, - }; - - static struct i2c_board_info __initdata beagle_i2c1_boardinfo[] = { -@@ -658,6 +710,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { - &leds_gpio, - &keys_gpio, - &beagle_dss_device, -+ &beagle_cam_device, - }; - - static void __init omap3beagle_flash_init(void) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0007-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0007-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch deleted file mode 100644 index 76140eb8..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0007-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 297b25089d0a06c89101e4f6a3189419be19369f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 16:52:25 -0500 -Subject: [PATCH 07/75] TEMP: omap3beagle: cam: Enable OMAP_MUX - -Signed-off-by: Sergio Aguirre ---- - arch/arm/configs/omap3_beagle_cam_defconfig | 6 ++++-- - 1 files changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/configs/omap3_beagle_cam_defconfig b/arch/arm/configs/omap3_beagle_cam_defconfig -index 0ea8300..bcd9418 100644 ---- a/arch/arm/configs/omap3_beagle_cam_defconfig -+++ b/arch/arm/configs/omap3_beagle_cam_defconfig -@@ -1,7 +1,7 @@ - # - # Automatically generated make config: don't edit - # Linux kernel version: 2.6.32 --# Fri Jun 11 14:25:23 2010 -+# Fri Jun 11 16:51:42 2010 - # - CONFIG_ARM=y - CONFIG_SYS_SUPPORTS_APM_EMULATION=y -@@ -240,7 +240,9 @@ CONFIG_ARCH_OMAP3=y - CONFIG_OMAP_SMARTREFLEX=y - # CONFIG_OMAP_SMARTREFLEX_TESTING is not set - CONFIG_OMAP_RESET_CLOCKS=y --# CONFIG_OMAP_MUX is not set -+CONFIG_OMAP_MUX=y -+# CONFIG_OMAP_MUX_DEBUG is not set -+CONFIG_OMAP_MUX_WARNINGS=y - CONFIG_OMAP_MCBSP=y - CONFIG_OMAP_MBOX_FWK=m - CONFIG_OMAP_IOMMU=y --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0008-omap3beagle-camera-Fix-null-pointer-dereference.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0008-omap3beagle-camera-Fix-null-pointer-dereference.patch deleted file mode 100644 index ecc83965..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0008-omap3beagle-camera-Fix-null-pointer-dereference.patch +++ /dev/null @@ -1,54 +0,0 @@ -From c46eeb468f9bb69ca4c82abd1ff07e0f35aaa50f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 11 Jun 2010 17:53:50 -0500 -Subject: [PATCH 08/75] omap3beagle: camera: Fix null pointer dereference - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 12 ++++-------- - 1 files changed, 4 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index af8581a..20174a7 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -54,8 +54,6 @@ - static struct regulator *beagle_mt9t111_reg1; - static struct regulator *beagle_mt9t111_reg2; - --static struct device *beaglecam_dev; -- - #if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) - static struct isp_interface_config mt9t111_if_config = { - .ccdc_par_ser = ISP_PARLL, -@@ -216,14 +214,14 @@ static int beagle_cam_probe(struct platform_device *pdev) - { - int err; - -- beagle_mt9t111_reg1 = regulator_get(beaglecam_dev, "vaux3_1"); -+ beagle_mt9t111_reg1 = regulator_get(&pdev->dev, "vaux3_1"); - if (IS_ERR(beagle_mt9t111_reg1)) { -- dev_err(beaglecam_dev, "vaux3_1 regulator missing\n"); -+ dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); - return PTR_ERR(beagle_mt9t111_reg1); - } -- beagle_mt9t111_reg2 = regulator_get(beaglecam_dev, "vaux4_1"); -+ beagle_mt9t111_reg2 = regulator_get(&pdev->dev, "vaux4_1"); - if (IS_ERR(beagle_mt9t111_reg2)) { -- dev_err(beaglecam_dev, "vaux4_1 regulator missing\n"); -+ dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); - regulator_put(beagle_mt9t111_reg1); - return PTR_ERR(beagle_mt9t111_reg2); - } -@@ -243,8 +241,6 @@ static int beagle_cam_probe(struct platform_device *pdev) - } - #endif - -- beaglecam_dev = &pdev->dev; -- - printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); - - return 0; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0009-Revert-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0009-Revert-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch deleted file mode 100644 index cfcd2360..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0009-Revert-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 4dc4c88bdb1f4be3de42f1cf5e8d5d62b6a2a04e Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Wed, 16 Jun 2010 03:23:57 +0300 -Subject: [PATCH 09/75] Revert "TEMP: omap3beagle: cam: Enable OMAP_MUX" - -This reverts commit 7d5f49845f06feadb9bc97d458d1ce03814ff5f4. - -Reason? - -Kernel panic on MMC partition mount, so probably muxing is broken -somewhere. ---- - arch/arm/configs/omap3_beagle_cam_defconfig | 6 ++---- - 1 files changed, 2 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/configs/omap3_beagle_cam_defconfig b/arch/arm/configs/omap3_beagle_cam_defconfig -index bcd9418..0ea8300 100644 ---- a/arch/arm/configs/omap3_beagle_cam_defconfig -+++ b/arch/arm/configs/omap3_beagle_cam_defconfig -@@ -1,7 +1,7 @@ - # - # Automatically generated make config: don't edit - # Linux kernel version: 2.6.32 --# Fri Jun 11 16:51:42 2010 -+# Fri Jun 11 14:25:23 2010 - # - CONFIG_ARM=y - CONFIG_SYS_SUPPORTS_APM_EMULATION=y -@@ -240,9 +240,7 @@ CONFIG_ARCH_OMAP3=y - CONFIG_OMAP_SMARTREFLEX=y - # CONFIG_OMAP_SMARTREFLEX_TESTING is not set - CONFIG_OMAP_RESET_CLOCKS=y --CONFIG_OMAP_MUX=y --# CONFIG_OMAP_MUX_DEBUG is not set --CONFIG_OMAP_MUX_WARNINGS=y -+# CONFIG_OMAP_MUX is not set - CONFIG_OMAP_MCBSP=y - CONFIG_OMAP_MBOX_FWK=m - CONFIG_OMAP_IOMMU=y --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0010-omap3beagle-camera-Change-arch-late_initcall.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0010-omap3beagle-camera-Change-arch-late_initcall.patch deleted file mode 100644 index c9f2340a..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0010-omap3beagle-camera-Change-arch-late_initcall.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e998edf3c99b4f8a16519a2dc968b1841a274b7f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Wed, 16 Jun 2010 04:28:06 +0300 -Subject: [PATCH 10/75] omap3beagle: camera: Change arch -> late_initcall - -This is for ensuring that the regulators are initialized already. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 20174a7..55a113c 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -293,4 +293,4 @@ int __init omap3beaglelmb_init(void) - platform_driver_register(&beagle_cam_driver); - return 0; - } --arch_initcall(omap3beaglelmb_init); -+late_initcall(omap3beaglelmb_init); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0011-omap3beagle-camera-Move-i2c-registration-to-the-main.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0011-omap3beagle-camera-Move-i2c-registration-to-the-main.patch deleted file mode 100644 index 15e647e5..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0011-omap3beagle-camera-Move-i2c-registration-to-the-main.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 17c85e1bf42b03f4e764280b8a626853506517e6 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Wed, 16 Jun 2010 04:58:46 +0300 -Subject: [PATCH 11/75] omap3beagle: camera: Move i2c registration to the main board - -This is because the board-omap3beagle-camera.c file now is -late_initcall, and the i2c bus registration needed to be before -i2c host init. - -So, in order to have the i2c init, meanwhile having late_initcall, -this is so far the best solution. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 24 +----------------------- - arch/arm/mach-omap2/board-omap3beagle.c | 12 +++++++++++- - 2 files changed, 12 insertions(+), 24 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 55a113c..1652f15 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -47,8 +47,6 @@ - - #define MODULE_NAME "omap3beaglelmb" - --#define MT9T111_I2C_BUSNUM (2) -- - #define CAM_USE_XCLKA 1 - - static struct regulator *beagle_mt9t111_reg1; -@@ -191,7 +189,7 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - return 0; - } - --static struct mt9t111_platform_data mt9t111_pdata = { -+struct mt9t111_platform_data mt9t111_pdata = { - .master = "omap34xxcam", - .power_set = mt9t111_power_set, - .priv_data_set = mt9t111_set_prv_data, -@@ -202,11 +200,6 @@ static struct mt9t111_platform_data mt9t111_pdata = { - .vs_polarity = 1, /* 0 - Active low, 1- Active high */ - }; - --static struct i2c_board_info __initdata mt9t111_i2c_board_info = { -- I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), -- .platform_data = &mt9t111_pdata, --}; -- - #endif /* #ifdef CONFIG_VIDEO_MT9T111 */ - - -@@ -225,21 +218,6 @@ static int beagle_cam_probe(struct platform_device *pdev) - regulator_put(beagle_mt9t111_reg1); - return PTR_ERR(beagle_mt9t111_reg2); - } -- /* -- * Register the I2C devices present in the board to the I2C -- * framework. -- * If more I2C devices are added, then each device information should -- * be registered with I2C using i2c_register_board_info(). -- */ --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -- err = i2c_register_board_info(MT9T111_I2C_BUSNUM, -- &mt9t111_i2c_board_info, 1); -- if (err) { -- printk(KERN_ERR MODULE_NAME \ -- ": MT9T111 I2C Board Registration failed \n"); -- return err; -- } --#endif - - printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index aa16acd..757d430 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -71,6 +71,11 @@ static struct omap_opp * _omap35x_l3_rate_table = NULL; - static struct omap_opp * _omap37x_l3_rate_table = NULL; - #endif /* CONFIG_PM */ - -+#ifdef CONFIG_VIDEO_MT9T111 -+#include -+#include -+extern struct mt9t111_platform_data mt9t111_pdata; -+#endif - - #define GPMC_CS0_BASE 0x60 - #define GPMC_CS_SIZE 0x30 -@@ -588,7 +593,12 @@ static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = { - static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = {}; - #endif - --static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = {}; -+static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { -+ { -+ I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), -+ .platform_data = &mt9t111_pdata, -+ }, -+}; - - static int __init omap3_beagle_i2c_init(void) - { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0012-ARM-OMAP3-make-camera-code-build-if-MT9T111-is-built.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0012-ARM-OMAP3-make-camera-code-build-if-MT9T111-is-built.patch deleted file mode 100644 index 7edb1563..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0012-ARM-OMAP3-make-camera-code-build-if-MT9T111-is-built.patch +++ /dev/null @@ -1,38 +0,0 @@ -From a36ff286ba2355488bd093f001a722d888cf9a8b Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Wed, 16 Jun 2010 09:45:46 +0200 -Subject: [PATCH 12/75] ARM: OMAP3: make camera code build if MT9T111 is built as module or disabled - ---- - arch/arm/mach-omap2/board-omap3beagle.c | 4 +++- - 1 files changed, 3 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 757d430..1e9a868 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -71,7 +71,7 @@ static struct omap_opp * _omap35x_l3_rate_table = NULL; - static struct omap_opp * _omap37x_l3_rate_table = NULL; - #endif /* CONFIG_PM */ - --#ifdef CONFIG_VIDEO_MT9T111 -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) - #include - #include - extern struct mt9t111_platform_data mt9t111_pdata; -@@ -594,10 +594,12 @@ static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = {}; - #endif - - static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) - { - I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), - .platform_data = &mt9t111_pdata, - }, -+#endif - }; - - static int __init omap3_beagle_i2c_init(void) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0013-DEBUG-omap3beagle-camera-Force-mode0-in-cam_xclka.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0013-DEBUG-omap3beagle-camera-Force-mode0-in-cam_xclka.patch deleted file mode 100644 index fceb5ed4..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0013-DEBUG-omap3beagle-camera-Force-mode0-in-cam_xclka.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 7c09434499a8daa650b934a62d3f651f868e0e70 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Wed, 23 Jun 2010 15:03:24 -0500 -Subject: [PATCH 13/75] DEBUG: omap3beagle: camera: Force mode0 in cam_xclka - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 3 +++ - 1 files changed, 3 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 1652f15..77f9469 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -34,6 +34,7 @@ - - #include - #include -+#include - - #include - #include -@@ -160,6 +161,7 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - switch (power) { - case V4L2_POWER_OFF: - case V4L2_POWER_STANDBY: -+ omap_ctrl_writew(0x0, 0x110); /* Control XCLKA output mux */ - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - - if (regulator_is_enabled(beagle_mt9t111_reg1)) -@@ -169,6 +171,7 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - break; - - case V4L2_POWER_ON: -+ omap_ctrl_writew(0x0, 0x110); /* Control XCLKA output mux */ - isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); - - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0014-OMAP3-CLOCK-Add-capability-to-change-rate-of-dpll4_m.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0014-OMAP3-CLOCK-Add-capability-to-change-rate-of-dpll4_m.patch deleted file mode 100644 index 0b4df884..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0014-OMAP3-CLOCK-Add-capability-to-change-rate-of-dpll4_m.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2841aa647058815680fe3ef969e7fda5e821016f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 4 Feb 2010 18:12:37 -0600 -Subject: [PATCH 14/75] OMAP3: CLOCK: Add capability to change rate of dpll4_m5_ck_3630 - -Add necessary clk_sel definitions to clock framework to allow changing -dpll4_m5_ck_3630 rate. - -Based on patch by Tuukka Toivonen with subject: - - OMAP3: CLOCK: Add capability to change rate of dpll4_m5_ck - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/clock34xx_data.c | 2 ++ - 1 files changed, 2 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c -index 89e2f61..8d101ef 100644 ---- a/arch/arm/mach-omap2/clock34xx_data.c -+++ b/arch/arm/mach-omap2/clock34xx_data.c -@@ -934,6 +934,8 @@ static struct clk dpll4_m5_ck_3630 __initdata = { - .clksel = div32_dpll4_clksel, - .clkdm_name = "dpll4_clkdm", - .recalc = &omap2_clksel_recalc, -+ .set_rate = &omap2_clksel_set_rate, -+ .round_rate = &omap2_clksel_round_rate, - }; - - /* The PWRDN bit is apparently only available on 3430ES2 and above */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0015-Revert-DEBUG-omap3beagle-camera-Force-mode0-in-cam_x.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0015-Revert-DEBUG-omap3beagle-camera-Force-mode0-in-cam_x.patch deleted file mode 100644 index 090043b9..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0015-Revert-DEBUG-omap3beagle-camera-Force-mode0-in-cam_x.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 1ae58f6d2ec41a1b7d0cdeca4de4b9d9760195bf Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 24 Jun 2010 14:27:39 -0500 -Subject: [PATCH 15/75] Revert "DEBUG: omap3beagle: camera: Force mode0 in cam_xclka" - -This reverts commit 158e14b3d449dde2c6aa9f8cddb86fbbee2d2cd7. ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 3 --- - 1 files changed, 0 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 77f9469..1652f15 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -34,7 +34,6 @@ - - #include - #include --#include - - #include - #include -@@ -161,7 +160,6 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - switch (power) { - case V4L2_POWER_OFF: - case V4L2_POWER_STANDBY: -- omap_ctrl_writew(0x0, 0x110); /* Control XCLKA output mux */ - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - - if (regulator_is_enabled(beagle_mt9t111_reg1)) -@@ -171,7 +169,6 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - break; - - case V4L2_POWER_ON: -- omap_ctrl_writew(0x0, 0x110); /* Control XCLKA output mux */ - isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); - - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0016-omap3beagle-camera-Fix-wrong-XCLKA-selection.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0016-omap3beagle-camera-Fix-wrong-XCLKA-selection.patch deleted file mode 100644 index 68dd1b50..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0016-omap3beagle-camera-Fix-wrong-XCLKA-selection.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 00bfc925651aa2c35a1726f15c028ef106f350ab Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 24 Jun 2010 17:31:49 -0500 -Subject: [PATCH 16/75] omap3beagle: camera: Fix wrong XCLKA selection - -The CAM_USE_XCLKA should have been 0 instead of 1. - -Otherwise it was activating XCLKB instead! - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 1652f15..75c8345 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -47,7 +47,7 @@ - - #define MODULE_NAME "omap3beaglelmb" - --#define CAM_USE_XCLKA 1 -+#define CAM_USE_XCLKA 0 - - static struct regulator *beagle_mt9t111_reg1; - static struct regulator *beagle_mt9t111_reg2; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0017-omap3isp-set-CAM_MCLK-to-172.8-MHz-allows-exact-9.6-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0017-omap3isp-set-CAM_MCLK-to-172.8-MHz-allows-exact-9.6-.patch deleted file mode 100644 index 78f7296a..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0017-omap3isp-set-CAM_MCLK-to-172.8-MHz-allows-exact-9.6-.patch +++ /dev/null @@ -1,91 +0,0 @@ -From fc6044176be3518fee98430ebe36cc144d6feed2 Mon Sep 17 00:00:00 2001 -From: Tuukka Toivonen -Date: Thu, 2 Jul 2009 16:17:55 +0200 -Subject: [PATCH 17/75] omap3isp: set CAM_MCLK to 172.8 MHz, allows exact 9.6 MHz for camera xclka/b - -Camera cam_xclka and cam_xclkb clocks are generated by dividing -CAM_MCLK with an integer. We want to use 9.6 MHz for cameras, -so CAM_MCLK should be multiple of it. Otherwise the generated -frequency is slightly off due to rounding. - -Signed-off-by: Tuukka Toivonen ---- - drivers/media/video/isp/isp.c | 14 ++++++++++++++ - drivers/media/video/isp/isp.h | 1 + - drivers/media/video/isp/ispreg.h | 2 +- - 3 files changed, 16 insertions(+), 1 deletions(-) - -diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c -index ceed870..9d46c01 100644 ---- a/drivers/media/video/isp/isp.c -+++ b/drivers/media/video/isp/isp.c -@@ -2333,6 +2333,11 @@ static int isp_enable_clocks(struct device *dev) - dev_err(dev, "clk_enable cam_ick failed\n"); - goto out_clk_enable_ick; - } -+ r = clk_set_rate(isp->dpll4_m5_ck, CM_CAM_MCLK_HZ/2); -+ if (r) { -+ dev_err(dev, "clk_set_rate for dpll4_m5_ck failed\n"); -+ goto out_clk_enable_mclk; -+ } - r = clk_enable(isp->cam_mclk); - if (r) { - dev_err(dev, "clk_enable cam_mclk failed\n"); -@@ -2499,6 +2504,7 @@ static int isp_remove(struct platform_device *pdev) - - clk_put(isp->cam_ick); - clk_put(isp->cam_mclk); -+ clk_put(isp->dpll4_m5_ck); - clk_put(isp->csi2_fck); - clk_put(isp->l3_ick); - -@@ -2674,6 +2680,12 @@ static int isp_probe(struct platform_device *pdev) - ret_err = PTR_ERR(isp->cam_mclk); - goto out_clk_get_mclk; - } -+ isp->dpll4_m5_ck = clk_get(&camera_dev, "dpll4_m5_ck"); -+ if (IS_ERR(isp->dpll4_m5_ck)) { -+ dev_err(isp->dev, "clk_get dpll4_m5_ck failed\n"); -+ ret_err = PTR_ERR(isp->dpll4_m5_ck); -+ goto out_clk_get_dpll4_m5_ck; -+ } - isp->csi2_fck = clk_get(&camera_dev, "csi2_96m_fck"); - if (IS_ERR(isp->csi2_fck)) { - dev_err(isp->dev, "clk_get csi2_96m_fck failed\n"); -@@ -2734,6 +2746,8 @@ out_request_irq: - out_clk_get_l3_ick: - clk_put(isp->csi2_fck); - out_clk_get_csi2_fclk: -+ clk_put(isp->dpll4_m5_ck); -+out_clk_get_dpll4_m5_ck: - clk_put(isp->cam_mclk); - out_clk_get_mclk: - clk_put(isp->cam_ick); -diff --git a/drivers/media/video/isp/isp.h b/drivers/media/video/isp/isp.h -index dc85d61..6b100b6 100644 ---- a/drivers/media/video/isp/isp.h -+++ b/drivers/media/video/isp/isp.h -@@ -414,6 +414,7 @@ struct isp_device { - int ref_count; - struct clk *cam_ick; - struct clk *cam_mclk; -+ struct clk *dpll4_m5_ck; - struct clk *csi2_fck; - struct clk *l3_ick; - struct isp_interface_config *config; -diff --git a/drivers/media/video/isp/ispreg.h b/drivers/media/video/isp/ispreg.h -index 676a33d..1240e0e 100644 ---- a/drivers/media/video/isp/ispreg.h -+++ b/drivers/media/video/isp/ispreg.h -@@ -116,7 +116,7 @@ - #define ISP_32B_BOUNDARY_BUF 0xFFFFFFE0 - #define ISP_32B_BOUNDARY_OFFSET 0x0000FFE0 - --#define CM_CAM_MCLK_HZ 216000000 -+#define CM_CAM_MCLK_HZ 172800000 /* Hz */ - - /* ISP Submodules offset */ - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0018-Fix-Moved-MCLK-setting-to-the-board-file.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0018-Fix-Moved-MCLK-setting-to-the-board-file.patch deleted file mode 100644 index a47ee196..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0018-Fix-Moved-MCLK-setting-to-the-board-file.patch +++ /dev/null @@ -1,209 +0,0 @@ -From 6e9a8ed420020b5692b511b3e8a7c2c1325e1ca2 Mon Sep 17 00:00:00 2001 -From: Penda, Naveen -Date: Thu, 22 Oct 2009 06:07:01 +0530 -Subject: [PATCH 18/75] Fix: Moved MCLK setting to the board file - -This patch provides the flexibility to set the MCLK frequency - from the board file - -Signed-off-by: Naveen Penda -Signed-off-by: Curran, Dominic ---- - arch/arm/mach-omap2/board-zoom2-camera.c | 10 ++++++ - drivers/media/video/isp/isp.c | 51 +++++++++++++++++++---------- - drivers/media/video/isp/isp.h | 6 +++ - 3 files changed, 49 insertions(+), 18 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-zoom2-camera.c b/arch/arm/mach-omap2/board-zoom2-camera.c -index 1ba2982..8c035c4 100644 ---- a/arch/arm/mach-omap2/board-zoom2-camera.c -+++ b/arch/arm/mach-omap2/board-zoom2-camera.c -@@ -41,6 +41,8 @@ static struct device *zoom2cam_dev; - - #define CAMZOOM2_USE_XCLKB 1 - -+#define ISP_IMX046_MCLK 216000000 -+ - /* Sensor specific GPIO signals */ - #define IMX046_RESET_GPIO 98 - #define IMX046_STANDBY_GPIO 58 -@@ -148,6 +150,7 @@ static struct isp_interface_config imx046_if_config = { - .shutter = 0x0, - .wenlog = ISPCCDC_CFG_WENLOG_AND, - .wait_hs_vs = 2, -+ .cam_mclk = ISP_IMX046_MCLK, - .u.csi.crc = 0x0, - .u.csi.mode = 0x0, - .u.csi.edge = 0x0, -@@ -264,6 +267,8 @@ static int imx046_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power po - #ifdef CONFIG_OMAP_PM_SRF - omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); - #endif -+ if (previous_power != V4L2_POWER_OFF) -+ isp_disable_mclk(isp); - break; - case V4L2_POWER_STANDBY: - printk(KERN_DEBUG "imx046_sensor_power_set(STANDBY)\n"); -@@ -272,9 +277,14 @@ static int imx046_sensor_power_set(struct v4l2_int_device *s, enum v4l2_power po - #ifdef CONFIG_OMAP_PM_SRF - omap_pm_set_min_bus_tput(vdev->cam->isp, OCP_INITIATOR_AGENT, 0); - #endif -+ -+ -+ isp_disable_mclk(isp); -+ - break; - } - -+ - /* Save powerstate to know what was before calling POWER_ON. */ - previous_power = power; - return err; -diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c -index 9d46c01..cf68720 100644 ---- a/drivers/media/video/isp/isp.c -+++ b/drivers/media/video/isp/isp.c -@@ -552,7 +552,7 @@ EXPORT_SYMBOL(isp_unset_callback); - * Configures the specified MCLK divisor in the ISP timing control register - * (TCTRL_CTRL) to generate the desired xclk clock value. - * -- * Divisor = CM_CAM_MCLK_HZ / xclk -+ * Divisor = mclk / xclk - * - * Returns the final frequency that is actually being generated - **/ -@@ -560,15 +560,16 @@ u32 isp_set_xclk(struct device *dev, u32 xclk, u8 xclksel) - { - u32 divisor; - u32 currentxclk; -+ struct isp_device *isp = dev_get_drvdata(dev); - -- if (xclk >= CM_CAM_MCLK_HZ) { -+ if (xclk >= isp->mclk) { - divisor = ISPTCTRL_CTRL_DIV_BYPASS; -- currentxclk = CM_CAM_MCLK_HZ; -+ currentxclk = isp->mclk; - } else if (xclk >= 2) { -- divisor = CM_CAM_MCLK_HZ / xclk; -+ divisor = isp->mclk / xclk; - if (divisor >= ISPTCTRL_CTRL_DIV_BYPASS) - divisor = ISPTCTRL_CTRL_DIV_BYPASS - 1; -- currentxclk = CM_CAM_MCLK_HZ / divisor; -+ currentxclk = isp->mclk / divisor; - } else { - divisor = xclk; - currentxclk = 0; -@@ -874,6 +875,8 @@ int isp_configure_interface(struct device *dev, - /* Set sensor specific fields in CCDC and Previewer module. */ - ispccdc_set_wenlog(&isp->isp_ccdc, config->wenlog); - -+ isp->mclk = config->cam_mclk; -+ isp_enable_mclk(dev); - /* FIXME: this should be set in ispccdc_config_vp() */ - fmtcfg = isp_reg_readl(dev, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_FMTCFG); - fmtcfg &= ISPCCDC_FMTCFG_VPIF_FRQ_MASK; -@@ -2333,16 +2336,6 @@ static int isp_enable_clocks(struct device *dev) - dev_err(dev, "clk_enable cam_ick failed\n"); - goto out_clk_enable_ick; - } -- r = clk_set_rate(isp->dpll4_m5_ck, CM_CAM_MCLK_HZ/2); -- if (r) { -- dev_err(dev, "clk_set_rate for dpll4_m5_ck failed\n"); -- goto out_clk_enable_mclk; -- } -- r = clk_enable(isp->cam_mclk); -- if (r) { -- dev_err(dev, "clk_enable cam_mclk failed\n"); -- goto out_clk_enable_mclk; -- } - r = clk_enable(isp->csi2_fck); - if (r) { - dev_err(dev, "clk_enable csi2_fck failed\n"); -@@ -2351,13 +2344,34 @@ static int isp_enable_clocks(struct device *dev) - return 0; - - out_clk_enable_csi2_fclk: -- clk_disable(isp->cam_mclk); --out_clk_enable_mclk: - clk_disable(isp->cam_ick); - out_clk_enable_ick: - return r; - } - -+int isp_enable_mclk(struct device *dev) -+{ -+ struct isp_device *isp = dev_get_drvdata(dev); -+ int r; -+ -+ r = clk_set_rate(isp->dpll4_m5_ck, isp->mclk); -+ if (r) { -+ dev_err(dev, "clk_set_rate for dpll4_m5_ck failed\n"); -+ return r; -+ } -+ r = clk_enable(isp->cam_mclk); -+ if (r) { -+ dev_err(dev, "clk_enable cam_mclk failed\n"); -+ return r; -+ } -+ return 0; -+} -+ -+void isp_disable_mclk(struct isp_device *isp) -+{ -+ clk_disable(isp->cam_mclk); -+} -+ - /** - * isp_disable_clocks - Disable ISP clocks - * @dev: Device pointer specific to the OMAP3 ISP. -@@ -2367,7 +2381,6 @@ static void isp_disable_clocks(struct device *dev) - struct isp_device *isp = dev_get_drvdata(dev); - - clk_disable(isp->cam_ick); -- clk_disable(isp->cam_mclk); - clk_disable(isp->csi2_fck); - } - -@@ -2668,6 +2681,8 @@ static int isp_probe(struct platform_device *pdev) - goto out_free_mmio; - } - -+ isp->mclk = CM_CAM_MCLK_HZ / 2; -+ - isp->cam_ick = clk_get(&camera_dev, "cam_ick"); - if (IS_ERR(isp->cam_ick)) { - dev_err(isp->dev, "clk_get cam_ick failed\n"); -diff --git a/drivers/media/video/isp/isp.h b/drivers/media/video/isp/isp.h -index 6b100b6..85c3fa9 100644 ---- a/drivers/media/video/isp/isp.h -+++ b/drivers/media/video/isp/isp.h -@@ -199,6 +199,7 @@ struct isp_interface_config { - u32 prev_slv; - u32 wenlog; - int wait_hs_vs; -+ u32 cam_mclk; - unsigned int pixelclk; - union { - struct par { -@@ -425,6 +426,7 @@ struct isp_device { - struct isp_irq irq; - struct isp_pipeline pipeline; - u32 interrupts; -+ u32 mclk; - enum isp_running running; - int current_field; - int bt656ifen; -@@ -489,6 +491,10 @@ struct device *isp_get(void); - - int isp_put(void); - -+int isp_enable_mclk(struct device *dev); -+ -+void isp_disable_mclk(struct isp_device *dev); -+ - int isp_queryctrl(struct v4l2_queryctrl *a); - - int isp_querymenu(struct v4l2_querymenu *a); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0019-omap3isp-core-Do-smarter-MCLK-setting.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0019-omap3isp-core-Do-smarter-MCLK-setting.patch deleted file mode 100644 index 53fe6219..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0019-omap3isp-core-Do-smarter-MCLK-setting.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 97761e2bdf286662e3c96f5a24fe568cac98fc9b Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Wed, 25 Nov 2009 12:30:46 -0600 -Subject: [PATCH 19/75] omap3isp: core: Do smarter MCLK setting - -Since the ratio between MCLK and DPLL4_M5 could not be 1:1 -(i.e. on 3430 its 2:1), it's necessary to check ratio -between those 2 first. - -This should make MCLK setting more adequate to different -chipsets. - -Tested on Zoom2 (3430 ES3.1) - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/isp/isp.c | 13 ++++++++++++- - 1 files changed, 12 insertions(+), 1 deletions(-) - -diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c -index cf68720..29dd005 100644 ---- a/drivers/media/video/isp/isp.c -+++ b/drivers/media/video/isp/isp.c -@@ -2353,8 +2353,19 @@ int isp_enable_mclk(struct device *dev) - { - struct isp_device *isp = dev_get_drvdata(dev); - int r; -+ unsigned long curr_mclk, curr_dpll4_m5, ratio; - -- r = clk_set_rate(isp->dpll4_m5_ck, isp->mclk); -+ /* Check ratio between DPLL4_M5 and CAM_MCLK */ -+ curr_mclk = clk_get_rate(isp->cam_mclk); -+ curr_dpll4_m5 = clk_get_rate(isp->dpll4_m5_ck); -+ -+ /* Protection for potential Zero division, or zero-ratio result */ -+ if (!curr_mclk || !curr_dpll4_m5) -+ BUG(); -+ -+ ratio = curr_mclk / curr_dpll4_m5; -+ -+ r = clk_set_rate(isp->dpll4_m5_ck, isp->mclk / ratio); - if (r) { - dev_err(dev, "clk_set_rate for dpll4_m5_ck failed\n"); - return r; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0020-omap3beagle-camera-set-mclk-for-mt9t111.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0020-omap3beagle-camera-set-mclk-for-mt9t111.patch deleted file mode 100644 index 97423f94..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0020-omap3beagle-camera-set-mclk-for-mt9t111.patch +++ /dev/null @@ -1,36 +0,0 @@ -From b744cbb89e3dd00a3f12d349ec0be604dffb5776 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 24 Jun 2010 16:34:13 -0500 -Subject: [PATCH 20/75] omap3beagle: camera: set mclk for mt9t111 - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 5 +++++ - 1 files changed, 5 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 75c8345..529a6be 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -49,6 +49,8 @@ - - #define CAM_USE_XCLKA 0 - -+#define ISP_MT9T111_MCLK 216000000 -+ - static struct regulator *beagle_mt9t111_reg1; - static struct regulator *beagle_mt9t111_reg2; - -@@ -60,6 +62,9 @@ static struct isp_interface_config mt9t111_if_config = { - .strobe = 0x0, - .prestrobe = 0x0, - .shutter = 0x0, -+ .cam_mclk = ISP_MT9T111_MCLK, -+ .wenlog = ISPCCDC_CFG_WENLOG_AND, -+ .wait_hs_vs = 2, - .u.par.par_bridge = 0x1, - .u.par.par_clk_pol = 0x0, - }; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0021-mt9t111-Fix-max-supported-xclk.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0021-mt9t111-Fix-max-supported-xclk.patch deleted file mode 100644 index 731f20e7..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0021-mt9t111-Fix-max-supported-xclk.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 3bca76ae1008ba2b2788214a59fd7813c69f9254 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 24 Jun 2010 17:43:23 -0500 -Subject: [PATCH 21/75] mt9t111: Fix max supported xclk - -According to Aptina documentation, the max should be 54 MHz, not 75 MHz. - -Signed-off-by: Sergio Aguirre ---- - include/media/mt9t111.h | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/include/media/mt9t111.h b/include/media/mt9t111.h -index aae3f99..cd34885 100644 ---- a/include/media/mt9t111.h -+++ b/include/media/mt9t111.h -@@ -42,7 +42,7 @@ - /*i2c adress for MT9T111*/ - #define MT9T111_I2C_ADDR (0x78 >> 1) - --#define MT9T111_CLK_MAX (75000000) /* 75MHz */ -+#define MT9T111_CLK_MAX (54000000) /* 54MHz */ - #define MT9T111_CLK_MIN (6000000) /* 6Mhz */ - - #define MT9T111_I2C_CONFIG (1) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0022-omap3beagle-camera-Clarify-regulators-names.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0022-omap3beagle-camera-Clarify-regulators-names.patch deleted file mode 100644 index 8dcb76bb..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0022-omap3beagle-camera-Clarify-regulators-names.patch +++ /dev/null @@ -1,103 +0,0 @@ -From db7e3a7af04196e80fe15e2a651440575f9313af Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 24 Jun 2010 17:53:55 -0500 -Subject: [PATCH 22/75] omap3beagle: camera: Clarify regulators names - -Changed: - - beagle_mt9t111_reg1 -> beagle_mt9t111_1_8v - - beagle_mt9t111_reg2 -> beagle_mt9t111_2_8v - -To help clarify sequence. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 42 ++++++++++++------------ - 1 files changed, 21 insertions(+), 21 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 529a6be..6babaf3 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -51,8 +51,8 @@ - - #define ISP_MT9T111_MCLK 216000000 - --static struct regulator *beagle_mt9t111_reg1; --static struct regulator *beagle_mt9t111_reg2; -+static struct regulator *beagle_mt9t111_1_8v; -+static struct regulator *beagle_mt9t111_2_8v; - - #if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) - static struct isp_interface_config mt9t111_if_config = { -@@ -167,10 +167,10 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - case V4L2_POWER_STANDBY: - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - -- if (regulator_is_enabled(beagle_mt9t111_reg1)) -- regulator_disable(beagle_mt9t111_reg1); -- if (regulator_is_enabled(beagle_mt9t111_reg2)) -- regulator_disable(beagle_mt9t111_reg2); -+ if (regulator_is_enabled(beagle_mt9t111_1_8v)) -+ regulator_disable(beagle_mt9t111_1_8v); -+ if (regulator_is_enabled(beagle_mt9t111_2_8v)) -+ regulator_disable(beagle_mt9t111_2_8v); - break; - - case V4L2_POWER_ON: -@@ -181,8 +181,8 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - #endif - - /* turn on analog power */ -- regulator_enable(beagle_mt9t111_reg1); -- regulator_enable(beagle_mt9t111_reg2); -+ regulator_enable(beagle_mt9t111_1_8v); -+ regulator_enable(beagle_mt9t111_2_8v); - udelay(100); - - break; -@@ -212,16 +212,16 @@ static int beagle_cam_probe(struct platform_device *pdev) - { - int err; - -- beagle_mt9t111_reg1 = regulator_get(&pdev->dev, "vaux3_1"); -- if (IS_ERR(beagle_mt9t111_reg1)) { -+ beagle_mt9t111_1_8v = regulator_get(&pdev->dev, "vaux3_1"); -+ if (IS_ERR(beagle_mt9t111_1_8v)) { - dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); -- return PTR_ERR(beagle_mt9t111_reg1); -+ return PTR_ERR(beagle_mt9t111_1_8v); - } -- beagle_mt9t111_reg2 = regulator_get(&pdev->dev, "vaux4_1"); -- if (IS_ERR(beagle_mt9t111_reg2)) { -+ beagle_mt9t111_2_8v = regulator_get(&pdev->dev, "vaux4_1"); -+ if (IS_ERR(beagle_mt9t111_2_8v)) { - dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); -- regulator_put(beagle_mt9t111_reg1); -- return PTR_ERR(beagle_mt9t111_reg2); -+ regulator_put(beagle_mt9t111_1_8v); -+ return PTR_ERR(beagle_mt9t111_2_8v); - } - - printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); -@@ -231,12 +231,12 @@ static int beagle_cam_probe(struct platform_device *pdev) - - static int beagle_cam_remove(struct platform_device *pdev) - { -- if (regulator_is_enabled(beagle_mt9t111_reg1)) -- regulator_disable(beagle_mt9t111_reg1); -- regulator_put(beagle_mt9t111_reg1); -- if (regulator_is_enabled(beagle_mt9t111_reg2)) -- regulator_disable(beagle_mt9t111_reg2); -- regulator_put(beagle_mt9t111_reg2); -+ if (regulator_is_enabled(beagle_mt9t111_1_8v)) -+ regulator_disable(beagle_mt9t111_1_8v); -+ regulator_put(beagle_mt9t111_1_8v); -+ if (regulator_is_enabled(beagle_mt9t111_2_8v)) -+ regulator_disable(beagle_mt9t111_2_8v); -+ regulator_put(beagle_mt9t111_2_8v); - - return 0; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0023-omap3beagle-camera-Fix-powerup-sequence.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0023-omap3beagle-camera-Fix-powerup-sequence.patch deleted file mode 100644 index 052b9152..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0023-omap3beagle-camera-Fix-powerup-sequence.patch +++ /dev/null @@ -1,103 +0,0 @@ -From e4f2c3641ccae2cb1614c8fda5ce307170b20921 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 24 Jun 2010 18:21:52 -0500 -Subject: [PATCH 23/75] omap3beagle: camera: Fix powerup sequence - -The powerup sequence was very incomplete. After revisiting the -Aptina developer's guide, the resulting powerup sequence is followed. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 49 ++++++++++++++++++++++-- - 1 files changed, 45 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 6babaf3..792c48d 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -51,6 +51,8 @@ - - #define ISP_MT9T111_MCLK 216000000 - -+#define LEOPARD_RESET_GPIO 98 -+ - static struct regulator *beagle_mt9t111_1_8v; - static struct regulator *beagle_mt9t111_2_8v; - -@@ -174,16 +176,42 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - break; - - case V4L2_POWER_ON: -- isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); -- - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - isp_configure_interface(vdev->cam->isp, &mt9t111_if_config); - #endif - -- /* turn on analog power */ -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); -+ -+ /* turn on VDD */ - regulator_enable(beagle_mt9t111_1_8v); -+ -+ mdelay(1); -+ -+ /* turn on VDD_IO */ - regulator_enable(beagle_mt9t111_2_8v); -- udelay(100); -+ -+ mdelay(50); -+ -+ /* Enable EXTCLK */ -+ isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); -+ -+ /* -+ * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -+ * ((1000000 * 70) / 6000000) = aprox 12 us. -+ */ -+ -+ udelay(12); -+ -+ /* Set RESET_BAR to 1 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 1); -+ -+ /* -+ * Wait at least 100 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -+ * ((1000000 * 100) / 6000000) = aprox 17 us. -+ */ -+ -+ udelay(17); - - break; - -@@ -224,6 +252,17 @@ static int beagle_cam_probe(struct platform_device *pdev) - return PTR_ERR(beagle_mt9t111_2_8v); - } - -+ if (gpio_request(LEOPARD_RESET_GPIO, "cam_rst") != 0) { -+ dev_err(&pdev->dev, "Could not request GPIO %d", -+ LEOPARD_RESET_GPIO); -+ regulator_put(beagle_mt9t111_2_8v); -+ regulator_put(beagle_mt9t111_1_8v); -+ return -ENODEV; -+ } -+ -+ /* set to output mode, default value 0 */ -+ gpio_direction_output(LEOPARD_RESET_GPIO, 0); -+ - printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); - - return 0; -@@ -238,6 +277,8 @@ static int beagle_cam_remove(struct platform_device *pdev) - regulator_disable(beagle_mt9t111_2_8v); - regulator_put(beagle_mt9t111_2_8v); - -+ gpio_free(LEOPARD_RESET_GPIO); -+ - return 0; - } - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0024-omap3beagle-camera-Change-vaux4-to-1.8v.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0024-omap3beagle-camera-Change-vaux4-to-1.8v.patch deleted file mode 100644 index a0a2e91b..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0024-omap3beagle-camera-Change-vaux4-to-1.8v.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 9f31f599f847c7eab995d22a683c8b32aaa5be7f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 25 Jun 2010 11:24:07 -0500 -Subject: [PATCH 24/75] omap3beagle: camera: Change vaux4 to 1.8v - -Both voltage sources seem to need 1.8v. - -After this, sensor is detected :) - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 1e9a868..af9b818 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -446,8 +446,8 @@ static struct regulator_init_data beagle_vaux3 = { - /* VAUX4 for CAM_2V8 */ - static struct regulator_init_data beagle_vaux4 = { - .constraints = { -- .min_uV = 2800000, -- .max_uV = 2800000, -+ .min_uV = 1800000, -+ .max_uV = 1800000, - .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0025-omap3beagle-camera-Rename-regulators-to-match-actual.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0025-omap3beagle-camera-Rename-regulators-to-match-actual.patch deleted file mode 100644 index c32c4405..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0025-omap3beagle-camera-Rename-regulators-to-match-actual.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 784407ada9241d907cf08145885410351a7eafc4 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 25 Jun 2010 12:03:59 -0500 -Subject: [PATCH 25/75] omap3beagle: camera: Rename regulators to match actual voltage levels - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 46 ++++++++++++------------ - 1 files changed, 23 insertions(+), 23 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 792c48d..8a4b7bc 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -53,8 +53,8 @@ - - #define LEOPARD_RESET_GPIO 98 - --static struct regulator *beagle_mt9t111_1_8v; --static struct regulator *beagle_mt9t111_2_8v; -+static struct regulator *beagle_mt9t111_1_8v1; -+static struct regulator *beagle_mt9t111_1_8v2; - - #if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) - static struct isp_interface_config mt9t111_if_config = { -@@ -169,10 +169,10 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - case V4L2_POWER_STANDBY: - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - -- if (regulator_is_enabled(beagle_mt9t111_1_8v)) -- regulator_disable(beagle_mt9t111_1_8v); -- if (regulator_is_enabled(beagle_mt9t111_2_8v)) -- regulator_disable(beagle_mt9t111_2_8v); -+ if (regulator_is_enabled(beagle_mt9t111_1_8v1)) -+ regulator_disable(beagle_mt9t111_1_8v1); -+ if (regulator_is_enabled(beagle_mt9t111_1_8v2)) -+ regulator_disable(beagle_mt9t111_1_8v2); - break; - - case V4L2_POWER_ON: -@@ -184,12 +184,12 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ -- regulator_enable(beagle_mt9t111_1_8v); -+ regulator_enable(beagle_mt9t111_1_8v1); - - mdelay(1); - - /* turn on VDD_IO */ -- regulator_enable(beagle_mt9t111_2_8v); -+ regulator_enable(beagle_mt9t111_1_8v2); - - mdelay(50); - -@@ -240,23 +240,23 @@ static int beagle_cam_probe(struct platform_device *pdev) - { - int err; - -- beagle_mt9t111_1_8v = regulator_get(&pdev->dev, "vaux3_1"); -- if (IS_ERR(beagle_mt9t111_1_8v)) { -+ beagle_mt9t111_1_8v1 = regulator_get(&pdev->dev, "vaux3_1"); -+ if (IS_ERR(beagle_mt9t111_1_8v1)) { - dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); -- return PTR_ERR(beagle_mt9t111_1_8v); -+ return PTR_ERR(beagle_mt9t111_1_8v1); - } -- beagle_mt9t111_2_8v = regulator_get(&pdev->dev, "vaux4_1"); -- if (IS_ERR(beagle_mt9t111_2_8v)) { -+ beagle_mt9t111_1_8v2 = regulator_get(&pdev->dev, "vaux4_1"); -+ if (IS_ERR(beagle_mt9t111_1_8v2)) { - dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); -- regulator_put(beagle_mt9t111_1_8v); -- return PTR_ERR(beagle_mt9t111_2_8v); -+ regulator_put(beagle_mt9t111_1_8v1); -+ return PTR_ERR(beagle_mt9t111_1_8v2); - } - - if (gpio_request(LEOPARD_RESET_GPIO, "cam_rst") != 0) { - dev_err(&pdev->dev, "Could not request GPIO %d", - LEOPARD_RESET_GPIO); -- regulator_put(beagle_mt9t111_2_8v); -- regulator_put(beagle_mt9t111_1_8v); -+ regulator_put(beagle_mt9t111_1_8v2); -+ regulator_put(beagle_mt9t111_1_8v1); - return -ENODEV; - } - -@@ -270,12 +270,12 @@ static int beagle_cam_probe(struct platform_device *pdev) - - static int beagle_cam_remove(struct platform_device *pdev) - { -- if (regulator_is_enabled(beagle_mt9t111_1_8v)) -- regulator_disable(beagle_mt9t111_1_8v); -- regulator_put(beagle_mt9t111_1_8v); -- if (regulator_is_enabled(beagle_mt9t111_2_8v)) -- regulator_disable(beagle_mt9t111_2_8v); -- regulator_put(beagle_mt9t111_2_8v); -+ if (regulator_is_enabled(beagle_mt9t111_1_8v1)) -+ regulator_disable(beagle_mt9t111_1_8v1); -+ regulator_put(beagle_mt9t111_1_8v1); -+ if (regulator_is_enabled(beagle_mt9t111_1_8v2)) -+ regulator_disable(beagle_mt9t111_1_8v2); -+ regulator_put(beagle_mt9t111_1_8v2); - - gpio_free(LEOPARD_RESET_GPIO); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0026-omap3beagle-camera-Complement-remainig-sensor-hw-con.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0026-omap3beagle-camera-Complement-remainig-sensor-hw-con.patch deleted file mode 100644 index 854d1979..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0026-omap3beagle-camera-Complement-remainig-sensor-hw-con.patch +++ /dev/null @@ -1,37 +0,0 @@ -From e14b36353ea3f3d55192cf986310c275ed8cfcc9 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 25 Jun 2010 12:04:48 -0500 -Subject: [PATCH 26/75] omap3beagle: camera: Complement remainig sensor hw config settings - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 6 ++++++ - 1 files changed, 6 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 8a4b7bc..b0148d6 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -57,6 +57,10 @@ static struct regulator *beagle_mt9t111_1_8v1; - static struct regulator *beagle_mt9t111_1_8v2; - - #if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+ -+/* Arbitrary memory handling limit */ -+#define MT9T111_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN(2048 * 1536 * 4) -+ - static struct isp_interface_config mt9t111_if_config = { - .ccdc_par_ser = ISP_PARLL, - .dataline_shift = 0x0, -@@ -125,6 +129,8 @@ static struct omap34xxcam_hw_config mt9t111_hwc = { - .dev_minor = 0, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 1, -+ .u.sensor.capture_mem = MT9T111_BIGGEST_FRAME_BYTE_SIZE * 2, -+ .u.sensor.ival_default = { 1, 10 }, - }; - #endif - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0027-mt9t111-Fix-detect-function-retval-and-cleanup-print.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0027-mt9t111-Fix-detect-function-retval-and-cleanup-print.patch deleted file mode 100644 index 4ca56e1d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0027-mt9t111-Fix-detect-function-retval-and-cleanup-print.patch +++ /dev/null @@ -1,48 +0,0 @@ -From db54f40408b0907a6cf314232bbf2b9f12ac0d9d Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 25 Jun 2010 13:43:54 -0500 -Subject: [PATCH 27/75] mt9t111: Fix detect function retval and cleanup prints - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t111.c | 8 +++----- - 1 files changed, 3 insertions(+), 5 deletions(-) - -diff --git a/drivers/media/video/mt9t111.c b/drivers/media/video/mt9t111.c -index 6a7b2c0..08122ff 100644 ---- a/drivers/media/video/mt9t111.c -+++ b/drivers/media/video/mt9t111.c -@@ -221,7 +221,6 @@ mt9t111_detect(struct i2c_client *client) - /* chip ID is at address 0 */ - if (mt9t111_read_reg(client, MT9T111_CHIP_ID, &val) < 0) - return -ENODEV; -- dev_info(&client->dev, "model id detected 0x%x\n", val); - - if (val != MT9T111_CHIP_ID_VALUE) { - dev_warn(&client->dev, "model id mismatch received 0x%x" -@@ -231,7 +230,7 @@ mt9t111_detect(struct i2c_client *client) - return -ENODEV; - } - -- return 0; -+ return (int)val; - - } - -@@ -390,11 +389,10 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - sensor->state = SENSOR_NOT_DETECTED; - return rval; - } -- mt9t111_loaddefault(c); -+ dev_info(&c->dev, "chip version 0x%02x detected\n", rval); - sensor->state = SENSOR_DETECTED; - sensor->ver = rval; -- pr_info("mt9t111" " chip version 0x%02x detected\n", -- sensor->ver); -+ mt9t111_loaddefault(c); - } - return 0; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0028-omap3beagle-camera-Set-padconf-settings-in-cam-init.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0028-omap3beagle-camera-Set-padconf-settings-in-cam-init.patch deleted file mode 100644 index c9dda1a9..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0028-omap3beagle-camera-Set-padconf-settings-in-cam-init.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 9d152df885cb6f6874259d93df558e649f62774f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 25 Jun 2010 16:01:00 -0500 -Subject: [PATCH 28/75] omap3beagle: camera: Set padconf settings in cam init - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 35 ++++++++++++++++++++++++ - 1 files changed, 35 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index b0148d6..75471f2 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -34,6 +34,7 @@ - - #include - #include -+#include - - #include - #include -@@ -285,6 +286,40 @@ static int beagle_cam_remove(struct platform_device *pdev) - - gpio_free(LEOPARD_RESET_GPIO); - -+ /* MUX init */ -+ omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -+ 0x10C); /* CAM_HS */ -+ omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -+ 0x10E); /* CAM_VS */ -+ omap_ctrl_writew(OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, -+ 0x110); /* CAM_XCLKA */ -+ omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -+ 0x112); /* CAM_PCLK */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x116); /* CAM_D0 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x118); /* CAM_D1 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x11A); /* CAM_D2 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x11C); /* CAM_D3 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x11E); /* CAM_D4 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x120); /* CAM_D5 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x122); /* CAM_D6 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x124); /* CAM_D7 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x126); /* CAM_D8 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x128); /* CAM_D9 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x12A); /* CAM_D10 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x12C); /* CAM_D11 */ -+ - return 0; - } - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0029-omap3beagle-camera-only-register-camera-driver-for-3.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0029-omap3beagle-camera-only-register-camera-driver-for-3.patch deleted file mode 100644 index d642d6cb..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0029-omap3beagle-camera-only-register-camera-driver-for-3.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7a8fe70470bd026b249f47c0aa37578a97fb2bb3 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sun, 27 Jun 2010 16:11:39 +0200 -Subject: [PATCH 29/75] omap3beagle: camera: only register camera driver for 36xx based SoCs - -This is a workaround for the bootcrash when used on 35xx based beagleboards. - -Signed-off-by: Koen Kooi ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 6 ++++-- - 1 files changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 75471f2..8faa437 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -355,7 +355,9 @@ static struct platform_driver beagle_cam_driver = { - */ - int __init omap3beaglelmb_init(void) - { -- platform_driver_register(&beagle_cam_driver); -- return 0; -+ if (cpu_is_omap3630()) { -+ platform_driver_register(&beagle_cam_driver); -+ } -+ return 0; - } - late_initcall(omap3beaglelmb_init); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0030-WIP-mt9t111-Work-in-progress-for-camera-enablement.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0030-WIP-mt9t111-Work-in-progress-for-camera-enablement.patch deleted file mode 100644 index 11abb8b4..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0030-WIP-mt9t111-Work-in-progress-for-camera-enablement.patch +++ /dev/null @@ -1,53 +0,0 @@ -From b310c5ad504443f0d125ca92106f497e14acd8bd Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 25 Jun 2010 16:01:47 -0500 -Subject: [PATCH 30/75] WIP: mt9t111: Work in progress for camera enablement - -This is changing so far: -- Remove useless printk's in enum_frameinterval calls. -- Call mt9t111_loaddefault instead of mt9t111_configure dummy function. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t111.c | 11 +---------- - 1 files changed, 1 insertions(+), 10 deletions(-) - -diff --git a/drivers/media/video/mt9t111.c b/drivers/media/video/mt9t111.c -index 08122ff..10080af 100644 ---- a/drivers/media/video/mt9t111.c -+++ b/drivers/media/video/mt9t111.c -@@ -288,14 +288,6 @@ static int ioctl_enum_frameintervals(struct v4l2_int_device *s, - { - int ifmt; - -- printk(KERN_INFO "entering ioctl_enum_frameintervals\n"); -- printk(KERN_INFO "index = %d, pixel_format = 0x%x," -- " width = %d, height = %d\n", -- frmi->index, frmi->pixel_format, -- frmi->width, frmi->height); -- printk(KERN_INFO "mt9t111 format = 0x%x\n", -- mt9t111_formats[0].pixelformat); -- - if (frmi->index >= NUM_CAPTURE_FRAMEINTERVALS) - return -EINVAL; - -@@ -379,7 +371,7 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - } - - if ((on == V4L2_POWER_ON) && (sensor->state == SENSOR_DETECTED)) -- mt9t111_configure(s); -+ mt9t111_loaddefault(c); - - if ((on == V4L2_POWER_ON) && (sensor->state == SENSOR_NOT_DETECTED)) { - rval = mt9t111_detect(c); -@@ -392,7 +384,6 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - dev_info(&c->dev, "chip version 0x%02x detected\n", rval); - sensor->state = SENSOR_DETECTED; - sensor->ver = rval; -- mt9t111_loaddefault(c); - } - return 0; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0031-BeagleXM-Cam-Add-support-for-MT9V113-VGA-Sensor.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0031-BeagleXM-Cam-Add-support-for-MT9V113-VGA-Sensor.patch deleted file mode 100644 index f8b4af9d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0031-BeagleXM-Cam-Add-support-for-MT9V113-VGA-Sensor.patch +++ /dev/null @@ -1,2441 +0,0 @@ -From 2355a460abc09be0a8c61360792a59056eb09230 Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Wed, 7 Jul 2010 11:55:43 +0530 -Subject: [PATCH 31/75] BeagleXM:Cam: Add support for MT9V113 VGA Sensor - -This patch replaces the MT9T111 to MT9V113 sensor. ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 132 ++- - arch/arm/mach-omap2/board-omap3beagle.c | 32 +- - drivers/media/video/Kconfig | 10 + - drivers/media/video/Makefile | 1 + - drivers/media/video/mt9v113.c | 1522 ++++++++++++++++++++++++ - drivers/media/video/mt9v113_regs.h | 294 +++++ - include/media/mt9v113.h | 83 ++ - include/media/v4l2-int-device.h | 27 + - 8 files changed, 2023 insertions(+), 78 deletions(-) - create mode 100644 drivers/media/video/mt9v113.c - create mode 100644 drivers/media/video/mt9v113_regs.h - create mode 100644 include/media/mt9v113.h - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 8faa437..6c06265 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -37,7 +37,7 @@ - #include - - #include --#include -+#include - - /* Include V4L2 ISP-Camera driver related header file */ - #include <../drivers/media/video/omap34xxcam.h> -@@ -50,99 +50,99 @@ - - #define CAM_USE_XCLKA 0 - --#define ISP_MT9T111_MCLK 216000000 -+#define ISP_MT9V113_MCLK 216000000 - - #define LEOPARD_RESET_GPIO 98 - --static struct regulator *beagle_mt9t111_1_8v1; --static struct regulator *beagle_mt9t111_1_8v2; -+static struct regulator *beagle_mt9v113_1_8v1; -+static struct regulator *beagle_mt9v113_1_8v2; - --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#if defined(CONFIG_VIDEO_MT9V113) || defined(CONFIG_VIDEO_MT9V113_MODULE) - - /* Arbitrary memory handling limit */ --#define MT9T111_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN(2048 * 1536 * 4) -+#define MT9V113_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN(2048 * 1536 * 4) - --static struct isp_interface_config mt9t111_if_config = { -- .ccdc_par_ser = ISP_PARLL, -+static struct isp_interface_config mt9v113_if_config = { -+ .ccdc_par_ser = ISP_PARLL, - .dataline_shift = 0x0, - .hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE, - .strobe = 0x0, - .prestrobe = 0x0, - .shutter = 0x0, -- .cam_mclk = ISP_MT9T111_MCLK, -+ .cam_mclk = ISP_MT9V113_MCLK, - .wenlog = ISPCCDC_CFG_WENLOG_AND, - .wait_hs_vs = 2, - .u.par.par_bridge = 0x1, - .u.par.par_clk_pol = 0x0, - }; - --static struct v4l2_ifparm mt9t111_ifparm_s = { -+static struct v4l2_ifparm mt9v113_ifparm_s = { - #if 1 -- .if_type = V4L2_IF_TYPE_RAW, -+ .if_type = V4L2_IF_TYPE_RAW, - .u = { -- .raw = { -+ .raw = { - .frame_start_on_rising_vs = 1, - .bt_sync_correct = 0, - .swap = 0, - .latch_clk_inv = 0, - .nobt_hs_inv = 0, /* active high */ - .nobt_vs_inv = 0, /* active high */ -- .clock_min = MT9T111_CLK_MIN, -- .clock_max = MT9T111_CLK_MAX, -+ .clock_min = MT9V113_CLK_MIN, -+ .clock_max = MT9V113_CLK_MAX, - }, - }, --#else -- .if_type = V4L2_IF_TYPE_YCbCr, -+#else -+ .if_type = V4L2_IF_TYPE_YCbCr, - .u = { -- .ycbcr = { -+ .ycbcr = { - .frame_start_on_rising_vs = 1, - .bt_sync_correct = 0, - .swap = 0, - .latch_clk_inv = 0, - .nobt_hs_inv = 0, /* active high */ - .nobt_vs_inv = 0, /* active high */ -- .clock_min = MT9T111_CLK_MIN, -- .clock_max = MT9T111_CLK_MAX, -+ .clock_min = MT9V113_CLK_MIN, -+ .clock_max = MT9V113_CLK_MAX, - }, - }, - #endif - }; - - /** -- * @brief mt9t111_ifparm - Returns the mt9t111 interface parameters -+ * @brief mt9v113_ifparm - Returns the mt9v113 interface parameters - * - * @param p - pointer to v4l2_ifparm structure - * - * @return result of operation - 0 is success - */ --static int mt9t111_ifparm(struct v4l2_ifparm *p) -+static int mt9v113_ifparm(struct v4l2_ifparm *p) - { - if (p == NULL) - return -EINVAL; - -- *p = mt9t111_ifparm_s; -+ *p = mt9v113_ifparm_s; - return 0; - } - - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) --static struct omap34xxcam_hw_config mt9t111_hwc = { -+static struct omap34xxcam_hw_config mt9v113_hwc = { - .dev_index = 0, - .dev_minor = 0, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 1, -- .u.sensor.capture_mem = MT9T111_BIGGEST_FRAME_BYTE_SIZE * 2, -+ .u.sensor.capture_mem = MT9V113_BIGGEST_FRAME_BYTE_SIZE * 2, - .u.sensor.ival_default = { 1, 10 }, - }; - #endif - - /** -- * @brief mt9t111_set_prv_data - Returns mt9t111 omap34xx driver private data -+ * @brief mt9v113_set_prv_data - Returns mt9v113 omap34xx driver private data - * - * @param priv - pointer to omap34xxcam_hw_config structure - * - * @return result of operation - 0 is success - */ --static int mt9t111_set_prv_data(void *priv) -+static int mt9v113_set_prv_data(void *priv) - { - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - struct omap34xxcam_hw_config *hwc = priv; -@@ -150,10 +150,10 @@ static int mt9t111_set_prv_data(void *priv) - if (priv == NULL) - return -EINVAL; - -- hwc->u.sensor = mt9t111_hwc.u.sensor; -- hwc->dev_index = mt9t111_hwc.dev_index; -- hwc->dev_minor = mt9t111_hwc.dev_minor; -- hwc->dev_type = mt9t111_hwc.dev_type; -+ hwc->u.sensor = mt9v113_hwc.u.sensor; -+ hwc->dev_index = mt9v113_hwc.dev_index; -+ hwc->dev_minor = mt9v113_hwc.dev_minor; -+ hwc->dev_type = mt9v113_hwc.dev_type; - return 0; - #else - return -EINVAL; -@@ -161,13 +161,13 @@ static int mt9t111_set_prv_data(void *priv) - } - - /** -- * @brief mt9t111_power_set - Power-on or power-off TVP5146 device -+ * @brief mt9v113_power_set - Power-on or power-off TVP5146 device - * - * @param power - enum, Power on/off, resume/standby - * - * @return result of operation - 0 is success - */ --static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) -+static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - { - struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; - -@@ -176,32 +176,32 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - case V4L2_POWER_STANDBY: - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - -- if (regulator_is_enabled(beagle_mt9t111_1_8v1)) -- regulator_disable(beagle_mt9t111_1_8v1); -- if (regulator_is_enabled(beagle_mt9t111_1_8v2)) -- regulator_disable(beagle_mt9t111_1_8v2); -+ if (regulator_is_enabled(beagle_mt9v113_1_8v1)) -+ regulator_disable(beagle_mt9v113_1_8v1); -+ if (regulator_is_enabled(beagle_mt9v113_1_8v2)) -+ regulator_disable(beagle_mt9v113_1_8v2); - break; - - case V4L2_POWER_ON: - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -- isp_configure_interface(vdev->cam->isp, &mt9t111_if_config); -+ isp_configure_interface(vdev->cam->isp, &mt9v113_if_config); - #endif - - /* Set RESET_BAR to 0 */ - gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ -- regulator_enable(beagle_mt9t111_1_8v1); -+ regulator_enable(beagle_mt9v113_1_8v1); - - mdelay(1); - - /* turn on VDD_IO */ -- regulator_enable(beagle_mt9t111_1_8v2); -+ regulator_enable(beagle_mt9v113_1_8v2); - - mdelay(50); - - /* Enable EXTCLK */ -- isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); -+ isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN, CAM_USE_XCLKA); - - /* - * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -@@ -229,44 +229,48 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - return 0; - } - --struct mt9t111_platform_data mt9t111_pdata = { -+struct mt9v113_platform_data mt9v113_pdata = { - .master = "omap34xxcam", -- .power_set = mt9t111_power_set, -- .priv_data_set = mt9t111_set_prv_data, -- .ifparm = mt9t111_ifparm, -+ .power_set = mt9v113_power_set, -+ .priv_data_set = mt9v113_set_prv_data, -+ .ifparm = mt9v113_ifparm, - /* Some interface dependent params */ - .clk_polarity = 0, /* data clocked out on falling edge */ - .hs_polarity = 1, /* 0 - Active low, 1- Active high */ - .vs_polarity = 1, /* 0 - Active low, 1- Active high */ - }; - --#endif /* #ifdef CONFIG_VIDEO_MT9T111 */ -+#endif /* #ifdef CONFIG_VIDEO_MT9V113 */ - - - static int beagle_cam_probe(struct platform_device *pdev) - { - int err; - -- beagle_mt9t111_1_8v1 = regulator_get(&pdev->dev, "vaux3_1"); -- if (IS_ERR(beagle_mt9t111_1_8v1)) { -+ printk("%s:%d\n", __func__, __LINE__); -+ beagle_mt9v113_1_8v1 = regulator_get(&pdev->dev, "vaux3_1"); -+ if (IS_ERR(beagle_mt9v113_1_8v1)) { - dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); -- return PTR_ERR(beagle_mt9t111_1_8v1); -+ return PTR_ERR(beagle_mt9v113_1_8v1); - } -- beagle_mt9t111_1_8v2 = regulator_get(&pdev->dev, "vaux4_1"); -- if (IS_ERR(beagle_mt9t111_1_8v2)) { -+ printk("%s:%d\n", __func__, __LINE__); -+ beagle_mt9v113_1_8v2 = regulator_get(&pdev->dev, "vaux4_1"); -+ if (IS_ERR(beagle_mt9v113_1_8v2)) { - dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); -- regulator_put(beagle_mt9t111_1_8v1); -- return PTR_ERR(beagle_mt9t111_1_8v2); -+ regulator_put(beagle_mt9v113_1_8v1); -+ return PTR_ERR(beagle_mt9v113_1_8v2); - } - -+ printk("%s:%d\n", __func__, __LINE__); - if (gpio_request(LEOPARD_RESET_GPIO, "cam_rst") != 0) { - dev_err(&pdev->dev, "Could not request GPIO %d", - LEOPARD_RESET_GPIO); -- regulator_put(beagle_mt9t111_1_8v2); -- regulator_put(beagle_mt9t111_1_8v1); -+ regulator_put(beagle_mt9v113_1_8v2); -+ regulator_put(beagle_mt9v113_1_8v1); - return -ENODEV; - } - -+ printk("%s:%d\n", __func__, __LINE__); - /* set to output mode, default value 0 */ - gpio_direction_output(LEOPARD_RESET_GPIO, 0); - -@@ -277,12 +281,13 @@ static int beagle_cam_probe(struct platform_device *pdev) - - static int beagle_cam_remove(struct platform_device *pdev) - { -- if (regulator_is_enabled(beagle_mt9t111_1_8v1)) -- regulator_disable(beagle_mt9t111_1_8v1); -- regulator_put(beagle_mt9t111_1_8v1); -- if (regulator_is_enabled(beagle_mt9t111_1_8v2)) -- regulator_disable(beagle_mt9t111_1_8v2); -- regulator_put(beagle_mt9t111_1_8v2); -+ printk("%s:%d\n", __func__, __LINE__); -+ if (regulator_is_enabled(beagle_mt9v113_1_8v1)) -+ regulator_disable(beagle_mt9v113_1_8v1); -+ regulator_put(beagle_mt9v113_1_8v1); -+ if (regulator_is_enabled(beagle_mt9v113_1_8v2)) -+ regulator_disable(beagle_mt9v113_1_8v2); -+ regulator_put(beagle_mt9v113_1_8v2); - - gpio_free(LEOPARD_RESET_GPIO); - -@@ -355,9 +360,12 @@ static struct platform_driver beagle_cam_driver = { - */ - int __init omap3beaglelmb_init(void) - { -+ printk("%s:%d\n", __func__, __LINE__); - if (cpu_is_omap3630()) { -- platform_driver_register(&beagle_cam_driver); -+ printk("%s:%d\n", __func__, __LINE__); -+ platform_driver_register(&beagle_cam_driver); - } -- return 0; -+ printk("%s:%d\n", __func__, __LINE__); -+ return 0; - } - late_initcall(omap3beaglelmb_init); -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index af9b818..d4b0b0a 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -71,10 +71,10 @@ static struct omap_opp * _omap35x_l3_rate_table = NULL; - static struct omap_opp * _omap37x_l3_rate_table = NULL; - #endif /* CONFIG_PM */ - --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#if defined(CONFIG_VIDEO_MT9V113) || defined(CONFIG_VIDEO_MT9V113_MODULE) - #include --#include --extern struct mt9t111_platform_data mt9t111_pdata; -+#include -+extern struct mt9v113_platform_data mt9v113_pdata; - #endif - - #define GPMC_CS0_BASE 0x60 -@@ -159,7 +159,7 @@ static void __init omap3beagle_ks8851_init(void) - printk(KERN_ERR "could not obtain gpio for KS8851_IRQ\n"); - return; - } -- -+ - spi_register_board_info(omap3beagle_zippy2_spi_board_info, - ARRAY_SIZE(omap3beagle_zippy2_spi_board_info)); - } -@@ -369,9 +369,9 @@ static int beagle_twl_gpio_setup(struct device *dev, - */ - - if (cpu_is_omap3630()) { -- /* Power on DVI, Serial and PWR led */ -+ /* Power on DVI, Serial and PWR led */ - gpio_request(gpio + 1, "nDVI_PWR_EN"); -- gpio_direction_output(gpio + 1, 0); -+ gpio_direction_output(gpio + 1, 0); - - /* Power on camera interface */ - gpio_request(gpio + 2, "CAM_EN"); -@@ -560,7 +560,7 @@ static struct i2c_board_info __initdata beagle_i2c1_boardinfo[] = { - }, - }; - -- -+ - #if defined(CONFIG_EEPROM_AT24) || defined(CONFIG_EEPROM_AT24_MODULE) - #include - -@@ -594,10 +594,10 @@ static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = {}; - #endif - - static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#if defined(CONFIG_VIDEO_MT9V113) || defined(CONFIG_VIDEO_MT9V113_MODULE) - { -- I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), -- .platform_data = &mt9t111_pdata, -+ I2C_BOARD_INFO("mt9v113", MT9V113_I2C_ADDR), -+ .platform_data = &mt9v113_pdata, - }, - #endif - }; -@@ -606,7 +606,7 @@ static int __init omap3_beagle_i2c_init(void) - { - omap_register_i2c_bus(1, 2600, beagle_i2c1_boardinfo, - ARRAY_SIZE(beagle_i2c1_boardinfo)); -- if(!strcmp(expansionboard_name, "zippy") || !strcmp(expansionboard_name, "zippy2")) -+ if(!strcmp(expansionboard_name, "zippy") || !strcmp(expansionboard_name, "zippy2")) - { - printk(KERN_INFO "Beagle expansionboard: registering i2c2 bus for zippy/zippy2\n"); - omap_register_i2c_bus(2, 400, beagle_zippy_i2c2_boardinfo, -@@ -681,7 +681,7 @@ static struct spi_board_info beaglefpga_mcspi_board_info[] = { - .modalias = "spidev", - .max_speed_hz = 48000000, //48 Mbps - .bus_num = 4, -- .chip_select = 0, -+ .chip_select = 0, - .mode = SPI_MODE_1, - }, - }; -@@ -830,7 +830,7 @@ static void __init omap3_beagle_init(void) - /* REVISIT leave DVI powered down until it's needed ... */ - gpio_direction_output(170, true); - -- if(!strcmp(expansionboard_name, "zippy")) -+ if(!strcmp(expansionboard_name, "zippy")) - { - printk(KERN_INFO "Beagle expansionboard: initializing enc28j60\n"); - omap3beagle_enc28j60_init(); -@@ -838,8 +838,8 @@ static void __init omap3_beagle_init(void) - mmc[1].gpio_wp = 141; - mmc[1].gpio_cd = 162; - } -- -- if(!strcmp(expansionboard_name, "zippy2")) -+ -+ if(!strcmp(expansionboard_name, "zippy2")) - { - printk(KERN_INFO "Beagle expansionboard: initializing ks_8851\n"); - omap3beagle_ks8851_init(); -@@ -880,7 +880,7 @@ static void __init omap3_beagle_init(void) - } - - if(!strcmp(expansionboard_name, "beaglefpga")) -- { -+ { - printk(KERN_INFO "Beagle expansionboard: Using McSPI for SPI\n"); - beaglefpga_init_spi(); - } -diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig -index f67ed46..c14d758 100644 ---- a/drivers/media/video/Kconfig -+++ b/drivers/media/video/Kconfig -@@ -329,6 +329,16 @@ config VIDEO_MT9V011 - mt0v011 1.3 Mpixel camera. It currently only works with the - em28xx driver. - -+config VIDEO_MT9V113 -+ tristate "Aptina MT9V113 VGA CMOS IMAGE SENSOR" -+ depends on VIDEO_V4L2 && I2C -+ ---help--- -+ This is a Video4Linux2 sensor-level driver for the Aptina MT9V113 -+ image sensor. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called mt9v113. -+ - config VIDEO_TCM825X - tristate "TCM825x camera sensor support" - depends on I2C && VIDEO_V4L2 -diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile -index 31688bf..763c157 100644 ---- a/drivers/media/video/Makefile -+++ b/drivers/media/video/Makefile -@@ -75,6 +75,7 @@ obj-$(CONFIG_VIDEO_OV7670) += ov7670.o - obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o - obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o - obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o -+obj-$(CONFIG_VIDEO_MT9V113) += mt9v113.o - - obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o - obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o -diff --git a/drivers/media/video/mt9v113.c b/drivers/media/video/mt9v113.c -new file mode 100644 -index 0000000..755a88a ---- /dev/null -+++ b/drivers/media/video/mt9v113.c -@@ -0,0 +1,1522 @@ -+/* -+ * drivers/media/video/mt9v113.c -+ * -+ * Based on TI TVP5146/47 decoder driver -+ * -+ * -+ * This package is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mt9v113_regs.h" -+ -+/* Module Name */ -+#define MT9V113_MODULE_NAME "mt9v113" -+ -+/* Private macros for TVP */ -+#define I2C_RETRY_COUNT (5) -+#define LOCK_RETRY_COUNT (5) -+#define LOCK_RETRY_DELAY (200) -+ -+/* Debug functions */ -+static int debug = 1; -+module_param(debug, bool, 0644); -+MODULE_PARM_DESC(debug, "Debug level (0-1)"); -+ -+#define dump_reg(client, reg, val) \ -+ do { \ -+ val = mt9v113_read_reg(client, reg); \ -+ v4l_info(client, "Reg(0x%.2X): 0x%.2X\n", reg, val); \ -+ } while (0) -+ -+/** -+ * enum mt9v113_std - enum for supported standards -+ */ -+enum mt9v113_std { -+ MT9V113_STD_VGA = 0, -+ MT9V113_STD_QVGA, -+ MT9V113_STD_INVALID -+}; -+ -+/** -+ * enum mt9v113_state - enum for different decoder states -+ */ -+enum mt9v113_state { -+ STATE_NOT_DETECTED, -+ STATE_DETECTED -+}; -+ -+/** -+ * struct mt9v113_std_info - Structure to store standard informations -+ * @width: Line width in pixels -+ * @height:Number of active lines -+ * @video_std: Value to write in REG_VIDEO_STD register -+ * @standard: v4l2 standard structure information -+ */ -+struct mt9v113_std_info { -+ unsigned long width; -+ unsigned long height; -+ u8 video_std; -+ struct v4l2_standard standard; -+}; -+ -+/** -+ * struct mt9v113_decoded - decoder object -+ * @v4l2_int_device: Slave handle -+ * @pdata: Board specific -+ * @client: I2C client data -+ * @id: Entry from I2C table -+ * @ver: Chip version -+ * @state: decoder state - detected or not-detected -+ * @pix: Current pixel format -+ * @num_fmts: Number of formats -+ * @fmt_list: Format list -+ * @current_std: Current standard -+ * @num_stds: Number of standards -+ * @std_list: Standards list -+ * @route: input and output routing at chip level -+ */ -+struct mt9v113_decoder { -+ struct v4l2_int_device *v4l2_int_device; -+ const struct mt9v113_platform_data *pdata; -+ struct i2c_client *client; -+ -+ struct i2c_device_id *id; -+ -+ int ver; -+ enum mt9v113_state state; -+ -+ struct v4l2_pix_format pix; -+ int num_fmts; -+ const struct v4l2_fmtdesc *fmt_list; -+ -+ enum mt9v113_std current_std; -+ int num_stds; -+ struct mt9v113_std_info *std_list; -+ -+ struct v4l2_routing route; -+}; -+ -+/* MT9V113 register set for VGA mode */ -+static struct mt9v113_reg mt9v113_vga_reg[] = { -+ {TOK_WRITE, 0x098C, 0x2739}, -+ {TOK_WRITE, 0x0990, 0x0000}, -+ {TOK_WRITE, 0x098C, 0x273B}, -+ {TOK_WRITE, 0x0990, 0x027F}, -+ {TOK_WRITE, 0x098C, 0x273D}, -+ {TOK_WRITE, 0x0990, 0x0000}, -+ {TOK_WRITE, 0x098C, 0x273F}, -+ {TOK_WRITE, 0x0990, 0x01DF}, -+ {TOK_WRITE, 0x098C, 0x2703}, -+ {TOK_WRITE, 0x0990, 0x0280}, -+ {TOK_WRITE, 0x098C, 0x2705}, -+ {TOK_WRITE, 0x0990, 0x01E0}, -+ {TOK_WRITE, 0x098C, 0xA103}, -+ {TOK_WRITE, 0x0990, 0x0005}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_TERM, 0, 0}, -+}; -+ -+/* MT9V113 default register values */ -+static struct mt9v113_reg mt9v113_reg_list[] = { -+ {TOK_WRITE, 0x0018, 0x4028}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_WRITE, 0x001A, 0x0011}, -+ {TOK_WRITE, 0x001A, 0x0010}, -+ {TOK_WRITE, 0x0018, 0x4028}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_WRITE, 0x098C, 0x02F0}, -+ {TOK_WRITE, 0x0990, 0x0000}, -+ {TOK_WRITE, 0x098C, 0x02F2}, -+ {TOK_WRITE, 0x0990, 0x0210}, -+ {TOK_WRITE, 0x098C, 0x02F4}, -+ {TOK_WRITE, 0x0990, 0x001A}, -+ {TOK_WRITE, 0x098C, 0x2145}, -+ {TOK_WRITE, 0x0990, 0x02F4}, -+ {TOK_WRITE, 0x098C, 0xA134}, -+ {TOK_WRITE, 0x0990, 0x0001}, -+ {TOK_WRITE, 0x31E0, 0x0001}, -+ {TOK_WRITE, 0x001A, 0x0210}, -+ {TOK_WRITE, 0x001E, 0x0777}, -+ {TOK_WRITE, 0x0016, 0x42DF}, -+ {TOK_WRITE, 0x0014, 0x2145}, -+ {TOK_WRITE, 0x0014, 0x2145}, -+ {TOK_WRITE, 0x0010, 0x0431}, -+ {TOK_WRITE, 0x0012, 0x0000}, -+ {TOK_WRITE, 0x0014, 0x244B}, -+ {TOK_WRITE, 0x0014, 0x304B}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_WRITE, 0x0014, 0xB04A}, -+ {TOK_WRITE, 0x098C, 0xAB1F}, -+ {TOK_WRITE, 0x0990, 0x00C7}, -+ {TOK_WRITE, 0x098C, 0xAB31}, -+ {TOK_WRITE, 0x0990, 0x001E}, -+ {TOK_WRITE, 0x098C, 0x274F}, -+ {TOK_WRITE, 0x0990, 0x0004}, -+ {TOK_WRITE, 0x098C, 0x2741}, -+ {TOK_WRITE, 0x0990, 0x0004}, -+ {TOK_WRITE, 0x098C, 0xAB20}, -+ {TOK_WRITE, 0x0990, 0x0054}, -+ {TOK_WRITE, 0x098C, 0xAB21}, -+ {TOK_WRITE, 0x0990, 0x0046}, -+ {TOK_WRITE, 0x098C, 0xAB22}, -+ {TOK_WRITE, 0x0990, 0x0002}, -+ {TOK_WRITE, 0x098C, 0xAB24}, -+ {TOK_WRITE, 0x0990, 0x0005}, -+ {TOK_WRITE, 0x098C, 0x2B28}, -+ {TOK_WRITE, 0x0990, 0x170C}, -+ {TOK_WRITE, 0x098C, 0x2B2A}, -+ {TOK_WRITE, 0x0990, 0x3E80}, -+ {TOK_WRITE, 0x3210, 0x09A8}, -+ {TOK_WRITE, 0x098C, 0x2306}, -+ {TOK_WRITE, 0x0990, 0x0315}, -+ {TOK_WRITE, 0x098C, 0x2308}, -+ {TOK_WRITE, 0x0990, 0xFDDC}, -+ {TOK_WRITE, 0x098C, 0x230A}, -+ {TOK_WRITE, 0x0990, 0x003A}, -+ {TOK_WRITE, 0x098C, 0x230C}, -+ {TOK_WRITE, 0x0990, 0xFF58}, -+ {TOK_WRITE, 0x098C, 0x230E}, -+ {TOK_WRITE, 0x0990, 0x02B7}, -+ {TOK_WRITE, 0x098C, 0x2310}, -+ {TOK_WRITE, 0x0990, 0xFF31}, -+ {TOK_WRITE, 0x098C, 0x2312}, -+ {TOK_WRITE, 0x0990, 0xFF4C}, -+ {TOK_WRITE, 0x098C, 0x2314}, -+ {TOK_WRITE, 0x0990, 0xFE4C}, -+ {TOK_WRITE, 0x098C, 0x2316}, -+ {TOK_WRITE, 0x0990, 0x039E}, -+ {TOK_WRITE, 0x098C, 0x2318}, -+ {TOK_WRITE, 0x0990, 0x001C}, -+ {TOK_WRITE, 0x098C, 0x231A}, -+ {TOK_WRITE, 0x0990, 0x0039}, -+ {TOK_WRITE, 0x098C, 0x231C}, -+ {TOK_WRITE, 0x0990, 0x007F}, -+ {TOK_WRITE, 0x098C, 0x231E}, -+ {TOK_WRITE, 0x0990, 0xFF77}, -+ {TOK_WRITE, 0x098C, 0x2320}, -+ {TOK_WRITE, 0x0990, 0x000A}, -+ {TOK_WRITE, 0x098C, 0x2322}, -+ {TOK_WRITE, 0x0990, 0x0020}, -+ {TOK_WRITE, 0x098C, 0x2324}, -+ {TOK_WRITE, 0x0990, 0x001B}, -+ {TOK_WRITE, 0x098C, 0x2326}, -+ {TOK_WRITE, 0x0990, 0xFFC6}, -+ {TOK_WRITE, 0x098C, 0x2328}, -+ {TOK_WRITE, 0x0990, 0x0086}, -+ {TOK_WRITE, 0x098C, 0x232A}, -+ {TOK_WRITE, 0x0990, 0x00B5}, -+ {TOK_WRITE, 0x098C, 0x232C}, -+ {TOK_WRITE, 0x0990, 0xFEC3}, -+ {TOK_WRITE, 0x098C, 0x232E}, -+ {TOK_WRITE, 0x0990, 0x0001}, -+ {TOK_WRITE, 0x098C, 0x2330}, -+ {TOK_WRITE, 0x0990, 0xFFEF}, -+ {TOK_WRITE, 0x098C, 0xA348}, -+ {TOK_WRITE, 0x0990, 0x0008}, -+ {TOK_WRITE, 0x098C, 0xA349}, -+ {TOK_WRITE, 0x0990, 0x0002}, -+ {TOK_WRITE, 0x098C, 0xA34A}, -+ {TOK_WRITE, 0x0990, 0x0090}, -+ {TOK_WRITE, 0x098C, 0xA34B}, -+ {TOK_WRITE, 0x0990, 0x00FF}, -+ {TOK_WRITE, 0x098C, 0xA34C}, -+ {TOK_WRITE, 0x0990, 0x0075}, -+ {TOK_WRITE, 0x098C, 0xA34D}, -+ {TOK_WRITE, 0x0990, 0x00EF}, -+ {TOK_WRITE, 0x098C, 0xA351}, -+ {TOK_WRITE, 0x0990, 0x0000}, -+ {TOK_WRITE, 0x098C, 0xA352}, -+ {TOK_WRITE, 0x0990, 0x007F}, -+ {TOK_WRITE, 0x098C, 0xA354}, -+ {TOK_WRITE, 0x0990, 0x0043}, -+ {TOK_WRITE, 0x098C, 0xA355}, -+ {TOK_WRITE, 0x0990, 0x0001}, -+ {TOK_WRITE, 0x098C, 0xA35D}, -+ {TOK_WRITE, 0x0990, 0x0078}, -+ {TOK_WRITE, 0x098C, 0xA35E}, -+ {TOK_WRITE, 0x0990, 0x0086}, -+ {TOK_WRITE, 0x098C, 0xA35F}, -+ {TOK_WRITE, 0x0990, 0x007E}, -+ {TOK_WRITE, 0x098C, 0xA360}, -+ {TOK_WRITE, 0x0990, 0x0082}, -+ {TOK_WRITE, 0x098C, 0x2361}, -+ {TOK_WRITE, 0x0990, 0x0040}, -+ {TOK_WRITE, 0x098C, 0xA363}, -+ {TOK_WRITE, 0x0990, 0x00D2}, -+ {TOK_WRITE, 0x098C, 0xA364}, -+ {TOK_WRITE, 0x0990, 0x00F6}, -+ {TOK_WRITE, 0x098C, 0xA302}, -+ {TOK_WRITE, 0x0990, 0x0000}, -+ {TOK_WRITE, 0x098C, 0xA303}, -+ {TOK_WRITE, 0x0990, 0x00EF}, -+ {TOK_WRITE, 0x098C, 0xAB20}, -+ {TOK_WRITE, 0x0990, 0x0024}, -+ {TOK_WRITE, 0x098C, 0xA103}, -+ {TOK_WRITE, 0x0990, 0x0006}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_WRITE, 0x098C, 0xA103}, -+ {TOK_WRITE, 0x0990, 0x0005}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_WRITE, 0x098C, 0x222D}, -+ {TOK_WRITE, 0x0990, 0x0088}, -+ {TOK_WRITE, 0x098C, 0xA408}, -+ {TOK_WRITE, 0x0990, 0x0020}, -+ {TOK_WRITE, 0x098C, 0xA409}, -+ {TOK_WRITE, 0x0990, 0x0023}, -+ {TOK_WRITE, 0x098C, 0xA40A}, -+ {TOK_WRITE, 0x0990, 0x0027}, -+ {TOK_WRITE, 0x098C, 0xA40B}, -+ {TOK_WRITE, 0x0990, 0x002A}, -+ {TOK_WRITE, 0x098C, 0x2411}, -+ {TOK_WRITE, 0x0990, 0x0088}, -+ {TOK_WRITE, 0x098C, 0x2413}, -+ {TOK_WRITE, 0x0990, 0x00A4}, -+ {TOK_WRITE, 0x098C, 0x2415}, -+ {TOK_WRITE, 0x0990, 0x0088}, -+ {TOK_WRITE, 0x098C, 0x2417}, -+ {TOK_WRITE, 0x0990, 0x00A4}, -+ {TOK_WRITE, 0x098C, 0xA404}, -+ {TOK_WRITE, 0x0990, 0x0010}, -+ {TOK_WRITE, 0x098C, 0xA40D}, -+ {TOK_WRITE, 0x0990, 0x0002}, -+ {TOK_WRITE, 0x098C, 0xA40E}, -+ {TOK_WRITE, 0x0990, 0x0003}, -+ {TOK_WRITE, 0x098C, 0xA103}, -+ {TOK_WRITE, 0x0990, 0x0006}, -+ {TOK_DELAY, 0, 100}, -+ /* test pattern all white*/ -+ /* {TOK_WRITE, 0x098C, 0xA766}, -+ {TOK_WRITE, 0x0990, 0x0001}, -+ */ -+ {TOK_WRITE, 0x098C, 0xA103}, -+ {TOK_WRITE, 0x0990, 0x0005}, -+ {TOK_DELAY, 0, 100}, -+ {TOK_TERM, 0, 0}, -+}; -+ -+/* List of image formats supported by mt9v113 -+ * Currently we are using 8 bit mode only, but can be -+ * extended to 10/20 bit mode. -+ */ -+static const struct v4l2_fmtdesc mt9v113_fmt_list[] = { -+ { -+ .index = 0, -+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, -+ .flags = 0, -+ .description = "8-bit UYVY 4:2:2 Format", -+ .pixelformat = V4L2_PIX_FMT_UYVY, -+ }, -+}; -+ -+/* -+ * Supported standards - -+ * -+ * Currently supports two standards only, need to add support for rest of the -+ * modes, like SECAM, etc... -+ */ -+static struct mt9v113_std_info mt9v113_std_list[] = { -+ /* Standard: STD_NTSC_MJ */ -+ [MT9V113_STD_VGA] = { -+ .width = VGA_NUM_ACTIVE_PIXELS, -+ .height = VGA_NUM_ACTIVE_LINES, -+ .video_std = MT9V113_IMAGE_STD_VGA, -+ .standard = { -+ .index = 0, -+ .id = MT9V113_IMAGE_STD_VGA, -+ .name = "VGA", -+ .frameperiod = {1001, 30000}, -+ .framelines = 480 -+ }, -+ /* Standard: STD_PAL_BDGHIN */ -+ }, -+ [MT9V113_STD_QVGA] = { -+ .width = QVGA_NUM_ACTIVE_PIXELS, -+ .height = QVGA_NUM_ACTIVE_LINES, -+ .video_std = MT9V113_IMAGE_STD_QVGA, -+ .standard = { -+ .index = 1, -+ .id = MT9V113_IMAGE_STD_QVGA, -+ .name = "QVGA", -+ .frameperiod = {1001, 30000}, -+ .framelines = 320 -+ }, -+ }, -+ /* Standard: need to add for additional standard */ -+}; -+/* -+ * Control structure for Auto Gain -+ * This is temporary data, will get replaced once -+ * v4l2_ctrl_query_fill supports it. -+ */ -+static const struct v4l2_queryctrl mt9v113_autogain_ctrl = { -+ .id = V4L2_CID_AUTOGAIN, -+ .name = "Gain, Automatic", -+ .type = V4L2_CTRL_TYPE_BOOLEAN, -+ .minimum = 0, -+ .maximum = 1, -+ .step = 1, -+ .default_value = 1, -+}; -+ -+static int mt9v113_read_reg(struct i2c_client *client, unsigned short reg) -+{ -+ int err = 0; -+ struct i2c_msg msg[1]; -+ unsigned char data[2]; -+ unsigned short val = 0; -+ -+ if (!client->adapter) { -+ err = -ENODEV; -+ return err; -+ }else { -+ // TODO: addr should be set up where else -+ msg->addr = MT9V113_I2C_ADDR;//client->addr; -+ msg->flags = 0; -+ msg->len = I2C_TWO_BYTE_TRANSFER; -+ msg->buf = data; -+ data[0] = (reg & I2C_TXRX_DATA_MASK_UPPER) >> -+ I2C_TXRX_DATA_SHIFT; -+ data[1] = (reg & I2C_TXRX_DATA_MASK); -+ err = i2c_transfer(client->adapter, msg, 1); -+ if (err >= 0) { -+ msg->flags = I2C_M_RD; -+ msg->len = I2C_TWO_BYTE_TRANSFER; /* 2 byte read */ -+ err = i2c_transfer(client->adapter, msg, 1); -+ if (err >= 0) { -+ val = ((data[0] & I2C_TXRX_DATA_MASK) -+ << I2C_TXRX_DATA_SHIFT) -+ | (data[1] & I2C_TXRX_DATA_MASK); -+ } -+ } -+ } -+ return (int)(0x0000ffff & val); -+} -+ -+ -+ -+static int mt9v113_write_reg(struct i2c_client *client, unsigned short reg, unsigned short val) -+{ -+ int err = 0; -+ int trycnt = 0; -+ -+ struct i2c_msg msg[1]; -+ unsigned char data[4]; -+ err = -1; -+ -+ v4l_dbg(1, debug, client, -+ "mt9v113_write_reg reg=0x%x, val=0x%x\n", -+ reg,val); -+ -+ while ((err < 0) && (trycnt < I2C_RETRY_COUNT)) { -+ trycnt++; -+ if (!client->adapter) { -+ err = -ENODEV; -+ } else { -+ // TODO: addr should be set up where else -+ msg->addr = MT9V113_I2C_ADDR;//client->addr; -+ msg->flags = 0; -+ msg->len = I2C_FOUR_BYTE_TRANSFER; -+ msg->buf = data; -+ data[0] = (reg & I2C_TXRX_DATA_MASK_UPPER) >> -+ I2C_TXRX_DATA_SHIFT; -+ data[1] = (reg & I2C_TXRX_DATA_MASK); -+ data[2] = (val & I2C_TXRX_DATA_MASK_UPPER) >> -+ I2C_TXRX_DATA_SHIFT; -+ data[3] = (val & I2C_TXRX_DATA_MASK); -+ err = i2c_transfer(client->adapter, msg, 1); -+ } -+ } -+ if (err < 0) { -+ printk(KERN_INFO "\n I2C write failed"); -+ } -+ return err; -+} -+ -+/* configure mux, for DM355 EVM only */ -+#ifndef CONFIG_MACH_DM355_LEOPARD -+static int mt9v113_en_mux(struct i2c_client *client) -+{ -+ int err = 0; -+ int trycnt = 0; -+ /* unsigned short readval = 0;*/ -+ -+ struct i2c_msg msg[1]; -+ unsigned char data[4]; -+ err = -1; -+ printk(KERN_INFO -+ "\n entering mt9v113_en_mux \n"); -+ -+ while ((err < 0) && (trycnt < 5)) { -+ trycnt++; -+ if (!client->adapter) { -+ err = -ENODEV; -+ } else { -+ msg->addr = 0x25; -+ msg->flags = 0; -+ msg->len = I2C_TWO_BYTE_TRANSFER; -+ msg->buf = data; -+ data[0] = (unsigned char)(0x08 & I2C_TXRX_DATA_MASK); -+ data[1] = (unsigned char)(0x80 & I2C_TXRX_DATA_MASK); -+ -+ err = i2c_transfer(client->adapter, msg, 1); -+ if (err < 0) { -+ printk(KERN_INFO -+ "\n ERROR in ECP register write\n"); -+ } -+ } -+ } -+ if (err < 0) { -+ printk(KERN_INFO "\n I2C write failed"); -+ } -+ return err; -+} -+#endif -+ -+/* -+ * mt9v113_write_regs : Initializes a list of registers -+ * if token is TOK_TERM, then entire write operation terminates -+ * if token is TOK_DELAY, then a delay of 'val' msec is introduced -+ * if token is TOK_SKIP, then the register write is skipped -+ * if token is TOK_WRITE, then the register write is performed -+ * -+ * reglist - list of registers to be written -+ * Returns zero if successful, or non-zero otherwise. -+ */ -+static int mt9v113_write_regs(struct i2c_client *client, -+ const struct mt9v113_reg reglist[]) -+{ -+ int err; -+ const struct mt9v113_reg *next = reglist; -+ -+ for (; next->token != TOK_TERM; next++) { -+ if (next->token == TOK_DELAY) { -+ msleep(next->val); -+ continue; -+ } -+ -+ if (next->token == TOK_SKIP) -+ continue; -+ -+ err = mt9v113_write_reg(client, next->reg, next->val); -+ if (err < 0) { -+ v4l_err(client, "Write failed. Err[%d]\n", err); -+ return err; -+ } -+ } -+ return 0; -+} -+ -+/* -+ * mt9v113_get_current_std: -+ * Returns the current standard -+ */ -+static enum mt9v113_std mt9v113_get_current_std(struct mt9v113_decoder -+ *decoder) -+{ -+ return MT9V113_STD_VGA; -+} -+ -+/* -+ * Configure the mt9v113 with the current register settings -+ * Returns zero if successful, or non-zero otherwise. -+ */ -+static int mt9v113_configure(struct mt9v113_decoder *decoder) -+{ -+ int err; -+ -+ /* common register initialization */ -+ err = -+ mt9v113_write_regs(decoder->client, mt9v113_reg_list); -+ if (err) -+ return err; -+ -+// if (debug) -+// mt9v113_reg_dump(decoder); -+ -+ return 0; -+} -+ -+/* -+ * Configure the MT9V113 to VGA mode -+ * Returns zero if successful, or non-zero otherwise. -+ */ -+static int mt9v113_vga_mode(struct mt9v113_decoder *decoder) -+{ -+ int err; -+ -+ err = -+ mt9v113_write_regs(decoder->client, mt9v113_vga_reg); -+ if (err) -+ return err; -+ -+ return 0; -+} -+ -+ -+/* -+ * Detect if an mt9v113 is present, and if so which revision. -+ * A device is considered to be detected if the chip ID (LSB and MSB) -+ * registers match the expected values. -+ * Any value of the rom version register is accepted. -+ * Returns ENODEV error number if no device is detected, or zero -+ * if a device is detected. -+ */ -+static int mt9v113_detect(struct mt9v113_decoder *decoder) -+{ -+ unsigned short val=0; -+ -+#ifndef CONFIG_MACH_DM355_LEOPARD -+// mt9v113_en_mux(decoder->client); -+#endif -+ -+ val = mt9v113_read_reg(decoder->client, REG_CHIP_ID); -+ -+ v4l_dbg(1, debug, decoder->client, -+ "chip id detected 0x%x\n", -+ val); -+ -+ if (MT9V113_CHIP_ID != val) { -+ /* We didn't read the values we expected, so this must not be -+ * MT9V113. -+ */ -+ v4l_err(decoder->client, -+ "chip id mismatch read 0x%x, expecting 0x%x\n", val, MT9V113_CHIP_ID); -+ return -ENODEV; -+ } -+ -+ decoder->ver = val; -+ decoder->state = STATE_DETECTED; -+ -+ v4l_info(decoder->client, -+ "%s found at 0x%x (%s)\n", decoder->client->name, -+ decoder->client->addr << 1, -+ decoder->client->adapter->name); -+ -+ return 0; -+} -+ -+/* -+ * Following are decoder interface functions implemented by -+ * mt9v113 decoder driver. -+ */ -+ -+/** -+ * ioctl_querystd - V4L2 decoder interface handler for VIDIOC_QUERYSTD ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @std_id: standard V4L2 std_id ioctl enum -+ * -+ * Returns the current standard detected by mt9v113. If no active input is -+ * detected, returns -EINVAL -+ */ -+static int ioctl_querystd(struct v4l2_int_device *s, v4l2_std_id *std_id) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ enum mt9v113_std current_std; -+ -+ if (std_id == NULL) -+ return -EINVAL; -+ -+ /* get the current standard */ -+ current_std = mt9v113_get_current_std(decoder); -+ if (current_std == MT9V113_IMAGE_STD_INVALID) -+ return -EINVAL; -+ -+ decoder->current_std = current_std; -+ *std_id = decoder->std_list[current_std].standard.id; -+ -+ v4l_dbg(1, debug, decoder->client, "Current STD: %s", -+ decoder->std_list[current_std].standard.name); -+ return 0; -+} -+ -+/** -+ * ioctl_s_std - V4L2 decoder interface handler for VIDIOC_S_STD ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @std_id: standard V4L2 v4l2_std_id ioctl enum -+ * -+ * If std_id is supported, sets the requested standard. Otherwise, returns -+ * -EINVAL -+ */ -+static int ioctl_s_std(struct v4l2_int_device *s, v4l2_std_id *std_id) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int err, i; -+ -+ if (std_id == NULL) -+ return -EINVAL; -+ -+ for (i = 0; i < decoder->num_stds; i++) -+ if (*std_id & decoder->std_list[i].standard.id) -+ break; -+ -+ if ((i == decoder->num_stds) || (i == MT9V113_STD_INVALID)) -+ return -EINVAL; -+ -+ err = mt9v113_write_reg(decoder->client, REG_VIDEO_STD, -+ decoder->std_list[i].video_std); -+ if (err) -+ return err; -+ -+ decoder->current_std = i; -+ mt9v113_reg_list[REG_VIDEO_STD].val = decoder->std_list[i].video_std; -+ -+ v4l_dbg(1, debug, decoder->client, "Standard set to: %s", -+ decoder->std_list[i].standard.name); -+ return 0; -+} -+ -+/** -+ * ioctl_s_routing - V4L2 decoder interface handler for VIDIOC_S_INPUT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @index: number of the input -+ * -+ * If index is valid, selects the requested input. Otherwise, returns -EINVAL if -+ * the input is not supported or there is no active signal present in the -+ * selected input. -+ */ -+static int ioctl_s_routing(struct v4l2_int_device *s, -+ struct v4l2_routing *route) -+{ -+ return 0; -+} -+ -+/** -+ * ioctl_queryctrl - V4L2 decoder interface handler for VIDIOC_QUERYCTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @qctrl: standard V4L2 v4l2_queryctrl structure -+ * -+ * If the requested control is supported, returns the control information. -+ * Otherwise, returns -EINVAL if the control is not supported. -+ */ -+static int -+ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qctrl) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int err = -EINVAL; -+ -+ if (qctrl == NULL) -+ return err; -+ -+ switch (qctrl->id) { -+ case V4L2_CID_BRIGHTNESS: -+ /* Brightness supported is same as standard one (0-255), -+ * so make use of standard API provided. -+ */ -+ err = v4l2_ctrl_query_fill(qctrl, 0, 255, 1, 128); -+ break; -+ case V4L2_CID_CONTRAST: -+ case V4L2_CID_SATURATION: -+ /* Saturation and Contrast supported is - -+ * Contrast: 0 - 255 (Default - 128) -+ * Saturation: 0 - 255 (Default - 128) -+ */ -+ err = v4l2_ctrl_query_fill(qctrl, 0, 255, 1, 128); -+ break; -+ case V4L2_CID_HUE: -+ /* Hue Supported is - -+ * Hue - -180 - +180 (Default - 0, Step - +180) -+ */ -+ err = v4l2_ctrl_query_fill(qctrl, -180, 180, 180, 0); -+ break; -+ case V4L2_CID_AUTOGAIN: -+ /* Autogain is either 0 or 1*/ -+ memcpy(qctrl, &mt9v113_autogain_ctrl, -+ sizeof(struct v4l2_queryctrl)); -+ err = 0; -+ break; -+ default: -+ v4l_err(decoder->client, -+ "invalid control id %d\n", qctrl->id); -+ return err; -+ } -+ -+ v4l_dbg(1, debug, decoder->client, -+ "Query Control: %s : Min - %d, Max - %d, Def - %d", -+ qctrl->name, -+ qctrl->minimum, -+ qctrl->maximum, -+ qctrl->default_value); -+ -+ return err; -+} -+ -+/** -+ * ioctl_g_ctrl - V4L2 decoder interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @ctrl: pointer to v4l2_control structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the decoder. Otherwise, returns -EINVAL if the control is not -+ * supported. -+ */ -+static int -+ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ -+ if (ctrl == NULL) -+ return -EINVAL; -+ -+ switch (ctrl->id) { -+ case V4L2_CID_BRIGHTNESS: -+ ctrl->value = mt9v113_reg_list[REG_BRIGHTNESS].val; -+ break; -+ case V4L2_CID_CONTRAST: -+ ctrl->value = mt9v113_reg_list[REG_CONTRAST].val; -+ break; -+ case V4L2_CID_SATURATION: -+ ctrl->value = mt9v113_reg_list[REG_SATURATION].val; -+ break; -+ case V4L2_CID_HUE: -+ ctrl->value = mt9v113_reg_list[REG_HUE].val; -+ if (ctrl->value == 0x7F) -+ ctrl->value = 180; -+ else if (ctrl->value == 0x80) -+ ctrl->value = -180; -+ else -+ ctrl->value = 0; -+ -+ break; -+ case V4L2_CID_AUTOGAIN: -+ ctrl->value = mt9v113_reg_list[REG_AFE_GAIN_CTRL].val; -+ if ((ctrl->value & 0x3) == 3) -+ ctrl->value = 1; -+ else -+ ctrl->value = 0; -+ -+ break; -+ default: -+ v4l_err(decoder->client, -+ "invalid control id %d\n", ctrl->id); -+ return -EINVAL; -+ } -+ -+ v4l_dbg(1, debug, decoder->client, -+ "Get Control: ID - %d - %d", -+ ctrl->id, ctrl->value); -+ return 0; -+} -+ -+/** -+ * ioctl_s_ctrl - V4L2 decoder interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @ctrl: pointer to v4l2_control structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW. Otherwise, returns -EINVAL if the control is not supported. -+ */ -+static int -+ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int err = -EINVAL, value; -+ -+ if (ctrl == NULL) -+ return err; -+ -+ value = (__s32) ctrl->value; -+ -+ switch (ctrl->id) { -+ case V4L2_CID_BRIGHTNESS: -+ if (ctrl->value < 0 || ctrl->value > 255) { -+ v4l_err(decoder->client, -+ "invalid brightness setting %d\n", -+ ctrl->value); -+ return -ERANGE; -+ } -+ err = mt9v113_write_reg(decoder->client, REG_BRIGHTNESS, -+ value); -+ if (err) -+ return err; -+ mt9v113_reg_list[REG_BRIGHTNESS].val = value; -+ break; -+ case V4L2_CID_CONTRAST: -+ if (ctrl->value < 0 || ctrl->value > 255) { -+ v4l_err(decoder->client, -+ "invalid contrast setting %d\n", -+ ctrl->value); -+ return -ERANGE; -+ } -+ err = mt9v113_write_reg(decoder->client, REG_CONTRAST, -+ value); -+ if (err) -+ return err; -+ mt9v113_reg_list[REG_CONTRAST].val = value; -+ break; -+ case V4L2_CID_SATURATION: -+ if (ctrl->value < 0 || ctrl->value > 255) { -+ v4l_err(decoder->client, -+ "invalid saturation setting %d\n", -+ ctrl->value); -+ return -ERANGE; -+ } -+ err = mt9v113_write_reg(decoder->client, REG_SATURATION, -+ value); -+ if (err) -+ return err; -+ mt9v113_reg_list[REG_SATURATION].val = value; -+ break; -+ case V4L2_CID_HUE: -+ if (value == 180) -+ value = 0x7F; -+ else if (value == -180) -+ value = 0x80; -+ else if (value == 0) -+ value = 0; -+ else { -+ v4l_err(decoder->client, -+ "invalid hue setting %d\n", -+ ctrl->value); -+ return -ERANGE; -+ } -+ err = mt9v113_write_reg(decoder->client, REG_HUE, -+ value); -+ if (err) -+ return err; -+ mt9v113_reg_list[REG_HUE].val = value; -+ break; -+ case V4L2_CID_AUTOGAIN: -+ if (value == 1) -+ value = 0x0F; -+ else if (value == 0) -+ value = 0x0C; -+ else { -+ v4l_err(decoder->client, -+ "invalid auto gain setting %d\n", -+ ctrl->value); -+ return -ERANGE; -+ } -+ err = mt9v113_write_reg(decoder->client, REG_AFE_GAIN_CTRL, -+ value); -+ if (err) -+ return err; -+ mt9v113_reg_list[REG_AFE_GAIN_CTRL].val = value; -+ break; -+ default: -+ v4l_err(decoder->client, -+ "invalid control id %d\n", ctrl->id); -+ return err; -+ } -+ -+ v4l_dbg(1, debug, decoder->client, -+ "Set Control: ID - %d - %d", -+ ctrl->id, ctrl->value); -+ -+ return err; -+} -+ -+/** -+ * ioctl_enum_fmt_cap - Implement the CAPTURE buffer VIDIOC_ENUM_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: standard V4L2 VIDIOC_ENUM_FMT ioctl structure -+ * -+ * Implement the VIDIOC_ENUM_FMT ioctl to enumerate supported formats -+ */ -+static int -+ioctl_enum_fmt_cap(struct v4l2_int_device *s, struct v4l2_fmtdesc *fmt) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int index; -+ -+ if (fmt == NULL) -+ return -EINVAL; -+ -+ index = fmt->index; -+ if ((index >= decoder->num_fmts) || (index < 0)) -+ return -EINVAL; /* Index out of bound */ -+ -+ if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; /* only capture is supported */ -+ -+ memcpy(fmt, &decoder->fmt_list[index], -+ sizeof(struct v4l2_fmtdesc)); -+ -+ v4l_dbg(1, debug, decoder->client, -+ "Current FMT: index - %d (%s)", -+ decoder->fmt_list[index].index, -+ decoder->fmt_list[index].description); -+ return 0; -+} -+ -+/** -+ * ioctl_try_fmt_cap - Implement the CAPTURE buffer VIDIOC_TRY_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 VIDIOC_TRY_FMT ioctl structure -+ * -+ * Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This -+ * ioctl is used to negotiate the image capture size and pixel format -+ * without actually making it take effect. -+ */ -+static int -+ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int ifmt; -+ struct v4l2_pix_format *pix; -+ enum mt9v113_std current_std; -+ -+ if (f == NULL) -+ return -EINVAL; -+ -+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ pix = &f->fmt.pix; -+ -+ /* Calculate height and width based on current standard */ -+ current_std = mt9v113_get_current_std(decoder); -+ if (current_std == MT9V113_STD_INVALID) -+ return -EINVAL; -+ -+ decoder->current_std = current_std; -+ pix->width = decoder->std_list[current_std].width; -+ pix->height = decoder->std_list[current_std].height; -+ -+ for (ifmt = 0; ifmt < decoder->num_fmts; ifmt++) { -+ if (pix->pixelformat == -+ decoder->fmt_list[ifmt].pixelformat) -+ break; -+ } -+ if (ifmt == decoder->num_fmts) -+ ifmt = 0; /* None of the format matched, select default */ -+ pix->pixelformat = decoder->fmt_list[ifmt].pixelformat; -+ -+ pix->field = V4L2_FIELD_NONE; -+ pix->bytesperline = pix->width * 2; -+ pix->sizeimage = pix->bytesperline * pix->height; -+ pix->colorspace = V4L2_COLORSPACE_SMPTE170M; -+ pix->priv = 0; -+ -+ v4l_dbg(1, debug, decoder->client, -+ "Try FMT: pixelformat - %s, bytesperline - %d" -+ "Width - %d, Height - %d", -+ decoder->fmt_list[ifmt].description, pix->bytesperline, -+ pix->width, pix->height); -+ return 0; -+} -+ -+/** -+ * ioctl_s_fmt_cap - V4L2 decoder interface handler for VIDIOC_S_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 VIDIOC_S_FMT ioctl structure -+ * -+ * If the requested format is supported, configures the HW to use that -+ * format, returns error code if format not supported or HW can't be -+ * correctly configured. -+ */ -+static int -+ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ struct v4l2_pix_format *pix; -+ int rval; -+ -+ if (f == NULL) -+ return -EINVAL; -+ -+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; /* only capture is supported */ -+ -+ pix = &f->fmt.pix; -+ rval = ioctl_try_fmt_cap(s, f); -+ if (rval) -+ return rval; -+ -+ decoder->pix = *pix; -+ -+ return rval; -+} -+ -+/** -+ * ioctl_g_fmt_cap - V4L2 decoder interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the decoder's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int -+ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ -+ if (f == NULL) -+ return -EINVAL; -+ -+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; /* only capture is supported */ -+ -+ f->fmt.pix = decoder->pix; -+ -+ v4l_dbg(1, debug, decoder->client, -+ "Current FMT: bytesperline - %d" -+ "Width - %d, Height - %d", -+ decoder->pix.bytesperline, -+ decoder->pix.width, decoder->pix.height); -+ return 0; -+} -+ -+/** -+ * ioctl_g_parm - V4L2 decoder interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the decoder's video CAPTURE parameters. -+ */ -+static int -+ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ struct v4l2_captureparm *cparm; -+ enum mt9v113_std current_std; -+ -+ if (a == NULL) -+ return -EINVAL; -+ -+ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; /* only capture is supported */ -+ -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ /* get the current standard */ -+ current_std = mt9v113_get_current_std(decoder); -+ if (current_std == MT9V113_STD_INVALID) -+ return -EINVAL; -+ -+ decoder->current_std = current_std; -+ -+ cparm = &a->parm.capture; -+ cparm->capability = V4L2_CAP_TIMEPERFRAME; -+ cparm->timeperframe = -+ decoder->std_list[current_std].standard.frameperiod; -+ -+ return 0; -+} -+ -+/** -+ * ioctl_s_parm - V4L2 decoder interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the decoder to use the input parameters, if possible. If -+ * not possible, returns the appropriate error code. -+ */ -+static int -+ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ struct v4l2_fract *timeperframe; -+ enum mt9v113_std current_std; -+ -+ if (a == NULL) -+ return -EINVAL; -+ -+ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; /* only capture is supported */ -+ -+ timeperframe = &a->parm.capture.timeperframe; -+ -+ /* get the current standard */ -+ current_std = mt9v113_get_current_std(decoder); -+ if (current_std == MT9V113_STD_INVALID) -+ return -EINVAL; -+ -+ decoder->current_std = current_std; -+ -+ *timeperframe = -+ decoder->std_list[current_std].standard.frameperiod; -+ -+ return 0; -+} -+ -+/** -+ * ioctl_g_ifparm - V4L2 decoder interface handler for vidioc_int_g_ifparm_num -+ * @s: pointer to standard V4L2 device structure -+ * @p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure -+ * -+ * Gets slave interface parameters. -+ * Calculates the required xclk value to support the requested -+ * clock parameters in p. This value is returned in the p -+ * parameter. -+ */ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int rval; -+ -+ if (p == NULL) -+ return -EINVAL; -+ -+ if (NULL == decoder->pdata->ifparm) -+ return -EINVAL; -+ -+ rval = decoder->pdata->ifparm(p); -+ if (rval) { -+ v4l_err(decoder->client, "g_ifparm.Err[%d]\n", rval); -+ return rval; -+ } -+ -+ p->u.bt656.clock_curr = 27000000; // TODO: read clock rate from sensor -+ -+ return 0; -+} -+ -+/** -+ * ioctl_g_priv - V4L2 decoder interface handler for vidioc_int_g_priv_num -+ * @s: pointer to standard V4L2 device structure -+ * @p: void pointer to hold decoder's private data address -+ * -+ * Returns device's (decoder's) private data area address in p parameter -+ */ -+static int ioctl_g_priv(struct v4l2_int_device *s, void *p) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ -+ if (NULL == decoder->pdata->priv_data_set) -+ return -EINVAL; -+ -+ return decoder->pdata->priv_data_set(p); -+} -+ -+/** -+ * ioctl_s_power - V4L2 decoder interface handler for vidioc_int_s_power_num -+ * @s: pointer to standard V4L2 device structure -+ * @on: power state to which device is to be set -+ * -+ * Sets devices power state to requrested state, if possible. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int err = 0; -+ -+ switch (on) { -+ case V4L2_POWER_OFF: -+ /* Power Down Sequence */ -+ err = -+ mt9v113_write_reg(decoder->client, REG_OPERATION_MODE, -+ 0x01); -+ /* Disable mux for mt9v113 data path */ -+ if (decoder->pdata->power_set) -+ err |= decoder->pdata->power_set(s, on); -+ decoder->state = STATE_NOT_DETECTED; -+ break; -+ -+ case V4L2_POWER_STANDBY: -+ if (decoder->pdata->power_set) -+ err = decoder->pdata->power_set(s, on); -+ break; -+ -+ case V4L2_POWER_ON: -+ /* Enable mux for mt9v113 data path */ -+ if ((decoder->pdata->power_set) && -+ (decoder->state == STATE_NOT_DETECTED)) { -+ -+ err = decoder->pdata->power_set(s, on); -+ -+ /* Detect the sensor is not already detected */ -+ err |= mt9v113_detect(decoder); -+ if (err) { -+ v4l_err(decoder->client, -+ "Unable to detect decoder\n"); -+ return err; -+ } -+ } -+ // Only VGA mode for now -+ err |= mt9v113_vga_mode(decoder); -+ break; -+ -+ default: -+ err = -ENODEV; -+ break; -+ } -+ -+ return err; -+} -+ -+/** -+ * ioctl_init - V4L2 decoder interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialize the decoder device (calls mt9v113_configure()) -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+// struct mt9v113_decoder *decoder = s->priv; -+ int err = 0; -+ -+ /* Set default standard to auto */ -+ //mt9v113_reg_list[REG_VIDEO_STD].val = -+ // VIDEO_STD_AUTO_SWITCH_BIT; -+// err |= mt9v113_configure(decoder); -+// err |= mt9v113_vga_mode(decoder); -+ -+ return err; -+} -+ -+/** -+ * ioctl_dev_exit - V4L2 decoder interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the dev. at slave detach. The complement of ioctl_dev_init. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ return 0; -+} -+ -+/** -+ * ioctl_dev_init - V4L2 decoder interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. Returns 0 if -+ * mt9v113 device could be found, otherwise returns appropriate error. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int err; -+ -+ printk("%s: %d\n", __func__, __LINE__); -+ err = mt9v113_detect(decoder); -+ if (err < 0) { -+ v4l_err(decoder->client, -+ "Unable to detect decoder\n"); -+ return err; -+ } -+ -+ v4l_info(decoder->client, -+ "chip version 0x%.2x detected\n", decoder->ver); -+ -+ err |= mt9v113_configure(decoder); -+ err |= mt9v113_vga_mode(decoder); -+ -+ return 0; -+} -+ -+static struct v4l2_int_ioctl_desc mt9v113_ioctl_desc[] = { -+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init}, -+ {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func*) ioctl_dev_exit}, -+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power}, -+ {vidioc_int_g_priv_num, (v4l2_int_ioctl_func*) ioctl_g_priv}, -+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm}, -+ {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init}, -+ {vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, -+ {vidioc_int_try_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_try_fmt_cap}, -+ {vidioc_int_g_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, -+ {vidioc_int_s_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, -+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, -+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, -+ {vidioc_int_queryctrl_num, -+ (v4l2_int_ioctl_func *) ioctl_queryctrl}, -+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, -+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, -+ {vidioc_int_querystd_num, (v4l2_int_ioctl_func *) ioctl_querystd}, -+ {vidioc_int_s_std_num, (v4l2_int_ioctl_func *) ioctl_s_std}, -+ {vidioc_int_s_video_routing_num, -+ (v4l2_int_ioctl_func *) ioctl_s_routing}, -+}; -+ -+static struct v4l2_int_slave mt9v113_slave = { -+ .ioctls = mt9v113_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(mt9v113_ioctl_desc), -+}; -+ -+static struct mt9v113_decoder mt9v113_dev = { -+ .state = STATE_NOT_DETECTED, -+ -+ .fmt_list = mt9v113_fmt_list, -+ .num_fmts = ARRAY_SIZE(mt9v113_fmt_list), -+ -+ .pix = { /* Default to 8-bit YUV 422 */ -+ .width = VGA_NUM_ACTIVE_PIXELS, -+ .height = VGA_NUM_ACTIVE_LINES, -+ .pixelformat = V4L2_PIX_FMT_UYVY, -+ .field = V4L2_FIELD_NONE, -+ .bytesperline = VGA_NUM_ACTIVE_PIXELS * 2, -+ .sizeimage = -+ VGA_NUM_ACTIVE_PIXELS * 2 * VGA_NUM_ACTIVE_LINES, -+ .colorspace = V4L2_COLORSPACE_SMPTE170M, -+ }, -+ -+ .current_std = MT9V113_STD_VGA, -+ .std_list = mt9v113_std_list, -+ .num_stds = ARRAY_SIZE(mt9v113_std_list), -+ -+}; -+ -+static struct v4l2_int_device mt9v113_int_device = { -+ .module = THIS_MODULE, -+ .name = MT9V113_MODULE_NAME, -+ .priv = &mt9v113_dev, -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &mt9v113_slave, -+ }, -+}; -+ -+/** -+ * mt9v113_probe - decoder driver i2c probe handler -+ * @client: i2c driver client device structure -+ * -+ * Register decoder as an i2c client device and V4L2 -+ * device. -+ */ -+static int -+mt9v113_probe(struct i2c_client *client, const struct i2c_device_id *id) -+{ -+ struct mt9v113_decoder *decoder = &mt9v113_dev; -+ int err; -+ -+ printk("%s: %d\n", __func__, __LINE__); -+ /* Check if the adapter supports the needed features */ -+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) -+ return -EIO; -+ -+ printk("%s: %d\n", __func__, __LINE__); -+ decoder->pdata = client->dev.platform_data; -+ if (!decoder->pdata) { -+ v4l_err(client, "No platform data!!\n"); -+ return -ENODEV; -+ } -+ printk("%s: %d\n", __func__, __LINE__); -+ /* -+ * Fetch platform specific data, and configure the -+ * mt9v113_reg_list[] accordingly. Since this is one -+ * time configuration, no need to preserve. -+ */ -+ -+ /*mt9v113_reg_list[REG_OUTPUT_FORMATTER2].val |= -+ (decoder->pdata->clk_polarity << 1); -+ mt9v113_reg_list[REG_SYNC_CONTROL].val |= -+ ((decoder->pdata->hs_polarity << 2) | -+ (decoder->pdata->vs_polarity << 3)); -+ */ -+ /* -+ * Save the id data, required for power up sequence -+ */ -+ decoder->id = (struct i2c_device_id *)id; -+ /* Attach to Master */ -+ strcpy(mt9v113_int_device.u.slave->attach_to, decoder->pdata->master); -+ decoder->v4l2_int_device = &mt9v113_int_device; -+ decoder->client = client; -+ i2c_set_clientdata(client, decoder); -+ -+ /* Register with V4L2 layer as slave device */ -+ err = v4l2_int_device_register(decoder->v4l2_int_device); -+ if (err) { -+ i2c_set_clientdata(client, NULL); -+ v4l_err(client, -+ "Unable to register to v4l2. Err[%d]\n", err); -+ -+ } else -+ v4l_info(client, "Registered to v4l2 master %s!!\n", -+ decoder->pdata->master); -+ -+ return 0; -+} -+ -+/** -+ * mt9v113_remove - decoder driver i2c remove handler -+ * @client: i2c driver client device structure -+ * -+ * Unregister decoder as an i2c client device and V4L2 -+ * device. Complement of mt9v113_probe(). -+ */ -+static int __exit mt9v113_remove(struct i2c_client *client) -+{ -+ struct mt9v113_decoder *decoder = i2c_get_clientdata(client); -+ -+ if (!client->adapter) -+ return -ENODEV; /* our client isn't attached */ -+ -+ v4l2_int_device_unregister(decoder->v4l2_int_device); -+ i2c_set_clientdata(client, NULL); -+ -+ return 0; -+} -+/* -+ * mt9v113 Init/Power on Sequence -+ */ -+static const struct mt9v113_reg mt9v113m_init_reg_seq[] = { -+ {TOK_WRITE, REG_OPERATION_MODE, 0x01}, -+ {TOK_WRITE, REG_OPERATION_MODE, 0x00}, -+}; -+static const struct mt9v113_init_seq mt9v113m_init = { -+ .no_regs = ARRAY_SIZE(mt9v113m_init_reg_seq), -+ .init_reg_seq = mt9v113m_init_reg_seq, -+}; -+/* -+ * I2C Device Table - -+ * -+ * name - Name of the actual device/chip. -+ * driver_data - Driver data -+ */ -+static const struct i2c_device_id mt9v113_id[] = { -+ {"mt9v113", (unsigned long)&mt9v113m_init}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, mt9v113_id); -+ -+static struct i2c_driver mt9v113_i2c_driver = { -+ .driver = { -+ .name = MT9V113_MODULE_NAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = mt9v113_probe, -+ .remove = __exit_p(mt9v113_remove), -+ .id_table = mt9v113_id, -+}; -+ -+/** -+ * mt9v113_init -+ * -+ * Module init function -+ */ -+static int __init mt9v113_init(void) -+{ -+ return i2c_add_driver(&mt9v113_i2c_driver); -+} -+ -+/** -+ * mt9v113_cleanup -+ * -+ * Module exit function -+ */ -+static void __exit mt9v113_cleanup(void) -+{ -+ i2c_del_driver(&mt9v113_i2c_driver); -+} -+ -+module_init(mt9v113_init); -+module_exit(mt9v113_cleanup); -+ -+MODULE_AUTHOR("Texas Instruments"); -+MODULE_DESCRIPTION("MT9V113 linux decoder driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/video/mt9v113_regs.h b/drivers/media/video/mt9v113_regs.h -new file mode 100644 -index 0000000..64b065f ---- /dev/null -+++ b/drivers/media/video/mt9v113_regs.h -@@ -0,0 +1,294 @@ -+/* -+ * drivers/media/video/mt9v113_regs.h -+ * -+ * Copyright (C) 2008 Texas Instruments Inc -+ * Author: Vaibhav Hiremath -+ * -+ * Contributors: -+ * Sivaraj R -+ * Brijesh R Jadav -+ * Hardik Shah -+ * Manjunath Hadli -+ * Karicheri Muralidharan -+ * -+ * This package is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#ifndef _MT9V113_REGS_H -+#define _MT9V113_REGS_H -+ -+/* -+ * MT9V113 registers -+ */ -+#define REG_CHIP_ID (0x00) -+ -+/* -+ * MT9V113 registers -+ */ -+#define REG_INPUT_SEL (0x00) -+#define REG_AFE_GAIN_CTRL (0x01) -+#define REG_VIDEO_STD (0x02) -+#define REG_OPERATION_MODE (0x03) -+#define REG_AUTOSWITCH_MASK (0x04) -+ -+#define REG_COLOR_KILLER (0x05) -+#define REG_LUMA_CONTROL1 (0x06) -+#define REG_LUMA_CONTROL2 (0x07) -+#define REG_LUMA_CONTROL3 (0x08) -+ -+#define REG_BRIGHTNESS (0x09) -+#define REG_CONTRAST (0x0A) -+#define REG_SATURATION (0x0B) -+#define REG_HUE (0x0C) -+ -+#define REG_CHROMA_CONTROL1 (0x0D) -+#define REG_CHROMA_CONTROL2 (0x0E) -+ -+/* 0x0F Reserved */ -+ -+#define REG_COMP_PR_SATURATION (0x10) -+#define REG_COMP_Y_CONTRAST (0x11) -+#define REG_COMP_PB_SATURATION (0x12) -+ -+/* 0x13 Reserved */ -+ -+#define REG_COMP_Y_BRIGHTNESS (0x14) -+ -+/* 0x15 Reserved */ -+ -+#define REG_AVID_START_PIXEL_LSB (0x16) -+#define REG_AVID_START_PIXEL_MSB (0x17) -+#define REG_AVID_STOP_PIXEL_LSB (0x18) -+#define REG_AVID_STOP_PIXEL_MSB (0x19) -+ -+#define REG_HSYNC_START_PIXEL_LSB (0x1A) -+#define REG_HSYNC_START_PIXEL_MSB (0x1B) -+#define REG_HSYNC_STOP_PIXEL_LSB (0x1C) -+#define REG_HSYNC_STOP_PIXEL_MSB (0x1D) -+ -+#define REG_VSYNC_START_LINE_LSB (0x1E) -+#define REG_VSYNC_START_LINE_MSB (0x1F) -+#define REG_VSYNC_STOP_LINE_LSB (0x20) -+#define REG_VSYNC_STOP_LINE_MSB (0x21) -+ -+#define REG_VBLK_START_LINE_LSB (0x22) -+#define REG_VBLK_START_LINE_MSB (0x23) -+#define REG_VBLK_STOP_LINE_LSB (0x24) -+#define REG_VBLK_STOP_LINE_MSB (0x25) -+ -+/* 0x26 - 0x27 Reserved */ -+ -+#define REG_FAST_SWTICH_CONTROL (0x28) -+ -+/* 0x29 Reserved */ -+ -+#define REG_FAST_SWTICH_SCART_DELAY (0x2A) -+ -+/* 0x2B Reserved */ -+ -+#define REG_SCART_DELAY (0x2C) -+#define REG_CTI_DELAY (0x2D) -+#define REG_CTI_CONTROL (0x2E) -+ -+/* 0x2F - 0x31 Reserved */ -+ -+#define REG_SYNC_CONTROL (0x32) -+#define REG_OUTPUT_FORMATTER1 (0x33) -+#define REG_OUTPUT_FORMATTER2 (0x34) -+#define REG_OUTPUT_FORMATTER3 (0x35) -+#define REG_OUTPUT_FORMATTER4 (0x36) -+#define REG_OUTPUT_FORMATTER5 (0x37) -+#define REG_OUTPUT_FORMATTER6 (0x38) -+#define REG_CLEAR_LOST_LOCK (0x39) -+ -+#define REG_STATUS1 (0x3A) -+#define REG_STATUS2 (0x3B) -+ -+#define REG_AGC_GAIN_STATUS_LSB (0x3C) -+#define REG_AGC_GAIN_STATUS_MSB (0x3D) -+ -+/* 0x3E Reserved */ -+ -+#define REG_VIDEO_STD_STATUS (0x3F) -+#define REG_GPIO_INPUT1 (0x40) -+#define REG_GPIO_INPUT2 (0x41) -+ -+/* 0x42 - 0x45 Reserved */ -+ -+#define REG_AFE_COARSE_GAIN_CH1 (0x46) -+#define REG_AFE_COARSE_GAIN_CH2 (0x47) -+#define REG_AFE_COARSE_GAIN_CH3 (0x48) -+#define REG_AFE_COARSE_GAIN_CH4 (0x49) -+ -+#define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A) -+#define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B) -+#define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C) -+#define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D) -+#define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E) -+#define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F) -+#define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50) -+#define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51) -+ -+/* 0x52 - 0x68 Reserved */ -+ -+#define REG_FBIT_VBIT_CONTROL1 (0x69) -+ -+/* 0x6A - 0x6B Reserved */ -+ -+#define REG_BACKEND_AGC_CONTROL (0x6C) -+ -+/* 0x6D - 0x6E Reserved */ -+ -+#define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F) -+#define REG_ROM_VERSION (0x70) -+ -+/* 0x71 - 0x73 Reserved */ -+ -+#define REG_AGC_WHITE_PEAK_PROCESSING (0x74) -+#define REG_FBIT_VBIT_CONTROL2 (0x75) -+#define REG_VCR_TRICK_MODE_CONTROL (0x76) -+#define REG_HORIZONTAL_SHAKE_INCREMENT (0x77) -+#define REG_AGC_INCREMENT_SPEED (0x78) -+#define REG_AGC_INCREMENT_DELAY (0x79) -+ -+/* 0x7A - 0x7F Reserved */ -+ -+#define REG_CHIP_ID_MSB (0x80) -+#define REG_CHIP_ID_LSB (0x81) -+ -+/* 0x82 Reserved */ -+ -+#define REG_CPLL_SPEED_CONTROL (0x83) -+ -+/* 0x84 - 0x96 Reserved */ -+ -+#define REG_STATUS_REQUEST (0x97) -+ -+/* 0x98 - 0x99 Reserved */ -+ -+#define REG_VERTICAL_LINE_COUNT_LSB (0x9A) -+#define REG_VERTICAL_LINE_COUNT_MSB (0x9B) -+ -+/* 0x9C - 0x9D Reserved */ -+ -+#define REG_AGC_DECREMENT_DELAY (0x9E) -+ -+/* 0x9F - 0xB0 Reserved */ -+ -+#define REG_VDP_TTX_FILTER_1_MASK1 (0xB1) -+#define REG_VDP_TTX_FILTER_1_MASK2 (0xB2) -+#define REG_VDP_TTX_FILTER_1_MASK3 (0xB3) -+#define REG_VDP_TTX_FILTER_1_MASK4 (0xB4) -+#define REG_VDP_TTX_FILTER_1_MASK5 (0xB5) -+#define REG_VDP_TTX_FILTER_2_MASK1 (0xB6) -+#define REG_VDP_TTX_FILTER_2_MASK2 (0xB7) -+#define REG_VDP_TTX_FILTER_2_MASK3 (0xB8) -+#define REG_VDP_TTX_FILTER_2_MASK4 (0xB9) -+#define REG_VDP_TTX_FILTER_2_MASK5 (0xBA) -+#define REG_VDP_TTX_FILTER_CONTROL (0xBB) -+#define REG_VDP_FIFO_WORD_COUNT (0xBC) -+#define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD) -+ -+/* 0xBE Reserved */ -+ -+#define REG_VDP_FIFO_RESET (0xBF) -+#define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0) -+#define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1) -+#define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2) -+#define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3) -+ -+/* 0xC4 - 0xD5 Reserved */ -+ -+#define REG_VDP_LINE_START (0xD6) -+#define REG_VDP_LINE_STOP (0xD7) -+#define REG_VDP_GLOBAL_LINE_MODE (0xD8) -+#define REG_VDP_FULL_FIELD_ENABLE (0xD9) -+#define REG_VDP_FULL_FIELD_MODE (0xDA) -+ -+/* 0xDB - 0xDF Reserved */ -+ -+#define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0) -+#define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1) -+#define REG_FIFO_READ_DATA (0xE2) -+ -+/* 0xE3 - 0xE7 Reserved */ -+ -+#define REG_VBUS_ADDRESS_ACCESS1 (0xE8) -+#define REG_VBUS_ADDRESS_ACCESS2 (0xE9) -+#define REG_VBUS_ADDRESS_ACCESS3 (0xEA) -+ -+/* 0xEB - 0xEF Reserved */ -+ -+#define REG_INTERRUPT_RAW_STATUS0 (0xF0) -+#define REG_INTERRUPT_RAW_STATUS1 (0xF1) -+#define REG_INTERRUPT_STATUS0 (0xF2) -+#define REG_INTERRUPT_STATUS1 (0xF3) -+#define REG_INTERRUPT_MASK0 (0xF4) -+#define REG_INTERRUPT_MASK1 (0xF5) -+#define REG_INTERRUPT_CLEAR0 (0xF6) -+#define REG_INTERRUPT_CLEAR1 (0xF7) -+ -+/* 0xF8 - 0xFF Reserved */ -+ -+/* The ID values we are looking for */ -+#define MT9V113_CHIP_ID_MSB (0x51) -+ -+#define MT9V113_IMAGE_STD_VGA (0x01) -+#define MT9V113_IMAGE_STD_QVGA (0x02) -+#define MT9V113_IMAGE_STD_INVALID (0xFF) -+ -+/* -+ * Status bit -+ */ -+#define STATUS_TV_VCR_BIT (1<<0) -+#define STATUS_HORZ_SYNC_LOCK_BIT (1<<1) -+#define STATUS_VIRT_SYNC_LOCK_BIT (1<<2) -+#define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3) -+#define STATUS_LOST_LOCK_DETECT_BIT (1<<4) -+#define STATUS_FEILD_RATE_BIT (1<<5) -+#define STATUS_LINE_ALTERNATING_BIT (1<<6) -+#define STATUS_PEAK_WHITE_DETECT_BIT (1<<7) -+ -+/* Tokens for register write */ -+#define TOK_WRITE (0) /* token for write operation */ -+#define TOK_TERM (1) /* terminating token */ -+#define TOK_DELAY (2) /* delay token for reg list */ -+#define TOK_SKIP (3) /* token to skip a register */ -+/** -+ * struct mt9v113_reg - Structure for TVP5146/47 register initialization values -+ * @token - Token: TOK_WRITE, TOK_TERM etc.. -+ * @reg - Register offset -+ * @val - Register Value for TOK_WRITE or delay in ms for TOK_DELAY -+ */ -+struct mt9v113_reg { -+ unsigned short token; -+ unsigned short reg; -+ unsigned short val; -+}; -+ -+/** -+ * struct mt9v113_init_seq - Structure for TVP5146/47/46M2/47M1 power up -+ * Sequence. -+ * @ no_regs - Number of registers to write for power up sequence. -+ * @ init_reg_seq - Array of registers and respective value to write. -+ */ -+struct mt9v113_init_seq { -+ unsigned int no_regs; -+ const struct mt9v113_reg *init_reg_seq; -+}; -+ -+#define MT9V113_CHIP_ID (0x2280) -+ -+#endif /* ifndef _MT9V113_REGS_H */ -diff --git a/include/media/mt9v113.h b/include/media/mt9v113.h -new file mode 100644 -index 0000000..c7ad362 ---- /dev/null -+++ b/include/media/mt9v113.h -@@ -0,0 +1,83 @@ -+/* -+ * drivers/media/video/mt9v113.h -+ * -+ * Copyright (C) 2008 Texas Instruments Inc -+ * Author: Vaibhav Hiremath -+ * -+ * Contributors: -+ * Sivaraj R -+ * Brijesh R Jadav -+ * Hardik Shah -+ * Manjunath Hadli -+ * Karicheri Muralidharan -+ * -+ * This package is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#ifndef _MT9V113_H -+#define _MT9V113_H -+ -+/* -+ * Other macros -+ */ -+#define MT9V113_MODULE_NAME "mt9v113" -+ -+/* Number of pixels and number of lines per frame for different standards */ -+#define VGA_NUM_ACTIVE_PIXELS (640*2) -+#define VGA_NUM_ACTIVE_LINES (480) -+#define QVGA_NUM_ACTIVE_PIXELS (320*2) -+#define QVGA_NUM_ACTIVE_LINES (240) -+ -+/** -+ * struct mt9v113_platform_data - Platform data values and access functions. -+ * @power_set: Power state access function, zero is off, non-zero is on. -+ * @ifparm: Interface parameters access function. -+ * @priv_data_set: Device private data (pointer) access function. -+ * @clk_polarity: Clock polarity of the current interface. -+ * @ hs_polarity: HSYNC Polarity configuration for current interface. -+ * @ vs_polarity: VSYNC Polarity configuration for current interface. -+ */ -+struct mt9v113_platform_data { -+ char *master; -+ int (*power_set) (struct v4l2_int_device *s, enum v4l2_power on); -+ int (*ifparm) (struct v4l2_ifparm *p); -+ int (*priv_data_set) (void *); -+ /* Interface control params */ -+ bool clk_polarity; -+ bool hs_polarity; -+ bool vs_polarity; -+}; -+ -+// new -+ -+/*i2c adress for MT9V113*/ -+#define MT9V113_I2C_ADDR (0x78 >>1) -+ -+#define I2C_ONE_BYTE_TRANSFER (1) -+#define I2C_TWO_BYTE_TRANSFER (2) -+#define I2C_THREE_BYTE_TRANSFER (3) -+#define I2C_FOUR_BYTE_TRANSFER (4) -+#define I2C_TXRX_DATA_MASK (0x00FF) -+#define I2C_TXRX_DATA_MASK_UPPER (0xFF00) -+#define I2C_TXRX_DATA_SHIFT (8) -+ -+#define MT9V113_VGA_30FPS (1130) -+#define MT9V113_QVGA_30FPS (1131) -+ -+#define MT9V113_CLK_MAX (54000000) /* 54MHz */ -+#define MT9V113_CLK_MIN (6000000) /* 6Mhz */ -+ -+#endif /* ifndef _MT9V113_H */ -+ -diff --git a/include/media/v4l2-int-device.h b/include/media/v4l2-int-device.h -index ce415ec..7827575 100644 ---- a/include/media/v4l2-int-device.h -+++ b/include/media/v4l2-int-device.h -@@ -115,6 +115,7 @@ enum v4l2_if_type { - V4L2_IF_TYPE_BT656, - V4L2_IF_TYPE_YCbCr, - V4L2_IF_TYPE_RAW, -+ V4L2_IF_TYPE_PARALLEL, - }; - - enum v4l2_if_type_bt656_mode { -@@ -215,12 +216,38 @@ struct v4l2_if_type_raw { - u32 clock_curr; - }; - -+struct v4l2_if_type_parallel { -+ /* -+ * 0: Frame begins when vsync is high. -+ * 1: Frame begins when vsync changes from low to high. -+ */ -+ unsigned frame_start_on_rising_vs:1; -+ /* Swap every two adjacent image data elements. */ -+ unsigned swap:1; -+ /* Inverted latch clock polarity from slave. */ -+ unsigned latch_clk_inv:1; -+ /* Hs polarity. 0 is active high, 1 active low. */ -+ unsigned no_hs_inv:1; -+ /* Vs polarity. 0 is active high, 1 active low. */ -+ unsigned no_vs_inv:1; -+ /* Minimum accepted bus clock for slave (in Hz). */ -+ u32 clock_min; -+ /* Maximum accepted bus clock for slave. */ -+ u32 clock_max; -+ /* -+ * Current wish of the slave. May only change in response to -+ * ioctls that affect image capture. -+ */ -+ u32 clock_curr; -+}; -+ - struct v4l2_ifparm { - enum v4l2_if_type if_type; - union { - struct v4l2_if_type_bt656 bt656; - struct v4l2_if_type_ycbcr ycbcr; - struct v4l2_if_type_raw raw; -+ struct v4l2_if_type_parallel parallel; - } u; - }; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0032-MT9V113-Fixed-sensor-nitialization-issues.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0032-MT9V113-Fixed-sensor-nitialization-issues.patch deleted file mode 100644 index 72d9aa66..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0032-MT9V113-Fixed-sensor-nitialization-issues.patch +++ /dev/null @@ -1,294 +0,0 @@ -From d35c02203462b5c94c7be1abeba9be2a175646fe Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Fri, 9 Jul 2010 17:38:09 +0530 -Subject: [PATCH 32/75] MT9V113: Fixed sensor nitialization issues - -With this patch sensor is now able to generate HS, VS and pixel clock, also -CCDC is able to generate HS/VS, VD0, VD1 interrupts. - -There are some issues with Buffer processing in ISR routine because of which -DQBUF still hangs. ---- - drivers/media/video/mt9v113.c | 155 ++++++++++++++++++++---------------- - drivers/media/video/omap34xxcam.c | 2 +- - 2 files changed, 87 insertions(+), 70 deletions(-) - -diff --git a/drivers/media/video/mt9v113.c b/drivers/media/video/mt9v113.c -index 755a88a..8f8ba35 100644 ---- a/drivers/media/video/mt9v113.c -+++ b/drivers/media/video/mt9v113.c -@@ -389,8 +389,8 @@ static int mt9v113_read_reg(struct i2c_client *client, unsigned short reg) - err = -ENODEV; - return err; - }else { -- // TODO: addr should be set up where else -- msg->addr = MT9V113_I2C_ADDR;//client->addr; -+ /* TODO: addr should be set up where else client->addr */ -+ msg->addr = MT9V113_I2C_ADDR; - msg->flags = 0; - msg->len = I2C_TWO_BYTE_TRANSFER; - msg->buf = data; -@@ -432,8 +432,8 @@ static int mt9v113_write_reg(struct i2c_client *client, unsigned short reg, unsi - if (!client->adapter) { - err = -ENODEV; - } else { -- // TODO: addr should be set up where else -- msg->addr = MT9V113_I2C_ADDR;//client->addr; -+ /* TODO:addr should be set up where else client->addr */ -+ msg->addr = MT9V113_I2C_ADDR; - msg->flags = 0; - msg->len = I2C_FOUR_BYTE_TRANSFER; - msg->buf = data; -@@ -446,51 +446,11 @@ static int mt9v113_write_reg(struct i2c_client *client, unsigned short reg, unsi - err = i2c_transfer(client->adapter, msg, 1); - } - } -- if (err < 0) { -+ if (err < 0) - printk(KERN_INFO "\n I2C write failed"); -- } -- return err; --} -- --/* configure mux, for DM355 EVM only */ --#ifndef CONFIG_MACH_DM355_LEOPARD --static int mt9v113_en_mux(struct i2c_client *client) --{ -- int err = 0; -- int trycnt = 0; -- /* unsigned short readval = 0;*/ -- -- struct i2c_msg msg[1]; -- unsigned char data[4]; -- err = -1; -- printk(KERN_INFO -- "\n entering mt9v113_en_mux \n"); -- -- while ((err < 0) && (trycnt < 5)) { -- trycnt++; -- if (!client->adapter) { -- err = -ENODEV; -- } else { -- msg->addr = 0x25; -- msg->flags = 0; -- msg->len = I2C_TWO_BYTE_TRANSFER; -- msg->buf = data; -- data[0] = (unsigned char)(0x08 & I2C_TXRX_DATA_MASK); -- data[1] = (unsigned char)(0x80 & I2C_TXRX_DATA_MASK); - -- err = i2c_transfer(client->adapter, msg, 1); -- if (err < 0) { -- printk(KERN_INFO -- "\n ERROR in ECP register write\n"); -- } -- } -- } -- if (err < 0) { -- printk(KERN_INFO "\n I2C write failed"); -- } - return err; - } --#endif - - /* - * mt9v113_write_regs : Initializes a list of registers -@@ -550,9 +510,10 @@ static int mt9v113_configure(struct mt9v113_decoder *decoder) - if (err) - return err; - --// if (debug) --// mt9v113_reg_dump(decoder); -- -+#if 0 -+ if (debug) -+ mt9v113_reg_dump(decoder); -+#endif - return 0; - } - -@@ -573,6 +534,62 @@ static int mt9v113_vga_mode(struct mt9v113_decoder *decoder) - } - - -+/** -+ * ioctl_enum_framesizes - V4L2 sensor if handler for vidioc_int_enum_framesizes -+ * @s: pointer to standard V4L2 device structure -+ * @frms: pointer to standard V4L2 framesizes enumeration structure -+ * -+ * Returns possible framesizes depending on choosen pixel format -+ **/ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *frms) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int ifmt; -+ -+ for (ifmt = 0; ifmt < decoder->num_fmts; ifmt++) { -+ if (frms->pixel_format == decoder->fmt_list[ifmt].pixelformat) -+ break; -+ } -+ /* Is requested pixelformat not found on sensor? */ -+ if (ifmt == decoder->num_fmts) -+ return -EINVAL; -+ -+ /* Do we already reached all discrete framesizes? */ -+ if (frms->index >= decoder->num_stds) -+ return -EINVAL; -+ -+ frms->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frms->discrete.width = decoder->std_list[frms->index].width; -+ frms->discrete.height = decoder->std_list[frms->index].height; -+ -+ return 0; -+ -+} -+ -+static int ioctl_enum_frameintervals(struct v4l2_int_device *s, -+ struct v4l2_frmivalenum *frmi) -+{ -+ struct mt9v113_decoder *decoder = s->priv; -+ int ifmt; -+ -+ if (frmi->index >= 1) -+ return -EINVAL; -+ -+ for (ifmt = 0; ifmt < decoder->num_fmts; ifmt++) { -+ if (frmi->pixel_format == decoder->fmt_list[ifmt].pixelformat) -+ break; -+ } -+ /* Is requested pixelformat not found on sensor? */ -+ if (ifmt == decoder->num_fmts) -+ return -EINVAL; -+ -+ frmi->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frmi->discrete.numerator = 1; -+ frmi->discrete.denominator = 10; -+ return 0; -+} -+ - /* - * Detect if an mt9v113 is present, and if so which revision. - * A device is considered to be detected if the chip ID (LSB and MSB) -@@ -585,15 +602,9 @@ static int mt9v113_detect(struct mt9v113_decoder *decoder) - { - unsigned short val=0; - --#ifndef CONFIG_MACH_DM355_LEOPARD --// mt9v113_en_mux(decoder->client); --#endif -- - val = mt9v113_read_reg(decoder->client, REG_CHIP_ID); - -- v4l_dbg(1, debug, decoder->client, -- "chip id detected 0x%x\n", -- val); -+ v4l_dbg(1, debug, decoder->client, "chip id detected 0x%x\n", val); - - if (MT9V113_CHIP_ID != val) { - /* We didn't read the values we expected, so this must not be -@@ -1042,7 +1053,7 @@ ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) - if (rval) - return rval; - -- decoder->pix = *pix; -+ decoder->pix = *pix; - - return rval; - } -@@ -1177,7 +1188,7 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) - return rval; - } - -- p->u.bt656.clock_curr = 27000000; // TODO: read clock rate from sensor -+ p->u.bt656.clock_curr = 27000000; /* TODO:read clock rate from sensor */ - - return 0; - } -@@ -1211,12 +1222,17 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - struct mt9v113_decoder *decoder = s->priv; - int err = 0; - -+ if (decoder->state == STATE_DETECTED) -+ return 0; -+ - switch (on) { - case V4L2_POWER_OFF: - /* Power Down Sequence */ -- err = -- mt9v113_write_reg(decoder->client, REG_OPERATION_MODE, -- 0x01); -+/* TODO: FIXME: implement proper OFF and Standby code here */ -+#if 0 -+ err = mt9v113_write_reg(decoder->client, REG_OPERATION_MODE, -+ 0x01); -+#endif - /* Disable mux for mt9v113 data path */ - if (decoder->pdata->power_set) - err |= decoder->pdata->power_set(s, on); -@@ -1242,9 +1258,10 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - "Unable to detect decoder\n"); - return err; - } -+ /* Only VGA mode for now */ -+ err |= mt9v113_configure(decoder); -+ err |= mt9v113_vga_mode(decoder); - } -- // Only VGA mode for now -- err |= mt9v113_vga_mode(decoder); - break; - - default: -@@ -1263,14 +1280,11 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - */ - static int ioctl_init(struct v4l2_int_device *s) - { --// struct mt9v113_decoder *decoder = s->priv; -+ struct mt9v113_decoder *decoder = s->priv; - int err = 0; - -- /* Set default standard to auto */ -- //mt9v113_reg_list[REG_VIDEO_STD].val = -- // VIDEO_STD_AUTO_SWITCH_BIT; --// err |= mt9v113_configure(decoder); --// err |= mt9v113_vga_mode(decoder); -+ err |= mt9v113_configure(decoder); -+ err |= mt9v113_vga_mode(decoder); - - return err; - } -@@ -1298,7 +1312,6 @@ static int ioctl_dev_init(struct v4l2_int_device *s) - struct mt9v113_decoder *decoder = s->priv; - int err; - -- printk("%s: %d\n", __func__, __LINE__); - err = mt9v113_detect(decoder); - if (err < 0) { - v4l_err(decoder->client, -@@ -1340,6 +1353,10 @@ static struct v4l2_int_ioctl_desc mt9v113_ioctl_desc[] = { - {vidioc_int_s_std_num, (v4l2_int_ioctl_func *) ioctl_s_std}, - {vidioc_int_s_video_routing_num, - (v4l2_int_ioctl_func *) ioctl_s_routing}, -+ {vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_framesizes}, -+ {vidioc_int_enum_frameintervals_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals}, - }; - - static struct v4l2_int_slave mt9v113_slave = { -diff --git a/drivers/media/video/omap34xxcam.c b/drivers/media/video/omap34xxcam.c -index 6301ed3..2e8153b 100644 ---- a/drivers/media/video/omap34xxcam.c -+++ b/drivers/media/video/omap34xxcam.c -@@ -1852,8 +1852,8 @@ static int omap34xxcam_open(struct file *file) - vdev->slave_config[OMAP34XXCAM_SLAVE_SENSOR] - .cur_input = route.input; - } -- sensor_format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - } -+ sensor_format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - - /* Get the format the sensor is using. */ - rval = vidioc_int_g_fmt_cap(vdev->vdev_sensor, &sensor_format); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0033-mt9v113-Fix-wrong-active-widths.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0033-mt9v113-Fix-wrong-active-widths.patch deleted file mode 100644 index 06eec34e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0033-mt9v113-Fix-wrong-active-widths.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 54295e317df7f12a7b9e4f5a55f4801717863bb1 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 9 Jul 2010 16:22:38 -0500 -Subject: [PATCH 33/75] mt9v113: Fix wrong active widths - -Signed-off-by: Sergio Aguirre ---- - include/media/mt9v113.h | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/media/mt9v113.h b/include/media/mt9v113.h -index c7ad362..0a30f4c 100644 ---- a/include/media/mt9v113.h -+++ b/include/media/mt9v113.h -@@ -35,9 +35,9 @@ - #define MT9V113_MODULE_NAME "mt9v113" - - /* Number of pixels and number of lines per frame for different standards */ --#define VGA_NUM_ACTIVE_PIXELS (640*2) -+#define VGA_NUM_ACTIVE_PIXELS (640) - #define VGA_NUM_ACTIVE_LINES (480) --#define QVGA_NUM_ACTIVE_PIXELS (320*2) -+#define QVGA_NUM_ACTIVE_PIXELS (320) - #define QVGA_NUM_ACTIVE_LINES (240) - - /** --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0034-omap3isp-Fix-Wrong-check-on-non-interlaced-sensor-on.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0034-omap3isp-Fix-Wrong-check-on-non-interlaced-sensor-on.patch deleted file mode 100644 index 6bf18244..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0034-omap3isp-Fix-Wrong-check-on-non-interlaced-sensor-on.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0cd100387c233429ce2b9c8ceb7a36e900785fce Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 9 Jul 2010 16:56:18 -0500 -Subject: [PATCH 34/75] omap3isp: Fix Wrong check on non-interlaced sensor on isr - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/isp/isp.c | 9 +++++---- - 1 files changed, 5 insertions(+), 4 deletions(-) - -diff --git a/drivers/media/video/isp/isp.c b/drivers/media/video/isp/isp.c -index 29dd005..2ef2d58 100644 ---- a/drivers/media/video/isp/isp.c -+++ b/drivers/media/video/isp/isp.c -@@ -978,11 +978,12 @@ static irqreturn_t omap34xx_isp_isr(int irq, void *_pdev) - } - - if (irqstatus & CCDC_VD0) { -- if (isp->pipeline.pix.field == V4L2_FIELD_INTERLACED) { -+ if (((isp->pipeline.pix.field == V4L2_FIELD_INTERLACED) && -+ (isp->current_field != 0)) || -+ (isp->pipeline.pix.field != V4L2_FIELD_INTERLACED)) { - /* Skip even fields, and process only odd fields */ -- if (isp->current_field != 0) -- if (RAW_CAPTURE(isp)) -- isp_buf_process(dev, bufs); -+ if (RAW_CAPTURE(isp)) -+ isp_buf_process(dev, bufs); - } - if (!ispccdc_busy(&isp->isp_ccdc)) - ispccdc_config_shadow_registers(&isp->isp_ccdc); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0035-omap3isp-Fix-bad-YUV_BT-checks-in-datapath_config.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0035-omap3isp-Fix-bad-YUV_BT-checks-in-datapath_config.patch deleted file mode 100644 index e0be1a82..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0035-omap3isp-Fix-bad-YUV_BT-checks-in-datapath_config.patch +++ /dev/null @@ -1,45 +0,0 @@ -From d9c512d63c23d8f60e897357263bef4668660b13 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Sat, 10 Jul 2010 09:51:16 -0500 -Subject: [PATCH 35/75] omap3isp: Fix bad YUV_BT checks in datapath_config - -The use of an external write enable signals (from ISP point of -view) shouldn't depend on the sensor parallel interface type. - -Also, the bit shift selection should NOT be other than 9_0 by -default (i.e. No shift). - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/isp/ispccdc.c | 15 +++++---------- - 1 files changed, 5 insertions(+), 10 deletions(-) - -diff --git a/drivers/media/video/isp/ispccdc.c b/drivers/media/video/isp/ispccdc.c -index 137a5e6..ea6d87c 100644 ---- a/drivers/media/video/isp/ispccdc.c -+++ b/drivers/media/video/isp/ispccdc.c -@@ -602,16 +602,11 @@ static int ispccdc_config_datapath(struct isp_ccdc_device *isp_ccdc, - syn_mode &= ~ISPCCDC_SYN_MODE_VP2SDR; - syn_mode &= ~ISPCCDC_SYN_MODE_SDR2RSZ; - syn_mode |= ISPCCDC_SYN_MODE_WEN; -- if (pipe->ccdc_in == CCDC_YUV_BT) { -- syn_mode &= ~ISPCCDC_SYN_MODE_EXWEN; -- isp_reg_and(isp_ccdc->dev, OMAP3_ISP_IOMEM_CCDC, -- ISPCCDC_CFG, ~ISPCCDC_CFG_WENLOG); -- } else { -- syn_mode |= ISPCCDC_SYN_MODE_EXWEN; -- isp_reg_or(isp_ccdc->dev, OMAP3_ISP_IOMEM_CCDC, -- ISPCCDC_CFG, ISPCCDC_CFG_WENLOG); -- } -- vpcfg.bitshift_sel = BIT11_2; -+ syn_mode &= ~ISPCCDC_SYN_MODE_EXWEN; -+ -+ isp_reg_and(isp_ccdc->dev, OMAP3_ISP_IOMEM_CCDC, -+ ISPCCDC_CFG, ~ISPCCDC_CFG_WENLOG); -+ vpcfg.bitshift_sel = BIT9_0; - vpcfg.freq_sel = PIXCLKBY2; - ispccdc_config_vp(isp_ccdc, vpcfg); - ispccdc_enable_vp(isp_ccdc, 0); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0036-omap3isp-Set-vd_pol-to-0-by-default-on-all-cases.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0036-omap3isp-Set-vd_pol-to-0-by-default-on-all-cases.patch deleted file mode 100644 index f5ceb0d7..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0036-omap3isp-Set-vd_pol-to-0-by-default-on-all-cases.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5f87765bb16091048e67bc56f7ce1ab0694d9186 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Sat, 10 Jul 2010 09:57:40 -0500 -Subject: [PATCH 36/75] omap3isp: Set vd_pol to 0 by default on all cases - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/isp/ispccdc.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/video/isp/ispccdc.c b/drivers/media/video/isp/ispccdc.c -index ea6d87c..b4691c0 100644 ---- a/drivers/media/video/isp/ispccdc.c -+++ b/drivers/media/video/isp/ispccdc.c -@@ -671,7 +671,7 @@ static int ispccdc_config_datapath(struct isp_ccdc_device *isp_ccdc, - syncif.fldstat = 0; - syncif.hdpol = 0; - syncif.ipmod = YUV16; -- syncif.vdpol = 1; -+ syncif.vdpol = 0; - syncif.bt_r656_en = 0; - ispccdc_config_imgattr(isp_ccdc, 0); - ispccdc_config_sync_if(isp_ccdc, syncif); -@@ -688,7 +688,7 @@ static int ispccdc_config_datapath(struct isp_ccdc_device *isp_ccdc, - syncif.fldstat = 0; - syncif.hdpol = 0; - syncif.ipmod = YUV8; -- syncif.vdpol = 1; -+ syncif.vdpol = 0; - syncif.bt_r656_en = 1; - ispccdc_config_imgattr(isp_ccdc, 0); - ispccdc_config_sync_if(isp_ccdc, syncif); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0037-omap3isp-ccdc-Set-datalines-to-10-for-YUV_SYNC.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0037-omap3isp-ccdc-Set-datalines-to-10-for-YUV_SYNC.patch deleted file mode 100644 index 12e59601..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0037-omap3isp-ccdc-Set-datalines-to-10-for-YUV_SYNC.patch +++ /dev/null @@ -1,29 +0,0 @@ -From d9c257a16e4f4c5c6bff57cbe3b9673d3cf61bfa Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 12 Jul 2010 14:09:38 -0500 -Subject: [PATCH 37/75] omap3isp: ccdc: Set datalines to 10 for YUV_SYNC - -Most of the sensors we use are 10 bits, so set this as -default. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/isp/ispccdc.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/drivers/media/video/isp/ispccdc.c b/drivers/media/video/isp/ispccdc.c -index b4691c0..280a721 100644 ---- a/drivers/media/video/isp/ispccdc.c -+++ b/drivers/media/video/isp/ispccdc.c -@@ -664,7 +664,7 @@ static int ispccdc_config_datapath(struct isp_ccdc_device *isp_ccdc, - case CCDC_YUV_SYNC: - syncif.ccdc_mastermode = 0; - syncif.datapol = 0; -- syncif.datsz = DAT8; -+ syncif.datsz = DAT10; - syncif.fldmode = 0; - syncif.fldout = 0; - syncif.fldpol = 0; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0038-omap3beagle-camera-Fix-parallel-i-f-settings.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0038-omap3beagle-camera-Fix-parallel-i-f-settings.patch deleted file mode 100644 index a9589719..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0038-omap3beagle-camera-Fix-parallel-i-f-settings.patch +++ /dev/null @@ -1,43 +0,0 @@ -From cd05a2c5c623cc497f0d56b35b29d28a9206a3bd Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 12 Jul 2010 14:11:44 -0500 -Subject: [PATCH 38/75] omap3beagle: camera: Fix parallel i/f settings - -This makes the sensor input be shifted from 13:4 -> 9:0, as -in YUV streaming, the 8 least significant pins are used. - -Also, activate the 8 to 16 bit conversion bridge in ISP, in -big endian mode. - -This makes the ISP interpret the data correctly now. ;) - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 6c06265..0a591a1 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -64,7 +64,7 @@ static struct regulator *beagle_mt9v113_1_8v2; - - static struct isp_interface_config mt9v113_if_config = { - .ccdc_par_ser = ISP_PARLL, -- .dataline_shift = 0x0, -+ .dataline_shift = 0x2, - .hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE, - .strobe = 0x0, - .prestrobe = 0x0, -@@ -72,7 +72,7 @@ static struct isp_interface_config mt9v113_if_config = { - .cam_mclk = ISP_MT9V113_MCLK, - .wenlog = ISPCCDC_CFG_WENLOG_AND, - .wait_hs_vs = 2, -- .u.par.par_bridge = 0x1, -+ .u.par.par_bridge = 0x3, - .u.par.par_clk_pol = 0x0, - }; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0039-omap3beagle-camera-Clean-up-Remove-unneccessary-code.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0039-omap3beagle-camera-Clean-up-Remove-unneccessary-code.patch deleted file mode 100644 index 77b19fad..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0039-omap3beagle-camera-Clean-up-Remove-unneccessary-code.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 6466bc74ab74cafb6aec47040b3408fc2be3455b Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Tue, 13 Jul 2010 19:38:51 +0530 -Subject: [PATCH 39/75] omap3beagle-camera:Clean up: Remove unneccessary code/printf - -Signed-off-by: Vaibhav Hiremath ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 25 +++-------------------- - 1 files changed, 4 insertions(+), 21 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 0a591a1..be59040 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -77,7 +77,7 @@ static struct isp_interface_config mt9v113_if_config = { - }; - - static struct v4l2_ifparm mt9v113_ifparm_s = { --#if 1 -+#if 0 - .if_type = V4L2_IF_TYPE_RAW, - .u = { - .raw = { -@@ -192,32 +192,24 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - - /* turn on VDD */ - regulator_enable(beagle_mt9v113_1_8v1); -- - mdelay(1); -- - /* turn on VDD_IO */ - regulator_enable(beagle_mt9v113_1_8v2); -- - mdelay(50); - - /* Enable EXTCLK */ - isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN, CAM_USE_XCLKA); -- - /* - * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): - * ((1000000 * 70) / 6000000) = aprox 12 us. - */ -- - udelay(12); -- - /* Set RESET_BAR to 1 */ - gpio_set_value(LEOPARD_RESET_GPIO, 1); -- - /* - * Wait at least 100 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): - * ((1000000 * 100) / 6000000) = aprox 17 us. - */ -- - udelay(17); - - break; -@@ -245,15 +237,11 @@ struct mt9v113_platform_data mt9v113_pdata = { - - static int beagle_cam_probe(struct platform_device *pdev) - { -- int err; -- -- printk("%s:%d\n", __func__, __LINE__); - beagle_mt9v113_1_8v1 = regulator_get(&pdev->dev, "vaux3_1"); - if (IS_ERR(beagle_mt9v113_1_8v1)) { - dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); - return PTR_ERR(beagle_mt9v113_1_8v1); - } -- printk("%s:%d\n", __func__, __LINE__); - beagle_mt9v113_1_8v2 = regulator_get(&pdev->dev, "vaux4_1"); - if (IS_ERR(beagle_mt9v113_1_8v2)) { - dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); -@@ -261,7 +249,6 @@ static int beagle_cam_probe(struct platform_device *pdev) - return PTR_ERR(beagle_mt9v113_1_8v2); - } - -- printk("%s:%d\n", __func__, __LINE__); - if (gpio_request(LEOPARD_RESET_GPIO, "cam_rst") != 0) { - dev_err(&pdev->dev, "Could not request GPIO %d", - LEOPARD_RESET_GPIO); -@@ -270,7 +257,6 @@ static int beagle_cam_probe(struct platform_device *pdev) - return -ENODEV; - } - -- printk("%s:%d\n", __func__, __LINE__); - /* set to output mode, default value 0 */ - gpio_direction_output(LEOPARD_RESET_GPIO, 0); - -@@ -281,10 +267,10 @@ static int beagle_cam_probe(struct platform_device *pdev) - - static int beagle_cam_remove(struct platform_device *pdev) - { -- printk("%s:%d\n", __func__, __LINE__); - if (regulator_is_enabled(beagle_mt9v113_1_8v1)) - regulator_disable(beagle_mt9v113_1_8v1); - regulator_put(beagle_mt9v113_1_8v1); -+ - if (regulator_is_enabled(beagle_mt9v113_1_8v2)) - regulator_disable(beagle_mt9v113_1_8v2); - regulator_put(beagle_mt9v113_1_8v2); -@@ -360,12 +346,9 @@ static struct platform_driver beagle_cam_driver = { - */ - int __init omap3beaglelmb_init(void) - { -- printk("%s:%d\n", __func__, __LINE__); -- if (cpu_is_omap3630()) { -- printk("%s:%d\n", __func__, __LINE__); -+ if (cpu_is_omap3630()) - platform_driver_register(&beagle_cam_driver); -- } -- printk("%s:%d\n", __func__, __LINE__); -+ - return 0; - } - late_initcall(omap3beaglelmb_init); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0040-mt9v113-Clean-Up-Remove-unneccessary-code-printf.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0040-mt9v113-Clean-Up-Remove-unneccessary-code-printf.patch deleted file mode 100644 index 80121607..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0040-mt9v113-Clean-Up-Remove-unneccessary-code-printf.patch +++ /dev/null @@ -1,390 +0,0 @@ -From 9c9215eade28a09ac12888e9a02af107955009c5 Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Tue, 13 Jul 2010 19:39:34 +0530 -Subject: [PATCH 40/75] mt9v113:Clean Up: Remove unneccessary code/printf - -Signed-off-by: Vaibhav Hiremath ---- - drivers/media/video/mt9v113.c | 105 ++++++++++++++++------------------------ - 1 files changed, 42 insertions(+), 63 deletions(-) - -diff --git a/drivers/media/video/mt9v113.c b/drivers/media/video/mt9v113.c -index 8f8ba35..9a86cce 100644 ---- a/drivers/media/video/mt9v113.c -+++ b/drivers/media/video/mt9v113.c -@@ -22,10 +22,10 @@ - #include - #include - #include -+#include -+ - #include - #include --#include --#include - - #include "mt9v113_regs.h" - -@@ -34,21 +34,13 @@ - - /* Private macros for TVP */ - #define I2C_RETRY_COUNT (5) --#define LOCK_RETRY_COUNT (5) --#define LOCK_RETRY_DELAY (200) - - /* Debug functions */ - static int debug = 1; - module_param(debug, bool, 0644); - MODULE_PARM_DESC(debug, "Debug level (0-1)"); - --#define dump_reg(client, reg, val) \ -- do { \ -- val = mt9v113_read_reg(client, reg); \ -- v4l_info(client, "Reg(0x%.2X): 0x%.2X\n", reg, val); \ -- } while (0) -- --/** -+/* - * enum mt9v113_std - enum for supported standards - */ - enum mt9v113_std { -@@ -57,7 +49,7 @@ enum mt9v113_std { - MT9V113_STD_INVALID - }; - --/** -+/* - * enum mt9v113_state - enum for different decoder states - */ - enum mt9v113_state { -@@ -65,7 +57,7 @@ enum mt9v113_state { - STATE_DETECTED - }; - --/** -+/* - * struct mt9v113_std_info - Structure to store standard informations - * @width: Line width in pixels - * @height:Number of active lines -@@ -79,7 +71,7 @@ struct mt9v113_std_info { - struct v4l2_standard standard; - }; - --/** -+/* - * struct mt9v113_decoded - decoder object - * @v4l2_int_device: Slave handle - * @pdata: Board specific -@@ -93,7 +85,6 @@ struct mt9v113_std_info { - * @current_std: Current standard - * @num_stds: Number of standards - * @std_list: Standards list -- * @route: input and output routing at chip level - */ - struct mt9v113_decoder { - struct v4l2_int_device *v4l2_int_device; -@@ -112,8 +103,6 @@ struct mt9v113_decoder { - enum mt9v113_std current_std; - int num_stds; - struct mt9v113_std_info *std_list; -- -- struct v4l2_routing route; - }; - - /* MT9V113 register set for VGA mode */ -@@ -160,7 +149,7 @@ static struct mt9v113_reg mt9v113_reg_list[] = { - {TOK_WRITE, 0x0016, 0x42DF}, - {TOK_WRITE, 0x0014, 0x2145}, - {TOK_WRITE, 0x0014, 0x2145}, -- {TOK_WRITE, 0x0010, 0x0431}, -+ {TOK_WRITE, 0x0010, 0x0231}, - {TOK_WRITE, 0x0012, 0x0000}, - {TOK_WRITE, 0x0014, 0x244B}, - {TOK_WRITE, 0x0014, 0x304B}, -@@ -378,6 +367,10 @@ static const struct v4l2_queryctrl mt9v113_autogain_ctrl = { - .default_value = 1, - }; - -+const struct v4l2_fract mt9v113_frameintervals[] = { -+ { .numerator = 1, .denominator = 10 } -+}; -+ - static int mt9v113_read_reg(struct i2c_client *client, unsigned short reg) - { - int err = 0; -@@ -510,10 +503,6 @@ static int mt9v113_configure(struct mt9v113_decoder *decoder) - if (err) - return err; - --#if 0 -- if (debug) -- mt9v113_reg_dump(decoder); --#endif - return 0; - } - -@@ -534,13 +523,13 @@ static int mt9v113_vga_mode(struct mt9v113_decoder *decoder) - } - - --/** -+/* - * ioctl_enum_framesizes - V4L2 sensor if handler for vidioc_int_enum_framesizes - * @s: pointer to standard V4L2 device structure - * @frms: pointer to standard V4L2 framesizes enumeration structure - * - * Returns possible framesizes depending on choosen pixel format -- **/ -+ */ - static int ioctl_enum_framesizes(struct v4l2_int_device *s, - struct v4l2_frmsizeenum *frms) - { -@@ -584,9 +573,14 @@ static int ioctl_enum_frameintervals(struct v4l2_int_device *s, - if (ifmt == decoder->num_fmts) - return -EINVAL; - -+ if (frmi->index >= ARRAY_SIZE(mt9v113_frameintervals)) -+ return -EINVAL; -+ - frmi->type = V4L2_FRMSIZE_TYPE_DISCRETE; -- frmi->discrete.numerator = 1; -- frmi->discrete.denominator = 10; -+ frmi->discrete.numerator = -+ mt9v113_frameintervals[frmi->index].numerator; -+ frmi->discrete.denominator = -+ mt9v113_frameintervals[frmi->index].denominator; - return 0; - } - -@@ -631,7 +625,7 @@ static int mt9v113_detect(struct mt9v113_decoder *decoder) - * mt9v113 decoder driver. - */ - --/** -+/* - * ioctl_querystd - V4L2 decoder interface handler for VIDIOC_QUERYSTD ioctl - * @s: pointer to standard V4L2 device structure - * @std_id: standard V4L2 std_id ioctl enum -@@ -660,7 +654,7 @@ static int ioctl_querystd(struct v4l2_int_device *s, v4l2_std_id *std_id) - return 0; - } - --/** -+/* - * ioctl_s_std - V4L2 decoder interface handler for VIDIOC_S_STD ioctl - * @s: pointer to standard V4L2 device structure - * @std_id: standard V4L2 v4l2_std_id ioctl enum -@@ -696,7 +690,7 @@ static int ioctl_s_std(struct v4l2_int_device *s, v4l2_std_id *std_id) - return 0; - } - --/** -+/* - * ioctl_s_routing - V4L2 decoder interface handler for VIDIOC_S_INPUT ioctl - * @s: pointer to standard V4L2 device structure - * @index: number of the input -@@ -711,7 +705,7 @@ static int ioctl_s_routing(struct v4l2_int_device *s, - return 0; - } - --/** -+/* - * ioctl_queryctrl - V4L2 decoder interface handler for VIDIOC_QUERYCTRL ioctl - * @s: pointer to standard V4L2 device structure - * @qctrl: standard V4L2 v4l2_queryctrl structure -@@ -771,7 +765,7 @@ ioctl_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qctrl) - return err; - } - --/** -+/* - * ioctl_g_ctrl - V4L2 decoder interface handler for VIDIOC_G_CTRL ioctl - * @s: pointer to standard V4L2 device structure - * @ctrl: pointer to v4l2_control structure -@@ -828,7 +822,7 @@ ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) - return 0; - } - --/** -+/* - * ioctl_s_ctrl - V4L2 decoder interface handler for VIDIOC_S_CTRL ioctl - * @s: pointer to standard V4L2 device structure - * @ctrl: pointer to v4l2_control structure -@@ -936,7 +930,7 @@ ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *ctrl) - return err; - } - --/** -+/* - * ioctl_enum_fmt_cap - Implement the CAPTURE buffer VIDIOC_ENUM_FMT ioctl - * @s: pointer to standard V4L2 device structure - * @fmt: standard V4L2 VIDIOC_ENUM_FMT ioctl structure -@@ -969,7 +963,7 @@ ioctl_enum_fmt_cap(struct v4l2_int_device *s, struct v4l2_fmtdesc *fmt) - return 0; - } - --/** -+/* - * ioctl_try_fmt_cap - Implement the CAPTURE buffer VIDIOC_TRY_FMT ioctl - * @s: pointer to standard V4L2 device structure - * @f: pointer to standard V4L2 VIDIOC_TRY_FMT ioctl structure -@@ -1026,7 +1020,7 @@ ioctl_try_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) - return 0; - } - --/** -+/* - * ioctl_s_fmt_cap - V4L2 decoder interface handler for VIDIOC_S_FMT ioctl - * @s: pointer to standard V4L2 device structure - * @f: pointer to standard V4L2 VIDIOC_S_FMT ioctl structure -@@ -1058,7 +1052,7 @@ ioctl_s_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) - return rval; - } - --/** -+/* - * ioctl_g_fmt_cap - V4L2 decoder interface handler for ioctl_g_fmt_cap - * @s: pointer to standard V4L2 device structure - * @f: pointer to standard V4L2 v4l2_format structure -@@ -1087,7 +1081,7 @@ ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) - return 0; - } - --/** -+/* - * ioctl_g_parm - V4L2 decoder interface handler for VIDIOC_G_PARM ioctl - * @s: pointer to standard V4L2 device structure - * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -@@ -1125,7 +1119,7 @@ ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) - return 0; - } - --/** -+/* - * ioctl_s_parm - V4L2 decoder interface handler for VIDIOC_S_PARM ioctl - * @s: pointer to standard V4L2 device structure - * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -@@ -1161,7 +1155,7 @@ ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) - return 0; - } - --/** -+/* - * ioctl_g_ifparm - V4L2 decoder interface handler for vidioc_int_g_ifparm_num - * @s: pointer to standard V4L2 device structure - * @p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure -@@ -1193,7 +1187,7 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) - return 0; - } - --/** -+/* - * ioctl_g_priv - V4L2 decoder interface handler for vidioc_int_g_priv_num - * @s: pointer to standard V4L2 device structure - * @p: void pointer to hold decoder's private data address -@@ -1210,7 +1204,7 @@ static int ioctl_g_priv(struct v4l2_int_device *s, void *p) - return decoder->pdata->priv_data_set(p); - } - --/** -+/* - * ioctl_s_power - V4L2 decoder interface handler for vidioc_int_s_power_num - * @s: pointer to standard V4L2 device structure - * @on: power state to which device is to be set -@@ -1272,7 +1266,7 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - return err; - } - --/** -+/* - * ioctl_init - V4L2 decoder interface handler for VIDIOC_INT_INIT - * @s: pointer to standard V4L2 device structure - * -@@ -1289,7 +1283,7 @@ static int ioctl_init(struct v4l2_int_device *s) - return err; - } - --/** -+/* - * ioctl_dev_exit - V4L2 decoder interface handler for vidioc_int_dev_exit_num - * @s: pointer to standard V4L2 device structure - * -@@ -1300,7 +1294,7 @@ static int ioctl_dev_exit(struct v4l2_int_device *s) - return 0; - } - --/** -+/* - * ioctl_dev_init - V4L2 decoder interface handler for vidioc_int_dev_init_num - * @s: pointer to standard V4L2 device structure - * -@@ -1397,7 +1391,7 @@ static struct v4l2_int_device mt9v113_int_device = { - }, - }; - --/** -+/* - * mt9v113_probe - decoder driver i2c probe handler - * @client: i2c driver client device structure - * -@@ -1410,30 +1404,15 @@ mt9v113_probe(struct i2c_client *client, const struct i2c_device_id *id) - struct mt9v113_decoder *decoder = &mt9v113_dev; - int err; - -- printk("%s: %d\n", __func__, __LINE__); - /* Check if the adapter supports the needed features */ - if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) - return -EIO; - -- printk("%s: %d\n", __func__, __LINE__); - decoder->pdata = client->dev.platform_data; - if (!decoder->pdata) { - v4l_err(client, "No platform data!!\n"); - return -ENODEV; - } -- printk("%s: %d\n", __func__, __LINE__); -- /* -- * Fetch platform specific data, and configure the -- * mt9v113_reg_list[] accordingly. Since this is one -- * time configuration, no need to preserve. -- */ -- -- /*mt9v113_reg_list[REG_OUTPUT_FORMATTER2].val |= -- (decoder->pdata->clk_polarity << 1); -- mt9v113_reg_list[REG_SYNC_CONTROL].val |= -- ((decoder->pdata->hs_polarity << 2) | -- (decoder->pdata->vs_polarity << 3)); -- */ - /* - * Save the id data, required for power up sequence - */ -@@ -1458,7 +1437,7 @@ mt9v113_probe(struct i2c_client *client, const struct i2c_device_id *id) - return 0; - } - --/** -+/* - * mt9v113_remove - decoder driver i2c remove handler - * @client: i2c driver client device structure - * -@@ -1511,7 +1490,7 @@ static struct i2c_driver mt9v113_i2c_driver = { - .id_table = mt9v113_id, - }; - --/** -+/* - * mt9v113_init - * - * Module init function -@@ -1521,7 +1500,7 @@ static int __init mt9v113_init(void) - return i2c_add_driver(&mt9v113_i2c_driver); - } - --/** -+/* - * mt9v113_cleanup - * - * Module exit function --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0041-MT9V113-Min-Max-clk-input-changed-as-per-the-spec.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0041-MT9V113-Min-Max-clk-input-changed-as-per-the-spec.patch deleted file mode 100644 index bae51993..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0041-MT9V113-Min-Max-clk-input-changed-as-per-the-spec.patch +++ /dev/null @@ -1,54 +0,0 @@ -From f92ea92f012235a17c04021de470b65aeb7fbe29 Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Tue, 13 Jul 2010 19:40:39 +0530 -Subject: [PATCH 41/75] MT9V113: Min, Max clk input changed as per the spec - -Signed-off-by: Vaibhav Hiremath ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 2 +- - drivers/media/video/isp/ispreg.h | 2 +- - include/media/mt9v113.h | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index be59040..8d4e5ab 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -198,7 +198,7 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - mdelay(50); - - /* Enable EXTCLK */ -- isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN, CAM_USE_XCLKA); -+ isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN*2, CAM_USE_XCLKA); - /* - * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): - * ((1000000 * 70) / 6000000) = aprox 12 us. -diff --git a/drivers/media/video/isp/ispreg.h b/drivers/media/video/isp/ispreg.h -index 1240e0e..098713e 100644 ---- a/drivers/media/video/isp/ispreg.h -+++ b/drivers/media/video/isp/ispreg.h -@@ -116,7 +116,7 @@ - #define ISP_32B_BOUNDARY_BUF 0xFFFFFFE0 - #define ISP_32B_BOUNDARY_OFFSET 0x0000FFE0 - --#define CM_CAM_MCLK_HZ 172800000 /* Hz */ -+#define CM_CAM_MCLK_HZ 216000000 /* Hz */ - - /* ISP Submodules offset */ - -diff --git a/include/media/mt9v113.h b/include/media/mt9v113.h -index 0a30f4c..4504f26 100644 ---- a/include/media/mt9v113.h -+++ b/include/media/mt9v113.h -@@ -76,7 +76,7 @@ struct mt9v113_platform_data { - #define MT9V113_VGA_30FPS (1130) - #define MT9V113_QVGA_30FPS (1131) - --#define MT9V113_CLK_MAX (54000000) /* 54MHz */ -+#define MT9V113_CLK_MAX (48000000) /* 48MHz */ - #define MT9V113_CLK_MIN (6000000) /* 6Mhz */ - - #endif /* ifndef _MT9V113_H */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0042-omap3beagle-camera-Further-clode-cleanup.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0042-omap3beagle-camera-Further-clode-cleanup.patch deleted file mode 100644 index 8855e6d6..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0042-omap3beagle-camera-Further-clode-cleanup.patch +++ /dev/null @@ -1,237 +0,0 @@ -From 7f6cbc648dcf2d7805f12e7b56bb2c7b602ca61d Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Wed, 14 Jul 2010 19:07:06 +0530 -Subject: [PATCH 42/75] omap3beagle-camera: Further clode cleanup - -Signed-off-by: Vaibhav Hiremath ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 89 ++++-------------------- - drivers/media/video/isp/isp.h | 13 ++++ - 2 files changed, 28 insertions(+), 74 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 8d4e5ab..90eadd0 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -46,21 +46,19 @@ - #include "mux.h" - #include "board-omap3beagle-camera.h" - --#define MODULE_NAME "omap3beaglelmb" -+#define MODULE_NAME "omap3beaglelmb" - --#define CAM_USE_XCLKA 0 -+#define CAM_USE_XCLKA 0 - --#define ISP_MT9V113_MCLK 216000000 -+#define ISP_MT9V113_MCLK 216000000 - --#define LEOPARD_RESET_GPIO 98 -+#define LEOPARD_RESET_GPIO 98 - - static struct regulator *beagle_mt9v113_1_8v1; - static struct regulator *beagle_mt9v113_1_8v2; - --#if defined(CONFIG_VIDEO_MT9V113) || defined(CONFIG_VIDEO_MT9V113_MODULE) -- - /* Arbitrary memory handling limit */ --#define MT9V113_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN(2048 * 1536 * 4) -+#define MT9V113_MAX_FRAME_SIZE PAGE_ALIGN(640 * 480 * 4) - - static struct isp_interface_config mt9v113_if_config = { - .ccdc_par_ser = ISP_PARLL, -@@ -77,21 +75,6 @@ static struct isp_interface_config mt9v113_if_config = { - }; - - static struct v4l2_ifparm mt9v113_ifparm_s = { --#if 0 -- .if_type = V4L2_IF_TYPE_RAW, -- .u = { -- .raw = { -- .frame_start_on_rising_vs = 1, -- .bt_sync_correct = 0, -- .swap = 0, -- .latch_clk_inv = 0, -- .nobt_hs_inv = 0, /* active high */ -- .nobt_vs_inv = 0, /* active high */ -- .clock_min = MT9V113_CLK_MIN, -- .clock_max = MT9V113_CLK_MAX, -- }, -- }, --#else - .if_type = V4L2_IF_TYPE_YCbCr, - .u = { - .ycbcr = { -@@ -99,13 +82,12 @@ static struct v4l2_ifparm mt9v113_ifparm_s = { - .bt_sync_correct = 0, - .swap = 0, - .latch_clk_inv = 0, -- .nobt_hs_inv = 0, /* active high */ -- .nobt_vs_inv = 0, /* active high */ -+ .nobt_hs_inv = 0, -+ .nobt_vs_inv = 0, - .clock_min = MT9V113_CLK_MIN, - .clock_max = MT9V113_CLK_MAX, - }, - }, --#endif - }; - - /** -@@ -124,16 +106,14 @@ static int mt9v113_ifparm(struct v4l2_ifparm *p) - return 0; - } - --#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - static struct omap34xxcam_hw_config mt9v113_hwc = { - .dev_index = 0, - .dev_minor = 0, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 1, -- .u.sensor.capture_mem = MT9V113_BIGGEST_FRAME_BYTE_SIZE * 2, -+ .u.sensor.capture_mem = MT9V113_MAX_FRAME_SIZE * 2, - .u.sensor.ival_default = { 1, 10 }, - }; --#endif - - /** - * @brief mt9v113_set_prv_data - Returns mt9v113 omap34xx driver private data -@@ -144,7 +124,6 @@ static struct omap34xxcam_hw_config mt9v113_hwc = { - */ - static int mt9v113_set_prv_data(void *priv) - { --#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - struct omap34xxcam_hw_config *hwc = priv; - - if (priv == NULL) -@@ -154,10 +133,8 @@ static int mt9v113_set_prv_data(void *priv) - hwc->dev_index = mt9v113_hwc.dev_index; - hwc->dev_minor = mt9v113_hwc.dev_minor; - hwc->dev_type = mt9v113_hwc.dev_type; -+ - return 0; --#else -- return -EINVAL; --#endif - } - - /** -@@ -172,21 +149,22 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; - - switch (power) { -- case V4L2_POWER_OFF: - case V4L2_POWER_STANDBY: -+ break; -+ -+ case V4L2_POWER_OFF: - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - - if (regulator_is_enabled(beagle_mt9v113_1_8v1)) - regulator_disable(beagle_mt9v113_1_8v1); - if (regulator_is_enabled(beagle_mt9v113_1_8v2)) - regulator_disable(beagle_mt9v113_1_8v2); -+ - break; - - case V4L2_POWER_ON: --#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -- isp_configure_interface(vdev->cam->isp, &mt9v113_if_config); --#endif - -+ isp_configure_interface(vdev->cam->isp, &mt9v113_if_config); - /* Set RESET_BAR to 0 */ - gpio_set_value(LEOPARD_RESET_GPIO, 0); - -@@ -216,8 +194,8 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - - default: - return -ENODEV; -- break; - } -+ - return 0; - } - -@@ -232,9 +210,6 @@ struct mt9v113_platform_data mt9v113_pdata = { - .vs_polarity = 1, /* 0 - Active low, 1- Active high */ - }; - --#endif /* #ifdef CONFIG_VIDEO_MT9V113 */ -- -- - static int beagle_cam_probe(struct platform_device *pdev) - { - beagle_mt9v113_1_8v1 = regulator_get(&pdev->dev, "vaux3_1"); -@@ -277,40 +252,6 @@ static int beagle_cam_remove(struct platform_device *pdev) - - gpio_free(LEOPARD_RESET_GPIO); - -- /* MUX init */ -- omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -- 0x10C); /* CAM_HS */ -- omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -- 0x10E); /* CAM_VS */ -- omap_ctrl_writew(OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, -- 0x110); /* CAM_XCLKA */ -- omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -- 0x112); /* CAM_PCLK */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x116); /* CAM_D0 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x118); /* CAM_D1 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x11A); /* CAM_D2 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x11C); /* CAM_D3 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x11E); /* CAM_D4 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x120); /* CAM_D5 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x122); /* CAM_D6 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x124); /* CAM_D7 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x126); /* CAM_D8 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x128); /* CAM_D9 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x12A); /* CAM_D10 */ -- omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -- 0x12C); /* CAM_D11 */ -- - return 0; - } - -diff --git a/drivers/media/video/isp/isp.h b/drivers/media/video/isp/isp.h -index 85c3fa9..4929fad 100644 ---- a/drivers/media/video/isp/isp.h -+++ b/drivers/media/video/isp/isp.h -@@ -482,10 +482,23 @@ int isp_set_callback(struct device *dev, enum isp_callback_type type, - - int isp_unset_callback(struct device *dev, enum isp_callback_type type); - -+#if defined(CONFIG_VIDEO_OMAP3_ISP) - u32 isp_set_xclk(struct device *dev, u32 xclk, u8 xclksel); - - int isp_configure_interface(struct device *dev, - struct isp_interface_config *config); -+#else -+static inline u32 isp_set_xclk(struct device *dev, u32 xclk, u8 xclksel) -+{ -+ return 0; -+} -+static inline int isp_configure_interface(struct device *dev, -+ struct isp_interface_config *config) -+{ -+ return 0; -+} -+ -+#endif - - struct device *isp_get(void); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0043-mt9v113-Settings-from-Aptima-used-to-increase-FPS.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0043-mt9v113-Settings-from-Aptima-used-to-increase-FPS.patch deleted file mode 100644 index af7e4d08..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0043-mt9v113-Settings-from-Aptima-used-to-increase-FPS.patch +++ /dev/null @@ -1,135 +0,0 @@ -From b13a4b53a958c182adf61af6b1ea35826fe97de5 Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Wed, 14 Jul 2010 19:07:34 +0530 -Subject: [PATCH 43/75] mt9v113: Settings from Aptima used to increase FPS - -The FPS is still low at around ~15FPS, expected one is 30FPS. - -Signed-off-by: Vaibhav Hiremath ---- - drivers/media/video/mt9v113.c | 55 +++++++++++++++++++++++++--------------- - 1 files changed, 34 insertions(+), 21 deletions(-) - -diff --git a/drivers/media/video/mt9v113.c b/drivers/media/video/mt9v113.c -index 9a86cce..466702e 100644 ---- a/drivers/media/video/mt9v113.c -+++ b/drivers/media/video/mt9v113.c -@@ -119,6 +119,21 @@ static struct mt9v113_reg mt9v113_vga_reg[] = { - {TOK_WRITE, 0x0990, 0x0280}, - {TOK_WRITE, 0x098C, 0x2705}, - {TOK_WRITE, 0x0990, 0x01E0}, -+ {TOK_WRITE, 0x098C, 0x2715}, -+ {TOK_WRITE, 0x0990, 0x0001}, -+ {TOK_WRITE, 0x098C, 0x2717}, -+ {TOK_WRITE, 0x0990, 0x0026}, -+ {TOK_WRITE, 0x098C, 0x2719}, -+ {TOK_WRITE, 0x0990, 0x001A}, -+ {TOK_WRITE, 0x098C, 0x271B}, -+ {TOK_WRITE, 0x0990, 0x006B}, -+ {TOK_WRITE, 0x098C, 0x271D}, -+ {TOK_WRITE, 0x0990, 0x006B}, -+ {TOK_WRITE, 0x098C, 0x271F}, -+ {TOK_WRITE, 0x0990, 0x0202}, -+ {TOK_WRITE, 0x098C, 0x2721}, -+ {TOK_WRITE, 0x0990, 0x034A}, -+ - {TOK_WRITE, 0x098C, 0xA103}, - {TOK_WRITE, 0x0990, 0x0005}, - {TOK_DELAY, 0, 100}, -@@ -148,8 +163,7 @@ static struct mt9v113_reg mt9v113_reg_list[] = { - {TOK_WRITE, 0x001E, 0x0777}, - {TOK_WRITE, 0x0016, 0x42DF}, - {TOK_WRITE, 0x0014, 0x2145}, -- {TOK_WRITE, 0x0014, 0x2145}, -- {TOK_WRITE, 0x0010, 0x0231}, -+ {TOK_WRITE, 0x0010, 0x0234}, - {TOK_WRITE, 0x0012, 0x0000}, - {TOK_WRITE, 0x0014, 0x244B}, - {TOK_WRITE, 0x0014, 0x304B}, -@@ -267,29 +281,31 @@ static struct mt9v113_reg mt9v113_reg_list[] = { - {TOK_WRITE, 0x0990, 0x0005}, - {TOK_DELAY, 0, 100}, - {TOK_WRITE, 0x098C, 0x222D}, -- {TOK_WRITE, 0x0990, 0x0088}, -+ {TOK_WRITE, 0x0990, 0x0081}, - {TOK_WRITE, 0x098C, 0xA408}, -- {TOK_WRITE, 0x0990, 0x0020}, -+ {TOK_WRITE, 0x0990, 0x001F}, - {TOK_WRITE, 0x098C, 0xA409}, -- {TOK_WRITE, 0x0990, 0x0023}, -+ {TOK_WRITE, 0x0990, 0x0021}, - {TOK_WRITE, 0x098C, 0xA40A}, -- {TOK_WRITE, 0x0990, 0x0027}, -+ {TOK_WRITE, 0x0990, 0x0025}, - {TOK_WRITE, 0x098C, 0xA40B}, -- {TOK_WRITE, 0x0990, 0x002A}, -+ {TOK_WRITE, 0x0990, 0x0027}, - {TOK_WRITE, 0x098C, 0x2411}, -- {TOK_WRITE, 0x0990, 0x0088}, -+ {TOK_WRITE, 0x0990, 0x0081}, - {TOK_WRITE, 0x098C, 0x2413}, -- {TOK_WRITE, 0x0990, 0x00A4}, -+ {TOK_WRITE, 0x0990, 0x009A}, - {TOK_WRITE, 0x098C, 0x2415}, -- {TOK_WRITE, 0x0990, 0x0088}, -+ {TOK_WRITE, 0x0990, 0x0081}, - {TOK_WRITE, 0x098C, 0x2417}, -- {TOK_WRITE, 0x0990, 0x00A4}, -+ {TOK_WRITE, 0x0990, 0x009A}, - {TOK_WRITE, 0x098C, 0xA404}, - {TOK_WRITE, 0x0990, 0x0010}, - {TOK_WRITE, 0x098C, 0xA40D}, - {TOK_WRITE, 0x0990, 0x0002}, - {TOK_WRITE, 0x098C, 0xA40E}, - {TOK_WRITE, 0x0990, 0x0003}, -+ {TOK_WRITE, 0x098C, 0xA410}, -+ {TOK_WRITE, 0x0990, 0x000A}, - {TOK_WRITE, 0x098C, 0xA103}, - {TOK_WRITE, 0x0990, 0x0006}, - {TOK_DELAY, 0, 100}, -@@ -1216,13 +1232,10 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - struct mt9v113_decoder *decoder = s->priv; - int err = 0; - -- if (decoder->state == STATE_DETECTED) -- return 0; -- - switch (on) { - case V4L2_POWER_OFF: - /* Power Down Sequence */ --/* TODO: FIXME: implement proper OFF and Standby code here */ -+ /* TODO: FIXME: implement proper OFF and Standby code here */ - #if 0 - err = mt9v113_write_reg(decoder->client, REG_OPERATION_MODE, - 0x01); -@@ -1240,10 +1253,10 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - - case V4L2_POWER_ON: - /* Enable mux for mt9v113 data path */ -- if ((decoder->pdata->power_set) && -- (decoder->state == STATE_NOT_DETECTED)) { -+ if (decoder->state == STATE_NOT_DETECTED) { - -- err = decoder->pdata->power_set(s, on); -+ if (decoder->pdata->power_set) -+ err = decoder->pdata->power_set(s, on); - - /* Detect the sensor is not already detected */ - err |= mt9v113_detect(decoder); -@@ -1252,10 +1265,10 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - "Unable to detect decoder\n"); - return err; - } -- /* Only VGA mode for now */ -- err |= mt9v113_configure(decoder); -- err |= mt9v113_vga_mode(decoder); - } -+ /* Only VGA mode for now */ -+ err |= mt9v113_configure(decoder); -+ err |= mt9v113_vga_mode(decoder); - break; - - default: --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0044-mt9v113-AE-param-tuned-to-get-28-30FPS.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0044-mt9v113-AE-param-tuned-to-get-28-30FPS.patch deleted file mode 100644 index bf8347ce..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0044-mt9v113-AE-param-tuned-to-get-28-30FPS.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 12b4010768d5bf36bdc1100204be1a9de913d4f4 Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath -Date: Thu, 15 Jul 2010 13:53:03 +0530 -Subject: [PATCH 44/75] mt9v113: AE param tuned to get 28~30FPS - -Please note that with this change we are compromising with -image quality, so should be used only in case of high FPS use-case. ---- - drivers/media/video/mt9v113.c | 8 ++++++++ - 1 files changed, 8 insertions(+), 0 deletions(-) - -diff --git a/drivers/media/video/mt9v113.c b/drivers/media/video/mt9v113.c -index 466702e..6714240 100644 ---- a/drivers/media/video/mt9v113.c -+++ b/drivers/media/video/mt9v113.c -@@ -306,6 +306,14 @@ static struct mt9v113_reg mt9v113_reg_list[] = { - {TOK_WRITE, 0x0990, 0x0003}, - {TOK_WRITE, 0x098C, 0xA410}, - {TOK_WRITE, 0x0990, 0x000A}, -+ -+ {TOK_WRITE, 0x098C, 0xA20C}, -+ {TOK_WRITE, 0x0990, 0x0003}, -+ {TOK_WRITE, 0x098C, 0xA20B}, -+ {TOK_WRITE, 0x0990, 0x0000}, -+ {TOK_WRITE, 0x098C, 0xA215}, -+ {TOK_WRITE, 0x0990, 0x0004}, -+ - {TOK_WRITE, 0x098C, 0xA103}, - {TOK_WRITE, 0x0990, 0x0006}, - {TOK_DELAY, 0, 100}, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0045-omap3beagle-camera-Cleanup-of-boardfile.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0045-omap3beagle-camera-Cleanup-of-boardfile.patch deleted file mode 100644 index f4c6ba02..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0045-omap3beagle-camera-Cleanup-of-boardfile.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 62059bb8a86836a042bf1720a9bc4bdfa301026f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 12 Jul 2010 15:44:18 -0500 -Subject: [PATCH 45/75] omap3beagle: camera: Cleanup of boardfile - -This removes a lot of dead code. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 51 ++++++++++++++++++------ - arch/arm/mach-omap2/board-omap3beagle-camera.h | 41 ------------------- - 2 files changed, 38 insertions(+), 54 deletions(-) - delete mode 100644 arch/arm/mach-omap2/board-omap3beagle-camera.h - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 90eadd0..befa7d4 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -44,9 +44,6 @@ - #include <../drivers/media/video/isp/ispreg.h> - - #include "mux.h" --#include "board-omap3beagle-camera.h" -- --#define MODULE_NAME "omap3beaglelmb" - - #define CAM_USE_XCLKA 0 - -@@ -129,11 +126,7 @@ static int mt9v113_set_prv_data(void *priv) - if (priv == NULL) - return -EINVAL; - -- hwc->u.sensor = mt9v113_hwc.u.sensor; -- hwc->dev_index = mt9v113_hwc.dev_index; -- hwc->dev_minor = mt9v113_hwc.dev_minor; -- hwc->dev_type = mt9v113_hwc.dev_type; -- -+ *hwc = mt9v113_hwc; - return 0; - } - -@@ -204,10 +197,6 @@ struct mt9v113_platform_data mt9v113_pdata = { - .power_set = mt9v113_power_set, - .priv_data_set = mt9v113_set_prv_data, - .ifparm = mt9v113_ifparm, -- /* Some interface dependent params */ -- .clk_polarity = 0, /* data clocked out on falling edge */ -- .hs_polarity = 1, /* 0 - Active low, 1- Active high */ -- .vs_polarity = 1, /* 0 - Active low, 1- Active high */ - }; - - static int beagle_cam_probe(struct platform_device *pdev) -@@ -217,6 +206,7 @@ static int beagle_cam_probe(struct platform_device *pdev) - dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); - return PTR_ERR(beagle_mt9v113_1_8v1); - } -+ - beagle_mt9v113_1_8v2 = regulator_get(&pdev->dev, "vaux4_1"); - if (IS_ERR(beagle_mt9v113_1_8v2)) { - dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); -@@ -235,7 +225,41 @@ static int beagle_cam_probe(struct platform_device *pdev) - /* set to output mode, default value 0 */ - gpio_direction_output(LEOPARD_RESET_GPIO, 0); - -- printk(KERN_INFO MODULE_NAME ": Driver registration complete \n"); -+ /* MUX init */ -+ omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -+ 0x10C); /* CAM_HS */ -+ omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -+ 0x10E); /* CAM_VS */ -+ omap_ctrl_writew(OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, -+ 0x110); /* CAM_XCLKA */ -+ omap_ctrl_writew(OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, -+ 0x112); /* CAM_PCLK */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x116); /* CAM_D0 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x118); /* CAM_D1 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x11A); /* CAM_D2 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x11C); /* CAM_D3 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x11E); /* CAM_D4 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x120); /* CAM_D5 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x122); /* CAM_D6 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x124); /* CAM_D7 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x126); /* CAM_D8 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x128); /* CAM_D9 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x12A); /* CAM_D10 */ -+ omap_ctrl_writew(OMAP_PIN_INPUT | OMAP_MUX_MODE0, -+ 0x12C); /* CAM_D11 */ -+ -+ printk(KERN_INFO "omap3beaglelmb: Driver registration complete\n"); - - return 0; - } -@@ -287,6 +311,7 @@ static struct platform_driver beagle_cam_driver = { - */ - int __init omap3beaglelmb_init(void) - { -+ /* NOTE: Beagle xM boards are the only ones with camera interface */ - if (cpu_is_omap3630()) - platform_driver_register(&beagle_cam_driver); - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.h b/arch/arm/mach-omap2/board-omap3beagle-camera.h -deleted file mode 100644 -index 1026aeb..0000000 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.h -+++ /dev/null -@@ -1,41 +0,0 @@ --/* -- * Copyright (C) 2010 Texas Instruments Inc -- * Author: Sergio Aguirre -- * -- * Based on work done by: -- * Vaibhav Hiremath -- * Anuj Aggarwal -- * Sivaraj R -- * -- * This package is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License version 2 as -- * published by the Free Software Foundation. -- * -- * This program is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * You should have received a copy of the GNU General Public License -- * along with this program; if not, write to the Free Software -- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- */ -- --#ifndef __BOARD_OMAP3BEAGLE_LMB_H_ --#define __BOARD_OMAP3BEAGLE_LMB_H_ -- --/* mux id to enable/disable signal routing to different peripherals */ --enum omap3beaglelmb_mux { -- MUX_TVP5146 = 0, -- MUX_CAMERA_SENSOR, -- MUX_EXP_CAMERA_SENSOR, -- NUM_MUX --}; -- --/* enum to enable or disable mux */ --enum config_mux { -- DISABLE_MUX, -- ENABLE_MUX --}; -- --#endif /* __BOARD_OMAP3BEAGLE_LMB_H_ */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0046-omap3beagle-camera-Cleanup-regulator-usage.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0046-omap3beagle-camera-Cleanup-regulator-usage.patch deleted file mode 100644 index 9f3cbb26..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0046-omap3beagle-camera-Cleanup-regulator-usage.patch +++ /dev/null @@ -1,172 +0,0 @@ -From d3ea23ea580848bb5e0ed423db4d914661cd1d7d Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 12 Jul 2010 15:53:44 -0500 -Subject: [PATCH 46/75] omap3beagle: camera: Cleanup regulator usage - -We were missing the point of regulator abstraction layer. - -Camera board file shouldn't be aware of what vaux is using, but -just asking for a specific power supply (for cam_1v8 and cam_2v8). - -How is that mapped before, is something that the regulator machine -should figure out. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 50 ++++++++++++------------ - arch/arm/mach-omap2/board-omap3beagle.c | 24 +++++------- - 2 files changed, 35 insertions(+), 39 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index befa7d4..c91529d 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -51,8 +51,8 @@ - - #define LEOPARD_RESET_GPIO 98 - --static struct regulator *beagle_mt9v113_1_8v1; --static struct regulator *beagle_mt9v113_1_8v2; -+static struct regulator *cam_1v8_reg; -+static struct regulator *cam_2v8_reg; - - /* Arbitrary memory handling limit */ - #define MT9V113_MAX_FRAME_SIZE PAGE_ALIGN(640 * 480 * 4) -@@ -148,10 +148,10 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - case V4L2_POWER_OFF: - isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); - -- if (regulator_is_enabled(beagle_mt9v113_1_8v1)) -- regulator_disable(beagle_mt9v113_1_8v1); -- if (regulator_is_enabled(beagle_mt9v113_1_8v2)) -- regulator_disable(beagle_mt9v113_1_8v2); -+ if (regulator_is_enabled(cam_1v8_reg)) -+ regulator_disable(cam_1v8_reg); -+ if (regulator_is_enabled(cam_2v8_reg)) -+ regulator_disable(cam_2v8_reg); - - break; - -@@ -162,10 +162,10 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ -- regulator_enable(beagle_mt9v113_1_8v1); -+ regulator_enable(cam_1v8_reg); - mdelay(1); - /* turn on VDD_IO */ -- regulator_enable(beagle_mt9v113_1_8v2); -+ regulator_enable(cam_2v8_reg); - mdelay(50); - - /* Enable EXTCLK */ -@@ -201,24 +201,24 @@ struct mt9v113_platform_data mt9v113_pdata = { - - static int beagle_cam_probe(struct platform_device *pdev) - { -- beagle_mt9v113_1_8v1 = regulator_get(&pdev->dev, "vaux3_1"); -- if (IS_ERR(beagle_mt9v113_1_8v1)) { -- dev_err(&pdev->dev, "vaux3_1 regulator missing\n"); -- return PTR_ERR(beagle_mt9v113_1_8v1); -+ cam_1v8_reg = regulator_get(&pdev->dev, "cam_1v8"); -+ if (IS_ERR(cam_1v8_reg)) { -+ dev_err(&pdev->dev, "cam_1v8 regulator missing\n"); -+ return PTR_ERR(cam_1v8_reg); - } - -- beagle_mt9v113_1_8v2 = regulator_get(&pdev->dev, "vaux4_1"); -- if (IS_ERR(beagle_mt9v113_1_8v2)) { -- dev_err(&pdev->dev, "vaux4_1 regulator missing\n"); -- regulator_put(beagle_mt9v113_1_8v1); -- return PTR_ERR(beagle_mt9v113_1_8v2); -+ cam_2v8_reg = regulator_get(&pdev->dev, "cam_2v8"); -+ if (IS_ERR(cam_2v8_reg)) { -+ dev_err(&pdev->dev, "cam_2v8 regulator missing\n"); -+ regulator_put(cam_1v8_reg); -+ return PTR_ERR(cam_2v8_reg); - } - - if (gpio_request(LEOPARD_RESET_GPIO, "cam_rst") != 0) { - dev_err(&pdev->dev, "Could not request GPIO %d", - LEOPARD_RESET_GPIO); -- regulator_put(beagle_mt9v113_1_8v2); -- regulator_put(beagle_mt9v113_1_8v1); -+ regulator_put(cam_2v8_reg); -+ regulator_put(cam_1v8_reg); - return -ENODEV; - } - -@@ -266,13 +266,13 @@ static int beagle_cam_probe(struct platform_device *pdev) - - static int beagle_cam_remove(struct platform_device *pdev) - { -- if (regulator_is_enabled(beagle_mt9v113_1_8v1)) -- regulator_disable(beagle_mt9v113_1_8v1); -- regulator_put(beagle_mt9v113_1_8v1); -+ if (regulator_is_enabled(cam_1v8_reg)) -+ regulator_disable(cam_1v8_reg); -+ regulator_put(cam_1v8_reg); - -- if (regulator_is_enabled(beagle_mt9v113_1_8v2)) -- regulator_disable(beagle_mt9v113_1_8v2); -- regulator_put(beagle_mt9v113_1_8v2); -+ if (regulator_is_enabled(cam_2v8_reg)) -+ regulator_disable(cam_2v8_reg); -+ regulator_put(cam_2v8_reg); - - gpio_free(LEOPARD_RESET_GPIO); - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index d4b0b0a..b0da483 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -414,18 +414,14 @@ static struct platform_device beagle_cam_device = { - .id = -1, - }; - --static struct regulator_consumer_supply beagle_vaux3_supplies[] = { -- { -- .supply = "vaux3_1", -- .dev = &beagle_cam_device.dev, -- }, -+static struct regulator_consumer_supply beagle_vaux3_supply = { -+ .supply = "cam_1v8", -+ .dev = &beagle_cam_device.dev, - }; - --static struct regulator_consumer_supply beagle_vaux4_supplies[] = { -- { -- .supply = "vaux4_1", -- .dev = &beagle_cam_device.dev, -- }, -+static struct regulator_consumer_supply beagle_vaux4_supply = { -+ .supply = "cam_2v8", -+ .dev = &beagle_cam_device.dev, - }; - - /* VAUX3 for CAM_1V8 */ -@@ -439,8 +435,8 @@ static struct regulator_init_data beagle_vaux3 = { - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = ARRAY_SIZE(beagle_vaux3_supplies), -- .consumer_supplies = beagle_vaux3_supplies, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &beagle_vaux3_supply, - }; - - /* VAUX4 for CAM_2V8 */ -@@ -454,8 +450,8 @@ static struct regulator_init_data beagle_vaux4 = { - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = ARRAY_SIZE(beagle_vaux4_supplies), -- .consumer_supplies = beagle_vaux4_supplies, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &beagle_vaux4_supply, - }; - - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0047-omap3beagle-camera-Bring-back-mt9t111-support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0047-omap3beagle-camera-Bring-back-mt9t111-support.patch deleted file mode 100644 index d8614776..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0047-omap3beagle-camera-Bring-back-mt9t111-support.patch +++ /dev/null @@ -1,251 +0,0 @@ -From e81cdbd3c914965685e213ceef5a14775bfb9397 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 12 Jul 2010 16:42:41 -0500 -Subject: [PATCH 47/75] omap3beagle: camera: Bring back mt9t111 support - -Restore MT9T111 sensor support. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 175 +++++++++++++++++++++++- - arch/arm/mach-omap2/board-omap3beagle.c | 12 ++ - 2 files changed, 184 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index c91529d..2e49158 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -37,7 +37,6 @@ - #include - - #include --#include - - /* Include V4L2 ISP-Camera driver related header file */ - #include <../drivers/media/video/omap34xxcam.h> -@@ -47,13 +46,16 @@ - - #define CAM_USE_XCLKA 0 - --#define ISP_MT9V113_MCLK 216000000 -- - #define LEOPARD_RESET_GPIO 98 - - static struct regulator *cam_1v8_reg; - static struct regulator *cam_2v8_reg; - -+#if defined(CONFIG_VIDEO_MT9V113) || defined(CONFIG_VIDEO_MT9V113_MODULE) -+#include -+ -+#define ISP_MT9V113_MCLK 216000000 -+ - /* Arbitrary memory handling limit */ - #define MT9V113_MAX_FRAME_SIZE PAGE_ALIGN(640 * 480 * 4) - -@@ -199,6 +201,173 @@ struct mt9v113_platform_data mt9v113_pdata = { - .ifparm = mt9v113_ifparm, - }; - -+#endif /* #ifdef CONFIG_VIDEO_MT9V113 */ -+ -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#include -+ -+#define ISP_MT9T111_MCLK 216000000 -+ -+/* Arbitrary memory handling limit */ -+#define MT9T111_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN((2048 * 2) * 1536 * 4) -+ -+static struct isp_interface_config mt9t111_if_config = { -+ .ccdc_par_ser = ISP_PARLL, -+ .dataline_shift = 0x2, -+ .hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE, -+ .strobe = 0x0, -+ .prestrobe = 0x0, -+ .shutter = 0x0, -+ .cam_mclk = ISP_MT9T111_MCLK, -+ .wenlog = ISPCCDC_CFG_WENLOG_AND, -+ .wait_hs_vs = 2, -+ .u.par.par_bridge = 0x3, -+ .u.par.par_clk_pol = 0x0, -+}; -+ -+static struct v4l2_ifparm mt9t111_ifparm_s = { -+ .if_type = V4L2_IF_TYPE_RAW, -+ .u = { -+ .raw = { -+ .frame_start_on_rising_vs = 1, -+ .bt_sync_correct = 0, -+ .swap = 0, -+ .latch_clk_inv = 0, -+ .nobt_hs_inv = 0, /* active high */ -+ .nobt_vs_inv = 0, /* active high */ -+ .clock_min = MT9T111_CLK_MIN, -+ .clock_max = MT9T111_CLK_MAX, -+ }, -+ }, -+}; -+ -+/** -+ * @brief mt9t111_ifparm - Returns the mt9t111 interface parameters -+ * -+ * @param p - pointer to v4l2_ifparm structure -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9t111_ifparm(struct v4l2_ifparm *p) -+{ -+ if (p == NULL) -+ return -EINVAL; -+ -+ *p = mt9t111_ifparm_s; -+ return 0; -+} -+ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+static struct omap34xxcam_hw_config mt9t111_hwc = { -+ .dev_index = 0, -+ .dev_minor = 0, -+ .dev_type = OMAP34XXCAM_SLAVE_SENSOR, -+ .u.sensor.sensor_isp = 0, -+ .u.sensor.capture_mem = MT9T111_BIGGEST_FRAME_BYTE_SIZE, -+ .u.sensor.ival_default = { 1, 10 }, -+}; -+#endif -+ -+/** -+ * @brief mt9t111_set_prv_data - Returns mt9t111 omap34xx driver private data -+ * -+ * @param priv - pointer to omap34xxcam_hw_config structure -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9t111_set_prv_data(void *priv) -+{ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+ struct omap34xxcam_hw_config *hwc = priv; -+ -+ if (priv == NULL) -+ return -EINVAL; -+ -+ *hwc = mt9t111_hwc; -+ return 0; -+#else -+ return -EINVAL; -+#endif -+} -+ -+/** -+ * @brief mt9t111_power_set - Power-on or power-off TVP5146 device -+ * -+ * @param power - enum, Power on/off, resume/standby -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) -+{ -+ struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; -+ -+ switch (power) { -+ case V4L2_POWER_OFF: -+ case V4L2_POWER_STANDBY: -+ isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); -+ -+ if (regulator_is_enabled(cam_1v8_reg)) -+ regulator_disable(cam_1v8_reg); -+ if (regulator_is_enabled(cam_2v8_reg)) -+ regulator_disable(cam_2v8_reg); -+ break; -+ -+ case V4L2_POWER_ON: -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+ isp_configure_interface(vdev->cam->isp, &mt9t111_if_config); -+#endif -+ -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); -+ -+ /* turn on VDD */ -+ regulator_enable(cam_1v8_reg); -+ -+ mdelay(1); -+ -+ /* turn on VDD_IO */ -+ regulator_enable(cam_2v8_reg); -+ -+ mdelay(50); -+ -+ /* Enable EXTCLK */ -+ isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); -+ -+ /* -+ * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -+ * ((1000000 * 70) / 6000000) = aprox 12 us. -+ */ -+ -+ udelay(12); -+ -+ /* Set RESET_BAR to 1 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 1); -+ -+ /* -+ * Wait at least 100 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -+ * ((1000000 * 100) / 6000000) = aprox 17 us. -+ */ -+ -+ udelay(17); -+ -+ break; -+ -+ default: -+ return -ENODEV; -+ break; -+ } -+ return 0; -+} -+ -+struct mt9t111_platform_data mt9t111_pdata = { -+ .master = "omap34xxcam", -+ .power_set = mt9t111_power_set, -+ .priv_data_set = mt9t111_set_prv_data, -+ .ifparm = mt9t111_ifparm, -+}; -+ -+#endif /* #ifdef CONFIG_VIDEO_MT9T111 */ -+ - static int beagle_cam_probe(struct platform_device *pdev) - { - cam_1v8_reg = regulator_get(&pdev->dev, "cam_1v8"); -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index b0da483..0e7e8b2 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -77,6 +77,12 @@ static struct omap_opp * _omap37x_l3_rate_table = NULL; - extern struct mt9v113_platform_data mt9v113_pdata; - #endif - -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#include -+#include -+extern struct mt9t111_platform_data mt9t111_pdata; -+#endif -+ - #define GPMC_CS0_BASE 0x60 - #define GPMC_CS_SIZE 0x30 - -@@ -596,6 +602,12 @@ static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { - .platform_data = &mt9v113_pdata, - }, - #endif -+#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+ { -+ I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), -+ .platform_data = &mt9t111_pdata, -+ }, -+#endif - }; - - static int __init omap3_beagle_i2c_init(void) --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0048-REMOVE-v4l2-Delete-MT9T111-sensor-driver.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0048-REMOVE-v4l2-Delete-MT9T111-sensor-driver.patch deleted file mode 100644 index 79ea2b57..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0048-REMOVE-v4l2-Delete-MT9T111-sensor-driver.patch +++ /dev/null @@ -1,2402 +0,0 @@ -From 59d42cae8d60b7e86013293055f6c989ab578f26 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 00:50:07 -0500 -Subject: [PATCH 48/75] REMOVE: v4l2: Delete MT9T111 sensor driver - -This removes MT9T111 support from the kernel. - -Reason? Driver already exists in open source, and we're going to -reuse that one instead. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/Kconfig | 8 - - drivers/media/video/Makefile | 1 - - drivers/media/video/mt9t111.c | 885 ------------------------ - drivers/media/video/mt9t111_reg.h | 1364 ------------------------------------- - include/media/mt9t111.h | 79 --- - 5 files changed, 0 insertions(+), 2337 deletions(-) - delete mode 100644 drivers/media/video/mt9t111.c - delete mode 100644 drivers/media/video/mt9t111_reg.h - delete mode 100644 include/media/mt9t111.h - -diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig -index c14d758..780b246 100644 ---- a/drivers/media/video/Kconfig -+++ b/drivers/media/video/Kconfig -@@ -354,14 +354,6 @@ config VIDEO_MT9P012 - MT9P012 camera. It is currently working with the TI OMAP3 - camera controller. - --config VIDEO_MT9T111 -- tristate "Micron MT9T111 raw sensor driver (3MP)" -- depends on I2C && VIDEO_V4L2 -- ---help--- -- This is a Video4Linux2 sensor-level driver for the Micron -- MT9T111 camera. It is currently working with the TI OMAP3 -- camera controller. -- - config VIDEO_DW9710 - tristate "Lens driver for DW9710" - depends on I2C && VIDEO_V4L2 -diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile -index 763c157..3828723 100644 ---- a/drivers/media/video/Makefile -+++ b/drivers/media/video/Makefile -@@ -128,7 +128,6 @@ obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o - obj-y += isp/ - obj-$(CONFIG_VIDEO_OMAP3) += omap34xxcam.o - obj-$(CONFIG_VIDEO_MT9P012) += mt9p012.o --obj-$(CONFIG_VIDEO_MT9T111) += mt9t111.o - obj-$(CONFIG_VIDEO_DW9710) += dw9710.o - obj-$(CONFIG_VIDEO_TPS61059) += tps61059.o - obj-$(CONFIG_VIDEO_OV3640) += ov3640.o -diff --git a/drivers/media/video/mt9t111.c b/drivers/media/video/mt9t111.c -deleted file mode 100644 -index 10080af..0000000 ---- a/drivers/media/video/mt9t111.c -+++ /dev/null -@@ -1,885 +0,0 @@ --/* -- * drivers/media/video/mt9t111.c -- * -- * mt9t111 sensor driver -- * -- * Copyright (C) 2009 Leopard Imaging -- * -- * This file is licensed under the terms of the GNU General Public License -- * version 2. This program is licensed "as is" without any warranty of any -- * kind, whether express or implied. -- */ -- --#include --#include --#include -- --#include --#include "mt9t111_reg.h" -- --/* YCbCr mode does not work yet */ --#define USE_RAW --/* Create a Color bar test pattern, Blue, Green, Red, Grey */ --/* #define COLOR_BAR */ -- --#define SENSOR_DETECTED 1 --#define SENSOR_NOT_DETECTED 0 -- --static void mt9t111_loaddefault(struct i2c_client *client); -- --/* -- * as a place holder for further development -- */ --static void debug_dummy(char *in_msg) --{ --} -- --/* list of image formats supported by mt9t111 sensor */ --const static struct v4l2_fmtdesc mt9t111_formats[] = { --#ifdef USE_RAW -- { -- .description = "RAW ", -- .pixelformat = V4L2_PIX_FMT_SGRBG10, -- }, --#else -- { -- .description = "YUV 422 ", -- .pixelformat = V4L2_PIX_FMT_YUYV, -- }, --#endif --}; -- --#define NUM_CAPTURE_FORMATS ARRAY_SIZE(mt9t111_formats) -- --/* -- * Array of image sizes supported by MT9T111. These must be ordered from -- * smallest image size to largest. -- */ --const static struct capture_size mt9t111_sizes[] = { -- { 640, 480 }, -- /* { 2048, 1536} */ --}; -- --#define NUM_CAPTURE_SIZE ARRAY_SIZE(mt9t111_sizes) -- -- --const struct v4l2_fract mt9t111_frameintervals[] = { -- { .numerator = 1, .denominator = 10 } --}; -- --#define NUM_CAPTURE_FRAMEINTERVALS ARRAY_SIZE(mt9t111_frameintervals) -- --/** -- * struct mt9t111_sensor - main structure for storage of sensor information -- * @pdata: access functions and data for platform level information -- * @v4l2_int_device: V4L2 device structure structure -- * @i2c_client: iic client device structure -- * @pix: V4L2 pixel format information structure -- * @timeperframe: time per frame expressed as V4L fraction -- * @scaler: -- * @ver: mt9t111 chip version -- * @fps: frames per second value -- */ --struct mt9t111_sensor { -- const struct mt9t111_platform_data *pdata; -- struct v4l2_int_device *v4l2_int_device; -- struct i2c_client *i2c_client; -- struct v4l2_pix_format pix; -- struct v4l2_fract timeperframe; -- int scaler; -- int ver; -- int fps; -- int state; --}; -- --static struct mt9t111_sensor mt9t111 = { -- .timeperframe = { -- .numerator = 1, -- .denominator = 10, -- }, -- .state = SENSOR_NOT_DETECTED, --}; -- --/** -- * mt9t111_read_reg - Read a value from a register in an mt9t111 sensor device -- * @client: i2c driver client structure -- * @data_length: length of data to be read -- * @reg: register address / offset -- * @val: stores the value that gets read -- * -- * Read a value from a register in an mt9t111 sensor device. -- * The value is returned in 'val'. -- * Returns zero if successful, or non-zero otherwise. -- */ --static int --mt9t111_read_reg(struct i2c_client *client, u16 reg, u16 *val) --{ -- struct i2c_msg msg[1]; -- u8 data[4]; -- int err; -- -- msg->addr = client->addr; -- msg->flags = 0; -- msg->len = 2; -- msg->buf = data; -- data[0] = (reg & 0xff00) >> 8; -- data[1] = (reg & 0x00ff); -- err = i2c_transfer(client->adapter, msg, 1); -- if (err >= 0) { -- msg->flags = I2C_M_RD; -- msg->len = 2; /* 2 byte read */ -- err = i2c_transfer(client->adapter, msg, 1); -- if (err >= 0) { -- *val = ((data[0] & 0x00ff) << 8) -- | (data[1] & 0x00ff); -- return 0; -- } -- } -- return err; --} -- --/** -- * mt9t111_write_reg - Write a value to a register in an mt9t111 sensor device -- * @client: i2c driver client structure -- * @data_length: length of data to be read -- * @reg: register address / offset -- * @val: value to be written to specified register -- * -- * Write a value to a register in an mt9t111 sensor device. -- * Returns zero if successful, or non-zero otherwise. -- */ --static int --mt9t111_write_reg(struct i2c_client *client, u16 reg, u16 val) --{ -- struct i2c_msg msg[1]; -- u8 data[20]; -- int err; -- -- msg->addr = client->addr; -- msg->flags = 0; -- msg->len = 4; -- msg->buf = data; -- data[0] = (u8)((reg & 0xff00) >> 8); -- data[1] = (u8)(reg & 0x00ff); -- data[2] = (u8)((val & 0xff00) >> 8); -- data[3] = (u8)(val & 0x00ff); -- err = i2c_transfer(client->adapter, msg, 1); -- -- return err; --} -- --/** -- * mt9t111_write_regs - Write registers to an mt9t111 sensor device -- * @client: i2c driver client structure -- * @reg_in: pointer to registers to write -- * @cnt: the number of registers -- * -- * Write registers . -- * Returns zero if successful, or non-zero otherwise. -- */ --static int --mt9t111_write_regs(struct i2c_client *client, mt9t111_regs *reg_in, int cnt) --{ -- int err = 0; -- int i; -- mt9t111_regs *reg = reg_in; -- -- for (i = 0; i < cnt; i++) { -- if (reg->delay_time == 0) { -- err |= mt9t111_write_reg(client, reg->addr, reg->data); -- } else if (reg->addr != 0 || reg->data != 0) { -- err |= mt9t111_write_reg(client, reg->addr, reg->data); -- mdelay(reg->delay_time); -- } else { -- mdelay(reg->delay_time); -- } -- -- if (err < 0) { -- dev_warn(&client->dev, "write reg error, addr = 0x%x," -- " data = 0x%x \n", -- reg->addr, reg->data); -- return err; -- } -- reg++; -- } -- return err; --} -- --/** -- * mt9t111_detect - Detect if an mt9t111 is present, and if so which revision -- * @client: pointer to the i2c client driver structure -- * -- * Detect if an mt9t111 is present -- * Returns a negative error number if no device is detected, or the -- * non-negative value of the version ID register if a device is detected. -- */ --static int --mt9t111_detect(struct i2c_client *client) --{ -- u16 val; -- -- /* chip ID is at address 0 */ -- if (mt9t111_read_reg(client, MT9T111_CHIP_ID, &val) < 0) -- return -ENODEV; -- -- if (val != MT9T111_CHIP_ID_VALUE) { -- dev_warn(&client->dev, "model id mismatch received 0x%x" -- " expecting 0x%x\n", -- val, MT9T111_CHIP_ID_VALUE); -- -- return -ENODEV; -- } -- -- return (int)val; -- --} -- --/** -- * mt9t111_configure - Configure the mt9t111 for the specified image mode -- * @s: pointer to standard V4L2 device structure -- * -- * Configure the mt9t111 for a specified image size, pixel format, and frame -- * period. xclk is the frequency (in Hz) of the xclk input to the mt9t111. -- * fper is the frame period (in seconds) expressed as a fraction. -- * Returns zero if successful, or non-zero otherwise. -- * The actual frame period is returned in fper. -- */ --static int mt9t111_configure(struct v4l2_int_device *s) --{ -- debug_dummy("debug_dummy -- to set imager mode"); -- -- return 0; --} -- --/** -- * ioctl_enum_framesizes - V4L2 sensor if handler for vidioc_int_enum_framesizes -- * @s: pointer to standard V4L2 device structure -- * @frms: pointer to standard V4L2 framesizes enumeration structure -- * -- * Returns possible framesizes depending on choosen pixel format -- **/ --static int ioctl_enum_framesizes(struct v4l2_int_device *s, -- struct v4l2_frmsizeenum *frms) --{ -- int ifmt; -- -- for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) { -- if (frms->pixel_format == mt9t111_formats[ifmt].pixelformat) -- break; -- } -- /* Is requested pixelformat not found on sensor? */ -- if (ifmt == NUM_CAPTURE_FORMATS) -- return -EINVAL; -- -- /* Do we already reached all discrete framesizes? */ -- if (frms->index >= NUM_CAPTURE_SIZE) -- return -EINVAL; -- -- frms->type = V4L2_FRMSIZE_TYPE_DISCRETE; -- frms->discrete.width = mt9t111_sizes[frms->index].width; -- frms->discrete.height = mt9t111_sizes[frms->index].height; -- -- return 0; -- --} -- --static int ioctl_enum_frameintervals(struct v4l2_int_device *s, -- struct v4l2_frmivalenum *frmi) --{ -- int ifmt; -- -- if (frmi->index >= NUM_CAPTURE_FRAMEINTERVALS) -- return -EINVAL; -- -- for (ifmt = 0; ifmt < NUM_CAPTURE_FORMATS; ifmt++) { -- if (frmi->pixel_format == mt9t111_formats[ifmt].pixelformat) -- break; -- } -- /* Is requested pixelformat not found on sensor? */ -- if (ifmt == NUM_CAPTURE_FORMATS) -- return -EINVAL; -- -- frmi->type = V4L2_FRMSIZE_TYPE_DISCRETE; -- frmi->discrete.numerator = -- mt9t111_frameintervals[frmi->index].numerator; -- frmi->discrete.denominator = -- mt9t111_frameintervals[frmi->index].denominator; -- return 0; --} -- --/** -- * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -- * @s: pointer to standard V4L2 device structure -- * -- * Initialize the sensor device (call mt9t111_configure()) -- */ --static int ioctl_init(struct v4l2_int_device *s) --{ -- return 0; --} -- --/** -- * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -- * @s: pointer to standard V4L2 device structure -- * -- * Delinitialise the dev. at slave detach. The complement of ioctl_dev_init. -- */ --static int ioctl_dev_exit(struct v4l2_int_device *s) --{ -- return 0; --} -- --/** -- * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -- * @s: pointer to standard V4L2 device structure -- * -- * Initialise the device when slave attaches to the master. Returns 0 if -- * mt9t111 device could be found, otherwise returns appropriate error. -- */ --static int ioctl_dev_init(struct v4l2_int_device *s) --{ -- return 0; --} -- --/** -- * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num -- * @s: pointer to standard V4L2 device structure -- * @on: power state to which device is to be set -- * -- * Sets devices power state to requrested state, if possible. -- */ --static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) --{ -- struct mt9t111_sensor *sensor = s->priv; -- struct i2c_client *c = sensor->i2c_client; -- int rval; -- -- if ((on == V4L2_POWER_STANDBY) && (sensor->state == SENSOR_DETECTED)) -- debug_dummy("debug_dummy -- put to standby\n"); -- -- if (on != V4L2_POWER_ON) -- debug_dummy("debug_dummy -- stop master clock\n"); -- else -- debug_dummy("debug_dummy -- enable clock\n");; -- -- rval = sensor->pdata->power_set(s, on); -- if (rval < 0) { -- dev_err(&c->dev, "Unable to set the power state: " "mt9t111" -- " sensor\n"); -- /* sensor->pdata->set_xclk(0); */ -- return rval; -- } -- -- if ((on == V4L2_POWER_ON) && (sensor->state == SENSOR_DETECTED)) -- mt9t111_loaddefault(c); -- -- if ((on == V4L2_POWER_ON) && (sensor->state == SENSOR_NOT_DETECTED)) { -- rval = mt9t111_detect(c); -- if (rval < 0) { -- dev_err(&c->dev, "Unable to detect " "mt9t111" -- " sensor\n"); -- sensor->state = SENSOR_NOT_DETECTED; -- return rval; -- } -- dev_info(&c->dev, "chip version 0x%02x detected\n", rval); -- sensor->state = SENSOR_DETECTED; -- sensor->ver = rval; -- } -- return 0; --} -- --/** -- * ioctl_g_priv - V4L2 sensor interface handler for vidioc_int_g_priv_num -- * @s: pointer to standard V4L2 device structure -- * @p: void pointer to hold sensor's private data address -- * -- * Returns device's (sensor's) private data area address in p parameter -- */ --static int ioctl_g_priv(struct v4l2_int_device *s, void *p) --{ -- struct mt9t111_sensor *sensor = s->priv; -- -- return sensor->pdata->priv_data_set(p); --} -- --/** -- * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -- * @s: pointer to standard V4L2 device structure -- * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -- * -- * Configures the sensor to use the input parameters, if possible. If -- * not possible, reverts to the old parameters and returns the -- * appropriate error code. -- */ --static int ioctl_s_parm(struct v4l2_int_device *s, -- struct v4l2_streamparm *a) --{ -- /* TODO: set paramters */ -- debug_dummy("debug_dummy -- VIDIOC_S_PARM "); -- return 0; --} -- --/** -- * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -- * @s: pointer to standard V4L2 device structure -- * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -- * -- * Returns the sensor's video CAPTURE parameters. -- */ --static int ioctl_g_parm(struct v4l2_int_device *s, -- struct v4l2_streamparm *a) --{ -- struct mt9t111_sensor *sensor = s->priv; -- struct v4l2_captureparm *cparm = &a->parm.capture; -- -- if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -- return -EINVAL; -- -- memset(a, 0, sizeof(*a)); -- a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -- -- cparm->capability = V4L2_CAP_TIMEPERFRAME; -- cparm->timeperframe = sensor->timeperframe; -- -- return 0; --} -- --/** -- * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -- * @s: pointer to standard V4L2 device structure -- * @f: pointer to standard V4L2 v4l2_format structure -- * -- * Returns the sensor's current pixel format in the v4l2_format -- * parameter. -- */ --static int ioctl_g_fmt_cap(struct v4l2_int_device *s, -- struct v4l2_format *f) --{ -- struct mt9t111_sensor *sensor = s->priv; -- f->fmt.pix = sensor->pix; -- -- return 0; --} -- --/** -- * ioctl_try_fmt_cap - Implement the CAPTURE buffer VIDIOC_TRY_FMT ioctl -- * @s: pointer to standard V4L2 device structure -- * @f: pointer to standard V4L2 VIDIOC_TRY_FMT ioctl structure -- * -- * Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This -- * ioctl is used to negotiate the image capture size and pixel format -- * without actually making it take effect. -- */ --static int ioctl_try_fmt_cap(struct v4l2_int_device *s, -- struct v4l2_format *f) --{ -- struct v4l2_pix_format *pix = &f->fmt.pix; -- struct mt9t111_sensor *sensor = s->priv; -- struct v4l2_pix_format *pix2 = &sensor->pix; -- -- pix->width = 640; -- pix->height = 480; --#ifdef USE_RAW -- pix->pixelformat = V4L2_PIX_FMT_SGRBG10; -- pix->bytesperline = pix->width; -- pix->colorspace = V4L2_COLORSPACE_SRGB; --#else -- pix->pixelformat = V4L2_PIX_FMT_YUYV; -- pix->bytesperline = pix->width * 2; -- pix->colorspace = V4L2_COLORSPACE_JPEG; --#endif -- pix->field = V4L2_FIELD_NONE; -- -- pix->sizeimage = pix->bytesperline * pix->height; -- pix->priv = 0; -- *pix2 = *pix; -- return 0; --} -- --/** -- * ioctl_s_fmt_cap - V4L2 sensor interface handler for VIDIOC_S_FMT ioctl -- * @s: pointer to standard V4L2 device structure -- * @f: pointer to standard V4L2 VIDIOC_S_FMT ioctl structure -- * -- * If the requested format is supported, configures the HW to use that -- * format, returns error code if format not supported or HW can't be -- * correctly configured. -- */ --static int ioctl_s_fmt_cap(struct v4l2_int_device *s, -- struct v4l2_format *f) --{ -- struct mt9t111_sensor *sensor = s->priv; -- struct v4l2_pix_format *pix = &f->fmt.pix; -- int rval; -- -- rval = ioctl_try_fmt_cap(s, f); -- if (!rval) -- sensor->pix = *pix; -- -- return rval; --} -- --/** -- * ioctl_enum_fmt_cap - Implement the CAPTURE buffer VIDIOC_ENUM_FMT ioctl -- * @s: pointer to standard V4L2 device structure -- * @fmt: standard V4L2 VIDIOC_ENUM_FMT ioctl structure -- * -- * Implement the VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. -- */ --static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -- struct v4l2_fmtdesc *fmt) --{ -- int index = fmt->index; -- enum v4l2_buf_type type = fmt->type; -- -- memset(fmt, 0, sizeof(*fmt)); -- fmt->index = index; -- fmt->type = type; -- -- switch (fmt->type) { -- case V4L2_BUF_TYPE_VIDEO_CAPTURE: -- if (index >= NUM_CAPTURE_FORMATS) -- return -EINVAL; -- break; -- default: -- return -EINVAL; -- } -- -- fmt->flags = mt9t111_formats[index].flags; -- strlcpy(fmt->description, mt9t111_formats[index].description, -- sizeof(fmt->description)); -- fmt->pixelformat = mt9t111_formats[index].pixelformat; -- -- return 0; --} -- --/** -- * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -- * @s: pointer to standard V4L2 device structure -- * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -- * -- * If the requested control is supported, sets the control's current -- * value in HW (and updates the video_control[] array). Otherwise, -- * returns -EINVAL if the control is not supported. -- */ --static int ioctl_s_ctrl(struct v4l2_int_device *s, -- struct v4l2_control *vc) --{ -- debug_dummy("debug_dummy -- s ctrl\n"); -- return 0; --} -- --/** -- * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -- * @s: pointer to standard V4L2 device structure -- * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -- * -- * If the requested control is supported, returns the control's current -- * value from the video_control[] array. Otherwise, returns -EINVAL -- * if the control is not supported. -- */ --static int ioctl_g_ctrl(struct v4l2_int_device *s, -- struct v4l2_control *vc) --{ -- debug_dummy("debug_dummy -- g ctrl\n"); -- return 0; --} -- --/** -- * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl -- * @s: pointer to standard V4L2 device structure -- * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure -- * -- * If the requested control is supported, returns the control information -- * from the video_control[] array. Otherwise, returns -EINVAL if the -- * control is not supported. -- */ --static int ioctl_queryctrl(struct v4l2_int_device *s, -- struct v4l2_queryctrl *qc) --{ -- debug_dummy("debug_dummy -- query ctrl\n"); -- return -EINVAL; --} -- --/** -- * ioctl_s_routing - V4L2 decoder interface handler for VIDIOC_S_INPUT ioctl -- * @s: pointer to standard V4L2 device structure -- * @index: number of the input -- * -- * If index is valid, selects the requested input. Otherwise, returns -EINVAL if -- * the input is not supported or there is no active signal present in the -- * selected input. -- */ --static int ioctl_s_routing(struct v4l2_int_device *s, -- struct v4l2_routing *route) --{ -- return 0; --} -- --/** -- * ioctl_g_ifparm - V4L2 decoder interface handler for vidioc_int_g_ifparm_num -- * @s: pointer to standard V4L2 device structure -- * @p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure -- * -- * Gets slave interface parameters. -- * Calculates the required xclk value to support the requested -- * clock parameters in p. This value is returned in the p -- * parameter. -- */ --static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) --{ -- struct mt9t111_sensor *sensor = s->priv; -- int rval; -- -- if (p == NULL) -- return -EINVAL; -- -- if (NULL == sensor->pdata->ifparm) -- return -EINVAL; -- -- rval = sensor->pdata->ifparm(p); -- if (rval) { -- v4l_err(sensor->i2c_client, "g_ifparm.Err[%d]\n", rval); -- return rval; -- } -- -- p->u.ycbcr.clock_curr = 40 * 1000000; /* temporal value */ -- -- return 0; --} -- --static struct v4l2_int_ioctl_desc mt9t111_ioctl_desc[] = { -- { .num = vidioc_int_enum_framesizes_num, -- .func = (v4l2_int_ioctl_func *)ioctl_enum_framesizes }, -- { .num = vidioc_int_enum_frameintervals_num, -- .func = (v4l2_int_ioctl_func *)ioctl_enum_frameintervals }, -- { .num = vidioc_int_dev_init_num, -- .func = (v4l2_int_ioctl_func *)ioctl_dev_init }, -- { .num = vidioc_int_dev_exit_num, -- .func = (v4l2_int_ioctl_func *)ioctl_dev_exit }, -- { .num = vidioc_int_s_power_num, -- .func = (v4l2_int_ioctl_func *)ioctl_s_power }, -- { .num = vidioc_int_g_priv_num, -- .func = (v4l2_int_ioctl_func *)ioctl_g_priv }, -- { .num = vidioc_int_g_ifparm_num, -- .func = (v4l2_int_ioctl_func *)ioctl_g_ifparm }, -- { .num = vidioc_int_init_num, -- .func = (v4l2_int_ioctl_func *)ioctl_init }, -- { .num = vidioc_int_enum_fmt_cap_num, -- .func = (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap }, -- { .num = vidioc_int_try_fmt_cap_num, -- .func = (v4l2_int_ioctl_func *)ioctl_try_fmt_cap }, -- { .num = vidioc_int_g_fmt_cap_num, -- .func = (v4l2_int_ioctl_func *)ioctl_g_fmt_cap }, -- { .num = vidioc_int_s_fmt_cap_num, -- .func = (v4l2_int_ioctl_func *)ioctl_s_fmt_cap }, -- { .num = vidioc_int_g_parm_num, -- .func = (v4l2_int_ioctl_func *)ioctl_g_parm }, -- { .num = vidioc_int_s_parm_num, -- .func = (v4l2_int_ioctl_func *)ioctl_s_parm }, -- { .num = vidioc_int_queryctrl_num, -- .func = (v4l2_int_ioctl_func *)ioctl_queryctrl }, -- { .num = vidioc_int_g_ctrl_num, -- .func = (v4l2_int_ioctl_func *)ioctl_g_ctrl }, -- { .num = vidioc_int_s_ctrl_num, -- .func = (v4l2_int_ioctl_func *)ioctl_s_ctrl }, -- { .num = vidioc_int_s_video_routing_num, -- .func = (v4l2_int_ioctl_func *)ioctl_s_routing }, --}; -- --static void mt9t111_refresh(struct i2c_client *client) --{ -- int i; -- unsigned short value; -- /* MCU_ADDRESS [SEQ_CMD] -- refresh */ -- mt9t111_write_reg(client, 0x098E, 0x8400); -- mt9t111_write_reg(client, 0x0990, 0x0006); -- for (i = 0; i < 100; i++) { -- mt9t111_write_reg(client, 0x098E, 0x8400); -- mt9t111_read_reg(client, 0x0990, &value); -- if (value == 0) -- break; -- mdelay(5); -- } --} -- --#ifdef COLOR_BAR --static void mt9t111_color_bar(struct i2c_client *client) --{ -- mt9t111_write_reg(client, 0x3210, 0x01B0); /* disable lens correction */ -- -- mt9t111_write_reg(client, 0x098E, 0x6003); -- mt9t111_write_reg(client, 0x0990, 0x0100); -- mt9t111_write_reg(client, 0x098E, 0x6025); -- mt9t111_write_reg(client, 0x0990, 0x0003); --} --#endif -- --static void mt9t111_bayer_format(struct i2c_client *client) --{ -- mt9t111_write_regs(client, bayer_pattern_regs, -- sizeof(bayer_pattern_regs) / sizeof(mt9t111_regs)); --} -- --static void mt9t111_enable_pll(struct i2c_client *client) --{ -- int i; -- unsigned short value; -- -- mt9t111_write_regs(client, pll_regs1, -- sizeof(pll_regs1) / sizeof(mt9t111_regs)); -- for (i = 0; i < 100; i++) { -- mt9t111_read_reg(client, 0x0014, &value); -- if ((value & 0x8000) != 0) -- break; -- mdelay(2); -- } -- mt9t111_write_regs(client, pll_regs2, -- sizeof(pll_regs2) / sizeof(mt9t111_regs)); --} -- -- --static void mt9t111_loaddefault(struct i2c_client *client) --{ -- mt9t111_write_reg(client, 0x001A, 0x0219); -- mt9t111_write_reg(client, 0x001A, 0x0218); -- -- mt9t111_enable_pll(client); -- mt9t111_write_regs(client, def_regs1, -- sizeof(def_regs1) / sizeof(mt9t111_regs)); -- mt9t111_write_regs(client, patch_rev6, -- sizeof(patch_rev6) / sizeof(mt9t111_regs)); -- mt9t111_write_regs(client, def_regs2, -- sizeof(def_regs2) / sizeof(mt9t111_regs)); -- --#ifdef USE_RAW -- mt9t111_bayer_format(client); --#endif -- --#ifdef COLOR_BAR -- mt9t111_color_bar(client); --#endif -- -- mt9t111_refresh(client); --} -- --static struct v4l2_int_slave mt9t111_slave = { -- .ioctls = mt9t111_ioctl_desc, -- .num_ioctls = ARRAY_SIZE(mt9t111_ioctl_desc), --}; -- --static struct v4l2_int_device mt9t111_int_device = { -- .module = THIS_MODULE, -- .name = "mt9t111", -- .priv = &mt9t111, -- .type = v4l2_int_type_slave, -- .u = { -- .slave = &mt9t111_slave, -- }, --}; -- --/** -- * mt9t111_probe - sensor driver i2c probe handler -- * @client: i2c driver client device structure -- * -- * Register sensor as an i2c client device and V4L2 -- * device. -- */ --static int --mt9t111_probe(struct i2c_client *client, const struct i2c_device_id *id) --{ -- struct mt9t111_sensor *sensor = &mt9t111; -- int err; -- -- if (i2c_get_clientdata(client)) -- return -EBUSY; -- -- sensor->pdata = client->dev.platform_data; -- -- if (!sensor->pdata) { -- dev_err(&client->dev, "no platform data?\n"); -- return -ENODEV; -- } -- -- sensor->v4l2_int_device = &mt9t111_int_device; -- sensor->i2c_client = client; -- -- i2c_set_clientdata(client, sensor); -- -- sensor->pix.width = 640; -- sensor->pix.height = 480; --#ifdef USE_RAW -- sensor->pix.pixelformat = V4L2_PIX_FMT_SGRBG10; --#else -- sensor->pix.pixelformat = V4L2_PIX_FMT_YUYV; --#endif -- err = v4l2_int_device_register(sensor->v4l2_int_device); -- if (err) -- i2c_set_clientdata(client, NULL); -- return err; --} -- --/** -- * mt9t111_remove - sensor driver i2c remove handler -- * @client: i2c driver client device structure -- * -- * Unregister sensor as an i2c client device and V4L2 -- * device. Complement of mt9t111_probe(). -- */ --static int __exit --mt9t111_remove(struct i2c_client *client) --{ -- struct mt9t111_sensor *sensor = i2c_get_clientdata(client); -- -- if (!client->adapter) -- return -ENODEV; /* our client isn't attached */ -- -- v4l2_int_device_unregister(sensor->v4l2_int_device); -- i2c_set_clientdata(client, NULL); -- -- return 0; --} -- --static const struct i2c_device_id mt9t111_id[] = { -- { "mt9t111", 0 }, -- { }, --}; --MODULE_DEVICE_TABLE(i2c, mt9t111_id); -- --static struct i2c_driver mt9t111sensor_i2c_driver = { -- .driver = { -- .name = "mt9t111", -- .owner = THIS_MODULE, -- }, -- .probe = mt9t111_probe, -- .remove = __exit_p(mt9t111_remove), -- .id_table = mt9t111_id, --}; -- --/** -- * mt9t111sensor_init - sensor driver module_init handler -- * -- * Registers driver as an i2c client driver. Returns 0 on success, -- * error code otherwise. -- */ --static int __init mt9t111sensor_init(void) --{ --printk(KERN_INFO "entering mt9t111sensor_init\n"); -- return i2c_add_driver(&mt9t111sensor_i2c_driver); --} --module_init(mt9t111sensor_init); -- --/** -- * mt9t111sensor_cleanup - sensor driver module_exit handler -- * -- * Unregisters/deletes driver as an i2c client driver. -- * Complement of mt9t111sensor_init. -- */ --static void __exit mt9t111sensor_cleanup(void) --{ -- i2c_del_driver(&mt9t111sensor_i2c_driver); --} --module_exit(mt9t111sensor_cleanup); -- --MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("mt9t111 camera sensor driver"); -diff --git a/drivers/media/video/mt9t111_reg.h b/drivers/media/video/mt9t111_reg.h -deleted file mode 100644 -index e226c37..0000000 ---- a/drivers/media/video/mt9t111_reg.h -+++ /dev/null -@@ -1,1364 +0,0 @@ --/* -- * drivers/media/video/mt9t111_reg.h -- * -- * mt9t111 sensor driver header file -- * -- * Copyright (C) 2009 Leopard Imaging -- * -- * This file is licensed under the terms of the GNU General Public License -- * version 2. This program is licensed "as is" without any warranty of any -- * kind, whether express or implied. -- */ -- --#ifndef MT9T111_REG_H --#define MT9T111_REG_H -- --/* register addr */ --#define MT9T111_CHIP_ID (0x0000) -- --/* register value */ --#define MT9T111_CHIP_ID_VALUE (0x2680) -- --typedef struct { -- u16 delay_time; -- u16 addr; -- u16 data; --} mt9t111_regs; -- --mt9t111_regs patch_rev6[] = { -- {0, 0x0982, 0x0}, -- {0, 0x098A, 0xCE7}, -- {0, 0x0990, 0x3C3C}, -- {0, 0x0992, 0x3C3C}, -- {0, 0x0994, 0x3C5F}, -- {0, 0x0996, 0x4F30}, -- {0, 0x0998, 0xED08}, -- {0, 0x099a, 0xBD61}, -- {0, 0x099c, 0xD5CE}, -- {0, 0x099e, 0x4CD}, -- {0, 0x098A, 0xCF7}, -- {0, 0x0990, 0x1F17}, -- {0, 0x0992, 0x211}, -- {0, 0x0994, 0xCC33}, -- {0, 0x0996, 0x2E30}, -- {0, 0x0998, 0xED02}, -- {0, 0x099a, 0xCCFF}, -- {0, 0x099c, 0xFDED}, -- {0, 0x099e, 0xCC}, -- {0, 0x098A, 0xD07}, -- {0, 0x0990, 0x2}, -- {0, 0x0992, 0xBD70}, -- {0, 0x0994, 0x6D18}, -- {0, 0x0996, 0xDE1F}, -- {0, 0x0998, 0x181F}, -- {0, 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-- {0, 0x0990, 0x00AB}, -- {0, 0x098E, 0xBC15}, -- {0, 0x0990, 0x00B6}, -- {0, 0x098E, 0xBC16}, -- {0, 0x0990, 0x00C1}, -- {0, 0x098E, 0xBC17}, -- {0, 0x0990, 0x00CB}, -- {0, 0x098E, 0xBC18}, -- {0, 0x0990, 0x00D5}, -- {0, 0x098E, 0xBC19}, -- {0, 0x0990, 0x00DE}, -- {0, 0x098E, 0xBC1A}, -- {0, 0x0990, 0x00E7}, -- {0, 0x098E, 0xBC1B}, -- {0, 0x0990, 0x00EF}, -- {0, 0x098E, 0xBC1C}, -- {0, 0x0990, 0x00F7}, -- {0, 0x098E, 0xBC1D}, -- {0, 0x0990, 0x00FF}, -- {0, 0x098E, 0xBC1E}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0xBC1F}, -- {0, 0x0990, 0x001B}, -- {0, 0x098E, 0xBC20}, -- {0, 0x0990, 0x002A}, -- {0, 0x098E, 0xBC21}, -- {0, 0x0990, 0x003E}, -- {0, 0x098E, 0xBC22}, -- {0, 0x0990, 0x005A}, -- {0, 0x098E, 0xBC23}, -- {0, 0x0990, 0x0070}, -- {0, 0x098E, 0xBC24}, -- {0, 0x0990, 0x0081}, -- {0, 0x098E, 0xBC25}, -- {0, 0x0990, 0x0090}, -- {0, 0x098E, 0xBC26}, -- {0, 0x0990, 0x009E}, -- {0, 0x098E, 0xBC27}, -- {0, 0x0990, 0x00AB}, -- {0, 0x098E, 0xBC28}, -- {0, 0x0990, 0x00B6}, -- {0, 0x098E, 0xBC29}, -- {0, 0x0990, 0x00C1}, -- {0, 0x098E, 0xBC2A}, -- {0, 0x0990, 0x00CB}, -- {0, 0x098E, 0xBC2B}, -- {0, 0x0990, 0x00D5}, -- {0, 0x098E, 0xBC2C}, -- {0, 0x0990, 0x00DE}, -- {0, 0x098E, 0xBC2D}, -- {0, 0x0990, 0x00E7}, -- {0, 0x098E, 0xBC2E}, -- {0, 0x0990, 0x00EF}, -- {0, 0x098E, 0xBC2F}, -- {0, 0x0990, 0x00F7}, -- {0, 0x098E, 0xBC30}, -- {0, 0x0990, 0x00FF}, -- {0, 0x098E, 0xBC31}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0xBC32}, -- {0, 0x0990, 0x000D}, -- {0, 0x098E, 0xBC33}, -- {0, 0x0990, 0x0019}, -- {0, 0x098E, 0xBC34}, -- {0, 0x0990, 0x0030}, -- {0, 0x098E, 0xBC35}, -- {0, 0x0990, 0x0056}, -- {0, 0x098E, 0xBC36}, -- {0, 0x0990, 0x0070}, -- {0, 0x098E, 0xBC37}, -- {0, 0x0990, 0x0081}, -- {0, 0x098E, 0xBC38}, -- {0, 0x0990, 0x0090}, -- {0, 0x098E, 0xBC39}, -- {0, 0x0990, 0x009E}, -- {0, 0x098E, 0xBC3A}, -- {0, 0x0990, 0x00AB}, -- {0, 0x098E, 0xBC3B}, -- {0, 0x0990, 0x00B6}, -- {0, 0x098E, 0xBC3C}, -- {0, 0x0990, 0x00C1}, -- {0, 0x098E, 0xBC3D}, -- {0, 0x0990, 0x00CB}, -- {0, 0x098E, 0xBC3E}, -- {0, 0x0990, 0x00D5}, -- {0, 0x098E, 0xBC3F}, -- {0, 0x0990, 0x00DE}, -- {0, 0x098E, 0xBC40}, -- {0, 0x0990, 0x00E7}, -- {0, 0x098E, 0xBC41}, -- {0, 0x0990, 0x00EF}, -- {0, 0x098E, 0xBC42}, -- {0, 0x0990, 0x00F7}, -- {0, 0x098E, 0xBC43}, -- {0, 0x0990, 0x00FF}, -- {0, 0x098E, 0x6865}, -- {0, 0x0990, 0x00E0}, -- {0, 0x098E, 0x6867}, -- {0, 0x0990, 0x00F4}, -- {0, 0x098E, 0x8400}, -- {0, 0x0990, 0x0006}, -- {0, 0x098E, 0xBC4A}, -- {0, 0x0990, 0x007F}, -- {0, 0x098E, 0xBC4B}, -- {0, 0x0990, 0x007F}, -- {0, 0x098E, 0xBC4C}, -- {0, 0x0990, 0x007F}, -- {0, 0x3542, 0x0010}, -- {0, 0x3544, 0x0030}, -- {0, 0x3546, 0x0040}, -- {0, 0x3548, 0x0080}, -- {0, 0x354A, 0x0100}, -- {0, 0x354C, 0x0200}, -- {0, 0x354E, 0x0300}, -- {0, 0x3550, 0x0010}, -- {0, 0x3552, 0x0030}, -- {0, 0x3554, 0x0040}, -- {0, 0x3556, 0x0080}, -- {0, 0x3558, 0x012C}, -- {0, 0x355A, 0x0320}, -- {0, 0x355C, 0x03E8}, -- {0, 0x3560, 0x0040}, -- {0, 0x3562, 0x0020}, -- {0, 0x3564, 0x0040}, -- {0, 0x3566, 0x0010}, -- {0, 0x3568, 0x0008}, -- {0, 0x356A, 0x0004}, -- {0, 0x356C, 0x0004}, -- {0, 0x356E, 0x0004}, -- {0, 0x098E, 0x3C4D}, -- {0, 0x0990, 0x0DAC}, -- {0, 0x098E, 0x3C4F}, -- {0, 0x0990, 0x148A}, -- {0, 0x098E, 0xC911}, -- {0, 0x0990, 0x00C8}, -- {0, 0x098E, 0xC8F4}, -- {0, 0x0990, 0x0004}, -- {0, 0x098E, 0xC8F5}, -- {0, 0x0990, 0x0002}, -- {0, 0x098E, 0x48F6}, -- {0, 0x0990, 0x3B4D}, -- {0, 0x098E, 0x48F8}, -- {0, 0x0990, 0x6380}, -- {0, 0x098E, 0x48FA}, -- {0, 0x0990, 0x9B18}, -- {0, 0x098E, 0x48FC}, -- {0, 0x0990, 0x5D51}, -- {0, 0x098E, 0x48FE}, -- {0, 0x0990, 0xEDE8}, -- {0, 0x098E, 0x4900}, -- {0, 0x0990, 0xE515}, -- {0, 0x098E, 0x4902}, -- {0, 0x0990, 0xBFF4}, -- {0, 0x098E, 0x4904}, -- {0, 0x0990, 0x001E}, -- {0, 0x098E, 0x4906}, -- {0, 0x0990, 0x0026}, -- {0, 0x098E, 0x4908}, -- {0, 0x0990, 0x0033}, -- {0, 0x098E, 0xE84A}, -- {0, 0x0990, 0x0083}, -- {0, 0x098E, 0xE84D}, -- {0, 0x0990, 0x0083}, -- {0, 0x098E, 0xE84C}, -- {0, 0x0990, 0x0080}, -- {0, 0x098E, 0xE84F}, -- {0, 0x0990, 0x0080}, -- {0, 0x098E, 0x8400}, -- {0, 0x0990, 0x0006}, -- {0, 0x098E, 0x48B0}, -- {0, 0x0990, 0x0180}, -- {0, 0x098E, 0x48B2}, -- {0, 0x0990, 0xFF7A}, -- {0, 0x098E, 0x48B4}, -- {0, 0x0990, 0x0018}, -- {0, 0x098E, 0x48B6}, -- {0, 0x0990, 0xFFCA}, -- {0, 0x098E, 0x48B8}, -- {0, 0x0990, 0x017C}, -- {0, 0x098E, 0x48BA}, -- {0, 0x0990, 0xFFCC}, -- {0, 0x098E, 0x48BC}, -- {0, 0x0990, 0x000C}, -- {0, 0x098E, 0x48BE}, -- {0, 0x0990, 0xFF1F}, -- {0, 0x098E, 0x48C0}, -- {0, 0x0990, 0x01E8}, -- {0, 0x098E, 0x48C2}, -- {0, 0x0990, 0x0020}, -- {0, 0x098E, 0x48C4}, -- {0, 0x0990, 0x0044}, -- {0, 0x098E, 0x48C6}, -- {0, 0x0990, 0x0079}, -- {0, 0x098E, 0x48C8}, -- {0, 0x0990, 0xFFAD}, -- {0, 0x098E, 0x48CA}, -- {0, 0x0990, 0xFFE2}, -- {0, 0x098E, 0x48CC}, -- {0, 0x0990, 0x0033}, -- {0, 0x098E, 0x48CE}, -- {0, 0x0990, 0x002A}, -- {0, 0x098E, 0x48D0}, -- {0, 0x0990, 0xFFAA}, -- {0, 0x098E, 0x48D2}, -- {0, 0x0990, 0x0017}, -- {0, 0x098E, 0x48D4}, -- {0, 0x0990, 0x004B}, -- {0, 0x098E, 0x48D6}, -- {0, 0x0990, 0xFFA5}, -- {0, 0x098E, 0x48D8}, -- {0, 0x0990, 0x0015}, -- {0, 0x098E, 0x48DA}, -- {0, 0x0990, 0xFFE2}, -- {0, 0x35A2, 0x0014}, -- {0, 0x098E, 0xC949}, -- {0, 0x0990, 0x0024}, -- {0, 0x35A4, 0x0596}, -- {0, 0x098E, 0xC94A}, -- {0, 0x0990, 0x0062}, -- {0, 0x098E, 0xC948}, -- {0, 0x0990, 0x0006}, -- {0, 0x098E, 0xC914}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0xC915}, -- {0, 0x0990, 0x00FF}, -- {0, 0x098E, 0xE86F}, -- {0, 0x0990, 0x0060}, -- {0, 0x098E, 0xE870}, -- {0, 0x0990, 0x003C}, -- {0, 0x098E, 0xEC6F}, -- {0, 0x0990, 0x0060}, -- {0, 0x098E, 0xEC70}, -- {0, 0x0990, 0x003C}, -- {0, 0x098E, 0xE883}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0xEC83}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0x8400}, -- {0, 0x0990, 0x0006}, -- {0, 0x098E, 0xE885}, -- {0, 0x0990, 0x001E}, -- {0, 0x098E, 0xE886}, -- {0, 0x0990, 0x00D8}, -- {0, 0x098E, 0xEC85}, -- {0, 0x0990, 0x001E}, -- {0, 0x098E, 0xEC86}, -- {0, 0x0990, 0x00D8}, -- {0, 0x098E, 0xE884}, -- {0, 0x0990, 0x005C}, -- {0, 0x098E, 0xEC84}, -- {0, 0x0990, 0x005C}, -- {0, 0x098E, 0x490A}, -- {0, 0x0990, 0x0666}, -- {0, 0x098E, 0x490C}, -- {0, 0x0990, 0x0140}, -- {0, 0x098E, 0x6857}, -- {0, 0x0990, 0x0014}, -- {0, 0x098E, 0x685C}, -- {0, 0x0990, 0x0005}, -- {0, 0x098E, 0x490E}, -- {0, 0x0990, 0x00A4}, -- {0, 0x098E, 0xB43D}, -- {0, 0x0990, 0x0031}, -- {0, 0x098E, 0xB43E}, -- {0, 0x0990, 0x001B}, -- {0, 0x098E, 0xB43F}, -- {0, 0x0990, 0x0028}, -- {0, 0x098E, 0xB440}, -- {0, 0x0990, 0x0003}, -- {0, 0x098E, 0xB441}, -- {0, 0x0990, 0x00CD}, -- {0, 0x098E, 0xB442}, -- {0, 0x0990, 0x0064}, -- {0, 0x098E, 0xB443}, -- {0, 0x0990, 0x000F}, -- {0, 0x098E, 0xB444}, -- {0, 0x0990, 0x0007}, -- {0, 0x098E, 0x300D}, -- {0, 0x0990, 0x000F}, -- {0, 0x098E, 0x3017}, -- {0, 0x0990, 0x0F0F}, -- {0, 0x098E, 0x8400}, -- {0, 0x0990, 0x0006}, -- {0, 0x098E, 0xE81F}, -- {0, 0x0990, 0x0020}, -- {0, 0x098E, 0x68A0}, -- {0, 0x0990, 0x082E}, -- {0, 0x098E, 0x6CA0}, -- {0, 0x0990, 0x082E}, -- {0, 0x098E, 0x70A0}, -- {0, 0x0990, 0x082E}, -- {0, 0x098E, 0x74A0}, -- {0, 0x0990, 0x082E}, -- {0, 0x3C52, 0x082E}, -- {0, 0x098E, 0x488E}, -- {0, 0x0990, 0x0020}, -- {0, 0x098E, 0xECAC}, -- {0, 0x0990, 0x0000} --}; -- --mt9t111_regs def_regs2[] = { -- {100, 0x0018, 0x0028}, -- {0, 0x316C, 0x350F}, -- {0, 0x098E, 0x6817}, -- {0, 0x0990, 0x000C}, -- {0, 0x0034, 0x0000} --}; -- --mt9t111_regs pll_regs1[] = { -- {0, 0x0014, 0x2425}, -- {0, 0x0014, 0x2425}, -- {0, 0x0014, 0x2145}, -- {0, 0x0010, 0x0219}, -- {0, 0x0012, 0x0090}, -- {0, 0x002A, 0x79DD}, -- {0, 0x0014, 0x2545}, -- {0, 0x0014, 0x2547}, -- {0, 0x0014, 0x3447}, -- {0, 0x0014, 0x3047} --}; -- --mt9t111_regs pll_regs2[] = { -- {0, 0x0014, 0x3046}, -- {0, 0x0022, 0x01E0}, -- {0, 0x001E, 0x0707}, -- {0, 0x3B84, 0x011D} --}; -- --mt9t111_regs bayer_pattern_regs[] = { -- {0, 0x098E, 0x6807}, -- {0, 0x0990, 0x0100}, -- {0, 0x098E, 0x6809}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0xE88E}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0x6C07}, -- {0, 0x0990, 0x0100}, -- {0, 0x098E, 0x6C09}, -- {0, 0x0990, 0x0000}, -- {0, 0x098E, 0xEC8E}, -- {0, 0x0990, 0x0000} --}; -- --#endif -diff --git a/include/media/mt9t111.h b/include/media/mt9t111.h -deleted file mode 100644 -index cd34885..0000000 ---- a/include/media/mt9t111.h -+++ /dev/null -@@ -1,79 +0,0 @@ --/* -- * include/media/mt9t111.h -- * -- * mt9t111 sensor driver -- * -- * Copyright (C) 2009 Leopard Imaging -- * -- * This file is licensed under the terms of the GNU General Public License -- * version 2. This program is licensed "as is" without any warranty of any -- * kind, whether express or implied. -- */ -- --#ifndef MT9T111_H --#define MT9T111_H -- --/********************************* -- * Defines and Macros and globals -- ********************************/ -- --#ifdef TRUE --#undef TRUE --#endif -- --#ifdef FALSE --#undef FALSE --#endif -- --#define TRUE 1 --#define FALSE 0 -- --#ifdef DEBUG --#undef DEBUG --#endif -- --#ifndef TYPES --#define TYPES --#endif -- --#define MT9T111_I2C_REGISTERED (1) --#define MT9T111_I2C_UNREGISTERED (0) -- --/*i2c adress for MT9T111*/ --#define MT9T111_I2C_ADDR (0x78 >> 1) -- --#define MT9T111_CLK_MAX (54000000) /* 54MHz */ --#define MT9T111_CLK_MIN (6000000) /* 6Mhz */ -- --#define MT9T111_I2C_CONFIG (1) --#define I2C_ONE_BYTE_TRANSFER (1) --#define I2C_TWO_BYTE_TRANSFER (2) --#define I2C_THREE_BYTE_TRANSFER (3) --#define I2C_FOUR_BYTE_TRANSFER (4) --#define I2C_TXRX_DATA_MASK (0x00FF) --#define I2C_TXRX_DATA_MASK_UPPER (0xFF00) --#define I2C_TXRX_DATA_SHIFT (8) -- --struct mt9t111_platform_data { -- char *master; -- int (*power_set) (struct v4l2_int_device *s, enum v4l2_power on); -- int (*ifparm) (struct v4l2_ifparm *p); -- int (*priv_data_set) (void *); -- /* Interface control params */ -- bool clk_polarity; -- bool hs_polarity; -- bool vs_polarity; --}; -- --/** -- * struct capture_size - image capture size information -- * @width: image width in pixels -- * @height: image height in pixels -- */ --struct capture_size { -- unsigned long width; -- unsigned long height; --}; -- --#endif /*for ifndef MT9T111 */ -- --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0049-V4L-DVB-13670-soc-camera-Add-mt9t112-camera-driver.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0049-V4L-DVB-13670-soc-camera-Add-mt9t112-camera-driver.patch deleted file mode 100644 index b4ca4a6c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0049-V4L-DVB-13670-soc-camera-Add-mt9t112-camera-driver.patch +++ /dev/null @@ -1,1285 +0,0 @@ -From 1164e8b10b5237d1cf60c1e9752324b62f30a6bc Mon Sep 17 00:00:00 2001 -From: Kuninori Morimoto -Date: Fri, 11 Dec 2009 11:53:55 -0300 -Subject: [PATCH 49/75] V4L/DVB (13670): soc-camera: Add mt9t112 camera driver - -create mode 100644 drivers/media/video/mt9t112.c - create mode 100644 include/media/mt9t112.h - -Signed-off-by: Kuninori Morimoto -Signed-off-by: Guennadi Liakhovetski -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/video/Kconfig | 6 + - drivers/media/video/Makefile | 1 + - drivers/media/video/mt9t112.c | 1177 +++++++++++++++++++++++++++++++++++++++ - include/media/mt9t112.h | 30 + - include/media/v4l2-chip-ident.h | 2 + - 5 files changed, 1216 insertions(+), 0 deletions(-) - create mode 100644 drivers/media/video/mt9t112.c - create mode 100644 include/media/mt9t112.h - -diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig -index 780b246..7caade9 100644 ---- a/drivers/media/video/Kconfig -+++ b/drivers/media/video/Kconfig -@@ -832,6 +832,12 @@ config SOC_CAMERA_MT9T031 - help - This driver supports MT9T031 cameras from Micron. - -+config SOC_CAMERA_MT9T112 -+ tristate "mt9t112 support" -+ depends on SOC_CAMERA && I2C -+ help -+ This driver supports MT9T112 cameras from Aptina. -+ - config SOC_CAMERA_MT9V022 - tristate "mt9v022 support" - depends on SOC_CAMERA && I2C -diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile -index 3828723..61ae13f 100644 ---- a/drivers/media/video/Makefile -+++ b/drivers/media/video/Makefile -@@ -80,6 +80,7 @@ obj-$(CONFIG_VIDEO_MT9V113) += mt9v113.o - obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o - obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o - obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031.o -+obj-$(CONFIG_SOC_CAMERA_MT9T112) += mt9t112.o - obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o - obj-$(CONFIG_SOC_CAMERA_OV772X) += ov772x.o - obj-$(CONFIG_SOC_CAMERA_OV9640) += ov9640.o -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -new file mode 100644 -index 0000000..fc4dd60 ---- /dev/null -+++ b/drivers/media/video/mt9t112.c -@@ -0,0 +1,1177 @@ -+/* -+ * mt9t112 Camera Driver -+ * -+ * Copyright (C) 2009 Renesas Solutions Corp. -+ * Kuninori Morimoto -+ * -+ * Based on ov772x driver, mt9m111 driver, -+ * -+ * Copyright (C) 2008 Kuninori Morimoto -+ * Copyright (C) 2008, Robert Jarzmik -+ * Copyright 2006-7 Jonathan Corbet -+ * Copyright (C) 2008 Magnus Damm -+ * Copyright (C) 2008, Guennadi Liakhovetski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+/* you can check PLL/clock info */ -+/* #define EXT_CLOCK 24000000 */ -+ -+/************************************************************************ -+ -+ -+ macro -+ -+ -+************************************************************************/ -+/* -+ * frame size -+ */ -+#define MAX_WIDTH 2048 -+#define MAX_HEIGHT 1536 -+ -+#define VGA_WIDTH 640 -+#define VGA_HEIGHT 480 -+ -+/* -+ * macro of read/write -+ */ -+#define ECHECKER(ret, x) \ -+ do { \ -+ (ret) = (x); \ -+ if ((ret) < 0) \ -+ return (ret); \ -+ } while (0) -+ -+#define mt9t112_reg_write(ret, client, a, b) \ -+ ECHECKER(ret, __mt9t112_reg_write(client, a, b)) -+#define mt9t112_mcu_write(ret, client, a, b) \ -+ ECHECKER(ret, __mt9t112_mcu_write(client, a, b)) -+ -+#define mt9t112_reg_mask_set(ret, client, a, b, c) \ -+ ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c)) -+#define mt9t112_mcu_mask_set(ret, client, a, b, c) \ -+ ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c)) -+ -+#define mt9t112_reg_read(ret, client, a) \ -+ ECHECKER(ret, __mt9t112_reg_read(client, a)) -+ -+/* -+ * Logical address -+ */ -+#define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) -+#define VAR(id, offset) _VAR(id, offset, 0x0000) -+#define VAR8(id, offset) _VAR(id, offset, 0x8000) -+ -+/************************************************************************ -+ -+ -+ struct -+ -+ -+************************************************************************/ -+struct mt9t112_frame_size { -+ u16 width; -+ u16 height; -+}; -+ -+struct mt9t112_format { -+ enum v4l2_mbus_pixelcode code; -+ enum v4l2_colorspace colorspace; -+ u16 fmt; -+ u16 order; -+}; -+ -+struct mt9t112_priv { -+ struct v4l2_subdev subdev; -+ struct mt9t112_camera_info *info; -+ struct i2c_client *client; -+ struct soc_camera_device icd; -+ struct mt9t112_frame_size frame; -+ const struct mt9t112_format *format; -+ int model; -+ u32 flags; -+/* for flags */ -+#define INIT_DONE (1<<0) -+}; -+ -+/************************************************************************ -+ -+ -+ supported format -+ -+ -+************************************************************************/ -+ -+static const struct mt9t112_format mt9t112_cfmts[] = { -+ { -+ .code = V4L2_MBUS_FMT_YUYV8_2X8_BE, -+ .colorspace = V4L2_COLORSPACE_JPEG, -+ .fmt = 1, -+ .order = 0, -+ }, { -+ .code = V4L2_MBUS_FMT_YVYU8_2X8_BE, -+ .colorspace = V4L2_COLORSPACE_JPEG, -+ .fmt = 1, -+ .order = 1, -+ }, { -+ .code = V4L2_MBUS_FMT_YUYV8_2X8_LE, -+ .colorspace = V4L2_COLORSPACE_JPEG, -+ .fmt = 1, -+ .order = 2, -+ }, { -+ .code = V4L2_MBUS_FMT_YVYU8_2X8_LE, -+ .colorspace = V4L2_COLORSPACE_JPEG, -+ .fmt = 1, -+ .order = 3, -+ }, { -+ .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, -+ .colorspace = V4L2_COLORSPACE_SRGB, -+ .fmt = 8, -+ .order = 2, -+ }, { -+ .code = V4L2_MBUS_FMT_RGB565_2X8_LE, -+ .colorspace = V4L2_COLORSPACE_SRGB, -+ .fmt = 4, -+ .order = 2, -+ }, -+}; -+ -+/************************************************************************ -+ -+ -+ general function -+ -+ -+************************************************************************/ -+static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client) -+{ -+ return container_of(i2c_get_clientdata(client), -+ struct mt9t112_priv, -+ subdev); -+} -+ -+static int __mt9t112_reg_read(const struct i2c_client *client, u16 command) -+{ -+ struct i2c_msg msg[2]; -+ u8 buf[2]; -+ int ret; -+ -+ command = swab16(command); -+ -+ msg[0].addr = client->addr; -+ msg[0].flags = 0; -+ msg[0].len = 2; -+ msg[0].buf = (u8 *)&command; -+ -+ msg[1].addr = client->addr; -+ msg[1].flags = I2C_M_RD; -+ msg[1].len = 2; -+ msg[1].buf = buf; -+ -+ /* -+ * if return value of this function is < 0, -+ * it mean error. -+ * else, under 16bit is valid data. -+ */ -+ ret = i2c_transfer(client->adapter, msg, 2); -+ if (ret < 0) -+ return ret; -+ -+ memcpy(&ret, buf, 2); -+ return swab16(ret); -+} -+ -+static int __mt9t112_reg_write(const struct i2c_client *client, -+ u16 command, u16 data) -+{ -+ struct i2c_msg msg; -+ u8 buf[4]; -+ int ret; -+ -+ command = swab16(command); -+ data = swab16(data); -+ -+ memcpy(buf + 0, &command, 2); -+ memcpy(buf + 2, &data, 2); -+ -+ msg.addr = client->addr; -+ msg.flags = 0; -+ msg.len = 4; -+ msg.buf = buf; -+ -+ /* -+ * i2c_transfer return message length, -+ * but this function should return 0 if correct case -+ */ -+ ret = i2c_transfer(client->adapter, &msg, 1); -+ if (ret >= 0) -+ ret = 0; -+ -+ return ret; -+} -+ -+static int __mt9t112_reg_mask_set(const struct i2c_client *client, -+ u16 command, -+ u16 mask, -+ u16 set) -+{ -+ int val = __mt9t112_reg_read(client, command); -+ if (val < 0) -+ return val; -+ -+ val &= ~mask; -+ val |= set & mask; -+ -+ return __mt9t112_reg_write(client, command, val); -+} -+ -+/* mcu access */ -+static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command) -+{ -+ int ret; -+ -+ ret = __mt9t112_reg_write(client, 0x098E, command); -+ if (ret < 0) -+ return ret; -+ -+ return __mt9t112_reg_read(client, 0x0990); -+} -+ -+static int __mt9t112_mcu_write(const struct i2c_client *client, -+ u16 command, u16 data) -+{ -+ int ret; -+ -+ ret = __mt9t112_reg_write(client, 0x098E, command); -+ if (ret < 0) -+ return ret; -+ -+ return __mt9t112_reg_write(client, 0x0990, data); -+} -+ -+static int __mt9t112_mcu_mask_set(const struct i2c_client *client, -+ u16 command, -+ u16 mask, -+ u16 set) -+{ -+ int val = __mt9t112_mcu_read(client, command); -+ if (val < 0) -+ return val; -+ -+ val &= ~mask; -+ val |= set & mask; -+ -+ return __mt9t112_mcu_write(client, command, val); -+} -+ -+static int mt9t112_reset(const struct i2c_client *client) -+{ -+ int ret; -+ -+ mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001); -+ msleep(1); -+ mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000); -+ -+ return ret; -+} -+ -+#ifndef EXT_CLOCK -+#define CLOCK_INFO(a, b) -+#else -+#define CLOCK_INFO(a, b) mt9t112_clock_info(a, b) -+static int mt9t112_clock_info(const struct i2c_client *client, u32 ext) -+{ -+ int m, n, p1, p2, p3, p4, p5, p6, p7; -+ u32 vco, clk; -+ char *enable; -+ -+ ext /= 1000; /* kbyte order */ -+ -+ mt9t112_reg_read(n, client, 0x0012); -+ p1 = n & 0x000f; -+ n = n >> 4; -+ p2 = n & 0x000f; -+ n = n >> 4; -+ p3 = n & 0x000f; -+ -+ mt9t112_reg_read(n, client, 0x002a); -+ p4 = n & 0x000f; -+ n = n >> 4; -+ p5 = n & 0x000f; -+ n = n >> 4; -+ p6 = n & 0x000f; -+ -+ mt9t112_reg_read(n, client, 0x002c); -+ p7 = n & 0x000f; -+ -+ mt9t112_reg_read(n, client, 0x0010); -+ m = n & 0x00ff; -+ n = (n >> 8) & 0x003f; -+ -+ enable = ((6000 > ext) || (54000 < ext)) ? "X" : ""; -+ dev_info(&client->dev, "EXTCLK : %10u K %s\n", ext, enable); -+ -+ vco = 2 * m * ext / (n+1); -+ enable = ((384000 > vco) || (768000 < vco)) ? "X" : ""; -+ dev_info(&client->dev, "VCO : %10u K %s\n", vco, enable); -+ -+ clk = vco / (p1+1) / (p2+1); -+ enable = (96000 < clk) ? "X" : ""; -+ dev_info(&client->dev, "PIXCLK : %10u K %s\n", clk, enable); -+ -+ clk = vco / (p3+1); -+ enable = (768000 < clk) ? "X" : ""; -+ dev_info(&client->dev, "MIPICLK : %10u K %s\n", clk, enable); -+ -+ clk = vco / (p6+1); -+ enable = (96000 < clk) ? "X" : ""; -+ dev_info(&client->dev, "MCU CLK : %10u K %s\n", clk, enable); -+ -+ clk = vco / (p5+1); -+ enable = (54000 < clk) ? "X" : ""; -+ dev_info(&client->dev, "SOC CLK : %10u K %s\n", clk, enable); -+ -+ clk = vco / (p4+1); -+ enable = (70000 < clk) ? "X" : ""; -+ dev_info(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable); -+ -+ clk = vco / (p7+1); -+ dev_info(&client->dev, "External sensor : %10u K\n", clk); -+ -+ clk = ext / (n+1); -+ enable = ((2000 > clk) || (24000 < clk)) ? "X" : ""; -+ dev_info(&client->dev, "PFD : %10u K %s\n", clk, enable); -+ -+ return 0; -+} -+#endif -+ -+static void mt9t112_frame_check(u32 *width, u32 *height) -+{ -+ if (*width > MAX_WIDTH) -+ *width = MAX_WIDTH; -+ -+ if (*height > MAX_HEIGHT) -+ *height = MAX_HEIGHT; -+} -+ -+static int mt9t112_set_a_frame_size(const struct i2c_client *client, -+ u16 width, -+ u16 height) -+{ -+ int ret; -+ u16 wstart = (MAX_WIDTH - width) / 2; -+ u16 hstart = (MAX_HEIGHT - height) / 2; -+ -+ /* (Context A) Image Width/Height */ -+ mt9t112_mcu_write(ret, client, VAR(26, 0), width); -+ mt9t112_mcu_write(ret, client, VAR(26, 2), height); -+ -+ /* (Context A) Output Width/Height */ -+ mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); -+ mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height); -+ -+ /* (Context A) Start Row/Column */ -+ mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); -+ mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart); -+ -+ /* (Context A) End Row/Column */ -+ mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); -+ mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart); -+ -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); -+ -+ return ret; -+} -+ -+static int mt9t112_set_pll_dividers(const struct i2c_client *client, -+ u8 m, u8 n, -+ u8 p1, u8 p2, u8 p3, -+ u8 p4, u8 p5, u8 p6, -+ u8 p7) -+{ -+ int ret; -+ u16 val; -+ -+ /* N/M */ -+ val = (n << 8) | -+ (m << 0); -+ mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); -+ -+ /* P1/P2/P3 */ -+ val = ((p3 & 0x0F) << 8) | -+ ((p2 & 0x0F) << 4) | -+ ((p1 & 0x0F) << 0); -+ mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); -+ -+ /* P4/P5/P6 */ -+ val = (0x7 << 12) | -+ ((p6 & 0x0F) << 8) | -+ ((p5 & 0x0F) << 4) | -+ ((p4 & 0x0F) << 0); -+ mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); -+ -+ /* P7 */ -+ val = (0x1 << 12) | -+ ((p7 & 0x0F) << 0); -+ mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); -+ -+ return ret; -+} -+ -+static int mt9t112_init_pll(const struct i2c_client *client) -+{ -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ int data, i, ret; -+ -+ mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001); -+ -+ /* PLL control: BYPASS PLL = 8517 */ -+ mt9t112_reg_write(ret, client, 0x0014, 0x2145); -+ -+ /* Replace these registers when new timing parameters are generated */ -+ mt9t112_set_pll_dividers(client, -+ priv->info->divider.m, -+ priv->info->divider.n, -+ priv->info->divider.p1, -+ priv->info->divider.p2, -+ priv->info->divider.p3, -+ priv->info->divider.p4, -+ priv->info->divider.p5, -+ priv->info->divider.p6, -+ priv->info->divider.p7); -+ -+ /* -+ * TEST_BYPASS on -+ * PLL_ENABLE on -+ * SEL_LOCK_DET on -+ * TEST_BYPASS off -+ */ -+ mt9t112_reg_write(ret, client, 0x0014, 0x2525); -+ mt9t112_reg_write(ret, client, 0x0014, 0x2527); -+ mt9t112_reg_write(ret, client, 0x0014, 0x3427); -+ mt9t112_reg_write(ret, client, 0x0014, 0x3027); -+ -+ mdelay(10); -+ -+ /* -+ * PLL_BYPASS off -+ * Reference clock count -+ * I2C Master Clock Divider -+ */ -+ mt9t112_reg_write(ret, client, 0x0014, 0x3046); -+ mt9t112_reg_write(ret, client, 0x0022, 0x0190); -+ mt9t112_reg_write(ret, client, 0x3B84, 0x0212); -+ -+ /* External sensor clock is PLL bypass */ -+ mt9t112_reg_write(ret, client, 0x002E, 0x0500); -+ -+ mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002); -+ mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004); -+ -+ /* MCU disabled */ -+ mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004); -+ -+ /* out of standby */ -+ mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0); -+ -+ mdelay(50); -+ -+ /* -+ * Standby Workaround -+ * Disable Secondary I2C Pads -+ */ -+ mt9t112_reg_write(ret, client, 0x0614, 0x0001); -+ mdelay(1); -+ mt9t112_reg_write(ret, client, 0x0614, 0x0001); -+ mdelay(1); -+ mt9t112_reg_write(ret, client, 0x0614, 0x0001); -+ mdelay(1); -+ mt9t112_reg_write(ret, client, 0x0614, 0x0001); -+ mdelay(1); -+ mt9t112_reg_write(ret, client, 0x0614, 0x0001); -+ mdelay(1); -+ mt9t112_reg_write(ret, client, 0x0614, 0x0001); -+ mdelay(1); -+ -+ /* poll to verify out of standby. Must Poll this bit */ -+ for (i = 0; i < 100; i++) { -+ mt9t112_reg_read(data, client, 0x0018); -+ if (0x4000 & data) -+ break; -+ -+ mdelay(10); -+ } -+ -+ return ret; -+} -+ -+static int mt9t112_init_setting(const struct i2c_client *client) -+{ -+ -+ int ret; -+ -+ /* Adaptive Output Clock (A) */ -+ mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); -+ -+ /* Read Mode (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024); -+ -+ /* Fine Correction (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC); -+ -+ /* Fine IT Min (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1); -+ -+ /* Fine IT Max Margin (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF); -+ -+ /* Base Frame Lines (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D); -+ -+ /* Min Line Length (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a); -+ -+ /* Line Length (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0); -+ -+ /* Adaptive Output Clock (B) */ -+ mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); -+ -+ /* Row Start (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004); -+ -+ /* Column Start (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004); -+ -+ /* Row End (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B); -+ -+ /* Column End (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B); -+ -+ /* Fine Correction (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C); -+ -+ /* Fine IT Min (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1); -+ -+ /* Fine IT Max Margin (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF); -+ -+ /* Base Frame Lines (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668); -+ -+ /* Min Line Length (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0); -+ -+ /* Line Length (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0); -+ -+ /* -+ * Flicker Dectection registers -+ * This section should be replaced whenever new Timing file is generated -+ * All the following registers need to be replaced -+ * Following registers are generated from Register Wizard but user can -+ * modify them. For detail see auto flicker detection tuning -+ */ -+ -+ /* FD_FDPERIOD_SELECT */ -+ mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01); -+ -+ /* PRI_B_CONFIG_FD_ALGO_RUN */ -+ mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003); -+ -+ /* PRI_A_CONFIG_FD_ALGO_RUN */ -+ mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003); -+ -+ /* -+ * AFD range detection tuning registers -+ */ -+ -+ /* search_f1_50 */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25); -+ -+ /* search_f2_50 */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28); -+ -+ /* search_f1_60 */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C); -+ -+ /* search_f2_60 */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F); -+ -+ /* period_50Hz (A) */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA); -+ -+ /* secret register by aptina */ -+ /* period_50Hz (A MSB) */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00); -+ -+ /* period_60Hz (A) */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B); -+ -+ /* secret register by aptina */ -+ /* period_60Hz (A MSB) */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00); -+ -+ /* period_50Hz (B) */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82); -+ -+ /* secret register by aptina */ -+ /* period_50Hz (B) MSB */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00); -+ -+ /* period_60Hz (B) */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D); -+ -+ /* secret register by aptina */ -+ /* period_60Hz (B) MSB */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00); -+ -+ /* FD Mode */ -+ mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10); -+ -+ /* Stat_min */ -+ mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02); -+ -+ /* Stat_max */ -+ mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03); -+ -+ /* Min_amplitude */ -+ mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A); -+ -+ /* RX FIFO Watermark (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014); -+ -+ /* RX FIFO Watermark (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014); -+ -+ /* MCLK: 16MHz -+ * PCLK: 73MHz -+ * CorePixCLK: 36.5 MHz -+ */ -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108); -+ -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35); -+ -+ return ret; -+} -+ -+static int mt9t112_auto_focus_setting(const struct i2c_client *client) -+{ -+ int ret; -+ -+ mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F); -+ mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F); -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); -+ -+ mt9t112_reg_write(ret, client, 0x0614, 0x0000); -+ -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); -+ mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02); -+ mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002); -+ mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001); -+ mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025); -+ mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193); -+ mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18); -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); -+ -+ return ret; -+} -+ -+static int mt9t112_auto_focus_trigger(const struct i2c_client *client) -+{ -+ int ret; -+ -+ mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01); -+ -+ return ret; -+} -+ -+static int mt9t112_init_camera(const struct i2c_client *client) -+{ -+ int ret; -+ -+ ECHECKER(ret, mt9t112_reset(client)); -+ -+ ECHECKER(ret, mt9t112_init_pll(client)); -+ -+ ECHECKER(ret, mt9t112_init_setting(client)); -+ -+ ECHECKER(ret, mt9t112_auto_focus_setting(client)); -+ -+ mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0); -+ -+ /* Analog setting B */ -+ mt9t112_reg_write(ret, client, 0x3084, 0x2409); -+ mt9t112_reg_write(ret, client, 0x3092, 0x0A49); -+ mt9t112_reg_write(ret, client, 0x3094, 0x4949); -+ mt9t112_reg_write(ret, client, 0x3096, 0x4950); -+ -+ /* -+ * Disable adaptive clock -+ * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR -+ * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR -+ */ -+ mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E); -+ mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E); -+ -+ /* Configure STatus in Status_before_length Format and enable header */ -+ /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ -+ mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4); -+ -+ /* Enable JPEG in context B */ -+ /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ -+ mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01); -+ -+ /* Disable Dac_TXLO */ -+ mt9t112_reg_write(ret, client, 0x316C, 0x350F); -+ -+ /* Set max slew rates */ -+ mt9t112_reg_write(ret, client, 0x1E, 0x777); -+ -+ return ret; -+} -+ -+/************************************************************************ -+ -+ -+ soc_camera_ops -+ -+ -+************************************************************************/ -+static int mt9t112_set_bus_param(struct soc_camera_device *icd, -+ unsigned long flags) -+{ -+ return 0; -+} -+ -+static unsigned long mt9t112_query_bus_param(struct soc_camera_device *icd) -+{ -+ struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ struct soc_camera_link *icl = to_soc_camera_link(icd); -+ unsigned long flags = SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH | -+ SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH; -+ -+ flags |= (priv->info->flags & MT9T112_FLAG_PCLK_RISING_EDGE) ? -+ SOCAM_PCLK_SAMPLE_RISING : SOCAM_PCLK_SAMPLE_FALLING; -+ -+ if (priv->info->flags & MT9T112_FLAG_DATAWIDTH_8) -+ flags |= SOCAM_DATAWIDTH_8; -+ else -+ flags |= SOCAM_DATAWIDTH_10; -+ -+ return soc_camera_apply_sensor_flags(icl, flags); -+} -+ -+static struct soc_camera_ops mt9t112_ops = { -+ .set_bus_param = mt9t112_set_bus_param, -+ .query_bus_param = mt9t112_query_bus_param, -+}; -+ -+/************************************************************************ -+ -+ -+ v4l2_subdev_core_ops -+ -+ -+************************************************************************/ -+static int mt9t112_g_chip_ident(struct v4l2_subdev *sd, -+ struct v4l2_dbg_chip_ident *id) -+{ -+ struct i2c_client *client = sd->priv; -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ -+ id->ident = priv->model; -+ id->revision = 0; -+ -+ return 0; -+} -+ -+#ifdef CONFIG_VIDEO_ADV_DEBUG -+static int mt9t112_g_register(struct v4l2_subdev *sd, -+ struct v4l2_dbg_register *reg) -+{ -+ struct i2c_client *client = sd->priv; -+ int ret; -+ -+ reg->size = 2; -+ mt9t112_reg_read(ret, client, reg->reg); -+ -+ reg->val = (__u64)ret; -+ -+ return 0; -+} -+ -+static int mt9t112_s_register(struct v4l2_subdev *sd, -+ struct v4l2_dbg_register *reg) -+{ -+ struct i2c_client *client = sd->priv; -+ int ret; -+ -+ mt9t112_reg_write(ret, client, reg->reg, reg->val); -+ -+ return ret; -+} -+#endif -+ -+static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = { -+ .g_chip_ident = mt9t112_g_chip_ident, -+#ifdef CONFIG_VIDEO_ADV_DEBUG -+ .g_register = mt9t112_g_register, -+ .s_register = mt9t112_s_register, -+#endif -+}; -+ -+ -+/************************************************************************ -+ -+ -+ v4l2_subdev_video_ops -+ -+ -+************************************************************************/ -+static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable) -+{ -+ struct i2c_client *client = sd->priv; -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ int ret = 0; -+ -+ if (!enable) { -+ /* FIXME -+ * -+ * If user selected large output size, -+ * and used it long time, -+ * mt9t112 camera will be very warm. -+ * -+ * But current driver can not stop mt9t112 camera. -+ * So, set small size here to solve this problem. -+ */ -+ mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); -+ return ret; -+ } -+ -+ if (!(priv->flags & INIT_DONE)) { -+ u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & -+ priv->info->flags) ? 0x0001 : 0x0000; -+ -+ ECHECKER(ret, mt9t112_init_camera(client)); -+ -+ /* Invert PCLK (Data sampled on falling edge of pixclk) */ -+ mt9t112_reg_write(ret, client, 0x3C20, param); -+ -+ mdelay(5); -+ -+ priv->flags |= INIT_DONE; -+ } -+ -+ mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt); -+ mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order); -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); -+ -+ mt9t112_set_a_frame_size(client, -+ priv->frame.width, -+ priv->frame.height); -+ -+ ECHECKER(ret, mt9t112_auto_focus_trigger(client)); -+ -+ dev_dbg(&client->dev, "format : %d\n", priv->format->code); -+ dev_dbg(&client->dev, "size : %d x %d\n", -+ priv->frame.width, -+ priv->frame.height); -+ -+ CLOCK_INFO(client, EXT_CLOCK); -+ -+ return ret; -+} -+ -+static int mt9t112_set_params(struct i2c_client *client, u32 width, u32 height, -+ enum v4l2_mbus_pixelcode code) -+{ -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ int i; -+ -+ priv->format = NULL; -+ -+ /* -+ * frame size check -+ */ -+ mt9t112_frame_check(&width, &height); -+ -+ /* -+ * get color format -+ */ -+ for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++) -+ if (mt9t112_cfmts[i].code == code) -+ break; -+ -+ if (i == ARRAY_SIZE(mt9t112_cfmts)) -+ return -EINVAL; -+ -+ priv->frame.width = (u16)width; -+ priv->frame.height = (u16)height; -+ -+ priv->format = mt9t112_cfmts + i; -+ -+ return 0; -+} -+ -+static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) -+{ -+ a->bounds.left = 0; -+ a->bounds.top = 0; -+ a->bounds.width = VGA_WIDTH; -+ a->bounds.height = VGA_HEIGHT; -+ a->defrect = a->bounds; -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ a->pixelaspect.numerator = 1; -+ a->pixelaspect.denominator = 1; -+ -+ return 0; -+} -+ -+static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) -+{ -+ a->c.left = 0; -+ a->c.top = 0; -+ a->c.width = VGA_WIDTH; -+ a->c.height = VGA_HEIGHT; -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ return 0; -+} -+ -+static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) -+{ -+ struct i2c_client *client = sd->priv; -+ struct v4l2_rect *rect = &a->c; -+ -+ return mt9t112_set_params(client, rect->width, rect->height, -+ V4L2_MBUS_FMT_YUYV8_2X8_BE); -+} -+ -+static int mt9t112_g_fmt(struct v4l2_subdev *sd, -+ struct v4l2_mbus_framefmt *mf) -+{ -+ struct i2c_client *client = sd->priv; -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ -+ if (!priv->format) { -+ int ret = mt9t112_set_params(client, VGA_WIDTH, VGA_HEIGHT, -+ V4L2_MBUS_FMT_YUYV8_2X8_BE); -+ if (ret < 0) -+ return ret; -+ } -+ -+ mf->width = priv->frame.width; -+ mf->height = priv->frame.height; -+ /* TODO: set colorspace */ -+ mf->code = priv->format->code; -+ mf->field = V4L2_FIELD_NONE; -+ -+ return 0; -+} -+ -+static int mt9t112_s_fmt(struct v4l2_subdev *sd, -+ struct v4l2_mbus_framefmt *mf) -+{ -+ struct i2c_client *client = sd->priv; -+ -+ /* TODO: set colorspace */ -+ return mt9t112_set_params(client, mf->width, mf->height, mf->code); -+} -+ -+static int mt9t112_try_fmt(struct v4l2_subdev *sd, -+ struct v4l2_mbus_framefmt *mf) -+{ -+ mt9t112_frame_check(&mf->width, &mf->height); -+ -+ /* TODO: set colorspace */ -+ mf->field = V4L2_FIELD_NONE; -+ -+ return 0; -+} -+ -+static int mt9t112_enum_fmt(struct v4l2_subdev *sd, int index, -+ enum v4l2_mbus_pixelcode *code) -+{ -+ if ((unsigned int)index >= ARRAY_SIZE(mt9t112_cfmts)) -+ return -EINVAL; -+ -+ *code = mt9t112_cfmts[index].code; -+ return 0; -+} -+ -+static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { -+ .s_stream = mt9t112_s_stream, -+ .g_mbus_fmt = mt9t112_g_fmt, -+ .s_mbus_fmt = mt9t112_s_fmt, -+ .try_mbus_fmt = mt9t112_try_fmt, -+ .cropcap = mt9t112_cropcap, -+ .g_crop = mt9t112_g_crop, -+ .s_crop = mt9t112_s_crop, -+ .enum_mbus_fmt = mt9t112_enum_fmt, -+}; -+ -+/************************************************************************ -+ -+ -+ i2c driver -+ -+ -+************************************************************************/ -+static struct v4l2_subdev_ops mt9t112_subdev_ops = { -+ .core = &mt9t112_subdev_core_ops, -+ .video = &mt9t112_subdev_video_ops, -+}; -+ -+static int mt9t112_camera_probe(struct soc_camera_device *icd, -+ struct i2c_client *client) -+{ -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ const char *devname; -+ int chipid; -+ -+ /* -+ * We must have a parent by now. And it cannot be a wrong one. -+ * So this entire test is completely redundant. -+ */ -+ if (!icd->dev.parent || -+ to_soc_camera_host(icd->dev.parent)->nr != icd->iface) -+ return -ENODEV; -+ -+ /* -+ * check and show chip ID -+ */ -+ mt9t112_reg_read(chipid, client, 0x0000); -+ -+ switch (chipid) { -+ case 0x2680: -+ devname = "mt9t111"; -+ priv->model = V4L2_IDENT_MT9T111; -+ break; -+ case 0x2682: -+ devname = "mt9t112"; -+ priv->model = V4L2_IDENT_MT9T112; -+ break; -+ default: -+ dev_err(&client->dev, "Product ID error %04x\n", chipid); -+ return -ENODEV; -+ } -+ -+ dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid); -+ -+ return 0; -+} -+ -+static int mt9t112_probe(struct i2c_client *client, -+ const struct i2c_device_id *did) -+{ -+ struct mt9t112_priv *priv; -+ struct soc_camera_device *icd = client->dev.platform_data; -+ struct soc_camera_link *icl; -+ int ret; -+ -+ if (!icd) { -+ dev_err(&client->dev, "mt9t112: missing soc-camera data!\n"); -+ return -EINVAL; -+ } -+ -+ icl = to_soc_camera_link(icd); -+ if (!icl || !icl->priv) -+ return -EINVAL; -+ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->info = icl->priv; -+ -+ v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops); -+ -+ icd->ops = &mt9t112_ops; -+ -+ ret = mt9t112_camera_probe(icd, client); -+ if (ret) { -+ icd->ops = NULL; -+ i2c_set_clientdata(client, NULL); -+ kfree(priv); -+ } -+ -+ return ret; -+} -+ -+static int mt9t112_remove(struct i2c_client *client) -+{ -+ struct mt9t112_priv *priv = to_mt9t112(client); -+ struct soc_camera_device *icd = client->dev.platform_data; -+ -+ icd->ops = NULL; -+ i2c_set_clientdata(client, NULL); -+ kfree(priv); -+ return 0; -+} -+ -+static const struct i2c_device_id mt9t112_id[] = { -+ { "mt9t112", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, mt9t112_id); -+ -+static struct i2c_driver mt9t112_i2c_driver = { -+ .driver = { -+ .name = "mt9t112", -+ }, -+ .probe = mt9t112_probe, -+ .remove = mt9t112_remove, -+ .id_table = mt9t112_id, -+}; -+ -+/************************************************************************ -+ -+ -+ module function -+ -+ -+************************************************************************/ -+static int __init mt9t112_module_init(void) -+{ -+ return i2c_add_driver(&mt9t112_i2c_driver); -+} -+ -+static void __exit mt9t112_module_exit(void) -+{ -+ i2c_del_driver(&mt9t112_i2c_driver); -+} -+ -+module_init(mt9t112_module_init); -+module_exit(mt9t112_module_exit); -+ -+MODULE_DESCRIPTION("SoC Camera driver for mt9t112"); -+MODULE_AUTHOR("Kuninori Morimoto"); -+MODULE_LICENSE("GPL v2"); -diff --git a/include/media/mt9t112.h b/include/media/mt9t112.h -new file mode 100644 -index 0000000..a43c74a ---- /dev/null -+++ b/include/media/mt9t112.h -@@ -0,0 +1,30 @@ -+/* mt9t112 Camera -+ * -+ * Copyright (C) 2009 Renesas Solutions Corp. -+ * Kuninori Morimoto -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef __MT9T112_H__ -+#define __MT9T112_H__ -+ -+#define MT9T112_FLAG_PCLK_RISING_EDGE (1 << 0) -+#define MT9T112_FLAG_DATAWIDTH_8 (1 << 1) /* default width is 10 */ -+ -+struct mt9t112_pll_divider { -+ u8 m, n; -+ u8 p1, p2, p3, p4, p5, p6, p7; -+}; -+ -+/* -+ * mt9t112 camera info -+ */ -+struct mt9t112_camera_info { -+ u32 flags; -+ struct mt9t112_pll_divider divider; -+}; -+ -+#endif /* __MT9T112_H__ */ -diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h -index 91942db..6cc107d 100644 ---- a/include/media/v4l2-chip-ident.h -+++ b/include/media/v4l2-chip-ident.h -@@ -267,6 +267,8 @@ enum { - V4L2_IDENT_MT9V022IX7ATC = 45010, /* No way to detect "normal" I77ATx */ - V4L2_IDENT_MT9V022IX7ATM = 45015, /* and "lead free" IA7ATx chips */ - V4L2_IDENT_MT9T031 = 45020, -+ V4L2_IDENT_MT9T111 = 45021, -+ V4L2_IDENT_MT9T112 = 45022, - V4L2_IDENT_MT9V111 = 45031, - V4L2_IDENT_MT9V112 = 45032, - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0050-soc-camera-mt9t112-modify-exiting-conditions-from-st.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0050-soc-camera-mt9t112-modify-exiting-conditions-from-st.patch deleted file mode 100644 index 551717dd..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0050-soc-camera-mt9t112-modify-exiting-conditions-from-st.patch +++ /dev/null @@ -1,31 +0,0 @@ -From eb14ff193fa8cbe52f47349c0aeca2d91ea5cfd8 Mon Sep 17 00:00:00 2001 -From: Kuninori Morimoto -Date: Tue, 2 Feb 2010 13:17:54 +0900 -Subject: [PATCH 50/75] soc-camera: mt9t112: modify exiting conditions from standby mode - -This polling is needed if camera is in standby mode, but current exiting -condition is inverted. - -Signed-off-by: Kuninori Morimoto -Signed-off-by: Guennadi Liakhovetski -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/video/mt9t112.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index fc4dd60..7438f8d 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -514,7 +514,7 @@ static int mt9t112_init_pll(const struct i2c_client *client) - /* poll to verify out of standby. Must Poll this bit */ - for (i = 0; i < 100; i++) { - mt9t112_reg_read(data, client, 0x0018); -- if (0x4000 & data) -+ if (!(0x4000 & data)) - break; - - mdelay(10); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0051-mt9t112-Migrate-from-soc_camera-to-v4l2-int-device.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0051-mt9t112-Migrate-from-soc_camera-to-v4l2-int-device.patch deleted file mode 100644 index 0c3b7af2..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0051-mt9t112-Migrate-from-soc_camera-to-v4l2-int-device.patch +++ /dev/null @@ -1,934 +0,0 @@ -From bd42ce1ffea1be835f54ac61bb7ea4e0cd99e7aa Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 1 Jul 2010 07:26:38 -0500 -Subject: [PATCH 51/75] mt9t112: Migrate from soc_camera to v4l2-int-device - -This is to use the driver with the old OMAP3 Camera-ISP platform. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/Kconfig | 12 +- - drivers/media/video/Makefile | 2 +- - drivers/media/video/mt9t112.c | 658 +++++++++++++++++++++++------------------ - include/media/mt9t112.h | 13 + - 4 files changed, 391 insertions(+), 294 deletions(-) - -diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig -index 7caade9..4c1fb0f 100644 ---- a/drivers/media/video/Kconfig -+++ b/drivers/media/video/Kconfig -@@ -354,6 +354,12 @@ config VIDEO_MT9P012 - MT9P012 camera. It is currently working with the TI OMAP3 - camera controller. - -+config VIDEO_MT9T112 -+ tristate "mt9t112 support" -+ depends on I2C && VIDEO_V4L2 -+ help -+ This driver supports MT9T112 cameras from Aptina. -+ - config VIDEO_DW9710 - tristate "Lens driver for DW9710" - depends on I2C && VIDEO_V4L2 -@@ -832,12 +838,6 @@ config SOC_CAMERA_MT9T031 - help - This driver supports MT9T031 cameras from Micron. - --config SOC_CAMERA_MT9T112 -- tristate "mt9t112 support" -- depends on SOC_CAMERA && I2C -- help -- This driver supports MT9T112 cameras from Aptina. -- - config SOC_CAMERA_MT9V022 - tristate "mt9v022 support" - depends on SOC_CAMERA && I2C -diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile -index 61ae13f..fb7e46c 100644 ---- a/drivers/media/video/Makefile -+++ b/drivers/media/video/Makefile -@@ -80,7 +80,6 @@ obj-$(CONFIG_VIDEO_MT9V113) += mt9v113.o - obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o - obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o - obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031.o --obj-$(CONFIG_SOC_CAMERA_MT9T112) += mt9t112.o - obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o - obj-$(CONFIG_SOC_CAMERA_OV772X) += ov772x.o - obj-$(CONFIG_SOC_CAMERA_OV9640) += ov9640.o -@@ -129,6 +128,7 @@ obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o - obj-y += isp/ - obj-$(CONFIG_VIDEO_OMAP3) += omap34xxcam.o - obj-$(CONFIG_VIDEO_MT9P012) += mt9p012.o -+obj-$(CONFIG_VIDEO_MT9T112) += mt9t112.o - obj-$(CONFIG_VIDEO_DW9710) += dw9710.o - obj-$(CONFIG_VIDEO_TPS61059) += tps61059.o - obj-$(CONFIG_VIDEO_OV3640) += ov3640.o -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 7438f8d..6f54394 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -25,10 +25,8 @@ - #include - - #include --#include --#include -+#include - #include --#include - - /* you can check PLL/clock info */ - /* #define EXT_CLOCK 24000000 */ -@@ -43,8 +41,8 @@ - /* - * frame size - */ --#define MAX_WIDTH 2048 --#define MAX_HEIGHT 1536 -+#define MAX_WIDTH 640 /* 2048 */ -+#define MAX_HEIGHT 480 /* 1536 */ - - #define VGA_WIDTH 640 - #define VGA_HEIGHT 480 -@@ -91,20 +89,12 @@ struct mt9t112_frame_size { - u16 height; - }; - --struct mt9t112_format { -- enum v4l2_mbus_pixelcode code; -- enum v4l2_colorspace colorspace; -- u16 fmt; -- u16 order; --}; -- - struct mt9t112_priv { -- struct v4l2_subdev subdev; -+ struct mt9t112_platform_data *pdata; -+ struct v4l2_int_device *v4l2_int_device; - struct mt9t112_camera_info *info; - struct i2c_client *client; -- struct soc_camera_device icd; -- struct mt9t112_frame_size frame; -- const struct mt9t112_format *format; -+ struct v4l2_pix_format pix; - int model; - u32 flags; - /* for flags */ -@@ -119,38 +109,42 @@ struct mt9t112_priv { - - ************************************************************************/ - --static const struct mt9t112_format mt9t112_cfmts[] = { -+const static struct v4l2_fmtdesc mt9t112_formats[] = { -+ { -+ .description = "YUYV (YUV 4:2:2), packed", -+ .pixelformat = V4L2_PIX_FMT_YUYV, -+ }, - { -- .code = V4L2_MBUS_FMT_YUYV8_2X8_BE, -- .colorspace = V4L2_COLORSPACE_JPEG, -- .fmt = 1, -- .order = 0, -- }, { -- .code = V4L2_MBUS_FMT_YVYU8_2X8_BE, -- .colorspace = V4L2_COLORSPACE_JPEG, -- .fmt = 1, -- .order = 1, -- }, { -- .code = V4L2_MBUS_FMT_YUYV8_2X8_LE, -- .colorspace = V4L2_COLORSPACE_JPEG, -- .fmt = 1, -- .order = 2, -- }, { -- .code = V4L2_MBUS_FMT_YVYU8_2X8_LE, -- .colorspace = V4L2_COLORSPACE_JPEG, -- .fmt = 1, -- .order = 3, -- }, { -- .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, -- .colorspace = V4L2_COLORSPACE_SRGB, -- .fmt = 8, -- .order = 2, -- }, { -- .code = V4L2_MBUS_FMT_RGB565_2X8_LE, -- .colorspace = V4L2_COLORSPACE_SRGB, -- .fmt = 4, -- .order = 2, -+ .description = "RGB555, le", -+ .pixelformat = V4L2_PIX_FMT_RGB555, - }, -+ { -+ .description = "RGB565, le", -+ .pixelformat = V4L2_PIX_FMT_RGB565, -+ }, -+}; -+ -+/************************************************************************ -+ -+ -+ supported sizes -+ -+ -+************************************************************************/ -+const static struct mt9t112_frame_size mt9t112_sizes[] = { -+ { 640, 480 }, -+ /* { 2048, 1536} */ -+}; -+ -+/************************************************************************ -+ -+ -+ supported sizes -+ -+ -+************************************************************************/ -+const struct v4l2_fract mt9t112_frameintervals[] = { -+ { .numerator = 1, .denominator = 10 } - }; - - /************************************************************************ -@@ -160,11 +154,32 @@ static const struct mt9t112_format mt9t112_cfmts[] = { - - - ************************************************************************/ --static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client) -+static u16 mt9t112_pixfmt_to_fmt(u32 pixelformat) - { -- return container_of(i2c_get_clientdata(client), -- struct mt9t112_priv, -- subdev); -+ switch (pixelformat) { -+ case V4L2_PIX_FMT_RGB555: -+ return 8; -+ case V4L2_PIX_FMT_RGB565: -+ return 4; -+ case V4L2_PIX_FMT_YUYV: -+ /* FALLTHROUGH */ -+ default: -+ return 1; -+ } -+} -+ -+static u16 mt9t112_pixfmt_to_order(u32 pixelformat) -+{ -+ switch (pixelformat) { -+ case V4L2_PIX_FMT_RGB555: -+ /* FALLTHROUGH */ -+ case V4L2_PIX_FMT_RGB565: -+ return 2; -+ case V4L2_PIX_FMT_YUYV: -+ /* FALLTHROUGH */ -+ default: -+ return 0; -+ } - } - - static int __mt9t112_reg_read(const struct i2c_client *client, u16 command) -@@ -438,7 +453,7 @@ static int mt9t112_set_pll_dividers(const struct i2c_client *client, - - static int mt9t112_init_pll(const struct i2c_client *client) - { -- struct mt9t112_priv *priv = to_mt9t112(client); -+ struct mt9t112_priv *priv = i2c_get_clientdata(client); - int data, i, ret; - - mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001); -@@ -757,167 +772,12 @@ static int mt9t112_init_camera(const struct i2c_client *client) - return ret; - } - --/************************************************************************ -- -- -- soc_camera_ops -- -- --************************************************************************/ --static int mt9t112_set_bus_param(struct soc_camera_device *icd, -- unsigned long flags) --{ -- return 0; --} -- --static unsigned long mt9t112_query_bus_param(struct soc_camera_device *icd) --{ -- struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd)); -- struct mt9t112_priv *priv = to_mt9t112(client); -- struct soc_camera_link *icl = to_soc_camera_link(icd); -- unsigned long flags = SOCAM_MASTER | SOCAM_VSYNC_ACTIVE_HIGH | -- SOCAM_HSYNC_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_HIGH; -- -- flags |= (priv->info->flags & MT9T112_FLAG_PCLK_RISING_EDGE) ? -- SOCAM_PCLK_SAMPLE_RISING : SOCAM_PCLK_SAMPLE_FALLING; -- -- if (priv->info->flags & MT9T112_FLAG_DATAWIDTH_8) -- flags |= SOCAM_DATAWIDTH_8; -- else -- flags |= SOCAM_DATAWIDTH_10; -- -- return soc_camera_apply_sensor_flags(icl, flags); --} -- --static struct soc_camera_ops mt9t112_ops = { -- .set_bus_param = mt9t112_set_bus_param, -- .query_bus_param = mt9t112_query_bus_param, --}; -- --/************************************************************************ -- -- -- v4l2_subdev_core_ops -- -- --************************************************************************/ --static int mt9t112_g_chip_ident(struct v4l2_subdev *sd, -- struct v4l2_dbg_chip_ident *id) --{ -- struct i2c_client *client = sd->priv; -- struct mt9t112_priv *priv = to_mt9t112(client); -- -- id->ident = priv->model; -- id->revision = 0; -- -- return 0; --} -- --#ifdef CONFIG_VIDEO_ADV_DEBUG --static int mt9t112_g_register(struct v4l2_subdev *sd, -- struct v4l2_dbg_register *reg) --{ -- struct i2c_client *client = sd->priv; -- int ret; -- -- reg->size = 2; -- mt9t112_reg_read(ret, client, reg->reg); -- -- reg->val = (__u64)ret; -- -- return 0; --} -- --static int mt9t112_s_register(struct v4l2_subdev *sd, -- struct v4l2_dbg_register *reg) --{ -- struct i2c_client *client = sd->priv; -- int ret; -- -- mt9t112_reg_write(ret, client, reg->reg, reg->val); -- -- return ret; --} --#endif -- --static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = { -- .g_chip_ident = mt9t112_g_chip_ident, --#ifdef CONFIG_VIDEO_ADV_DEBUG -- .g_register = mt9t112_g_register, -- .s_register = mt9t112_s_register, --#endif --}; -- -- --/************************************************************************ -- -- -- v4l2_subdev_video_ops -- -- --************************************************************************/ --static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable) --{ -- struct i2c_client *client = sd->priv; -- struct mt9t112_priv *priv = to_mt9t112(client); -- int ret = 0; -- -- if (!enable) { -- /* FIXME -- * -- * If user selected large output size, -- * and used it long time, -- * mt9t112 camera will be very warm. -- * -- * But current driver can not stop mt9t112 camera. -- * So, set small size here to solve this problem. -- */ -- mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); -- return ret; -- } -- -- if (!(priv->flags & INIT_DONE)) { -- u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & -- priv->info->flags) ? 0x0001 : 0x0000; -- -- ECHECKER(ret, mt9t112_init_camera(client)); -- -- /* Invert PCLK (Data sampled on falling edge of pixclk) */ -- mt9t112_reg_write(ret, client, 0x3C20, param); -- -- mdelay(5); -- -- priv->flags |= INIT_DONE; -- } -- -- mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt); -- mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order); -- mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); -- -- mt9t112_set_a_frame_size(client, -- priv->frame.width, -- priv->frame.height); -- -- ECHECKER(ret, mt9t112_auto_focus_trigger(client)); -- -- dev_dbg(&client->dev, "format : %d\n", priv->format->code); -- dev_dbg(&client->dev, "size : %d x %d\n", -- priv->frame.width, -- priv->frame.height); -- -- CLOCK_INFO(client, EXT_CLOCK); -- -- return ret; --} -- - static int mt9t112_set_params(struct i2c_client *client, u32 width, u32 height, -- enum v4l2_mbus_pixelcode code) -+ u32 pixelformat) - { -- struct mt9t112_priv *priv = to_mt9t112(client); -+ struct mt9t112_priv *priv = i2c_get_clientdata(client); - int i; - -- priv->format = NULL; -- - /* - * frame size check - */ -@@ -926,22 +786,23 @@ static int mt9t112_set_params(struct i2c_client *client, u32 width, u32 height, - /* - * get color format - */ -- for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++) -- if (mt9t112_cfmts[i].code == code) -+ for (i = 0; i < ARRAY_SIZE(mt9t112_formats); i++) -+ if (mt9t112_formats[i].pixelformat == pixelformat) - break; - -- if (i == ARRAY_SIZE(mt9t112_cfmts)) -+ if (i == ARRAY_SIZE(mt9t112_formats)) - return -EINVAL; - -- priv->frame.width = (u16)width; -- priv->frame.height = (u16)height; -+ priv->pix.width = (u16)width; -+ priv->pix.height = (u16)height; - -- priv->format = mt9t112_cfmts + i; -+ priv->pix.pixelformat = pixelformat; - - return 0; - } - --static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) -+static int mt9t112_v4l2_int_cropcap(struct v4l2_int_device *s, -+ struct v4l2_cropcap *a) - { - a->bounds.left = 0; - a->bounds.top = 0; -@@ -955,7 +816,8 @@ static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) - return 0; - } - --static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) -+static int mt9t112_v4l2_int_g_crop(struct v4l2_int_device *s, -+ struct v4l2_crop *a) - { - a->c.left = 0; - a->c.top = 0; -@@ -966,77 +828,116 @@ static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) - return 0; - } - --static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) -+static int mt9t112_v4l2_int_s_crop(struct v4l2_int_device *s, -+ struct v4l2_crop *a) - { -- struct i2c_client *client = sd->priv; -- struct v4l2_rect *rect = &a->c; -- -- return mt9t112_set_params(client, rect->width, rect->height, -- V4L2_MBUS_FMT_YUYV8_2X8_BE); -+ if ((a->c.left != 0) || -+ (a->c.top != 0) || -+ (a->c.width != VGA_WIDTH) || -+ (a->c.height != VGA_HEIGHT)) { -+ return -EINVAL; -+ } -+ return 0; - } - --static int mt9t112_g_fmt(struct v4l2_subdev *sd, -- struct v4l2_mbus_framefmt *mf) -+static int mt9t112_v4l2_int_g_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) - { -- struct i2c_client *client = sd->priv; -- struct mt9t112_priv *priv = to_mt9t112(client); -+ struct mt9t112_priv *priv = s->priv; -+ struct i2c_client *client = priv->client; - -- if (!priv->format) { -+ if ((priv->pix.pixelformat == 0) || -+ (priv->pix.width == 0) || -+ (priv->pix.height == 0)) { - int ret = mt9t112_set_params(client, VGA_WIDTH, VGA_HEIGHT, -- V4L2_MBUS_FMT_YUYV8_2X8_BE); -+ V4L2_PIX_FMT_YUYV); - if (ret < 0) - return ret; - } - -- mf->width = priv->frame.width; -- mf->height = priv->frame.height; -+ f->fmt.pix.width = priv->pix.width; -+ f->fmt.pix.height = priv->pix.height; - /* TODO: set colorspace */ -- mf->code = priv->format->code; -- mf->field = V4L2_FIELD_NONE; -+ f->fmt.pix.pixelformat = priv->pix.pixelformat; -+ f->fmt.pix.field = V4L2_FIELD_NONE; - - return 0; - } - --static int mt9t112_s_fmt(struct v4l2_subdev *sd, -- struct v4l2_mbus_framefmt *mf) -+ -+static int mt9t112_v4l2_int_s_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) - { -- struct i2c_client *client = sd->priv; -+ struct mt9t112_priv *priv = s->priv; -+ struct i2c_client *client = priv->client; - - /* TODO: set colorspace */ -- return mt9t112_set_params(client, mf->width, mf->height, mf->code); -+ return mt9t112_set_params(client, f->fmt.pix.width, f->fmt.pix.height, -+ f->fmt.pix.pixelformat); - } - --static int mt9t112_try_fmt(struct v4l2_subdev *sd, -- struct v4l2_mbus_framefmt *mf) -+static int mt9t112_v4l2_int_try_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) - { -- mt9t112_frame_check(&mf->width, &mf->height); -+ mt9t112_frame_check(&f->fmt.pix.width, &f->fmt.pix.height); - - /* TODO: set colorspace */ -- mf->field = V4L2_FIELD_NONE; -+ f->fmt.pix.field = V4L2_FIELD_NONE; - - return 0; - } - --static int mt9t112_enum_fmt(struct v4l2_subdev *sd, int index, -- enum v4l2_mbus_pixelcode *code) -+static int mt9t112_v4l2_int_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) - { -- if ((unsigned int)index >= ARRAY_SIZE(mt9t112_cfmts)) -+ int index = fmt->index; -+ enum v4l2_buf_type type = fmt->type; -+ -+ memset(fmt, 0, sizeof(*fmt)); -+ fmt->index = index; -+ fmt->type = type; -+ -+ switch (fmt->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ if (index >= ARRAY_SIZE(mt9t112_formats)) -+ return -EINVAL; -+ break; -+ default: - return -EINVAL; -+ } - -- *code = mt9t112_cfmts[index].code; -+ fmt->flags = mt9t112_formats[index].flags; -+ strlcpy(fmt->description, mt9t112_formats[index].description, -+ sizeof(fmt->description)); -+ fmt->pixelformat = mt9t112_formats[index].pixelformat; - return 0; - } - --static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { -- .s_stream = mt9t112_s_stream, -- .g_mbus_fmt = mt9t112_g_fmt, -- .s_mbus_fmt = mt9t112_s_fmt, -- .try_mbus_fmt = mt9t112_try_fmt, -- .cropcap = mt9t112_cropcap, -- .g_crop = mt9t112_g_crop, -- .s_crop = mt9t112_s_crop, -- .enum_mbus_fmt = mt9t112_enum_fmt, --}; -+static int mt9t112_v4l2_int_s_parm(struct v4l2_int_device *s, -+ struct v4l2_streamparm *a) -+{ -+ /* TODO: set paramters */ -+ return 0; -+} -+ -+static int mt9t112_v4l2_int_g_parm(struct v4l2_int_device *s, -+ struct v4l2_streamparm *a) -+{ -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ -+ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; -+ -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ cparm->capability = V4L2_CAP_TIMEPERFRAME; -+ /* FIXME: Is 10 fps really the only option? */ -+ cparm->timeperframe.numerator = 1; -+ cparm->timeperframe.denominator = 10; -+ -+ return 0; -+} - - /************************************************************************ - -@@ -1045,27 +946,14 @@ static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { - - - ************************************************************************/ --static struct v4l2_subdev_ops mt9t112_subdev_ops = { -- .core = &mt9t112_subdev_core_ops, -- .video = &mt9t112_subdev_video_ops, --}; - --static int mt9t112_camera_probe(struct soc_camera_device *icd, -- struct i2c_client *client) -+static int mt9t112_detect(struct i2c_client *client) - { -- struct mt9t112_priv *priv = to_mt9t112(client); -+ struct mt9t112_priv *priv = i2c_get_clientdata(client); - const char *devname; - int chipid; - - /* -- * We must have a parent by now. And it cannot be a wrong one. -- * So this entire test is completely redundant. -- */ -- if (!icd->dev.parent || -- to_soc_camera_host(icd->dev.parent)->nr != icd->iface) -- return -ENODEV; -- -- /* - * check and show chip ID - */ - mt9t112_reg_read(chipid, client, 0x0000); -@@ -1089,37 +977,232 @@ static int mt9t112_camera_probe(struct soc_camera_device *icd, - return 0; - } - -+static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, -+ enum v4l2_power power) -+{ -+ struct mt9t112_priv *priv = s->priv; -+ struct i2c_client *client = priv->client; -+ int ret; -+ -+ switch (power) { -+ case V4L2_POWER_STANDBY: -+ /* FALLTHROUGH */ -+ case V4L2_POWER_OFF: -+ /* FIXME -+ * -+ * If user selected large output size, -+ * and used it long time, -+ * mt9t112 camera will be very warm. -+ * -+ * But current driver can not stop mt9t112 camera. -+ * So, set small size here to solve this problem. -+ */ -+ mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); -+ -+ ret = priv->pdata->power_set(s, power); -+ if (ret < 0) { -+ dev_err(&client->dev, "Unable to set target board power " -+ "state (OFF/STANDBY)\n"); -+ return ret; -+ } -+ break; -+ case V4L2_POWER_ON: -+ ret = priv->pdata->power_set(s, power); -+ if (ret < 0) { -+ dev_err(&client->dev, "Unable to set target board power " -+ "state (ON)\n"); -+ return ret; -+ } -+ if (!(priv->flags & INIT_DONE)) { -+ u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & -+ priv->info->flags) ? 0x0001 : 0x0000; -+ -+ ECHECKER(ret, mt9t112_detect(client)); -+ ECHECKER(ret, mt9t112_init_camera(client)); -+ -+ /* Invert PCLK (Data sampled on falling edge of pixclk) */ -+ mt9t112_reg_write(ret, client, 0x3C20, param); -+ -+ mdelay(5); -+ -+ priv->flags |= INIT_DONE; -+ } -+ -+ mt9t112_mcu_write(ret, client, VAR(26, 7), -+ mt9t112_pixfmt_to_fmt(priv->pix.pixelformat)); -+ mt9t112_mcu_write(ret, client, VAR(26, 9), -+ mt9t112_pixfmt_to_order(priv->pix.pixelformat)); -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); -+ -+ mt9t112_set_a_frame_size(client, -+ priv->pix.width, -+ priv->pix.height); -+ -+ ECHECKER(ret, mt9t112_auto_focus_trigger(client)); -+ -+ dev_dbg(&client->dev, "format : %d\n", priv->pix.pixelformat); -+ dev_dbg(&client->dev, "size : %d x %d\n", -+ priv->pix.width, -+ priv->pix.height); -+ -+ CLOCK_INFO(client, EXT_CLOCK); -+ } -+ return 0; -+} -+ -+static int mt9t112_v4l2_int_g_priv(struct v4l2_int_device *s, void *p) -+{ -+ struct mt9t112_priv *priv = s->priv; -+ -+ return priv->pdata->priv_data_set(p); -+} -+ -+static int mt9t112_v4l2_int_g_ifparm(struct v4l2_int_device *s, -+ struct v4l2_ifparm *p) -+{ -+ struct mt9t112_priv *priv = s->priv; -+ int rval; -+ -+ if (p == NULL) -+ return -EINVAL; -+ -+ if (!priv->pdata->ifparm) -+ return -EINVAL; -+ -+ rval = priv->pdata->ifparm(p); -+ if (rval) { -+ v4l_err(priv->client, "g_ifparm.Err[%d]\n", rval); -+ return rval; -+ } -+ -+ p->u.ycbcr.clock_curr = 40 * 1000000; /* temporal value */ -+ -+ return 0; -+} -+ -+static int mt9t112_v4l2_int_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *frms) -+{ -+ int ifmt; -+ -+ for (ifmt = 0; ifmt < ARRAY_SIZE(mt9t112_formats); ifmt++) -+ if (mt9t112_formats[ifmt].pixelformat == frms->pixel_format) -+ break; -+ -+ if (ifmt == ARRAY_SIZE(mt9t112_formats)) -+ return -EINVAL; -+ -+ /* Do we already reached all discrete framesizes? */ -+ if (frms->index >= ARRAY_SIZE(mt9t112_sizes)) -+ return -EINVAL; -+ -+ frms->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frms->discrete.width = mt9t112_sizes[frms->index].width; -+ frms->discrete.height = mt9t112_sizes[frms->index].height; -+ -+ return 0; -+ -+} -+ -+static int mt9t112_v4l2_int_enum_frameintervals(struct v4l2_int_device *s, -+ struct v4l2_frmivalenum *frmi) -+{ -+ int ifmt; -+ -+ for (ifmt = 0; ifmt < ARRAY_SIZE(mt9t112_formats); ifmt++) -+ if (mt9t112_formats[ifmt].pixelformat == frmi->pixel_format) -+ break; -+ -+ if (ifmt == ARRAY_SIZE(mt9t112_formats)) -+ return -EINVAL; -+ -+ if (frmi->index >= ARRAY_SIZE(mt9t112_frameintervals)) -+ return -EINVAL; -+ -+ frmi->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frmi->discrete.numerator = -+ mt9t112_frameintervals[frmi->index].numerator; -+ frmi->discrete.denominator = -+ mt9t112_frameintervals[frmi->index].denominator; -+ return 0; -+} -+ -+static struct v4l2_int_ioctl_desc mt9t112_ioctl_desc[] = { -+ { .num = vidioc_int_enum_framesizes_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_enum_framesizes }, -+ { .num = vidioc_int_enum_frameintervals_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_enum_frameintervals }, -+ { .num = vidioc_int_s_power_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_s_power }, -+ { .num = vidioc_int_g_priv_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_g_priv }, -+ { .num = vidioc_int_g_ifparm_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_g_ifparm }, -+ { .num = vidioc_int_enum_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_enum_fmt_cap }, -+ { .num = vidioc_int_try_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_try_fmt_cap }, -+ { .num = vidioc_int_g_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_g_fmt_cap }, -+ { .num = vidioc_int_s_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_s_fmt_cap }, -+ { .num = vidioc_int_g_parm_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_g_parm }, -+ { .num = vidioc_int_s_parm_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_s_parm }, -+ { .num = vidioc_int_cropcap_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_cropcap }, -+ { .num = vidioc_int_g_crop_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_g_crop }, -+ { .num = vidioc_int_s_crop_num, -+ .func = (v4l2_int_ioctl_func *)mt9t112_v4l2_int_s_crop }, -+}; -+ -+static struct v4l2_int_slave mt9t112_slave = { -+ .ioctls = mt9t112_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(mt9t112_ioctl_desc), -+}; -+ - static int mt9t112_probe(struct i2c_client *client, - const struct i2c_device_id *did) - { - struct mt9t112_priv *priv; -- struct soc_camera_device *icd = client->dev.platform_data; -- struct soc_camera_link *icl; -+ struct v4l2_int_device *v4l2_int_device; - int ret; - -- if (!icd) { -- dev_err(&client->dev, "mt9t112: missing soc-camera data!\n"); -- return -EINVAL; -+ if (!client->dev.platform_data) { -+ dev_err(&client->dev, "no platform data?\n"); -+ return -ENODEV; - } - -- icl = to_soc_camera_link(icd); -- if (!icl || !icl->priv) -- return -EINVAL; -- - priv = kzalloc(sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - -- priv->info = icl->priv; -+ v4l2_int_device = kzalloc(sizeof(*v4l2_int_device), GFP_KERNEL); -+ if (!v4l2_int_device) { -+ kfree(priv); -+ return -ENOMEM; -+ } - -- v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops); -+ v4l2_int_device->module = THIS_MODULE; -+ strncpy(v4l2_int_device->name, "mt9t112", sizeof(v4l2_int_device->name)); -+ v4l2_int_device->type = v4l2_int_type_slave; -+ v4l2_int_device->u.slave = &mt9t112_slave; -+ v4l2_int_device->priv = priv; - -- icd->ops = &mt9t112_ops; -+ priv->v4l2_int_device = v4l2_int_device; -+ priv->client = client; -+ priv->pdata = client->dev.platform_data; - -- ret = mt9t112_camera_probe(icd, client); -+ i2c_set_clientdata(client, priv); -+ -+ //ret = mt9t112_detect(client); -+ -+ ret = v4l2_int_device_register(priv->v4l2_int_device); - if (ret) { -- icd->ops = NULL; - i2c_set_clientdata(client, NULL); -+ kfree(v4l2_int_device); - kfree(priv); - } - -@@ -1128,11 +1211,12 @@ static int mt9t112_probe(struct i2c_client *client, - - static int mt9t112_remove(struct i2c_client *client) - { -- struct mt9t112_priv *priv = to_mt9t112(client); -- struct soc_camera_device *icd = client->dev.platform_data; -+ struct mt9t112_priv *priv = i2c_get_clientdata(client); - -- icd->ops = NULL; -+ v4l2_int_device_unregister(priv->v4l2_int_device); - i2c_set_clientdata(client, NULL); -+ -+ kfree(priv->v4l2_int_device); - kfree(priv); - return 0; - } -@@ -1172,6 +1256,6 @@ static void __exit mt9t112_module_exit(void) - module_init(mt9t112_module_init); - module_exit(mt9t112_module_exit); - --MODULE_DESCRIPTION("SoC Camera driver for mt9t112"); -+MODULE_DESCRIPTION("mt9t112 sensor driver"); - MODULE_AUTHOR("Kuninori Morimoto"); - MODULE_LICENSE("GPL v2"); -diff --git a/include/media/mt9t112.h b/include/media/mt9t112.h -index a43c74a..62caaf5 100644 ---- a/include/media/mt9t112.h -+++ b/include/media/mt9t112.h -@@ -11,6 +11,8 @@ - #ifndef __MT9T112_H__ - #define __MT9T112_H__ - -+#include -+ - #define MT9T112_FLAG_PCLK_RISING_EDGE (1 << 0) - #define MT9T112_FLAG_DATAWIDTH_8 (1 << 1) /* default width is 10 */ - -@@ -27,4 +29,15 @@ struct mt9t112_camera_info { - struct mt9t112_pll_divider divider; - }; - -+struct mt9t112_platform_data { -+ char *master; -+ int (*power_set) (struct v4l2_int_device *s, enum v4l2_power on); -+ int (*ifparm) (struct v4l2_ifparm *p); -+ int (*priv_data_set) (void *); -+ /* Interface control params */ -+ bool clk_polarity; -+ bool hs_polarity; -+ bool vs_polarity; -+}; -+ - #endif /* __MT9T112_H__ */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0052-mt9t112-Add-more-info-to-public-header.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0052-mt9t112-Add-more-info-to-public-header.patch deleted file mode 100644 index 3aeea03a..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0052-mt9t112-Add-more-info-to-public-header.patch +++ /dev/null @@ -1,29 +0,0 @@ -From d72241c7dc39f0976bcd7d05d43a86935e0deb68 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 1 Jul 2010 07:33:49 -0500 -Subject: [PATCH 52/75] mt9t112: Add more info to public header - -Signed-off-by: Sergio Aguirre ---- - include/media/mt9t112.h | 5 +++++ - 1 files changed, 5 insertions(+), 0 deletions(-) - -diff --git a/include/media/mt9t112.h b/include/media/mt9t112.h -index 62caaf5..49fa042 100644 ---- a/include/media/mt9t112.h -+++ b/include/media/mt9t112.h -@@ -13,6 +13,11 @@ - - #include - -+#define MT9T112_I2C_ADDR (0x78 >> 1) -+ -+#define MT9T112_CLK_MAX (54000000) /* 54MHz */ -+#define MT9T112_CLK_MIN (6000000) /* 6Mhz */ -+ - #define MT9T112_FLAG_PCLK_RISING_EDGE (1 << 0) - #define MT9T112_FLAG_DATAWIDTH_8 (1 << 1) /* default width is 10 */ - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0053-mt9t112-Fix-null-pointer-kernel-bug.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0053-mt9t112-Fix-null-pointer-kernel-bug.patch deleted file mode 100644 index d03795f5..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0053-mt9t112-Fix-null-pointer-kernel-bug.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 0f6b697fb422f8eb8df539f82df49f0f6f976bc3 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 1 Jul 2010 09:12:37 -0500 -Subject: [PATCH 53/75] mt9t112: Fix null pointer kernel bug - -We were trying to access a null pointer (info) which we weren't -initializing anywhere. - -Fix this. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 34 +++++++++++++++++++++++----------- - 1 files changed, 23 insertions(+), 11 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 6f54394..98a4ea9 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -92,7 +92,7 @@ struct mt9t112_frame_size { - struct mt9t112_priv { - struct mt9t112_platform_data *pdata; - struct v4l2_int_device *v4l2_int_device; -- struct mt9t112_camera_info *info; -+ struct mt9t112_camera_info info; - struct i2c_client *client; - struct v4l2_pix_format pix; - int model; -@@ -463,15 +463,15 @@ static int mt9t112_init_pll(const struct i2c_client *client) - - /* Replace these registers when new timing parameters are generated */ - mt9t112_set_pll_dividers(client, -- priv->info->divider.m, -- priv->info->divider.n, -- priv->info->divider.p1, -- priv->info->divider.p2, -- priv->info->divider.p3, -- priv->info->divider.p4, -- priv->info->divider.p5, -- priv->info->divider.p6, -- priv->info->divider.p7); -+ priv->info.divider.m, -+ priv->info.divider.n, -+ priv->info.divider.p1, -+ priv->info.divider.p2, -+ priv->info.divider.p3, -+ priv->info.divider.p4, -+ priv->info.divider.p5, -+ priv->info.divider.p6, -+ priv->info.divider.p7); - - /* - * TEST_BYPASS on -@@ -1015,7 +1015,7 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - } - if (!(priv->flags & INIT_DONE)) { - u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & -- priv->info->flags) ? 0x0001 : 0x0000; -+ priv->info.flags) ? 0x0001 : 0x0000; - - ECHECKER(ret, mt9t112_detect(client)); - ECHECKER(ret, mt9t112_init_camera(client)); -@@ -1195,6 +1195,18 @@ static int mt9t112_probe(struct i2c_client *client, - priv->client = client; - priv->pdata = client->dev.platform_data; - -+ /* Revisit: Init Sensor info settings */ -+ priv->info.divider.m = 25; -+ priv->info.divider.n = 2; -+ priv->info.divider.p1 = 0; -+ priv->info.divider.p2 = 9; -+ priv->info.divider.p3 = 0; -+ priv->info.divider.p4 = 13; -+ priv->info.divider.p5 = 13; -+ priv->info.divider.p6 = 9; -+ priv->info.divider.p7 = 0; -+ priv->info.flags = MT9T112_FLAG_PCLK_RISING_EDGE; -+ - i2c_set_clientdata(client, priv); - - //ret = mt9t112_detect(client); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0054-DEBUG-omap3beagle-Add-MT9T112-to-defconfig.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0054-DEBUG-omap3beagle-Add-MT9T112-to-defconfig.patch deleted file mode 100644 index e5ae822d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0054-DEBUG-omap3beagle-Add-MT9T112-to-defconfig.patch +++ /dev/null @@ -1,26 +0,0 @@ -From f66312bff0655778847882a26dfb14a54e9b92ca Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 00:55:43 -0500 -Subject: [PATCH 54/75] DEBUG: omap3beagle: Add MT9T112 to defconfig - -Signed-off-by: Sergio Aguirre ---- - arch/arm/configs/omap3_beagle_cam_defconfig | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/configs/omap3_beagle_cam_defconfig b/arch/arm/configs/omap3_beagle_cam_defconfig -index 0ea8300..80b64db 100644 ---- a/arch/arm/configs/omap3_beagle_cam_defconfig -+++ b/arch/arm/configs/omap3_beagle_cam_defconfig -@@ -1737,7 +1737,7 @@ CONFIG_VIDEO_WM8775=m - CONFIG_VIDEO_MT9V011=m - # CONFIG_VIDEO_TCM825X is not set - CONFIG_VIDEO_MT9P012=m --CONFIG_VIDEO_MT9T111=y -+CONFIG_VIDEO_MT9T112=y - # CONFIG_VIDEO_DW9710 is not set - # CONFIG_VIDEO_OV3640 is not set - # CONFIG_VIDEO_IMX046 is not set --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0055-omap3beagle-camera-Change-MT9T111-references-to-new-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0055-omap3beagle-camera-Change-MT9T111-references-to-new-.patch deleted file mode 100644 index 1a58dea8..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0055-omap3beagle-camera-Change-MT9T111-references-to-new-.patch +++ /dev/null @@ -1,207 +0,0 @@ -From fad06fbbfb3e25683672d41c3f5649500d5eda73 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 15:47:23 -0500 -Subject: [PATCH 55/75] omap3beagle: camera: Change MT9T111 references to new MT9T112 driver - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 52 ++++++++++++------------ - arch/arm/mach-omap2/board-omap3beagle.c | 12 +++--- - 2 files changed, 32 insertions(+), 32 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 2e49158..0b4dff7 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -203,29 +203,29 @@ struct mt9v113_platform_data mt9v113_pdata = { - - #endif /* #ifdef CONFIG_VIDEO_MT9V113 */ - --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) --#include -+#if defined(CONFIG_VIDEO_MT9T112) || defined(CONFIG_VIDEO_MT9T112_MODULE) -+#include - --#define ISP_MT9T111_MCLK 216000000 -+#define ISP_MT9T112_MCLK 216000000 - - /* Arbitrary memory handling limit */ --#define MT9T111_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN((2048 * 2) * 1536 * 4) -+#define MT9T112_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN((2048 * 2) * 1536 * 4) - --static struct isp_interface_config mt9t111_if_config = { -+static struct isp_interface_config mt9t112_if_config = { - .ccdc_par_ser = ISP_PARLL, - .dataline_shift = 0x2, - .hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE, - .strobe = 0x0, - .prestrobe = 0x0, - .shutter = 0x0, -- .cam_mclk = ISP_MT9T111_MCLK, -+ .cam_mclk = ISP_MT9T112_MCLK, - .wenlog = ISPCCDC_CFG_WENLOG_AND, - .wait_hs_vs = 2, - .u.par.par_bridge = 0x3, - .u.par.par_clk_pol = 0x0, - }; - --static struct v4l2_ifparm mt9t111_ifparm_s = { -+static struct v4l2_ifparm mt9t112_ifparm_s = { - .if_type = V4L2_IF_TYPE_RAW, - .u = { - .raw = { -@@ -235,47 +235,47 @@ static struct v4l2_ifparm mt9t111_ifparm_s = { - .latch_clk_inv = 0, - .nobt_hs_inv = 0, /* active high */ - .nobt_vs_inv = 0, /* active high */ -- .clock_min = MT9T111_CLK_MIN, -- .clock_max = MT9T111_CLK_MAX, -+ .clock_min = MT9T112_CLK_MIN, -+ .clock_max = MT9T112_CLK_MAX, - }, - }, - }; - - /** -- * @brief mt9t111_ifparm - Returns the mt9t111 interface parameters -+ * @brief mt9t112_ifparm - Returns the mt9t112 interface parameters - * - * @param p - pointer to v4l2_ifparm structure - * - * @return result of operation - 0 is success - */ --static int mt9t111_ifparm(struct v4l2_ifparm *p) -+static int mt9t112_ifparm(struct v4l2_ifparm *p) - { - if (p == NULL) - return -EINVAL; - -- *p = mt9t111_ifparm_s; -+ *p = mt9t112_ifparm_s; - return 0; - } - - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) --static struct omap34xxcam_hw_config mt9t111_hwc = { -+static struct omap34xxcam_hw_config mt9t112_hwc = { - .dev_index = 0, - .dev_minor = 0, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 0, -- .u.sensor.capture_mem = MT9T111_BIGGEST_FRAME_BYTE_SIZE, -+ .u.sensor.capture_mem = MT9T112_BIGGEST_FRAME_BYTE_SIZE, - .u.sensor.ival_default = { 1, 10 }, - }; - #endif - - /** -- * @brief mt9t111_set_prv_data - Returns mt9t111 omap34xx driver private data -+ * @brief mt9t112_set_prv_data - Returns mt9t112 omap34xx driver private data - * - * @param priv - pointer to omap34xxcam_hw_config structure - * - * @return result of operation - 0 is success - */ --static int mt9t111_set_prv_data(void *priv) -+static int mt9t112_set_prv_data(void *priv) - { - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - struct omap34xxcam_hw_config *hwc = priv; -@@ -283,7 +283,7 @@ static int mt9t111_set_prv_data(void *priv) - if (priv == NULL) - return -EINVAL; - -- *hwc = mt9t111_hwc; -+ *hwc = mt9t112_hwc; - return 0; - #else - return -EINVAL; -@@ -291,13 +291,13 @@ static int mt9t111_set_prv_data(void *priv) - } - - /** -- * @brief mt9t111_power_set - Power-on or power-off TVP5146 device -+ * @brief mt9t112_power_set - Power-on or power-off TVP5146 device - * - * @param power - enum, Power on/off, resume/standby - * - * @return result of operation - 0 is success - */ --static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) -+static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power) - { - struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; - -@@ -314,7 +314,7 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - - case V4L2_POWER_ON: - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -- isp_configure_interface(vdev->cam->isp, &mt9t111_if_config); -+ isp_configure_interface(vdev->cam->isp, &mt9t112_if_config); - #endif - - /* Set RESET_BAR to 0 */ -@@ -331,7 +331,7 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - mdelay(50); - - /* Enable EXTCLK */ -- isp_set_xclk(vdev->cam->isp, MT9T111_CLK_MIN, CAM_USE_XCLKA); -+ isp_set_xclk(vdev->cam->isp, MT9T112_CLK_MIN, CAM_USE_XCLKA); - - /* - * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -@@ -359,14 +359,14 @@ static int mt9t111_power_set(struct v4l2_int_device *s, enum v4l2_power power) - return 0; - } - --struct mt9t111_platform_data mt9t111_pdata = { -+struct mt9t112_platform_data mt9t112_pdata = { - .master = "omap34xxcam", -- .power_set = mt9t111_power_set, -- .priv_data_set = mt9t111_set_prv_data, -- .ifparm = mt9t111_ifparm, -+ .power_set = mt9t112_power_set, -+ .priv_data_set = mt9t112_set_prv_data, -+ .ifparm = mt9t112_ifparm, - }; - --#endif /* #ifdef CONFIG_VIDEO_MT9T111 */ -+#endif /* #ifdef CONFIG_VIDEO_MT9T112 */ - - static int beagle_cam_probe(struct platform_device *pdev) - { -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 0e7e8b2..7c9e40a 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -77,10 +77,10 @@ static struct omap_opp * _omap37x_l3_rate_table = NULL; - extern struct mt9v113_platform_data mt9v113_pdata; - #endif - --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#if defined(CONFIG_VIDEO_MT9T112) || defined(CONFIG_VIDEO_MT9T112_MODULE) - #include --#include --extern struct mt9t111_platform_data mt9t111_pdata; -+#include -+extern struct mt9t112_platform_data mt9t112_pdata; - #endif - - #define GPMC_CS0_BASE 0x60 -@@ -602,10 +602,10 @@ static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { - .platform_data = &mt9v113_pdata, - }, - #endif --#if defined(CONFIG_VIDEO_MT9T111) || defined(CONFIG_VIDEO_MT9T111_MODULE) -+#if defined(CONFIG_VIDEO_MT9T112) || defined(CONFIG_VIDEO_MT9T112_MODULE) - { -- I2C_BOARD_INFO("mt9t111", MT9T111_I2C_ADDR), -- .platform_data = &mt9t111_pdata, -+ I2C_BOARD_INFO("mt9t112", MT9T112_I2C_ADDR), -+ .platform_data = &mt9t112_pdata, - }, - #endif - }; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0056-omap34xxcam-Fix-multi-pixel-format-negotiation.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0056-omap34xxcam-Fix-multi-pixel-format-negotiation.patch deleted file mode 100644 index 9c041c75..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0056-omap34xxcam-Fix-multi-pixel-format-negotiation.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 13238be1e612ab4113413cf21e83307ea9e18f1e Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 1 Jul 2010 13:57:26 -0500 -Subject: [PATCH 56/75] omap34xxcam: Fix multi pixel format negotiation - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/omap34xxcam.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/drivers/media/video/omap34xxcam.c b/drivers/media/video/omap34xxcam.c -index 2e8153b..051c6a7 100644 ---- a/drivers/media/video/omap34xxcam.c -+++ b/drivers/media/video/omap34xxcam.c -@@ -544,7 +544,7 @@ static int try_pix_parm(struct omap34xxcam_videodev *vdev, - pix_tmp_out.height = pix_tmp_in.height; - rval = isp_try_fmt_cap(isp, &pix_tmp_in, &pix_tmp_out); - if (rval) -- return rval; -+ break; - - dev_dbg(&vdev->vfd->dev, "this w %d\th %d\tfmt %8.8x\t" - "-> w %d\th %d\t fmt %8.8x" --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0057-SQUASH-omap3beagle-camera-Bring-back-mt9t111-support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0057-SQUASH-omap3beagle-camera-Bring-back-mt9t111-support.patch deleted file mode 100644 index 4ee6758c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0057-SQUASH-omap3beagle-camera-Bring-back-mt9t111-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 535b7f5333636f7e42f6bea67ed9f298afe0fe3c Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 17:53:07 -0500 -Subject: [PATCH 57/75] SQUASH: omap3beagle: camera: Bring back mt9t111 support - ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 8 ++++---- - 1 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 0b4dff7..3118026 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -221,14 +221,14 @@ static struct isp_interface_config mt9t112_if_config = { - .cam_mclk = ISP_MT9T112_MCLK, - .wenlog = ISPCCDC_CFG_WENLOG_AND, - .wait_hs_vs = 2, -- .u.par.par_bridge = 0x3, -+ .u.par.par_bridge = 0x2, - .u.par.par_clk_pol = 0x0, - }; - - static struct v4l2_ifparm mt9t112_ifparm_s = { -- .if_type = V4L2_IF_TYPE_RAW, -+ .if_type = V4L2_IF_TYPE_YCbCr, - .u = { -- .raw = { -+ .ycbcr = { - .frame_start_on_rising_vs = 1, - .bt_sync_correct = 0, - .swap = 0, -@@ -262,7 +262,7 @@ static struct omap34xxcam_hw_config mt9t112_hwc = { - .dev_index = 0, - .dev_minor = 0, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, -- .u.sensor.sensor_isp = 0, -+ .u.sensor.sensor_isp = 1, - .u.sensor.capture_mem = MT9T112_BIGGEST_FRAME_BYTE_SIZE, - .u.sensor.ival_default = { 1, 10 }, - }; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0058-mt9t112-Do-init_camera-every-powerup.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0058-mt9t112-Do-init_camera-every-powerup.patch deleted file mode 100644 index 66c4e173..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0058-mt9t112-Do-init_camera-every-powerup.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 52bfcc9b6bcb30cf81589c483f1344c568be7300 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 17:53:44 -0500 -Subject: [PATCH 58/75] mt9t112: Do init_camera every powerup - -This is because we want to ensure we always come from a known state. - -Probably this could be revisited later for optimization. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 17 ++++++++--------- - 1 files changed, 8 insertions(+), 9 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 98a4ea9..eebc2b5 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -982,6 +982,8 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - { - struct mt9t112_priv *priv = s->priv; - struct i2c_client *client = priv->client; -+ u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & -+ priv->info.flags) ? 0x0001 : 0x0000; - int ret; - - switch (power) { -@@ -1014,20 +1016,17 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - return ret; - } - if (!(priv->flags & INIT_DONE)) { -- u16 param = (MT9T112_FLAG_PCLK_RISING_EDGE & -- priv->info.flags) ? 0x0001 : 0x0000; -- - ECHECKER(ret, mt9t112_detect(client)); -- ECHECKER(ret, mt9t112_init_camera(client)); -- -- /* Invert PCLK (Data sampled on falling edge of pixclk) */ -- mt9t112_reg_write(ret, client, 0x3C20, param); -- -- mdelay(5); - - priv->flags |= INIT_DONE; - } - -+ ECHECKER(ret, mt9t112_init_camera(client)); -+ -+ /* Invert PCLK (Data sampled on falling edge of pixclk) */ -+ mt9t112_reg_write(ret, client, 0x3C20, param); -+ -+ mdelay(5); - mt9t112_mcu_write(ret, client, VAR(26, 7), - mt9t112_pixfmt_to_fmt(priv->pix.pixelformat)); - mt9t112_mcu_write(ret, client, VAR(26, 9), --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0059-omap3beagle-camera-Switch-flag-for-no-sensor-ISP.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0059-omap3beagle-camera-Switch-flag-for-no-sensor-ISP.patch deleted file mode 100644 index 9c856742..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0059-omap3beagle-camera-Switch-flag-for-no-sensor-ISP.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 1865b5a5f27a7de1e12d52a096e435e5dd177a48 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 18:15:32 -0500 -Subject: [PATCH 59/75] omap3beagle: camera: Switch flag for no sensor ISP - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 3118026..75622bf 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -262,7 +262,7 @@ static struct omap34xxcam_hw_config mt9t112_hwc = { - .dev_index = 0, - .dev_minor = 0, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, -- .u.sensor.sensor_isp = 1, -+ .u.sensor.sensor_isp = 0, - .u.sensor.capture_mem = MT9T112_BIGGEST_FRAME_BYTE_SIZE, - .u.sensor.ival_default = { 1, 10 }, - }; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0060-mt9t112-Add-back-3MP-basesize.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0060-mt9t112-Add-back-3MP-basesize.patch deleted file mode 100644 index 32b825bf..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0060-mt9t112-Add-back-3MP-basesize.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 9cfb19dd4093463361f279276e67d2c61e0f7d5e Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 18:33:00 -0500 -Subject: [PATCH 60/75] mt9t112: Add back 3MP basesize - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 6 +++--- - 1 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index eebc2b5..46d1bd6 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -41,8 +41,8 @@ - /* - * frame size - */ --#define MAX_WIDTH 640 /* 2048 */ --#define MAX_HEIGHT 480 /* 1536 */ -+#define MAX_WIDTH 2048 -+#define MAX_HEIGHT 1536 - - #define VGA_WIDTH 640 - #define VGA_HEIGHT 480 -@@ -133,7 +133,7 @@ const static struct v4l2_fmtdesc mt9t112_formats[] = { - ************************************************************************/ - const static struct mt9t112_frame_size mt9t112_sizes[] = { - { 640, 480 }, -- /* { 2048, 1536} */ -+ { 2048, 1536} - }; - - /************************************************************************ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0061-mt9t112-Prepare-for-24MHz-EXTCLK-and-30-fps.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0061-mt9t112-Prepare-for-24MHz-EXTCLK-and-30-fps.patch deleted file mode 100644 index af30cb73..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0061-mt9t112-Prepare-for-24MHz-EXTCLK-and-30-fps.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 8da9ec7ae90f238bd9b245bc80a1c6559df61f59 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 23:41:32 -0500 -Subject: [PATCH 61/75] mt9t112: Prepare for 24MHz EXTCLK and 30 fps - -Set Aptina recommended values to get 30 FPS with VGA, which -are achievable given the new PLL divider settings, considering -an input of 24MHz in the master clock. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 18 +++++++++--------- - 1 files changed, 9 insertions(+), 9 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 46d1bd6..44234e4 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -144,7 +144,7 @@ const static struct mt9t112_frame_size mt9t112_sizes[] = { - - ************************************************************************/ - const struct v4l2_fract mt9t112_frameintervals[] = { -- { .numerator = 1, .denominator = 10 } -+ { .numerator = 1, .denominator = 30 } - }; - - /************************************************************************ -@@ -932,9 +932,9 @@ static int mt9t112_v4l2_int_g_parm(struct v4l2_int_device *s, - a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - - cparm->capability = V4L2_CAP_TIMEPERFRAME; -- /* FIXME: Is 10 fps really the only option? */ -+ /* FIXME: Is 30 fps really the only option? */ - cparm->timeperframe.numerator = 1; -- cparm->timeperframe.denominator = 10; -+ cparm->timeperframe.denominator = 30; - - return 0; - } -@@ -1195,14 +1195,14 @@ static int mt9t112_probe(struct i2c_client *client, - priv->pdata = client->dev.platform_data; - - /* Revisit: Init Sensor info settings */ -- priv->info.divider.m = 25; -- priv->info.divider.n = 2; -+ priv->info.divider.m = 24; -+ priv->info.divider.n = 1; - priv->info.divider.p1 = 0; -- priv->info.divider.p2 = 9; -+ priv->info.divider.p2 = 8; - priv->info.divider.p3 = 0; -- priv->info.divider.p4 = 13; -- priv->info.divider.p5 = 13; -- priv->info.divider.p6 = 9; -+ priv->info.divider.p4 = 11; -+ priv->info.divider.p5 = 11; -+ priv->info.divider.p6 = 8; - priv->info.divider.p7 = 0; - priv->info.flags = MT9T112_FLAG_PCLK_RISING_EDGE; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0062-omap3beagle-camera-Prepare-24MHz-xclk-for-mt9t112.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0062-omap3beagle-camera-Prepare-24MHz-xclk-for-mt9t112.patch deleted file mode 100644 index 2550430c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0062-omap3beagle-camera-Prepare-24MHz-xclk-for-mt9t112.patch +++ /dev/null @@ -1,62 +0,0 @@ -From b00bc4caeb798661983eca4f548f0f69301bfb32 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 15 Jul 2010 23:43:20 -0500 -Subject: [PATCH 62/75] omap3beagle: camera: Prepare 24MHz xclk for mt9t112 - -Adjust calculations of timings based on # of EXTCLK cycles. - -Also, set default requested framerate to 30 fps. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 16 ++++++++-------- - 1 files changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 75622bf..520e1d8 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -264,7 +264,7 @@ static struct omap34xxcam_hw_config mt9t112_hwc = { - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 0, - .u.sensor.capture_mem = MT9T112_BIGGEST_FRAME_BYTE_SIZE, -- .u.sensor.ival_default = { 1, 10 }, -+ .u.sensor.ival_default = { 1, 30 }, - }; - #endif - -@@ -331,24 +331,24 @@ static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power) - mdelay(50); - - /* Enable EXTCLK */ -- isp_set_xclk(vdev->cam->isp, MT9T112_CLK_MIN, CAM_USE_XCLKA); -+ isp_set_xclk(vdev->cam->isp, 24000000, CAM_USE_XCLKA); - - /* -- * Wait at least 70 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -- * ((1000000 * 70) / 6000000) = aprox 12 us. -+ * Wait at least 70 CLK cycles (w/EXTCLK = 24MHz): -+ * ((1000000 * 70) / 24000000) = aprox 2.91 us. - */ - -- udelay(12); -+ udelay(3); - - /* Set RESET_BAR to 1 */ - gpio_set_value(LEOPARD_RESET_GPIO, 1); - - /* -- * Wait at least 100 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): -- * ((1000000 * 100) / 6000000) = aprox 17 us. -+ * Wait at least 100 CLK cycles (w/EXTCLK = 24MHz): -+ * ((1000000 * 100) / 24000000) = aprox 4.16 us. - */ - -- udelay(17); -+ udelay(5); - - break; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0063-mt9t112-Correct-register-settings-for-mt9t111-sensor.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0063-mt9t112-Correct-register-settings-for-mt9t111-sensor.patch deleted file mode 100644 index 7f5261fb..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0063-mt9t112-Correct-register-settings-for-mt9t111-sensor.patch +++ /dev/null @@ -1,109 +0,0 @@ -From fa6380a53783b185189c372dd5e9d17f46c5c4d7 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 16 Jul 2010 07:52:06 -0500 -Subject: [PATCH 63/75] mt9t112: Correct register settings for mt9t111 sensor - -This now matches with Aptina's recommended values. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 46 ++++++++++++++++++++++++++++------------ - 1 files changed, 32 insertions(+), 14 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 44234e4..ac295dd 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -44,6 +44,9 @@ - #define MAX_WIDTH 2048 - #define MAX_HEIGHT 1536 - -+#define MAX_WIDTH_PREV 1024 -+#define MAX_HEIGHT_PREV 768 -+ - #define VGA_WIDTH 640 - #define VGA_HEIGHT 480 - -@@ -392,24 +395,39 @@ static int mt9t112_set_a_frame_size(const struct i2c_client *client, - u16 height) - { - int ret; -- u16 wstart = (MAX_WIDTH - width) / 2; -- u16 hstart = (MAX_HEIGHT - height) / 2; -+ u16 wstart, hstart, wend, hend; -+ u16 max_width = MAX_WIDTH_PREV, max_height = MAX_HEIGHT_PREV; -+ -+ if ((width > max_width) || (height > max_height)) { -+ /* Capture case */ -+ max_width = MAX_WIDTH; -+ max_height = MAX_HEIGHT; -+ hstart = 4; -+ wstart = 4; -+ hend = 1547; -+ wend = 2059; -+ } else { -+ hstart = 0; -+ wstart = 0; -+ hend = 1549; -+ wend = 2061; -+ } - - /* (Context A) Image Width/Height */ - mt9t112_mcu_write(ret, client, VAR(26, 0), width); - mt9t112_mcu_write(ret, client, VAR(26, 2), height); - - /* (Context A) Output Width/Height */ -- mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); -- mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height); -+ mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + max_width); -+ mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + max_height); - - /* (Context A) Start Row/Column */ -- mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); -- mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart); -+ mt9t112_mcu_write(ret, client, VAR(18, 2), hstart); -+ mt9t112_mcu_write(ret, client, VAR(18, 4), wstart); - - /* (Context A) End Row/Column */ -- mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); -- mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart); -+ mt9t112_mcu_write(ret, client, VAR(18, 6), hend); -+ mt9t112_mcu_write(ret, client, VAR(18, 8), wend); - - mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); - -@@ -547,25 +565,25 @@ static int mt9t112_init_setting(const struct i2c_client *client) - mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); - - /* Read Mode (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024); -+ mt9t112_mcu_write(ret, client, VAR(18, 12), 0x046C); - - /* Fine Correction (A) */ - mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC); - - /* Fine IT Min (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1); -+ mt9t112_mcu_write(ret, client, VAR(18, 17), 0x0381); - - /* Fine IT Max Margin (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF); -+ mt9t112_mcu_write(ret, client, VAR(18, 19), 0x024F); - - /* Base Frame Lines (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D); -+ mt9t112_mcu_write(ret, client, VAR(18, 29), 0x0378); - - /* Min Line Length (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a); -+ mt9t112_mcu_write(ret, client, VAR(18, 31), 0x05D0); - - /* Line Length (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0); -+ mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07AC); - - /* Adaptive Output Clock (B) */ - mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0064-mt9t112-Remove-smart-size-selection.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0064-mt9t112-Remove-smart-size-selection.patch deleted file mode 100644 index b3506dc2..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0064-mt9t112-Remove-smart-size-selection.patch +++ /dev/null @@ -1,188 +0,0 @@ -From 2c8e7e157de32ebc5c8d60bf642c2f29f607c3d0 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Fri, 16 Jul 2010 17:09:10 -0500 -Subject: [PATCH 64/75] mt9t112: Remove "smart" size selection - -This code is broken, as it doesn't really adjust all other -settings, but output size to desired size. It isn't really -toggling everything that needs, and giving the false impression -of good size flexibility. - -So, meanwhile, let's put fixed init settings for the contexts, -and toggle between them (implemented in other patch). - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 105 ++++++++++++++++------------------------- - 1 files changed, 41 insertions(+), 64 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index ac295dd..ee991ef 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -390,50 +390,6 @@ static void mt9t112_frame_check(u32 *width, u32 *height) - *height = MAX_HEIGHT; - } - --static int mt9t112_set_a_frame_size(const struct i2c_client *client, -- u16 width, -- u16 height) --{ -- int ret; -- u16 wstart, hstart, wend, hend; -- u16 max_width = MAX_WIDTH_PREV, max_height = MAX_HEIGHT_PREV; -- -- if ((width > max_width) || (height > max_height)) { -- /* Capture case */ -- max_width = MAX_WIDTH; -- max_height = MAX_HEIGHT; -- hstart = 4; -- wstart = 4; -- hend = 1547; -- wend = 2059; -- } else { -- hstart = 0; -- wstart = 0; -- hend = 1549; -- wend = 2061; -- } -- -- /* (Context A) Image Width/Height */ -- mt9t112_mcu_write(ret, client, VAR(26, 0), width); -- mt9t112_mcu_write(ret, client, VAR(26, 2), height); -- -- /* (Context A) Output Width/Height */ -- mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + max_width); -- mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + max_height); -- -- /* (Context A) Start Row/Column */ -- mt9t112_mcu_write(ret, client, VAR(18, 2), hstart); -- mt9t112_mcu_write(ret, client, VAR(18, 4), wstart); -- -- /* (Context A) End Row/Column */ -- mt9t112_mcu_write(ret, client, VAR(18, 6), hend); -- mt9t112_mcu_write(ret, client, VAR(18, 8), wend); -- -- mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); -- -- return ret; --} -- - static int mt9t112_set_pll_dividers(const struct i2c_client *client, - u8 m, u8 n, - u8 p1, u8 p2, u8 p3, -@@ -561,9 +517,27 @@ static int mt9t112_init_setting(const struct i2c_client *client) - - int ret; - -+ /* Output Width (A) */ -+ mt9t112_mcu_write(ret, client, VAR(26, 0), 640); -+ -+ /* Output Height (A) */ -+ mt9t112_mcu_write(ret, client, VAR(26, 2), 480); -+ - /* Adaptive Output Clock (A) */ - mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); - -+ /* Row Start (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 2), 0); -+ -+ /* Column Start (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 4), 0); -+ -+ /* Row End (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 6), 1549); -+ -+ /* Column End (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 8), 2061); -+ - /* Read Mode (A) */ - mt9t112_mcu_write(ret, client, VAR(18, 12), 0x046C); - -@@ -585,6 +559,18 @@ static int mt9t112_init_setting(const struct i2c_client *client) - /* Line Length (A) */ - mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07AC); - -+ /* Context Width (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + 1024); -+ -+ /* Context Height (A) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + 768); -+ -+ /* Output Width (B) */ -+ mt9t112_mcu_write(ret, client, VAR(27, 0), 2048); -+ -+ /* Output Hieght (B) */ -+ mt9t112_mcu_write(ret, client, VAR(27, 2), 1536); -+ - /* Adaptive Output Clock (B) */ - mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); - -@@ -610,13 +596,19 @@ static int mt9t112_init_setting(const struct i2c_client *client) - mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF); - - /* Base Frame Lines (B) */ -- mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668); -+ mt9t112_mcu_write(ret, client, VAR(18, 101), 0x066C); - - /* Min Line Length (B) */ -- mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0); -+ mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0378); - - /* Line Length (B) */ -- mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0); -+ mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0CB1); -+ -+ /* Context Width (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 115), 8 + 2048); -+ -+ /* Context Height (B) */ -+ mt9t112_mcu_write(ret, client, VAR(18, 117), 8 + 1536); - - /* - * Flicker Dectection registers -@@ -692,10 +684,10 @@ static int mt9t112_init_setting(const struct i2c_client *client) - mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A); - - /* RX FIFO Watermark (A) */ -- mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014); -+ mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0080); - - /* RX FIFO Watermark (B) */ -- mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014); -+ mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0080); - - /* MCLK: 16MHz - * PCLK: 73MHz -@@ -1008,17 +1000,6 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - case V4L2_POWER_STANDBY: - /* FALLTHROUGH */ - case V4L2_POWER_OFF: -- /* FIXME -- * -- * If user selected large output size, -- * and used it long time, -- * mt9t112 camera will be very warm. -- * -- * But current driver can not stop mt9t112 camera. -- * So, set small size here to solve this problem. -- */ -- mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); -- - ret = priv->pdata->power_set(s, power); - if (ret < 0) { - dev_err(&client->dev, "Unable to set target board power " -@@ -1051,10 +1032,6 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - mt9t112_pixfmt_to_order(priv->pix.pixelformat)); - mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); - -- mt9t112_set_a_frame_size(client, -- priv->pix.width, -- priv->pix.height); -- - ECHECKER(ret, mt9t112_auto_focus_trigger(client)); - - dev_dbg(&client->dev, "format : %d\n", priv->pix.pixelformat); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0065-rtl8192su-remove-bogus-Kconfig-depend-on-PCI-and-add.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0065-rtl8192su-remove-bogus-Kconfig-depend-on-PCI-and-add.patch deleted file mode 100644 index 72697f74..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0065-rtl8192su-remove-bogus-Kconfig-depend-on-PCI-and-add.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 132469e10e712ff4b386fb78a4c78343f151ebc4 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sun, 18 Jul 2010 11:25:12 +0200 -Subject: [PATCH 65/75] rtl8192su: remove bogus Kconfig depend on PCI and add another product ID - -Signed-off-by: Koen Kooi ---- - drivers/staging/rtl8192su/Kconfig | 2 +- - drivers/staging/rtl8192su/r8192U_core.c | 1 + - 2 files changed, 2 insertions(+), 1 deletions(-) - -diff --git a/drivers/staging/rtl8192su/Kconfig b/drivers/staging/rtl8192su/Kconfig -index 123fa6d..9888927 100644 ---- a/drivers/staging/rtl8192su/Kconfig -+++ b/drivers/staging/rtl8192su/Kconfig -@@ -1,6 +1,6 @@ - config RTL8192SU - tristate "RealTek RTL8192SU Wireless LAN NIC driver" -- depends on PCI && WLAN && USB -+ depends on WLAN && USB - depends on WIRELESS_EXT - default N - ---help--- -diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c -index 66274d7..48e4c29 100644 ---- a/drivers/staging/rtl8192su/r8192U_core.c -+++ b/drivers/staging/rtl8192su/r8192U_core.c -@@ -112,6 +112,7 @@ u32 rt_global_debug_component = \ - - static struct usb_device_id rtl8192_usb_id_tbl[] = { - /* Realtek */ -+ {USB_DEVICE(0x0bda, 0x8171)}, - {USB_DEVICE(0x0bda, 0x8192)}, - {USB_DEVICE(0x0bda, 0x8709)}, - /* Corega */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0066-mt9t112-Add-Context-selection-to-configuration.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0066-mt9t112-Add-Context-selection-to-configuration.patch deleted file mode 100644 index 0afb340d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0066-mt9t112-Add-Context-selection-to-configuration.patch +++ /dev/null @@ -1,96 +0,0 @@ -From a1066fd19c56f96201b877b394247db9c41c3c18 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Sun, 18 Jul 2010 01:12:41 -0500 -Subject: [PATCH 66/75] mt9t112: Add Context selection to configuration - -Thsi makes always start at least with preview mode -(context A), and then, if needed, transition to capture -mode (context B) - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 54 +++++++++++++++++++++++++++++++++++++++++ - 1 files changed, 54 insertions(+), 0 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index ee991ef..ec7514f 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -73,6 +73,9 @@ - #define mt9t112_reg_read(ret, client, a) \ - ECHECKER(ret, __mt9t112_reg_read(client, a)) - -+#define mt9t112_mcu_read(ret, client, a) \ -+ ECHECKER(ret, __mt9t112_mcu_read(client, a)) -+ - /* - * Logical address - */ -@@ -737,6 +740,50 @@ static int mt9t112_auto_focus_trigger(const struct i2c_client *client) - return ret; - } - -+static int mt9t112_goto_preview(const struct i2c_client *client) -+{ -+ int ret, trycount = 0; -+ -+ /* Is it already in preview mode? */ -+ mt9t112_mcu_read(ret, client, VAR8(1, 1)); -+ if (ret == 0x3) -+ return 0; -+ -+ /* Go to preview mode */ -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 1); -+ do { -+ mt9t112_mcu_read(ret, client, VAR8(1, 1)); -+ mdelay(1); -+ } while ((ret != 0x3) && (++trycount < 100)); -+ -+ if (trycount >= 100) -+ return -EBUSY; -+ -+ return 0; -+} -+ -+static int mt9t112_goto_capture(const struct i2c_client *client) -+{ -+ int ret, trycount = 0; -+ -+ /* Is it already in capture mode? */ -+ mt9t112_mcu_read(ret, client, VAR8(1, 1)); -+ if (ret == 0x7) -+ return 0; -+ -+ /* Go to capture mode */ -+ mt9t112_mcu_write(ret, client, VAR8(1, 0), 2); -+ do { -+ mt9t112_mcu_read(ret, client, VAR8(1, 1)); -+ mdelay(1); -+ } while ((ret != 0x7) && (++trycount < 100)); -+ -+ if (trycount >= 100) -+ return -EBUSY; -+ -+ return 0; -+} -+ - static int mt9t112_init_camera(const struct i2c_client *client) - { - int ret; -@@ -1034,6 +1081,13 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - - ECHECKER(ret, mt9t112_auto_focus_trigger(client)); - -+ ECHECKER(ret, mt9t112_goto_preview(client)); -+ -+ if ((priv->pix.width == MAX_WIDTH) && -+ (priv->pix.height == MAX_HEIGHT)) { -+ ECHECKER(ret, mt9t112_goto_capture(client)); -+ } -+ - dev_dbg(&client->dev, "format : %d\n", priv->pix.pixelformat); - dev_dbg(&client->dev, "size : %d x %d\n", - priv->pix.width, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0067-mt9t112-Disable-JPEG-in-Context-B.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0067-mt9t112-Disable-JPEG-in-Context-B.patch deleted file mode 100644 index 954e0761..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0067-mt9t112-Disable-JPEG-in-Context-B.patch +++ /dev/null @@ -1,32 +0,0 @@ -From b1196ec5f007cef5cd3342ed3dbf3415bf721bd4 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Sun, 18 Jul 2010 01:45:29 -0500 -Subject: [PATCH 67/75] mt9t112: Disable JPEG in Context B - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 8 -------- - 1 files changed, 0 insertions(+), 8 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index ec7514f..18d7ce5 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -812,14 +812,6 @@ static int mt9t112_init_camera(const struct i2c_client *client) - mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E); - mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E); - -- /* Configure STatus in Status_before_length Format and enable header */ -- /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ -- mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4); -- -- /* Enable JPEG in context B */ -- /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ -- mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01); -- - /* Disable Dac_TXLO */ - mt9t112_reg_write(ret, client, 0x316C, 0x350F); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0068-mt9t112-Make-context-B-stream-unlimited-frames.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0068-mt9t112-Make-context-B-stream-unlimited-frames.patch deleted file mode 100644 index 6025dc29..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0068-mt9t112-Make-context-B-stream-unlimited-frames.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 362f211f85aa5e0f7519fca599428e03b05cb05f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Sun, 18 Jul 2010 01:47:41 -0500 -Subject: [PATCH 68/75] mt9t112: Make context B stream unlimited frames - -Context A does this by default, so, only context B needs -to be configured like this. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 3 +++ - 1 files changed, 3 insertions(+), 0 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 18d7ce5..3c516b4 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -771,6 +771,9 @@ static int mt9t112_goto_capture(const struct i2c_client *client) - if (ret == 0x7) - return 0; - -+ /* Num Frames Run (B) */ -+ mt9t112_mcu_write(ret, client, VAR(27, 5), 0); -+ - /* Go to capture mode */ - mt9t112_mcu_write(ret, client, VAR8(1, 0), 2); - do { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0069-mt9t112-Fix-pll-p-dividers-abstraction.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0069-mt9t112-Fix-pll-p-dividers-abstraction.patch deleted file mode 100644 index 07c2e201..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0069-mt9t112-Fix-pll-p-dividers-abstraction.patch +++ /dev/null @@ -1,58 +0,0 @@ -From bf70e34844f0a3984d4ca48614fa39896ce5ca5f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 19 Jul 2010 12:31:47 -0500 -Subject: [PATCH 69/75] mt9t112: Fix pll p-dividers abstraction - -Previously, it wasn't clear that the values needed to be filled -were (val - 1). Fix that. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 16 +++++++++------- - 1 files changed, 9 insertions(+), 7 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 3c516b4..c1a9b41 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -393,6 +393,8 @@ static void mt9t112_frame_check(u32 *width, u32 *height) - *height = MAX_HEIGHT; - } - -+#define PLL_ADJ(x) ((x != 0) ? x - 1 : 0) -+ - static int mt9t112_set_pll_dividers(const struct i2c_client *client, - u8 m, u8 n, - u8 p1, u8 p2, u8 p3, -@@ -408,21 +410,21 @@ static int mt9t112_set_pll_dividers(const struct i2c_client *client, - mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); - - /* P1/P2/P3 */ -- val = ((p3 & 0x0F) << 8) | -- ((p2 & 0x0F) << 4) | -- ((p1 & 0x0F) << 0); -+ val = ((PLL_ADJ(p3) & 0x0F) << 8) | -+ ((PLL_ADJ(p2) & 0x0F) << 4) | -+ ((PLL_ADJ(p1) & 0x0F) << 0); - mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); - - /* P4/P5/P6 */ - val = (0x7 << 12) | -- ((p6 & 0x0F) << 8) | -- ((p5 & 0x0F) << 4) | -- ((p4 & 0x0F) << 0); -+ ((PLL_ADJ(p6) & 0x0F) << 8) | -+ ((PLL_ADJ(p5) & 0x0F) << 4) | -+ ((PLL_ADJ(p4) & 0x0F) << 0); - mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); - - /* P7 */ - val = (0x1 << 12) | -- ((p7 & 0x0F) << 0); -+ ((PLL_ADJ(p7) & 0x0F) << 0); - mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); - - return ret; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0070-mt9t112-Adjust-50-60Hz-flickering-settings.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0070-mt9t112-Adjust-50-60Hz-flickering-settings.patch deleted file mode 100644 index e9d4fe87..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0070-mt9t112-Adjust-50-60Hz-flickering-settings.patch +++ /dev/null @@ -1,51 +0,0 @@ -From aa90dfe987d42500ff2306baf66f526509fdfae0 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 19 Jul 2010 17:30:29 -0500 -Subject: [PATCH 70/75] mt9t112: Adjust 50/60Hz flickering settings - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 24 ++++++++++++++---------- - 1 files changed, 14 insertions(+), 10 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index c1a9b41..8528417 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -694,19 +694,23 @@ static int mt9t112_init_setting(const struct i2c_client *client) - /* RX FIFO Watermark (B) */ - mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0080); - -- /* MCLK: 16MHz -+ /* MCLK: 24MHz - * PCLK: 73MHz - * CorePixCLK: 36.5 MHz - */ -- mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133); -- mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110); -- mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130); -- mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108); -- -- mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27); -- mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30); -- mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32); -- mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 11); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x012F), 1); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 222); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x012D), 0); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 161); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x0130), 0); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 134); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x012E), 0); -+ -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 36); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 38); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 43); -+ mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 45); - - return ret; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0071-mt9t112-Trigger-autofocus-at-the-end-of-context-swit.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0071-mt9t112-Trigger-autofocus-at-the-end-of-context-swit.patch deleted file mode 100644 index 10ba57db..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0071-mt9t112-Trigger-autofocus-at-the-end-of-context-swit.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 18589703f191cee2568324b475ae479dd7f3b779 Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Mon, 19 Jul 2010 17:45:38 -0500 -Subject: [PATCH 71/75] mt9t112: Trigger autofocus at the end of context switch - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9t112.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c -index 8528417..0769f66 100644 ---- a/drivers/media/video/mt9t112.c -+++ b/drivers/media/video/mt9t112.c -@@ -1080,8 +1080,6 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - mt9t112_pixfmt_to_order(priv->pix.pixelformat)); - mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); - -- ECHECKER(ret, mt9t112_auto_focus_trigger(client)); -- - ECHECKER(ret, mt9t112_goto_preview(client)); - - if ((priv->pix.width == MAX_WIDTH) && -@@ -1089,6 +1087,8 @@ static int mt9t112_v4l2_int_s_power(struct v4l2_int_device *s, - ECHECKER(ret, mt9t112_goto_capture(client)); - } - -+ ECHECKER(ret, mt9t112_auto_focus_trigger(client)); -+ - dev_dbg(&client->dev, "format : %d\n", priv->pix.pixelformat); - dev_dbg(&client->dev, "size : %d x %d\n", - priv->pix.width, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0072-omap3beagle-camera-Fix-dual-sensor-registration.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0072-omap3beagle-camera-Fix-dual-sensor-registration.patch deleted file mode 100644 index 409c08fb..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0072-omap3beagle-camera-Fix-dual-sensor-registration.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 838aed68f8efa16e9915795ddb968157d40fca6b Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 22 Jul 2010 11:03:33 -0500 -Subject: [PATCH 72/75] omap3beagle: camera: Fix dual sensor registration - -dev_index should be different, which represents an internal index -in the master camera driver. - -Also, make device video nodes be alloted with the "first free", by setting -dev_minor to -1. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 6 +++--- - 1 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 520e1d8..c0218e3 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -107,7 +107,7 @@ static int mt9v113_ifparm(struct v4l2_ifparm *p) - - static struct omap34xxcam_hw_config mt9v113_hwc = { - .dev_index = 0, -- .dev_minor = 0, -+ .dev_minor = -1, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 1, - .u.sensor.capture_mem = MT9V113_MAX_FRAME_SIZE * 2, -@@ -259,8 +259,8 @@ static int mt9t112_ifparm(struct v4l2_ifparm *p) - - #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) - static struct omap34xxcam_hw_config mt9t112_hwc = { -- .dev_index = 0, -- .dev_minor = 0, -+ .dev_index = 1, -+ .dev_minor = -1, - .dev_type = OMAP34XXCAM_SLAVE_SENSOR, - .u.sensor.sensor_isp = 0, - .u.sensor.capture_mem = MT9T112_BIGGEST_FRAME_BYTE_SIZE, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0073-mt9v113-Fix-State-variable-handling.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0073-mt9v113-Fix-State-variable-handling.patch deleted file mode 100644 index 9bd006e1..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0073-mt9v113-Fix-State-variable-handling.patch +++ /dev/null @@ -1,68 +0,0 @@ -From e3d5c3eb67e2ef91e08b0fcd26778b8505268a8a Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 22 Jul 2010 13:29:16 -0500 -Subject: [PATCH 73/75] mt9v113: Fix State variable handling - -State variable was misused, and was running detection all the -time the sensor was powered back on. - -Reason? power off code was putting it to "not detected" always. - -Signed-off-by: Sergio Aguirre ---- - drivers/media/video/mt9v113.c | 23 ++++++++++++++--------- - 1 files changed, 14 insertions(+), 9 deletions(-) - -diff --git a/drivers/media/video/mt9v113.c b/drivers/media/video/mt9v113.c -index 6714240..37e3e19 100644 ---- a/drivers/media/video/mt9v113.c -+++ b/drivers/media/video/mt9v113.c -@@ -1251,7 +1251,6 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - /* Disable mux for mt9v113 data path */ - if (decoder->pdata->power_set) - err |= decoder->pdata->power_set(s, on); -- decoder->state = STATE_NOT_DETECTED; - break; - - case V4L2_POWER_STANDBY: -@@ -1260,23 +1259,29 @@ static int ioctl_s_power(struct v4l2_int_device *s, enum v4l2_power on) - break; - - case V4L2_POWER_ON: -- /* Enable mux for mt9v113 data path */ -- if (decoder->state == STATE_NOT_DETECTED) { -- -- if (decoder->pdata->power_set) -- err = decoder->pdata->power_set(s, on); -+ if (decoder->pdata->power_set) { -+ err = decoder->pdata->power_set(s, on); -+ if (err) -+ return err; -+ } - -+ if (decoder->state == STATE_NOT_DETECTED) { - /* Detect the sensor is not already detected */ -- err |= mt9v113_detect(decoder); -+ err = mt9v113_detect(decoder); - if (err) { - v4l_err(decoder->client, - "Unable to detect decoder\n"); -+ WARN_ON(1); - return err; - } - } - /* Only VGA mode for now */ -- err |= mt9v113_configure(decoder); -- err |= mt9v113_vga_mode(decoder); -+ err = mt9v113_configure(decoder); -+ if (err) -+ return err; -+ err = mt9v113_vga_mode(decoder); -+ if (err) -+ return err; - break; - - default: --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0074-Move-sensor-rest-to-after-applying-power.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0074-Move-sensor-rest-to-after-applying-power.patch deleted file mode 100644 index 24fb458a..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0074-Move-sensor-rest-to-after-applying-power.patch +++ /dev/null @@ -1,65 +0,0 @@ -From f68eb83d33624b83b4ddd77daf3966de686ffaf0 Mon Sep 17 00:00:00 2001 -From: Steve Kipisz -Date: Thu, 5 Aug 2010 10:51:11 -0500 -Subject: [PATCH 74/75] Move sensor rest to after applying power. - ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 12 ++++++++---- - 1 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index c0218e3..110c2c9 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -160,8 +160,6 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - case V4L2_POWER_ON: - - isp_configure_interface(vdev->cam->isp, &mt9v113_if_config); -- /* Set RESET_BAR to 0 */ -- gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ - regulator_enable(cam_1v8_reg); -@@ -170,6 +168,9 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - regulator_enable(cam_2v8_reg); - mdelay(50); - -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); -+ - /* Enable EXTCLK */ - isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN*2, CAM_USE_XCLKA); - /* -@@ -177,8 +178,10 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - * ((1000000 * 70) / 6000000) = aprox 12 us. - */ - udelay(12); -+ - /* Set RESET_BAR to 1 */ - gpio_set_value(LEOPARD_RESET_GPIO, 1); -+ - /* - * Wait at least 100 CLK cycles (w/EXTCLK = 6MHz, or CLK_MIN): - * ((1000000 * 100) / 6000000) = aprox 17 us. -@@ -317,8 +320,6 @@ static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power) - isp_configure_interface(vdev->cam->isp, &mt9t112_if_config); - #endif - -- /* Set RESET_BAR to 0 */ -- gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ - regulator_enable(cam_1v8_reg); -@@ -330,6 +331,9 @@ static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power) - - mdelay(50); - -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); -+ - /* Enable EXTCLK */ - isp_set_xclk(vdev->cam->isp, 24000000, CAM_USE_XCLKA); - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0075-omap3beagle-Add-camera-bootarg.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0075-omap3beagle-Add-camera-bootarg.patch deleted file mode 100644 index 066bbb48..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/0075-omap3beagle-Add-camera-bootarg.patch +++ /dev/null @@ -1,108 +0,0 @@ -From d15c09a8ed5441dd843257b6a4396dd058a2e68f Mon Sep 17 00:00:00 2001 -From: Sergio Aguirre -Date: Thu, 22 Jul 2010 15:38:43 -0500 -Subject: [PATCH 75/75] omap3beagle: Add camera bootarg - -This adds a new 'camera' bootarg, with (so far) 2 new possible types: -- lbcmvga: Leopard Board Camera Module: MT9V113 VGA -- lbcm3m1: Leopard Board Camera Module: MT9T111 3MP - -Also, cleans up a little bit the current i2c2 bus init code. - -Signed-off-by: Sergio Aguirre ---- - arch/arm/mach-omap2/board-omap3beagle.c | 42 +++++++++++++++++++++++++------ - 1 files changed, 34 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 7c9e40a..1e8b77b 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -89,6 +89,7 @@ extern struct mt9t112_platform_data mt9t112_pdata; - #define NAND_BLOCK_SIZE SZ_128K - - char expansionboard_name[16]; -+char cameraboard_name[16]; - - #if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - -@@ -595,13 +596,16 @@ static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = { - static struct i2c_board_info __initdata beagle_zippy_i2c2_boardinfo[] = {}; - #endif - --static struct i2c_board_info __initdata beagle_i2c2_boardinfo[] = { -+static struct i2c_board_info __initdata beagle_lbcmvga_i2c2_boardinfo[] = { - #if defined(CONFIG_VIDEO_MT9V113) || defined(CONFIG_VIDEO_MT9V113_MODULE) - { - I2C_BOARD_INFO("mt9v113", MT9V113_I2C_ADDR), - .platform_data = &mt9v113_pdata, - }, - #endif -+}; -+ -+static struct i2c_board_info __initdata beagle_lbcm3m1_i2c2_boardinfo[] = { - #if defined(CONFIG_VIDEO_MT9T112) || defined(CONFIG_VIDEO_MT9T112_MODULE) - { - I2C_BOARD_INFO("mt9t112", MT9T112_I2C_ADDR), -@@ -614,15 +618,27 @@ static int __init omap3_beagle_i2c_init(void) - { - omap_register_i2c_bus(1, 2600, beagle_i2c1_boardinfo, - ARRAY_SIZE(beagle_i2c1_boardinfo)); -- if(!strcmp(expansionboard_name, "zippy") || !strcmp(expansionboard_name, "zippy2")) -- { -- printk(KERN_INFO "Beagle expansionboard: registering i2c2 bus for zippy/zippy2\n"); -+ -+ if (!strcmp(expansionboard_name, "zippy") || -+ !strcmp(expansionboard_name, "zippy2")) { -+ printk(KERN_INFO "Beagle expansionboard:" -+ " registering i2c2 bus for zippy/zippy2\n"); - omap_register_i2c_bus(2, 400, beagle_zippy_i2c2_boardinfo, - ARRAY_SIZE(beagle_zippy_i2c2_boardinfo)); -- } else -- { -- omap_register_i2c_bus(2, 400, beagle_i2c2_boardinfo, -- ARRAY_SIZE(beagle_i2c2_boardinfo)); -+ } else { -+ if (!strcmp(cameraboard_name, "lbcmvga")) { -+ printk(KERN_INFO "Beagle cameraboard:" -+ " registering i2c2 bus for lbcmvga\n"); -+ omap_register_i2c_bus(2, 400, beagle_lbcmvga_i2c2_boardinfo, -+ ARRAY_SIZE(beagle_lbcmvga_i2c2_boardinfo)); -+ } else if (!strcmp(cameraboard_name, "lbcm3m1")) { -+ printk(KERN_INFO "Beagle cameraboard:" -+ " registering i2c2 bus for lbcm3m1\n"); -+ omap_register_i2c_bus(2, 400, beagle_lbcm3m1_i2c2_boardinfo, -+ ARRAY_SIZE(beagle_lbcm3m1_i2c2_boardinfo)); -+ } else { -+ omap_register_i2c_bus(2, 400, NULL, 0); -+ } - } - /* Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz */ -@@ -825,6 +841,15 @@ static int __init expansionboard_setup(char *str) - return 0; - } - -+static int __init cameraboard_setup(char *str) -+{ -+ if (!str) -+ return -EINVAL; -+ strncpy(cameraboard_name, str, 16); -+ printk(KERN_INFO "Beagle cameraboard: %s\n", cameraboard_name); -+ return 0; -+} -+ - static void __init omap3_beagle_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -@@ -910,6 +935,7 @@ static void __init omap3_beagle_map_io(void) - } - - early_param("buddy", expansionboard_setup); -+early_param("camera", cameraboard_setup); - - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") - /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/5m03/0001-mt9p031-import-driver-from-https-github.com-Aptina-B.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/5m03/0001-mt9p031-import-driver-from-https-github.com-Aptina-B.patch deleted file mode 100644 index ee728b9d..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/5m03/0001-mt9p031-import-driver-from-https-github.com-Aptina-B.patch +++ /dev/null @@ -1,1547 +0,0 @@ -From eefcf5de4689fbd00119d7a7df75244ca6ca1187 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sun, 1 May 2011 16:40:54 +0200 -Subject: [PATCH 1/2] mt9p031: import driver from https://github.com/Aptina/BeagleBoard-xM/tree/master/Angstrom/MT9P031 - -Signed-off-by: Koen Kooi ---- - drivers/media/video/Kconfig | 6 + - drivers/media/video/Makefile | 1 + - drivers/media/video/mt9p031.c | 1445 +++++++++++++++++++++++++++++++++++++++ - include/media/mt9p031.h | 30 + - include/media/v4l2-chip-ident.h | 1 + - 5 files changed, 1483 insertions(+), 0 deletions(-) - create mode 100644 drivers/media/video/mt9p031.c - create mode 100644 include/media/mt9p031.h - -diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig -index 4c1fb0f..59f1133 100644 ---- a/drivers/media/video/Kconfig -+++ b/drivers/media/video/Kconfig -@@ -832,6 +832,12 @@ config SOC_CAMERA_MT9M111 - help - This driver supports MT9M111 and MT9M112 cameras from Micron - -+config SOC_CAMERA_MT9P031 -+ tristate "mt9p031 support" -+ depends on SOC_CAMERA && I2C -+ help -+ This driver supports MT9P031 cameras from Micron. -+ - config SOC_CAMERA_MT9T031 - tristate "mt9t031 support" - depends on SOC_CAMERA && I2C -diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile -index fb7e46c..f3110e7 100644 ---- a/drivers/media/video/Makefile -+++ b/drivers/media/video/Makefile -@@ -79,6 +79,7 @@ obj-$(CONFIG_VIDEO_MT9V113) += mt9v113.o - - obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o - obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o -+obj-$(CONFIG_SOC_CAMERA_MT9P031) += mt9p031.o - obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031.o - obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o - obj-$(CONFIG_SOC_CAMERA_OV772X) += ov772x.o -diff --git a/drivers/media/video/mt9p031.c b/drivers/media/video/mt9p031.c -new file mode 100644 -index 0000000..3047e43 ---- /dev/null -+++ b/drivers/media/video/mt9p031.c -@@ -0,0 +1,1445 @@ -+/* -+ * drivers/media/video/mt9p031.c -+ * -+ * Aptina mt9p031 sensor driver -+ * -+ * -+ * Copyright (C) 2010 Aptina Imaging -+ * -+ * -+ * Leverage mt9p012.c -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define MT9P031_DEBUG -+ -+#ifdef MT9P031_DEBUG -+#define DPRINTK_DRIVER(format, ...) \ -+ printk(KERN_INFO "_MT9P031_DRIVER: " format, ## __VA_ARGS__) -+#else -+#define DPRINTK_DRIVER(format, ...) -+#endif -+/************************************************************************ -+ macro -+************************************************************************/ -+// Macro to configure I2c level shifter. Use only for MT9P031 Headboards from Aptina; not required for Leopard Imaging or elsewise. -+#define MT9P031_HEADBOARD -+ -+#define MT9P031_CHIP_ID 0x1801 -+#define MT9P031_MAX_HEIGHT 1944 -+#define MT9P031_MAX_WIDTH 2592 -+#define MT9P031_MIN_HEIGHT 2 -+#define MT9P031_MIN_WIDTH 2 -+ -+#define VGA_HEIGHT 480 -+#define VGA_WIDTH 640 -+ -+#define MT9P031_NORMAL_OPERATION_MODE (0x1F82) //write -+#define MT9P031_OUTPUT_CTRL_CHIP_UNSELECT (0x1F80) -+#define MT9P031_OUTPUT_CTRL_HALT (0x1F83) -+ -+/* FPS Capabilities */ -+#define MT9P031_MIN_FPS 10 -+#define MT9P031_DEF_FPS 30 -+#define MT9P031_MAX_FPS 50 -+ -+#define MT9P031_XCLK_NOM_1 12000000 -+#define MT9P031_XCLK_NOM_2 24000000 -+ -+/* Analog gain values */ -+#define MT9P031_EV_MIN_GAIN 0 -+#define MT9P031_EV_MAX_GAIN 47 -+#define MT9P031_EV_DEF_GAIN 24 -+#define MT9P031_EV_GAIN_STEP 1 -+ -+/* Exposure time values */ -+#define MT9P031_MIN_EXPOSURE 15000 -+#define MT9P031_MAX_EXPOSURE 128000 -+#define MT9P031_DEF_EXPOSURE 33000 -+#define MT9P031_EXPOSURE_STEP 100 -+#define Q12 4096 -+/************************************************************************ -+ Register Address -+************************************************************************/ -+ -+#define REG_MT9P031_CHIP_VERSION 0x00 -+#define REG_MT9P031_ROWSTART 0x01 -+#define REG_MT9P031_COLSTART 0x02 -+#define REG_MT9P031_HEIGHT 0x03 -+#define REG_MT9P031_WIDTH 0x04 -+#define REG_MT9P031_HBLANK 0x05 -+#define REG_MT9P031_VBLANK 0x06 -+#define REG_MT9P031_OUT_CTRL 0x07 -+#define REG_MT9P031_SHUTTER_WIDTH_U 0x08 -+#define REG_MT9P031_SHUTTER_WIDTH_L 0x09 -+#define REG_MT9P031_PCLK_CTRL 0x0a -+#define REG_MT9P031_RESTART 0x0b -+#define REG_MT9P031_SHUTTER_DELAY 0x0c -+#define REG_MT9P031_RESET 0x0d -+ -+#define REG_MT9P031_PLL_CTRL 0x10 -+#define REG_MT9P031_PLL_CONF1 0x11 -+#define REG_MT9P031_PLL_CONF2 0x12 -+ -+#define REG_MT9P031_READ_MODE1 0x1e -+#define REG_MT9P031_READ_MODE2 0x20 -+#define REG_MT9P031_ROW_ADDR_MODE 0x22 -+#define REG_MT9P031_COL_ADDR_MODE 0x23 -+#define REG_MT9P031_GREEN_1_GAIN 0x2b -+#define REG_MT9P031_BLUE_GAIN 0x2c -+#define REG_MT9P031_RED_GAIN 0x2d -+#define REG_MT9P031_GREEN_2_GAIN 0x2e -+#define REG_MT9P031_GLOBAL_GAIN 0x35 -+#define REG_MT9P031_CHIP_VERSION_ALT 0x0FF -+ -+/************************************************************************ -+ struct -+************************************************************************/ -+struct mt9p031_frame_size { -+ u16 width; -+ u16 height; -+}; -+ -+struct mt9p031_priv { -+ struct mt9p031_platform_data *pdata; -+ struct v4l2_int_device *v4l2_int_device; -+ struct i2c_client *client; -+ struct v4l2_pix_format pix; -+ struct v4l2_fract timeperframe; -+ unsigned long xclk_current; -+ int fps; -+ int scaler; -+ int ver; -+ int model; -+ u32 flags; -+/* for flags */ -+#define INIT_DONE (1<<0) -+}; -+ -+struct mt9p031_priv sysPriv; -+ -+static const struct v4l2_fmtdesc mt9p031_formats[] = { -+ { -+ .description = "Bayer (sRGB) 10 bit", -+ .pixelformat = V4L2_PIX_FMT_SRGGB10, -+ }, -+}; -+ -+static const unsigned int mt9p031_num_formats = ARRAY_SIZE(mt9p031_formats); -+ -+/***********************Minimum Horizontal blanking*********************/ -+int hb_min[4][4] = { -+ { 450, 430, 0, 420 }, -+ { 796, 776, 0, 766 }, -+ { 0, 0, 0, 0 }, -+ { 1488, 1468, 0, 1458 }, -+}; -+ -+/**************************supported sizes******************************/ -+const static struct mt9p031_frame_size mt9p031_sizes[] = { -+ { 640, 480 }, -+ { 1280, 720 }, -+ { 1920, 1080 }, -+ { 2048, 1536 }, //3MP -+ { 2592, 1944 }, //5MP -+}; -+ -+ -+struct mt9p031_format_params { -+ int width; -+ int height; -+ int row_start; -+ int col_start; -+ int row_size; -+ int col_size; -+ int hblank; -+ int vblank; -+ int integ_time; -+ int row_addr_mode; -+ int col_addr_mode; -+ int read_mode_2_config; -+ int shutter_width_hi; -+ int shutter_delay; -+ int row_bin; -+ int col_bin; -+}; -+ -+enum mt9p031_image_size { -+ VGA_BIN_30FPS, -+ HDV_720P_30FPS, -+ //HDV_720P_60FPS, -+ //HDV_720P_60FPS_LVB, -+ HDV_1080P_30FPS, -+ MT9P031_THREE_MP, -+ MT9P031_FIVE_MP, -+}; -+ -+enum mt9p031_image_size mt9p031_current_format; -+ -+const struct mt9p031_format_params mt9p031_supported_formats[] = { -+ { 640, 480, 64, 24, 1919, 2559, 0, 0, 0x0296, 0x0033, 0x0033, 0x0060, 0, 0, 3, 3 }, // VGA_BIN_30FPS -+ { 1280, 720, 64, 24, 1439, 2559, 0, 0, 0x0296, 0x0011, 0x0011, 0x0060, 0, 0, 1, 1 }, // 720P_HD_30FPS -+ //{ 1280, 720, 0x0040, 0x0018, 0x059F, 0x09FF, 0, 0, 0x0296, 0x0011, 0x0011, 0x0060, 0, 0, 1, 1 }, // 720P_HD_60FPS -+ //{ 1280, 720, 0x0040, 0x0018, 0x059F, 0x09FF, 0, 0x02D0, 0x0296, 0x0011, 0x0011, 0x0060, 0, 0, 1, 1 }, // 720P_HD_60FPS_LVB -+ { 1920, 1080, 431, 335, 1079, 1919, 0, 0x0037, 0x01AC, 0, 0, 0x0040, 0, 0, 0, 0 }, // 1080P_30FPS -+ { 2048, 1536, 431, 335, 1535, 2047, 0, 0x0037, 0x01AC, 0, 0, 0x0040, 0, 0, 0, 0 }, // 3MP CAPTURE -+ { 2592, 1944, 431, 335, 1943, 2591, 0, 0x0037, 0x01AC, 0, 0, 0x0040, 0, 0, 0, 0 }, // 5MP CAPTURE -+}; -+ -+ -+const struct v4l2_fract mt9p031_frameintervals[] = { -+ { .numerator = 1, .denominator = 10 }, -+ { .numerator = 1, .denominator = 20 }, -+ { .numerator = 1, .denominator = 30 }, -+ { .numerator = 1, .denominator = 40 }, -+ { .numerator = 1, .denominator = 50 }, -+}; -+ -+ -+const u16 MT9P031_EV_GAIN_TBL[48] = { -+ /* Gain x1 */ -+ 8, 9, 10, 11, 12, 13, 14, 15, -+ /* Gain x2 */ -+ 16, 17, 18, 19, 20, 21, 22, 23, -+ /* Gain x3 */ -+ 24, 25, 26, 27, 28, 29, 30, 31, -+ /* Gain x4 */ -+ 32, 33, 34, 35, -+ /* Gain x5 */ -+ 81, 82, 83, -+ /* Gain x6 */ -+ 84, 85, 86, 87, 88, 89, 90, 91, -+ /* Gain x7 */ -+ 92, 93, 94, 95, 96, 97, 98, 99, -+ /* Gain x8 */ -+ 100, -+}; -+ -+#ifdef MT9P031_HEADBOARD -+/** -+ * mt9p031_config_PCA9543A - configure on-board I2c level-shifter PCA9543A of MT9P031 Headboards from Aptina -+ * @client: pointer to i2c client -+ * Configures the level shifter to enable channel 0 -+ */ -+static int mt9p031_config_PCA9543A(const struct i2c_client *client) -+{ -+ struct i2c_msg msg; -+ int ret; -+ u8 buf; -+ buf = 0x21; -+ -+ msg.addr = (0xE6 >> 1); //slave address of PCA9543A -+ msg.flags = 0; -+ msg.len = 1; -+ msg.buf = &buf; -+ -+ ret = i2c_transfer(client->adapter, &msg, 1); -+ -+ return 0; -+ -+} -+#endif //MT9P031_HEADBOARD -+ -+/** -+ * mt9p031_reg_read - read resgiter value -+ * @client: pointer to i2c client -+ * @command: register address -+ */ -+static int mt9p031_reg_read(const struct i2c_client *client, u16 command, u16 *val) -+{ -+ struct i2c_msg msg[2]; -+ u8 buf[2]; -+ int ret; -+ -+ // 8-bit/ byte addressable register -+ buf[0] = command & 0xff; -+ -+ msg[0].addr = client->addr; -+ msg[0].flags = 0; -+ msg[0].len = 1; -+ msg[0].buf = buf ; -+ ret = i2c_transfer(client->adapter, &msg[0], 1); -+ -+ if(ret >= 0) { -+ msg[1].addr = client->addr; -+ msg[1].flags = I2C_M_RD; //1 -+ msg[1].len = 2; -+ msg[1].buf = buf; -+ ret = i2c_transfer(client->adapter, &msg[1], 1); -+ } -+ /* -+ * if return value of this function is < 0, -+ * it mean error. -+ * else, under 16bit is valid data. -+ */ -+ if(ret >= 0) { -+ *val = 0; -+ *val = buf[1] + (buf[0] << 8); -+ return 0; -+ } -+ -+ v4l_err(client, "read from offset 0x%x error %d", command, ret); -+ return ret; -+} -+ -+/** -+ * mt9p031_reg_write - read resgiter value -+ * @client: pointer to i2c client -+ * @command: register address -+ * @data: value to be written -+ */ -+static int mt9p031_reg_write(const struct i2c_client *client, -+ u16 command, u16 data) -+{ -+ struct i2c_msg msg; -+ u8 buf[3]; -+ int ret; -+ -+ // 8-bit/ byte addressable register -+ -+ buf[0] = command & 0xff; -+ data = swab16(data); -+ memcpy(buf + 1, &data, 2); -+ -+ msg.addr = client->addr; -+ msg.flags = 0; -+ msg.len = 3; -+ msg.buf = buf; -+ -+ /* -+ * i2c_transfer return message length, -+ * but this function should return 0 if correct case -+ */ -+ ret = i2c_transfer(client->adapter, &msg, 1); -+ if (ret >= 0) -+ ret = 0; -+ -+ return ret; -+} -+ -+/** -+ * struct vcontrol - Video controls -+ * @v4l2_queryctrl: V4L2 VIDIOC_QUERYCTRL ioctl structure -+ * @current_value: current value of this control -+ */ -+static struct vcontrol { -+ struct v4l2_queryctrl qc; -+ int current_value; -+} mt9p031_video_control[] = { -+ { -+ { -+ .id = V4L2_CID_EXPOSURE, -+ .type = V4L2_CTRL_TYPE_INTEGER, -+ .name = "Exposure", -+ .minimum = MT9P031_MIN_EXPOSURE, -+ .maximum = MT9P031_MAX_EXPOSURE, -+ .step = MT9P031_EXPOSURE_STEP, -+ .default_value = MT9P031_DEF_EXPOSURE, -+ }, -+ .current_value = MT9P031_DEF_EXPOSURE, -+ }, -+ { -+ { -+ .id = V4L2_CID_GAIN, -+ .type = V4L2_CTRL_TYPE_INTEGER, -+ .name = "Analog Gain", -+ .minimum = MT9P031_EV_MIN_GAIN, -+ .maximum = MT9P031_EV_MAX_GAIN, -+ .step = MT9P031_EV_GAIN_STEP, -+ .default_value = MT9P031_EV_DEF_GAIN, -+ }, -+ .current_value = MT9P031_EV_DEF_GAIN, -+ }, -+}; -+ -+/** -+ * find_vctrl - Finds the requested ID in the video control structure array -+ * @id: ID of control to search the video control array for -+ * -+ * Returns the index of the requested ID from the control structure array -+ */ -+static int -+find_vctrl(int id) -+{ -+ int i; -+ -+ if (id < V4L2_CID_BASE) -+ return -EDOM; -+ -+ for (i = (ARRAY_SIZE(mt9p031_video_control) - 1); i >= 0; i--) -+ if (mt9p031_video_control[i].qc.id == id) -+ break; -+ if (i < 0) -+ i = -EINVAL; -+ return i; -+} -+ -+/** -+ * mt9p031_calc_size - Find the best match for a requested image capture size -+ * @width: requested image width in pixels -+ * @height: requested image height in pixels -+ * -+ * Find the best match for a requested image capture size. The best match -+ * is chosen as the nearest match that has the same number or fewer pixels -+ * as the requested size, or the smallest image size if the requested size -+ * has fewer pixels than the smallest image. -+ */ -+static enum mt9p031_image_size mt9p031_calc_size(unsigned int width, -+ unsigned int height) -+{ -+ enum mt9p031_image_size isize; -+ unsigned long pixels = width * height; -+ -+ for (isize = VGA_BIN_30FPS; isize <= MT9P031_FIVE_MP; isize++) { -+ if (mt9p031_sizes[isize].height * -+ mt9p031_sizes[isize].width >= pixels) { -+ -+ return isize; -+ } -+ } -+ -+ return MT9P031_FIVE_MP; -+} -+ -+/** -+ * mt9p031_find_isize - Find the best match for a requested image capture size -+ * @width: requested image width in pixels -+ * @height: requested image height in pixels -+ * -+ * Find the best match for a requested image capture size. The best match -+ * is chosen as the nearest match that has the same number or fewer pixels -+ * as the requested size, or the smallest image size if the requested size -+ * has fewer pixels than the smallest image. -+ */ -+static enum mt9p031_image_size mt9p031_find_isize(unsigned int width) -+{ -+ enum mt9p031_image_size isize; -+ -+ for (isize = VGA_BIN_30FPS; isize <= MT9P031_FIVE_MP; isize++) { -+ if (mt9p031_sizes[isize].width >= width) -+ break; -+ } -+ -+ return isize; -+} -+ -+/** -+ * mt9p031_calc_xclk - Calculate the required xclk frequency -+ * @c: i2c client driver structure -+ * -+ * Given the image capture format in pix, the nominal frame period in -+ * timeperframe, calculate and return the required xclk frequency -+ */ -+static unsigned long mt9p031_calc_xclk(struct i2c_client *c) -+{ -+ struct mt9p031_priv *priv = i2c_get_clientdata(c); -+ struct v4l2_fract *timeperframe = &priv->timeperframe; -+ -+ if (timeperframe->numerator == 0 || -+ timeperframe->denominator == 0) { -+ /* supply a default nominal_timeperframe */ -+ timeperframe->numerator = 1; -+ timeperframe->denominator = MT9P031_DEF_FPS; -+ } -+ -+ priv->fps = timeperframe->denominator / timeperframe->numerator; -+ if (priv->fps < MT9P031_MIN_FPS) -+ priv->fps = MT9P031_MIN_FPS; -+ else if (priv->fps > MT9P031_MAX_FPS) -+ priv->fps = MT9P031_MAX_FPS; -+ -+ timeperframe->numerator = 1; -+ timeperframe->denominator = priv->fps; -+ -+ return MT9P031_XCLK_NOM_1; -+} -+ -+/** -+ * mt9p031_set_params - sets register settings according to resolution -+ * @client: pointer to standard i2c client -+ * @width: width as queried by ioctl -+ * @height: height as queried by ioctl -+ */ -+static int mt9p031_set_params(struct i2c_client *client, u32 width, u32 height) -+{ -+ struct mt9p031_priv *priv = i2c_get_clientdata(client); -+ struct v4l2_pix_format *pix = &priv->pix; -+ int ret; -+ enum mt9p031_image_size i; -+ -+ i = mt9p031_find_isize(pix->width); -+ priv->pix.width = mt9p031_supported_formats[i].width; -+ priv->pix.height = mt9p031_supported_formats[i].height; -+ -+ ret = mt9p031_reg_write(client, REG_MT9P031_ROWSTART, mt9p031_supported_formats[i].row_start); //ROW_WINDOW_START_REG -+ ret |= mt9p031_reg_write(client, REG_MT9P031_COLSTART, mt9p031_supported_formats[i].col_start); //COL_WINDOW_START_REG -+ ret |= mt9p031_reg_write(client, REG_MT9P031_HEIGHT, mt9p031_supported_formats[i].row_size); //ROW_WINDOW_SIZE_REG=1439 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_WIDTH, mt9p031_supported_formats[i].col_size); //COL_WINDOW_SIZE_REG=2559 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_HBLANK, mt9p031_supported_formats[i].hblank); //HORZ_BLANK=0 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_VBLANK, mt9p031_supported_formats[i].vblank); //VERT_BLANK_REG=720 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_SHUTTER_WIDTH_L, 0x0400); //SHUTTER_WIDTH_LOW (INTEG_TIME_REG = 1024) -+ ret |= mt9p031_reg_write(client, REG_MT9P031_ROW_ADDR_MODE, mt9p031_supported_formats[i].row_addr_mode); //ROW_MODE, ROW_SKIP=1, ROW_BIN=1 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_COL_ADDR_MODE, mt9p031_supported_formats[i].col_addr_mode); //COL_MODE, COL_SKIP=1, COL_BIN=1 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_READ_MODE2, mt9p031_supported_formats[i].read_mode_2_config); //READ_MODE_2, COL_SUM -+ ret |= mt9p031_reg_write(client, REG_MT9P031_SHUTTER_WIDTH_U, mt9p031_supported_formats[i].shutter_width_hi); //SHUTTER_WIDTH_HI -+ ret |= mt9p031_reg_write(client, REG_MT9P031_SHUTTER_WIDTH_L, mt9p031_supported_formats[i].integ_time); //SHUTTER_WIDTH_LOW (INTEG_TIME_REG) -+ ret |= mt9p031_reg_write(client, REG_MT9P031_SHUTTER_DELAY, mt9p031_supported_formats[i].shutter_delay); //SHUTTER_DELAY_REG -+ -+ return ret; -+} -+ -+/** -+ * mt9p031_init_camera - initialize camera settings -+ * @client: pointer to i2c client -+ * Initialize camera settings -+ */ -+static int mt9p031_init_camera(const struct i2c_client *client) -+{ -+ int ret; -+ struct mt9p031_priv *priv = i2c_get_clientdata(client); -+ struct v4l2_pix_format *pix = &priv->pix; -+ -+ ret = mt9p031_reg_write(client, REG_MT9P031_PLL_CTRL, 0x0051); //PLL_CTRL; power up pll -+ ret |= mt9p031_reg_write(client, REG_MT9P031_PLL_CONF1, 0x1801); //PLL_CONFIG_1: m=24, n=1 -+ ret |= mt9p031_reg_write(client, REG_MT9P031_PLL_CONF2, 0x0002); //PLL_CONFIG_2: p1=2, p2=0 -+ mdelay(10); //wait 10 ms for VCO to lock -+ ret |= mt9p031_reg_write(client, REG_MT9P031_PLL_CTRL, 0x0053); //PLL_CONTROL; use PLL -+ mdelay(200); -+ -+ ret |= mt9p031_set_params(priv->client, pix->width, pix->height); -+ -+ ret |= mt9p031_reg_write(client, REG_MT9P031_RESET, 0x0001); //High -+ ret |= mt9p031_reg_write(client, REG_MT9P031_RESET, 0x0000); //Low -+ mdelay(100); -+ -+ ret |= mt9p031_reg_write(client, REG_MT9P031_GREEN_1_GAIN, 0x0051); //Green1_gain_reg -+ ret |= mt9p031_reg_write(client, REG_MT9P031_BLUE_GAIN, 0x0051); //Blue_gain_reg -+ ret |= mt9p031_reg_write(client, REG_MT9P031_RED_GAIN, 0x0051); //Red_gain_reg -+ ret |= mt9p031_reg_write(client, REG_MT9P031_GREEN_2_GAIN, 0x0051); //Green2_gain_reg -+ ret |= mt9p031_reg_write(client, REG_MT9P031_GLOBAL_GAIN, 0x0008); //Analog Gain -+ ret |= mt9p031_reg_write(client, REG_MT9P031_READ_MODE1, 0x0006); //Read_mode_1 //disable AB -+ ret |= mt9p031_reg_write(client, REG_MT9P031_OUT_CTRL, 0x1F8E); //Enable parll fifo data -+ -+ return ret>= 0 ? 0 : -EIO; -+} -+ -+/************************************************************************ -+ i2c driver -+************************************************************************/ -+/** -+ * mt9p031_detect - Detect if an mt9p031 is present, and if so which revision -+ * @client: pointer to the i2c client driver structure -+ * -+ * Returns a negative error number if no device is detected -+ */ -+static int mt9p031_detect(struct i2c_client *client) -+{ -+ struct mt9p031_priv *priv = i2c_get_clientdata(client); -+ const char *devname; -+ u16 chipid; -+ -+ if (!client) -+ return -ENODEV; -+ /* -+ * Set Normal Mode -+ */ -+ if(mt9p031_reg_write(client, REG_MT9P031_OUT_CTRL, MT9P031_NORMAL_OPERATION_MODE)) -+ return -ENODEV; -+ /* -+ * check and show chip ID -+ */ -+ if(mt9p031_reg_read(client, REG_MT9P031_CHIP_VERSION, &chipid)) -+ return -ENODEV; -+ -+ if(chipid == MT9P031_CHIP_ID) { -+ devname = "mt9p031"; -+ priv->model = V4L2_IDENT_MT9P031; -+ dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid); -+ return 0; -+ } -+ -+ dev_err(&client->dev, "Product ID error %04x\n", chipid); -+ return -ENODEV; -+} -+ -+/** -+ * mt9p031_set_exposure_time - sets exposure time per input value -+ * @exp_time: exposure time to be set on device -+ * @client: pointer to standard i2c client -+ * @lvc: pointer to V4L2 exposure entry in video_controls array -+ * -+ * If the requested exposure time is within the allowed limits, the HW -+ * is configured to use the new exposure time, and the video_controls -+ * array is updated with the new current value. -+ * The function returns 0 upon success. Otherwise an error code is -+ * returned. -+ */ -+static int mt9p031_set_exposure_time(u32 exp_time, struct i2c_client *client, -+ struct vcontrol *lvc) -+{ -+ int ret = 0, i, shutter_width, so_p, t_pix_clk, sd_p, shutter_delay; -+ int sw_l ,sw_u ,W ,h_blanking, t_row; -+ -+ if(exp_time < MT9P031_MIN_EXPOSURE) -+ exp_time = MT9P031_MIN_EXPOSURE; -+ else if(exp_time > MT9P031_MAX_EXPOSURE) -+ exp_time = MT9P031_MAX_EXPOSURE; -+ -+ shutter_delay = mt9p031_supported_formats[mt9p031_current_format].shutter_delay; -+ sd_p = min(shutter_delay + 1, 1504); -+ so_p = 208 * (mt9p031_supported_formats[mt9p031_current_format].row_bin + 1) + 98 + sd_p - 94; -+ t_pix_clk = (Q12/96 ); -+ h_blanking = mt9p031_supported_formats[mt9p031_current_format].hblank + 1; -+ W = 2 * (int)((mt9p031_supported_formats[mt9p031_current_format].row_size + 1) / (2 * (mt9p031_supported_formats[mt9p031_current_format].row_bin + 1)) + 1); -+ t_row = 2 * t_pix_clk * max(W/2 + max(h_blanking, hb_min[mt9p031_supported_formats[mt9p031_current_format].row_bin][mt9p031_supported_formats[mt9p031_current_format].col_bin]), -+ (41 + 346 * (mt9p031_supported_formats[mt9p031_current_format].row_bin + 1) + 99))/Q12; -+ -+ shutter_width = (exp_time + 2*so_p*t_pix_clk) / t_row; -+ -+ if (shutter_width< 3) { -+ sd_p = 1232 > shutter_delay ? 1232 : shutter_delay; -+ so_p = 208 * (mt9p031_supported_formats[mt9p031_current_format].row_bin + 1) + 98 + sd_p - 94; -+ shutter_width = ((exp_time*Q12 + 2*so_p*t_pix_clk) / (t_row * Q12)); -+ } -+ -+ if (shutter_width < 1) -+ shutter_width = 1; -+ sw_l = shutter_width& 0xffff; -+ sw_u = (shutter_width)>> 16; -+ ret = mt9p031_reg_write(client, REG_MT9P031_SHUTTER_WIDTH_L,sw_l); -+ mdelay(1); -+ ret = mt9p031_reg_write(client, REG_MT9P031_SHUTTER_WIDTH_U,sw_u); -+ -+ if (ret) -+ dev_err(&client->dev, "Error setting exposure time %d\n", -+ ret); -+ else{ -+ i = find_vctrl(V4L2_CID_EXPOSURE); -+ if (i >= 0) { -+ lvc = &mt9p031_video_control[i]; -+ lvc->current_value = exp_time; -+ } -+ } -+ -+ return ret; -+} -+ -+/** -+ * mt9p031_set_gain - sets sensor analog gain per input value -+ * @lineargain: analog gain value index to be set on device -+ * @client: pointer to standard i2c client -+ * @lvc: pointer to V4L2 analog gain entry in video_controls array -+ * -+ * If the requested analog gain is within the allowed limits, the HW -+ * is configured to use the new gain value, and the video_controls -+ * array is updated with the new current value. -+ * The function returns 0 upon success. Otherwise an error code is -+ * returned. -+ */ -+int mt9p031_set_gain(u16 lineargain, struct i2c_client *client, -+ struct vcontrol *lvc) -+{ -+ int ret= 0, i; -+ u16 reg_gain = 0; -+ -+ if (lineargain < MT9P031_EV_MIN_GAIN) { -+ lineargain = MT9P031_EV_MIN_GAIN; -+ v4l_err(client, "Gain out of legal range."); -+ } -+ if (lineargain > MT9P031_EV_MAX_GAIN) { -+ lineargain = MT9P031_EV_MAX_GAIN; -+ v4l_err(client, "Gain out of legal range."); -+ } -+ -+ reg_gain = MT9P031_EV_GAIN_TBL[lineargain]; -+ ret = mt9p031_reg_write(client, REG_MT9P031_GLOBAL_GAIN, -+ reg_gain); -+ -+ if (ret) { -+ dev_err(&client->dev, "Error setting gain.%d", ret); -+ return ret; -+ } -+ else { -+ i = find_vctrl(V4L2_CID_GAIN); -+ if (i >= 0) { -+ lvc = &mt9p031_video_control[i]; -+ lvc->current_value = lineargain; -+ } -+ } -+ -+ return ret; -+} -+ -+/************************************************************************ -+ v4l2_ioctls -+************************************************************************/ -+ -+/** -+ * mt9p031_v4l2_int_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num -+ * @s: pointer to standard V4L2 device structure -+ * @on: power state to which device is to be set -+ * -+ * Sets devices power state to requrested state, if possible. -+ */ -+static int mt9p031_v4l2_int_s_power(struct v4l2_int_device *s, -+ enum v4l2_power power) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ struct i2c_client *client = priv->client; -+ -+ int ret; -+ -+ switch (power) { -+ case V4L2_POWER_STANDBY: -+ /* FALLTHROUGH */ -+ case V4L2_POWER_OFF: -+ ret = priv->pdata->power_set(s, power); -+ if (ret < 0) { -+ dev_err(&client->dev, "Unable to set target board power " -+ "state (OFF/STANDBY)\n"); -+ return ret; -+ } -+ break; -+ case V4L2_POWER_ON: -+ ret = priv->pdata->power_set(s, power); -+ -+ if (ret < 0) { -+ dev_err(&client->dev, "Unable to set target board power " -+ "state (ON)\n"); -+ return ret; -+ } -+ if (!(priv->flags & INIT_DONE)) { -+ ret = mt9p031_detect(client); -+ if (ret < 0) { -+ dev_err(&client->dev, "Unable to detect sensor\n"); -+ return ret; -+ } -+ priv->flags |= INIT_DONE; -+ } -+ -+ ret = mt9p031_init_camera(client); -+ if (ret < 0) { -+ dev_err(&client->dev, "Unable to initialize sensor\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int mt9p031_v4l2_s_ctrl(struct v4l2_int_device *s, -+ struct v4l2_control *vc) -+{ -+ int retval = -EINVAL; -+ int i; -+ struct vcontrol *lvc; -+ struct mt9p031_priv *priv = s->priv; -+ struct i2c_client *client = priv->client; -+ -+ i = find_vctrl(vc->id); -+ if (i < 0) -+ return -EINVAL; -+ lvc = &mt9p031_video_control[i]; -+ -+ switch (vc->id) { -+ case V4L2_CID_EXPOSURE: -+ retval = mt9p031_set_exposure_time(vc->value, client, lvc); -+ break; -+ case V4L2_CID_GAIN: -+ retval = mt9p031_set_gain(vc->value, client, lvc); -+ break; -+ } -+ -+ return retval; -+} -+ -+/** -+ * mt9p031_v4l2_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int mt9p031_v4l2_g_ctrl(struct v4l2_int_device *s, -+ struct v4l2_control *vc) -+{ -+ struct vcontrol *lvc; -+ int i; -+ -+ i = find_vctrl(vc->id); -+ if (i < 0) -+ return -EINVAL; -+ lvc = &mt9p031_video_control[i]; -+ -+ switch (vc->id) { -+ case V4L2_CID_EXPOSURE: -+ vc->value = lvc->current_value; -+ break; -+ case V4L2_CID_GAIN: -+ vc->value = lvc->current_value; -+ break; -+ } -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control information -+ * from the video_control[] array. Otherwise, returns -EINVAL if the -+ * control is not supported. -+ */ -+static int mt9p031_v4l2_queryctrl(struct v4l2_int_device *s, struct v4l2_queryctrl *qc) -+{ -+ int i; -+ -+ i = find_vctrl(qc->id); -+ if (i == -EINVAL) -+ qc->flags = V4L2_CTRL_FLAG_DISABLED; -+ -+ if (i < 0) -+ return -EINVAL; -+ -+ *qc = mt9p031_video_control[i].qc; -+ return 0; -+} -+ -+ -+/** -+ * mt9p031_v4l2_int_enum_fmt_cap - Implement the CAPTURE buffer VIDIOC_ENUM_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: standard V4L2 VIDIOC_ENUM_FMT ioctl structure -+ * -+ * Implement the VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. -+ */ -+static int mt9p031_v4l2_int_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ int index = fmt->index; -+ enum v4l2_buf_type type = fmt->type; -+ -+ memset(fmt, 0, sizeof(*fmt)); -+ fmt->index = index; -+ fmt->type = type; -+ -+ switch (fmt->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ if (index >= ARRAY_SIZE(mt9p031_formats)) -+ return -EINVAL; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ strlcpy(fmt->description, mt9p031_formats[index].description, -+ sizeof(fmt->description)); -+ fmt->pixelformat = mt9p031_formats[index].pixelformat; -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_int_try_fmt_cap - Implement the CAPTURE buffer VIDIOC_TRY_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 VIDIOC_TRY_FMT ioctl structure -+ * -+ * Implement the VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. This -+ * ioctl is used to negotiate the image capture size and pixel format -+ * without actually making it take effect. -+ */ -+static int mt9p031_v4l2_int_try_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ enum mt9p031_image_size isize; -+ int ifmt; -+ struct v4l2_pix_format *pix = &f->fmt.pix; -+ struct mt9p031_priv *priv = s->priv; -+ struct v4l2_pix_format *pix2 = &priv->pix; -+ -+ isize = mt9p031_calc_size(pix->width, pix->height); -+ mt9p031_current_format = isize; -+ -+ pix->width = mt9p031_sizes[isize].width; -+ pix->height = mt9p031_sizes[isize].height; -+ for (ifmt = 0; ifmt < mt9p031_num_formats; ifmt++) { -+ if (pix->pixelformat == mt9p031_formats[ifmt].pixelformat) -+ break; -+ } -+ if (ifmt == mt9p031_num_formats) -+ ifmt = 0; -+ pix->pixelformat = mt9p031_formats[ifmt].pixelformat; -+ pix->field = V4L2_FIELD_NONE; -+ pix->bytesperline = pix->width * 2; -+ pix->sizeimage = pix->bytesperline * pix->height; -+ pix->priv = 0; -+ pix->colorspace = V4L2_COLORSPACE_SRGB; -+ -+ *pix2 = *pix; -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_int_s_fmt_cap - V4L2 sensor interface handler for VIDIOC_S_FMT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 VIDIOC_S_FMT ioctl structure -+ * -+ * If the requested format is supported, configures the HW to use that -+ * format, returns error code if format not supported or HW can't be -+ * correctly configured. -+ */ -+static int mt9p031_v4l2_int_s_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ struct v4l2_pix_format *pix = &f->fmt.pix; -+ int rval; -+ -+ rval = mt9p031_v4l2_int_try_fmt_cap(s, f); -+ if (!rval) -+ priv->pix = *pix; -+ -+ return rval; -+} -+ -+/** -+ * mt9p031_v4l2_int_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int mt9p031_v4l2_int_g_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ -+ f->fmt.pix.width = priv->pix.width; -+ f->fmt.pix.height = priv->pix.height; -+ f->fmt.pix.pixelformat = V4L2_COLORSPACE_SRGB; -+ f->fmt.pix.pixelformat = priv->pix.pixelformat; -+ f->fmt.pix.field = V4L2_FIELD_NONE; -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_int_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+ -+ -+static int mt9p031_v4l2_int_s_parm(struct v4l2_int_device *s, -+ struct v4l2_streamparm *a) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ struct i2c_client *client = priv->client; -+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; -+ -+ priv->timeperframe = *timeperframe; -+ priv->xclk_current = mt9p031_calc_xclk(client); -+ *timeperframe = priv->timeperframe; -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_int_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int mt9p031_v4l2_int_g_parm(struct v4l2_int_device *s, -+ struct v4l2_streamparm *a) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ -+ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; -+ -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ cparm->capability = V4L2_CAP_TIMEPERFRAME; -+ cparm->timeperframe.numerator = 1; -+ cparm->timeperframe = priv->timeperframe; -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_int_g_priv - V4L2 sensor interface handler for vidioc_int_g_priv_num -+ * @s: pointer to standard V4L2 device structure -+ * @p: void pointer to hold sensor's private data address -+ * -+ * Returns device's (sensor's) private data area address in p parameter -+ */ -+static int mt9p031_v4l2_int_g_priv(struct v4l2_int_device *s, void *p) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ -+ return priv->pdata->priv_data_set(p); -+} -+ -+/** -+ * mt9p031_v4l2_int_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_priv_num -+ * @s: pointer to standard V4L2 device structure -+ * @p: void pointer to hold sensor's ifparm -+ * -+ * Returns device's (sensor's) ifparm in p parameter -+ */ -+static int mt9p031_v4l2_int_g_ifparm(struct v4l2_int_device *s, -+ struct v4l2_ifparm *p) -+{ -+ struct mt9p031_priv *priv = s->priv; -+ int rval; -+ -+ if (p == NULL) -+ return -EINVAL; -+ -+ if (!priv->pdata->ifparm) -+ return -EINVAL; -+ -+ rval = priv->pdata->ifparm(p); -+ if (rval) { -+ v4l_err(priv->client, "g_ifparm.Err[%d]\n", rval); -+ return rval; -+ } -+ -+ return 0; -+} -+ -+/** -+ * mt9p031_v4l2_int_enum_framesizes - V4L2 sensor if handler for vidioc_int_enum_framesizes -+ * @s: pointer to standard V4L2 device structure -+ * @frms: pointer to standard V4L2 framesizes enumeration structure -+ * -+ * Returns possible framesizes depending on choosen pixel format -+ */ -+static int mt9p031_v4l2_int_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *frms) -+{ -+ int ifmt; -+ -+ for (ifmt = 0; ifmt < ARRAY_SIZE(mt9p031_formats); ifmt++) -+ if (mt9p031_formats[ifmt].pixelformat == frms->pixel_format) -+ break; -+ -+ if (ifmt == ARRAY_SIZE(mt9p031_formats)) -+ return -EINVAL; -+ -+ /* Do we already reached all discrete framesizes? */ -+ if (frms->index >= ARRAY_SIZE(mt9p031_sizes)) -+ return -EINVAL; -+ -+ frms->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frms->discrete.width = mt9p031_sizes[frms->index].width; -+ frms->discrete.height = mt9p031_sizes[frms->index].height; -+ -+ return 0; -+} -+ -+static int mt9p031_v4l2_int_enum_frameintervals(struct v4l2_int_device *s, -+ struct v4l2_frmivalenum *frmi) -+{ -+ int ifmt; -+ int max_size; -+ -+ for (ifmt = 0; ifmt < ARRAY_SIZE(mt9p031_formats); ifmt++) -+ if (mt9p031_formats[ifmt].pixelformat == frmi->pixel_format) -+ break; -+ -+ if (ifmt == ARRAY_SIZE(mt9p031_formats)) -+ return -EINVAL; -+ -+ max_size = ARRAY_SIZE(mt9p031_sizes); -+ -+ for(ifmt = 0; ifmt < max_size; ifmt++) { -+ if(frmi->width <= mt9p031_sizes[ifmt].width) { -+ frmi->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ frmi->discrete.numerator = -+ mt9p031_frameintervals[frmi->index].numerator; -+ frmi->discrete.denominator = -+ mt9p031_frameintervals[frmi->index].denominator; -+ -+ if(frmi->discrete.denominator <= mt9p031_frameintervals[max_size - ifmt - 1].denominator) -+ return 0; -+ else -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+static struct v4l2_int_ioctl_desc mt9p031_ioctl_desc[] = { -+ { .num = vidioc_int_enum_framesizes_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_enum_framesizes }, -+ { .num = vidioc_int_enum_frameintervals_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_enum_frameintervals }, -+ { .num = vidioc_int_s_power_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_s_power }, -+ { .num = vidioc_int_g_priv_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_g_priv }, -+ { .num = vidioc_int_g_ifparm_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_g_ifparm }, -+ { .num = vidioc_int_enum_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_enum_fmt_cap }, -+ { .num = vidioc_int_try_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_try_fmt_cap }, -+ { .num = vidioc_int_g_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_g_fmt_cap }, -+ { .num = vidioc_int_s_fmt_cap_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_s_fmt_cap }, -+ { .num = vidioc_int_g_parm_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_g_parm }, -+ { .num = vidioc_int_s_parm_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_int_s_parm }, -+ { .num = vidioc_int_g_ctrl_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_g_ctrl }, -+ { .num = vidioc_int_s_ctrl_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_s_ctrl }, -+ { .num = vidioc_int_queryctrl_num, -+ .func = (v4l2_int_ioctl_func *)mt9p031_v4l2_queryctrl }, -+}; -+ -+#ifdef MT9P031_DEBUG -+/** -+ * --------------------------------------------------------------------------------- -+ * Sysfs -+ * --------------------------------------------------------------------------------- -+ */ -+ -+/* Basic register read write support */ -+static u16 mt9p031_attr_basic_addr = 0x0000; -+ -+static ssize_t -+mt9p031_basic_reg_addr_show( struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "0x%x\n", mt9p031_attr_basic_addr); -+} -+ -+static ssize_t -+mt9p031_basic_reg_addr_store( struct device *dev, struct device_attribute *attr, const char *buf, size_t n) -+{ -+ u16 val; -+ sscanf(buf, "%hx", &val); -+ mt9p031_attr_basic_addr = (u16) val; -+ return n; -+} -+ -+static DEVICE_ATTR( basic_reg_addr, S_IRUGO|S_IWUSR, mt9p031_basic_reg_addr_show, mt9p031_basic_reg_addr_store); -+ -+ -+static ssize_t -+mt9p031_basic_reg_val_show( struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ u16 val; -+ int ret; -+ ret = mt9p031_reg_read(sysPriv.client, mt9p031_attr_basic_addr, &val); -+ if(ret < 0){ -+ printk(KERN_INFO "mt9p031: Basic register read failed"); -+ return 1; // nothing processed -+ } else { -+ return sprintf(buf, "0x%x\n", val); -+ } -+} -+ -+static ssize_t -+mt9p031_basic_reg_val_store( struct device *dev, struct device_attribute *attr, const char *buf, size_t n) -+{ -+ u32 val; -+ sscanf(buf, "%x", &val); -+ -+ if (mt9p031_reg_write(sysPriv.client, mt9p031_attr_basic_addr, (u16)val)) { -+ printk(KERN_INFO "mt9p031: Basic regiser write failed"); -+ return n; // nothing processed -+ } else { -+ return n; -+ } -+} -+static DEVICE_ATTR( basic_reg_val, S_IRUGO|S_IWUSR, mt9p031_basic_reg_val_show, mt9p031_basic_reg_val_store); -+ -+ -+/* Exposure time access support */ -+static ssize_t -+mt9p031_exposure_val_show( struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ u32 val; -+ struct vcontrol *lvc; -+ int i = find_vctrl(V4L2_CID_EXPOSURE); -+ if (i < 0) -+ return -EINVAL; -+ lvc = &mt9p031_video_control[i]; -+ val = lvc->current_value; -+ -+ if(val < 0){ -+ printk(KERN_INFO "mt9p031: Exposure value read failed"); -+ return 1; // nothing processed -+ } else { -+ return sprintf(buf, "%d\n", val); -+ } -+} -+ -+ -+static ssize_t -+mt9p031_exposure_val_store( struct device *dev, struct device_attribute *attr, const char *buf, size_t n) -+{ -+ u32 val; -+ struct i2c_client *client; -+ struct vcontrol *lvc; -+ -+ sscanf(buf, "%d", &val); -+ client = sysPriv.client; -+ -+ lvc = &mt9p031_video_control[V4L2_CID_EXPOSURE]; -+ -+ if (mt9p031_set_exposure_time((u32)val, client, lvc)) { -+ printk(KERN_INFO "mt9p031: Exposure write failed"); -+ return n; // nothing processed -+ } else { -+ return n; -+ } -+} -+ -+static DEVICE_ATTR( exposure_val, S_IRUGO|S_IWUSR, mt9p031_exposure_val_show, mt9p031_exposure_val_store); -+ -+ -+/* Global Gain access support */ -+static ssize_t -+mt9p031_gain_val_show( struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ u16 val; -+ struct vcontrol *lvc; -+ -+ int i = find_vctrl(V4L2_CID_GAIN); -+ if (i < 0) -+ return -EINVAL; -+ lvc = &mt9p031_video_control[i]; -+ val = lvc->current_value; -+ -+ if(val < 0){ -+ printk(KERN_INFO "mt9p031: Global Gain value read failed"); -+ return 1; // nothing processed -+ } else { -+ return sprintf(buf, "%d\n", val); -+ } -+} -+ -+static ssize_t -+mt9p031_gain_val_store( struct device *dev, struct device_attribute *attr, const char *buf, size_t n) -+{ -+ u16 val; -+ struct i2c_client *client; -+ struct vcontrol *lvc; -+ -+ sscanf(buf, "%hd", &val); -+ client = sysPriv.client; -+ -+ lvc = &mt9p031_video_control[V4L2_CID_GAIN]; -+ -+ if (mt9p031_set_gain(val, client, lvc)) { -+ printk(KERN_INFO "mt9p031: Global gain write failed"); -+ return n; // nothing processed -+ } else { -+ return n; -+ } -+} -+ -+static DEVICE_ATTR( gain_val, S_IRUGO|S_IWUSR, mt9p031_gain_val_show, mt9p031_gain_val_store); -+ -+ -+static struct attribute *mt9p031_sysfs_attr[] = { -+ &dev_attr_basic_reg_addr.attr, -+ &dev_attr_basic_reg_val.attr, -+ &dev_attr_exposure_val.attr, -+ &dev_attr_gain_val.attr, -+}; -+ -+static int mt9p031_sysfs_add(struct kobject *kobj) -+{ -+ int i = ARRAY_SIZE(mt9p031_sysfs_attr); -+ int rval = 0; -+ -+ do { -+ rval = sysfs_create_file(kobj, mt9p031_sysfs_attr[--i]); -+ } while((i > 0) && (rval == 0)); -+ return rval; -+} -+ -+static int mt9p031_sysfs_rm(struct kobject *kobj) -+{ -+ int i = ARRAY_SIZE(mt9p031_sysfs_attr); -+ int rval = 0; -+ -+ do { -+ sysfs_remove_file(kobj, mt9p031_sysfs_attr[--i]); -+ } while(i > 0); -+ return rval; -+} -+#endif //MT9P031_DEBUG -+ -+static struct v4l2_int_slave mt9p031_slave = { -+ .ioctls = mt9p031_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(mt9p031_ioctl_desc), -+}; -+ -+static int mt9p031_probe(struct i2c_client *client, -+ const struct i2c_device_id *did) -+{ -+ struct mt9p031_priv *priv; -+ struct v4l2_int_device *v4l2_int_device; -+ int ret; -+ if (!client->dev.platform_data) { -+ dev_err(&client->dev, "no platform data?\n"); -+ return -ENODEV; -+ } -+ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ v4l2_int_device = kzalloc(sizeof(*v4l2_int_device), GFP_KERNEL); -+ if (!v4l2_int_device) { -+ kfree(priv); -+ return -ENOMEM; -+ } -+ -+#ifdef MT9P031_HEADBOARD -+ mt9p031_config_PCA9543A(client); //configure i2c level shifter on mt9p031 head-board, no need for Leopard module -+ mdelay(10); -+#endif //MT9P031_HEADBOARD -+ -+ v4l2_int_device->module = THIS_MODULE; -+ strncpy(v4l2_int_device->name, "mt9p031", sizeof(v4l2_int_device->name)); -+ -+ v4l2_int_device->type = v4l2_int_type_slave; -+ v4l2_int_device->u.slave = &mt9p031_slave; -+ -+ v4l2_int_device->priv = priv; -+ -+ priv->v4l2_int_device = v4l2_int_device; -+ priv->client = client; -+ priv->pdata = client->dev.platform_data; -+ -+ priv->pdata->flags = MT9P031_FLAG_PCLK_RISING_EDGE; -+ -+ /* Setting Pixel Values */ -+ priv->pix.width = mt9p031_sizes[0].width; -+ priv->pix.height = mt9p031_sizes[0].height; -+ priv->pix.pixelformat = mt9p031_formats[0].pixelformat; -+ -+ i2c_set_clientdata(client, priv); -+ -+ sysPriv.client = priv->client; -+ -+ ret = v4l2_int_device_register(priv->v4l2_int_device); -+ if (ret) { -+ i2c_set_clientdata(client, NULL); -+ kfree(v4l2_int_device); -+ kfree(priv); -+ } -+ -+#ifdef MT9P031_DEBUG -+ mt9p031_sysfs_add(&client->dev.kobj); -+#endif //MT9P031_DEBUG -+ return ret; -+} -+ -+static int mt9p031_remove(struct i2c_client *client) -+{ -+ struct mt9p031_priv *priv = i2c_get_clientdata(client); -+ -+ v4l2_int_device_unregister(priv->v4l2_int_device); -+ i2c_set_clientdata(client, NULL); -+ mt9p031_sysfs_rm(&client->dev.kobj); -+ -+ kfree(priv->v4l2_int_device); -+ kfree(priv); -+ return 0; -+} -+ -+static const struct i2c_device_id mt9p031_id[] = { -+ { "mt9p031", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, mt9p031_id); -+ -+static struct i2c_driver mt9p031_i2c_driver = { -+ .driver = { -+ .name = "mt9p031", -+ }, -+ .probe = mt9p031_probe, -+ .remove = mt9p031_remove, -+ .id_table = mt9p031_id, -+}; -+ -+/************************************************************************ -+ module function -+************************************************************************/ -+static int __init mt9p031_module_init(void) -+{ -+ return i2c_add_driver(&mt9p031_i2c_driver); -+} -+ -+static void __exit mt9p031_module_exit(void) -+{ -+ i2c_del_driver(&mt9p031_i2c_driver); -+} -+ -+module_init(mt9p031_module_init); -+module_exit(mt9p031_module_exit); -+ -+MODULE_DESCRIPTION("mt9p031 sensor driver"); -+MODULE_AUTHOR("Aptina"); -+MODULE_LICENSE("GPL v2"); -+ -diff --git a/include/media/mt9p031.h b/include/media/mt9p031.h -new file mode 100644 -index 0000000..d119589 ---- /dev/null -+++ b/include/media/mt9p031.h -@@ -0,0 +1,30 @@ -+/* mt9p031 Camera -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef __MT9P031_H__ -+#define __MT9P031_H__ -+ -+#include -+ -+#define MT9P031_I2C_ADDR 0x48 //(0x90 >> 1) -+ -+#define MT9P031_CLK_MAX (27000000) /* 27MHz */ -+#define MT9P031_CLK_MIN (6000000) /* 6Mhz */ -+ -+#define MT9P031_FLAG_PCLK_RISING_EDGE (1 << 0) -+#define MT9P031_FLAG_DATAWIDTH_8 (1 << 1) /* default width is 10 */ -+ -+struct mt9p031_platform_data { -+ char *master; -+ int (*power_set) (struct v4l2_int_device *s, enum v4l2_power on); -+ int (*ifparm) (struct v4l2_ifparm *p); -+ int (*priv_data_set) (void *); -+ u32 (*set_xclk) (struct v4l2_int_device *s, u32 xclkfreq); -+ u32 flags; -+}; -+ -+#endif /* __MT9P031_H__ */ -diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h -index 6cc107d..7599bf1 100644 ---- a/include/media/v4l2-chip-ident.h -+++ b/include/media/v4l2-chip-ident.h -@@ -271,6 +271,7 @@ enum { - V4L2_IDENT_MT9T112 = 45022, - V4L2_IDENT_MT9V111 = 45031, - V4L2_IDENT_MT9V112 = 45032, -+ V4L2_IDENT_MT9P031 = 6145, - - /* HV7131R CMOS sensor: just ident 46000 */ - V4L2_IDENT_HV7131R = 46000, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/5m03/0002-board-omap3beagle-import-li5m03-driver-from-https-gi.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/5m03/0002-board-omap3beagle-import-li5m03-driver-from-https-gi.patch deleted file mode 100644 index 2b45f197..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/cam/5m03/0002-board-omap3beagle-import-li5m03-driver-from-https-gi.patch +++ /dev/null @@ -1,294 +0,0 @@ -From 675ad06f53fbb0c7f398aaff8c3508196dfeb9bc Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Sun, 1 May 2011 16:41:57 +0200 -Subject: [PATCH 2/2] board-omap3beagle: import li5m03 driver from https://github.com/Aptina/BeagleBoard-xM/tree/master/Angstrom/MT9P031 - -Properly hook it into the board file and some more updates - -Signed-off-by: Koen Kooi ---- - arch/arm/mach-omap2/board-omap3beagle-camera.c | 186 +++++++++++++++++++++++- - arch/arm/mach-omap2/board-omap3beagle.c | 20 +++ - 2 files changed, 198 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle-camera.c b/arch/arm/mach-omap2/board-omap3beagle-camera.c -index 110c2c9..97f0e7a 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle-camera.c -+++ b/arch/arm/mach-omap2/board-omap3beagle-camera.c -@@ -160,6 +160,8 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - case V4L2_POWER_ON: - - isp_configure_interface(vdev->cam->isp, &mt9v113_if_config); -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ - regulator_enable(cam_1v8_reg); -@@ -168,9 +170,6 @@ static int mt9v113_power_set(struct v4l2_int_device *s, enum v4l2_power power) - regulator_enable(cam_2v8_reg); - mdelay(50); - -- /* Set RESET_BAR to 0 */ -- gpio_set_value(LEOPARD_RESET_GPIO, 0); -- - /* Enable EXTCLK */ - isp_set_xclk(vdev->cam->isp, MT9V113_CLK_MIN*2, CAM_USE_XCLKA); - /* -@@ -294,7 +293,7 @@ static int mt9t112_set_prv_data(void *priv) - } - - /** -- * @brief mt9t112_power_set - Power-on or power-off TVP5146 device -+ * @brief mt9t112_power_set - Power-on or power-off MT9T112 device - * - * @param power - enum, Power on/off, resume/standby - * -@@ -320,6 +319,8 @@ static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power) - isp_configure_interface(vdev->cam->isp, &mt9t112_if_config); - #endif - -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); - - /* turn on VDD */ - regulator_enable(cam_1v8_reg); -@@ -331,11 +332,8 @@ static int mt9t112_power_set(struct v4l2_int_device *s, enum v4l2_power power) - - mdelay(50); - -- /* Set RESET_BAR to 0 */ -- gpio_set_value(LEOPARD_RESET_GPIO, 0); -- - /* Enable EXTCLK */ -- isp_set_xclk(vdev->cam->isp, 24000000, CAM_USE_XCLKA); -+ isp_set_xclk(vdev->cam->isp, 12000000, CAM_USE_XCLKA); - - /* - * Wait at least 70 CLK cycles (w/EXTCLK = 24MHz): -@@ -372,6 +370,178 @@ struct mt9t112_platform_data mt9t112_pdata = { - - #endif /* #ifdef CONFIG_VIDEO_MT9T112 */ - -+#if defined(CONFIG_SOC_CAMERA_MT9P031) || defined(CONFIG_SOC_CAMERA_MT9P031_MODULE) -+#include -+ -+#define ISP_MT9P031_MCLK 216000000 -+ -+/* Arbitrary memory handling limit */ -+#define MT9P031_BIGGEST_FRAME_BYTE_SIZE PAGE_ALIGN((2592 * 1944) * 2 * 4 ) -+ -+static struct isp_interface_config mt9p031_if_config = { -+ .ccdc_par_ser = ISP_PARLL, -+ .dataline_shift = 0x1, -+ .hsvs_syncdetect = ISPCTRL_SYNC_DETECT_VSRISE, -+ .strobe = 0x0, -+ .prestrobe = 0x0, -+ .shutter = 0x0, -+ .cam_mclk = ISP_MT9P031_MCLK, -+ .wenlog = ISPCCDC_CFG_WENLOG_AND, -+ .wait_hs_vs = 2, -+ .u.par.par_bridge = 0x0, -+ .u.par.par_clk_pol = 0x0, -+}; -+ -+static struct v4l2_ifparm mt9p031_ifparm_s = { -+ .if_type = V4L2_IF_TYPE_RAW, -+ .u = { -+ .raw = { -+ .frame_start_on_rising_vs = 1, -+ .bt_sync_correct = 0, -+ .swap = 0, -+ .latch_clk_inv = 0, -+ .nobt_hs_inv = 0, /* active high */ -+ .nobt_vs_inv = 0, /* active high */ -+ .clock_min = MT9P031_CLK_MIN, -+ .clock_max = MT9P031_CLK_MAX, -+ }, -+ }, -+}; -+ -+/** -+ * @brief mt9p031_ifparm - Returns the mt9p031 interface parameters -+ * -+ * @param p - pointer to v4l2_ifparm structure -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9p031_ifparm(struct v4l2_ifparm *p) -+{ -+ if (p == NULL) -+ return -EINVAL; -+ -+ *p = mt9p031_ifparm_s; -+ return 0; -+} -+ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+static struct omap34xxcam_hw_config mt9p031_hwc = { -+ .dev_index = 1, -+ .dev_minor = -1, -+ .dev_type = OMAP34XXCAM_SLAVE_SENSOR, -+ .u.sensor.sensor_isp = 0, -+ .u.sensor.capture_mem = MT9P031_BIGGEST_FRAME_BYTE_SIZE, -+ .u.sensor.ival_default = { 1, 30 }, -+}; -+#endif -+ -+/** -+ * @brief mt9p031_set_prv_data - Returns mt9p031 omap34xx driver private data -+ * -+ * @param priv - pointer to omap34xxcam_hw_config structure -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9p031_set_prv_data(void *priv) -+{ -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+ struct omap34xxcam_hw_config *hwc = priv; -+ -+ if (priv == NULL) -+ return -EINVAL; -+ -+ *hwc = mt9p031_hwc; -+ return 0; -+#else -+ return -EINVAL; -+#endif -+} -+ -+/** -+ * @brief mt9p031_power_set - Power-on or power-off mt9p031 device -+ * -+ * @param power - enum, Power on/off, resume/standby -+ * -+ * @return result of operation - 0 is success -+ */ -+static int mt9p031_power_set(struct v4l2_int_device *s, enum v4l2_power power) -+{ -+ struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; -+ switch (power) { -+ case V4L2_POWER_OFF: -+ case V4L2_POWER_STANDBY: -+ isp_set_xclk(vdev->cam->isp, 0, CAM_USE_XCLKA); -+ -+ if (regulator_is_enabled(cam_1v8_reg)) -+ regulator_disable(cam_1v8_reg); -+ if (regulator_is_enabled(cam_2v8_reg)) -+ regulator_disable(cam_2v8_reg); -+ break; -+ -+ case V4L2_POWER_ON: -+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) -+ isp_configure_interface(vdev->cam->isp, &mt9p031_if_config); -+#endif -+ -+ /* Set RESET_BAR to 0 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 0); -+ -+ /* turn on VDD */ -+ regulator_enable(cam_1v8_reg); -+ -+ mdelay(1); -+ -+ /* turn on VDD_IO */ -+ regulator_enable(cam_2v8_reg); -+ -+ mdelay(50); -+ -+ /* Enable EXTCLK */ -+ isp_set_xclk(vdev->cam->isp, 24000000, CAM_USE_XCLKA); //works for 36MHz too; try at lower freq -+ -+ /* -+ * Wait at least 70 CLK cycles (w/EXTCLK = 24MHz): -+ * ((1000000 * 70) / 24000000) = aprox 2.91 us. -+ */ -+ -+ udelay(3); -+ -+ /* Set RESET_BAR to 1 */ -+ gpio_set_value(LEOPARD_RESET_GPIO, 1); -+ -+ /* -+ * Wait at least 100 CLK cycles (w/EXTCLK = 24MHz): -+ * ((1000000 * 100) / 24000000) = aprox 4.16 us. -+ */ -+ -+ udelay(5); -+ -+ break; -+ -+ default: -+ return -ENODEV; -+ break; -+ } -+ return 0; -+} -+ -+static u32 mt9p031_set_xclk(struct v4l2_int_device *s, u32 xclkfreq) -+{ -+ struct omap34xxcam_videodev *vdev = s->u.slave->master->priv; -+ return isp_set_xclk(vdev->cam->isp, xclkfreq, 0); -+} -+ -+ -+struct mt9p031_platform_data mt9p031_pdata = { -+ .master = "omap34xxcam", -+ .power_set = mt9p031_power_set, -+ .set_xclk = mt9p031_set_xclk, -+ .priv_data_set = mt9p031_set_prv_data, -+ .ifparm = mt9p031_ifparm, -+}; -+ -+#endif /* #ifdef CONFIG_SOC_CAMERA_MT9P031 */ -+ - static int beagle_cam_probe(struct platform_device *pdev) - { - cam_1v8_reg = regulator_get(&pdev->dev, "cam_1v8"); -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 2677b41..e561431 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -83,6 +83,12 @@ extern struct mt9v113_platform_data mt9v113_pdata; - extern struct mt9t112_platform_data mt9t112_pdata; - #endif - -+#if defined(CONFIG_SOC_CAMERA_MT9P031) || defined(CONFIG_SOC_CAMERA_MT9P031_MODULE) -+#include -+#include -+extern struct mt9p031_platform_data mt9p031_pdata; -+#endif -+ - #define GPMC_CS0_BASE 0x60 - #define GPMC_CS_SIZE 0x30 - -@@ -614,6 +620,15 @@ static struct i2c_board_info __initdata beagle_lbcm3m1_i2c2_boardinfo[] = { - #endif - }; - -+static struct i2c_board_info __initdata beagle_lbcm5m03_i2c2_boardinfo[] = { -+#if defined(CONFIG_SOC_CAMERA_MT9P031) || defined(CONFIG_SOC_CAMERA_MT9P031_MODULE) -+ { -+ I2C_BOARD_INFO("mt9p031", MT9P031_I2C_ADDR), -+ .platform_data = &mt9p031_pdata, -+ }, -+#endif -+}; -+ - static int __init omap3_beagle_i2c_init(void) - { - omap_register_i2c_bus(1, 2600, beagle_i2c1_boardinfo, -@@ -636,6 +651,11 @@ static int __init omap3_beagle_i2c_init(void) - " registering i2c2 bus for lbcm3m1\n"); - omap_register_i2c_bus(2, 400, beagle_lbcm3m1_i2c2_boardinfo, - ARRAY_SIZE(beagle_lbcm3m1_i2c2_boardinfo)); -+ } else if (!strcmp(cameraboard_name, "lbcm5m03")) { -+ printk(KERN_INFO "Beagle cameraboard:" -+ " registering i2c2 bus for lbcm5m03\n"); -+ omap_register_i2c_bus(2, 400, beagle_lbcm5m03_i2c2_boardinfo, -+ ARRAY_SIZE(beagle_lbcm5m03_i2c2_boardinfo)); - } else { - omap_register_i2c_bus(2, 400, NULL, 0); - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/dm37x-evm/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/dm37x-evm/defconfig deleted file mode 100644 index 8f1868df..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/dm37x-evm/defconfig +++ /dev/null @@ -1,2024 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Fri Jul 9 10:08:46 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=m -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -# CONFIG_OMAP_MBOX_FWK is not set -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_LL_DEBUG_UART1=y -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -# CONFIG_OMAP_LL_DEBUG_UART3 is not set -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -CONFIG_OMAP_PM_NOOP=y -# CONFIG_OMAP_PM_SRF is not set -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -CONFIG_MACH_OMAP3EVM=y -CONFIG_PMIC_TWL4030=y -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -# CONFIG_ARM_THUMBEE is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_USER_L2_PLE is not set -# CONFIG_USER_PMON is not set -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -# CONFIG_KEXEC is not set - -# -# CPU Power Management -# -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_OMAP_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -# CONFIG_MTD_NAND_OMAP_PREFETCH is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -# CONFIG_MTD_ONENAND_GENERIC is not set -CONFIG_MTD_ONENAND_OMAP2=y -# CONFIG_MTD_ONENAND_OTP is not set -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -# CONFIG_MTD_ONENAND_SIM is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_USB_ZD1201 is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -CONFIG_USB_USBNET=y -# CONFIG_USB_NET_AX8817X is not set -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set -CONFIG_TWL4030_CODEC=y -# CONFIG_TWL4030_MADC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=y - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=y -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_TEA5761=y -CONFIG_MEDIA_TUNER_TEA5767=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_MC44S803=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_MSP3400 is not set -# CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_WM8775 is not set -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_MT9V011 is not set -# CONFIG_VIDEO_TCM825X is not set -# CONFIG_VIDEO_MT9P012 is not set -# CONFIG_VIDEO_MT9T111 is not set -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -CONFIG_VIDEO_TVP514X=y -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -# CONFIG_VIDEO_CX25840 is not set - -# -# MPEG video encoders -# -# CONFIG_VIDEO_CX2341X is not set - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -CONFIG_TI_MEDIA=y -# CONFIG_VIDEO_VPSS_SYSTEM is not set -# CONFIG_VIDEO_VPFE_CAPTURE is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -# CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER is not set -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=y -# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set -# CONFIG_USB_GSPCA is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -# CONFIG_USB_PWC_INPUT_EVDEV is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=4 -# CONFIG_OMAP2_DSS_DEBUG_SUPPORT is not set -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 -CONFIG_FB_OMAP2=y -# CONFIG_FB_OMAP2_DEBUG_SUPPORT is not set -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=1 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_LOGO is not set -CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -# CONFIG_SND_USB_CAIAQ is not set -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3EVM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -CONFIG_USB_MUSB_DEBUG=y - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -# CONFIG_TWL4030_USB is not set -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y -# CONFIG_EARLY_PRINTK is not set -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0001-ARM-OMAP-add-spi-platform-devices.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0001-ARM-OMAP-add-spi-platform-devices.patch deleted file mode 100644 index 8988fd82..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0001-ARM-OMAP-add-spi-platform-devices.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 0031d3fb2d067f4c46e434f5f5c6c14cef2a83a3 Mon Sep 17 00:00:00 2001 -From: Tim Yamin -Date: Sat, 11 Apr 2009 13:05:21 -0700 -Subject: [PATCH 01/17] ARM: OMAP: add spi platform devices - ---- - arch/arm/mach-omap2/devices.c | 32 ++++++++++++++++++++++++++++++++ - 1 files changed, 32 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c -index 18ad931..ae67ada 100644 ---- a/arch/arm/mach-omap2/devices.c -+++ b/arch/arm/mach-omap2/devices.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -373,6 +374,37 @@ static struct platform_device omap2_mcspi4 = { - .platform_data = &omap2_mcspi4_config, - }, - }; -+ -+static struct spi_gpio_platform_data spi3_gpio_platform_data = { -+ .miso = 132, -+ .mosi = 131, -+ .sck = 130, -+ .num_chipselect = 1, -+}; -+ -+static struct platform_device spi3_gpio = { -+ .name = "spi_gpio", -+ .id = 3, -+ .dev = { -+ .platform_data = &spi3_gpio_platform_data, -+ }, -+}; -+ -+static struct spi_gpio_platform_data spi4_gpio_platform_data = { -+ .miso = 159, -+ .mosi = 158, -+ .sck = 156, -+ .num_chipselect = 1, -+}; -+ -+static struct platform_device spi4_gpio = { -+ .name = "spi_gpio", -+ .id = 4, -+ .dev = { -+ .platform_data = &spi4_gpio_platform_data, -+ }, -+}; -+ - #endif - - #ifdef CONFIG_ARCH_OMAP4 --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0002-MMA7455L-accelerometer-driver.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0002-MMA7455L-accelerometer-driver.patch deleted file mode 100644 index f9c7702e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0002-MMA7455L-accelerometer-driver.patch +++ /dev/null @@ -1,683 +0,0 @@ -From 0c804b06c04a14da575d592c89408537c21fb26b Mon Sep 17 00:00:00 2001 -From: Tim Yamin -Date: Tue, 23 Mar 2010 09:52:10 +0100 -Subject: [PATCH 02/17] MMA7455L accelerometer driver - ---- - drivers/input/misc/Kconfig | 9 + - drivers/input/misc/Makefile | 1 + - drivers/input/misc/mma7455l.c | 615 +++++++++++++++++++++++++++++++++++++++++ - include/linux/mma7455l.h | 11 + - 4 files changed, 636 insertions(+), 0 deletions(-) - create mode 100644 drivers/input/misc/mma7455l.c - create mode 100644 include/linux/mma7455l.h - -diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig -index 16ec523..d35ae19 100644 ---- a/drivers/input/misc/Kconfig -+++ b/drivers/input/misc/Kconfig -@@ -319,4 +319,13 @@ config INPUT_PCAP - To compile this driver as a module, choose M here: the - module will be called pcap_keys. - -+config INPUT_MMA7455L -+ tristate "Freescale MMA7455L 3-axis accelerometer" -+ depends on SPI_MASTER -+ help -+ SPI driver for the Freescale MMA7455L 3-axis accelerometer. -+ -+ The userspace interface is a 3-axis (X/Y/Z) relative movement -+ Linux input device, reporting REL_[XYZ] events. -+ - endif -diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile -index a8b8485..75b8baa 100644 ---- a/drivers/input/misc/Makefile -+++ b/drivers/input/misc/Makefile -@@ -30,4 +30,5 @@ obj-$(CONFIG_INPUT_WINBOND_CIR) += winbond-cir.o - obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o - obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o - obj-$(CONFIG_INPUT_YEALINK) += yealink.o -+obj-$(CONFIG_INPUT_MMA7455L) += mma7455l.o - -diff --git a/drivers/input/misc/mma7455l.c b/drivers/input/misc/mma7455l.c -new file mode 100644 -index 0000000..b907cc6 ---- /dev/null -+++ b/drivers/input/misc/mma7455l.c -@@ -0,0 +1,615 @@ -+/* Linux kernel driver for the Freescale MMA7455L 3-axis accelerometer -+ * -+ * Copyright (C) 2009 by Always Innovating, Inc. -+ * Author: Gregoire Gentil -+ * Author: Tim Yamin -+ * All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * -+ */ -+ -+/* -+ * What this driver doesn't yet support: -+ * -+ * - I2C -+ * - INT2 handling -+ * - Pulse detection (and the sysctls to control it) -+ * - 10-bit measurement -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define MMA7455L_WHOAMI_MAGIC 0x55 -+ -+enum mma7455l_reg { -+ MMA7455L_REG_XOUTL = 0x00, -+ MMA7455L_REG_XOUTH = 0x01, -+ MMA7455L_REG_YOUTL = 0x02, -+ MMA7455L_REG_YOUTH = 0x03, -+ MMA7455L_REG_ZOUTL = 0x04, -+ MMA7455L_REG_ZOUTH = 0x05, -+ MMA7455L_REG_XOUT8 = 0x06, -+ MMA7455L_REG_YOUT8 = 0x07, -+ MMA7455L_REG_ZOUT8 = 0x08, -+ MMA7455L_REG_STATUS = 0x09, -+ MMA7455L_REG_DETSRC = 0x0a, -+ MMA7455L_REG_TOUT = 0x0b, -+ MMA7455L_REG_RESERVED1 = 0x0c, -+ MMA7455L_REG_I2CAD = 0x0d, -+ MMA7455L_REG_USRINF = 0x0e, -+ MMA7455L_REG_WHOAMI = 0x0f, -+ MMA7455L_REG_XOFFL = 0x10, -+ MMA7455L_REG_XOFFH = 0x11, -+ MMA7455L_REG_YOFFL = 0x12, -+ MMA7455L_REG_YOFFH = 0x13, -+ MMA7455L_REG_ZOFFL = 0x14, -+ MMA7455L_REG_ZOFFH = 0x15, -+ MMA7455L_REG_MCTL = 0x16, -+ MMA7455L_REG_INTRST = 0x17, -+ MMA7455L_REG_CTL1 = 0x18, -+ MMA7455L_REG_CTL2 = 0x19, -+ MMA7455L_REG_LDTH = 0x1a, -+ MMA7455L_REG_PDTH = 0x1b, -+ MMA7455L_REG_PW = 0x1c, -+ MMA7455L_REG_LT = 0x1d, -+ MMA7455L_REG_TW = 0x1e, -+ MMA7455L_REG_RESERVED2 = 0x1f, -+}; -+ -+enum mma7455l_reg_status { -+ MMA7455L_STATUS_XDA = 0x08, -+ MMA7455L_STATUS_YDA = 0x10, -+ MMA7455L_STATUS_ZDA = 0x20, -+}; -+ -+enum mma7455l_mode { -+ MMA7455L_MODE_STANDBY = 0, -+ MMA7455L_MODE_MEASUREMENT = 1, -+ MMA7455L_MODE_LEVELDETECTION = 0x42, /* Set DRPD to on */ -+ MMA7455L_MODE_PULSEDETECTION = 0x43, /* Set DRPD to on */ -+ MMA7455L_MODE_MASK = 0x43, -+}; -+ -+enum mma7455l_gselect { -+ MMA7455L_GSELECT_8 = 0x0, -+ MMA7455L_GSELECT_2 = 0x4, -+ MMA7455L_GSELECT_4 = 0x8, -+ MMA7455L_GSELECT_MASK = 0xC, -+}; -+ -+/* FIXME */ -+#define MMA7455L_F_FS 0x0020 /* ADC full scale */ -+ -+struct mma7455l_info { -+ struct spi_device *spi_dev; -+ struct input_dev *input_dev; -+ struct mutex lock; -+ struct delayed_work work; -+ -+ u8 mode; -+ u8 gSelect; -+ -+ u8 flags; -+ u8 working; -+}; -+ -+/* lowlevel register access functions */ -+ -+#define WRITE_BIT (1 << 7) -+#define ADDR_SHIFT 1 -+ -+static inline u_int8_t __reg_read(struct mma7455l_info *mma, u_int8_t reg) -+{ -+ int rc; -+ u_int8_t cmd; -+ -+ cmd = ((reg & 0x3f) << ADDR_SHIFT); -+ rc = spi_w8r8(mma->spi_dev, cmd); -+ -+ return rc; -+} -+ -+static u_int8_t reg_read(struct mma7455l_info *mma, u_int8_t reg) -+{ -+ u_int8_t ret; -+ -+ mutex_lock(&mma->lock); -+ ret = __reg_read(mma, reg); -+ mutex_unlock(&mma->lock); -+ -+ return ret; -+} -+ -+static s16 __reg_read_10(struct mma7455l_info *mma, u8 reg1, u8 reg2) -+{ -+ u8 v1, v2; -+ -+ v1 = __reg_read(mma, reg1); -+ v2 = __reg_read(mma, reg2); -+ -+ return (v2 & 0x4) << 13 | (v2 & 0x3) << 8 | v1; -+} -+ -+static inline int __reg_write(struct mma7455l_info *mma, u_int8_t reg, u_int8_t val) -+{ -+ u_int8_t buf[2]; -+ -+ buf[0] = ((reg & 0x3f) << ADDR_SHIFT) | WRITE_BIT; -+ buf[1] = val; -+ -+ return spi_write(mma->spi_dev, buf, sizeof(buf)); -+} -+ -+static int reg_write(struct mma7455l_info *mma, u_int8_t reg, u_int8_t val) -+{ -+ int ret; -+ -+ mutex_lock(&mma->lock); -+ ret = __reg_write(mma, reg, val); -+ mutex_unlock(&mma->lock); -+ -+ return ret; -+} -+ -+static s16 __reg_write_10(struct mma7455l_info *mma, u8 reg1, u8 reg2, s16 value) -+{ -+ int ret; -+ u8 v1, v2; -+ -+ v1 = value & 0xFF; -+ if(value < 0) -+ v2 = ((value >> 8) & 0x3) | 0x4; -+ else -+ v2 = 0; -+ -+ ret = __reg_write(mma, reg1, v1); -+ ret = __reg_write(mma, reg2, v2); -+ return ret; -+} -+ -+static void mma7455l_work(struct work_struct *work) -+{ -+ struct mma7455l_info *mma = -+ container_of(work, struct mma7455l_info, work.work); -+ -+ s8 val; -+ mma->working = 1; -+ -+ /* FIXME: 10 bit accuracy? */ -+ if (!(mma->flags & MMA7455L_STATUS_XDA)) { -+ val = reg_read(mma, MMA7455L_REG_XOUT8); -+ input_report_abs(mma->input_dev, ABS_X, val); -+ } -+ if (!(mma->flags & MMA7455L_STATUS_YDA)) { -+ val = reg_read(mma, MMA7455L_REG_YOUT8); -+ input_report_abs(mma->input_dev, ABS_Y, val); -+ } -+ if (!(mma->flags & MMA7455L_STATUS_ZDA)) { -+ val = reg_read(mma, MMA7455L_REG_ZOUT8); -+ input_report_abs(mma->input_dev, ABS_Z, val); -+ } -+ -+ mma->working = 0; -+ input_sync(mma->input_dev); -+ put_device(&mma->spi_dev->dev); -+ -+ /* Enable IRQ and clear out interrupt */ -+ reg_write(mma, MMA7455L_REG_INTRST, 0x3); -+ reg_write(mma, MMA7455L_REG_INTRST, 0x0); -+ enable_irq(mma->spi_dev->irq); -+} -+ -+static void mma7455l_schedule_work(struct mma7455l_info *mma) -+{ -+ int status; -+ -+ get_device(&mma->spi_dev->dev); -+ status = schedule_delayed_work(&mma->work, HZ / 10); -+} -+ -+static irqreturn_t mma7455l_interrupt(int irq, void *_mma) -+{ -+ struct mma7455l_info *mma = _mma; -+ -+ /* Disable any further interrupts until we have processed -+ * the current one */ -+ disable_irq_nosync(mma->spi_dev->irq); -+ -+ mma7455l_schedule_work(mma); -+ return IRQ_HANDLED; -+} -+ -+/* sysfs */ -+ -+static void get_mode(struct mma7455l_info *mma, u8 *mode, u8 *gSelect) -+{ -+ u8 tmp = reg_read(mma, MMA7455L_REG_MCTL); -+ -+ *mode = tmp & MMA7455L_MODE_MASK; -+ *gSelect = tmp & MMA7455L_GSELECT_MASK; -+} -+ -+static void set_mode(struct mma7455l_info *mma, u8 mode, u8 gSelect) -+{ -+ reg_write(mma, MMA7455L_REG_MCTL, mode | gSelect); -+} -+ -+static void update_mode(struct mma7455l_info *mma, u8 mode, u8 gSelect) -+{ -+ mma->mode = mode; -+ mma->gSelect = gSelect; -+ -+ reg_write(mma, MMA7455L_REG_MCTL, mma->mode | mma->gSelect); -+} -+ -+static ssize_t show_measure(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ s8 x, y, z; -+ u8 old_Mode, old_gSelect; -+ -+ get_mode(mma, &old_Mode, &old_gSelect); -+ set_mode(mma, MMA7455L_MODE_MEASUREMENT, MMA7455L_GSELECT_2); -+ -+ while (reg_read(mma, MMA7455L_REG_STATUS) == 0) { -+ msleep(10); -+ } -+ -+ x = reg_read(mma, MMA7455L_REG_XOUT8); -+ y = reg_read(mma, MMA7455L_REG_YOUT8); -+ z = reg_read(mma, MMA7455L_REG_ZOUT8); -+ -+ set_mode(mma, old_Mode, old_gSelect); -+ return sprintf(buf, "%d %d %d\n", x, y, z); -+} -+ -+static ssize_t show_mode(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ switch(mma->mode) -+ { -+ case MMA7455L_MODE_STANDBY: -+ return sprintf(buf, "Standby\n"); -+ break; -+ case MMA7455L_MODE_MEASUREMENT: -+ return sprintf(buf, "Measurement\n"); -+ break; -+ case MMA7455L_MODE_LEVELDETECTION: -+ return sprintf(buf, "Level Detection\n"); -+ break; -+ case MMA7455L_MODE_PULSEDETECTION: -+ return sprintf(buf, "Pulse Detection\n"); -+ break; -+ } -+ -+ return sprintf(buf, "Unknown mode!\n"); -+} -+ -+static ssize_t show_gSelect(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ switch(mma->gSelect) -+ { -+ case MMA7455L_GSELECT_8: -+ return sprintf(buf, "8\n"); -+ break; -+ case MMA7455L_GSELECT_4: -+ return sprintf(buf, "4\n"); -+ break; -+ case MMA7455L_GSELECT_2: -+ return sprintf(buf, "2\n"); -+ break; -+ } -+ -+ return sprintf(buf, "Unknown gSelect!\n"); -+} -+ -+static ssize_t show_level_threshold(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ return sprintf(buf, "%u\n", reg_read(mma, MMA7455L_REG_LDTH)); -+} -+ -+static ssize_t show_calibration(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ s16 x, y, z; -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ mutex_lock(&mma->lock); -+ x = __reg_read_10(mma, MMA7455L_REG_XOFFL, MMA7455L_REG_XOFFH); -+ y = __reg_read_10(mma, MMA7455L_REG_YOFFL, MMA7455L_REG_YOFFH); -+ z = __reg_read_10(mma, MMA7455L_REG_ZOFFL, MMA7455L_REG_ZOFFH); -+ mutex_unlock(&mma->lock); -+ -+ return sprintf(buf, "%d %d %d\n", x, y, z); -+} -+ -+static ssize_t write_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ if (!strncmp(buf, "Standby", count)) -+ update_mode(mma, MMA7455L_MODE_STANDBY, mma->gSelect); -+ else if (!strncmp(buf, "Measurement", count)) -+ update_mode(mma, MMA7455L_MODE_MEASUREMENT, mma->gSelect); -+ else if (!strncmp(buf, "Level Detection", count)) -+ update_mode(mma, MMA7455L_MODE_LEVELDETECTION, mma->gSelect); -+ else if (!strncmp(buf, "Pulse Detection", count)) -+ update_mode(mma, MMA7455L_MODE_PULSEDETECTION, mma->gSelect); -+ -+ return count; -+} -+ -+static ssize_t write_gSelect(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned long v; -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ if(strict_strtoul(buf, 10, &v) == 0) -+ { -+ switch(v) -+ { -+ case 8: -+ update_mode(mma, mma->mode, MMA7455L_GSELECT_8); -+ break; -+ case 4: -+ update_mode(mma, mma->mode, MMA7455L_GSELECT_4); -+ break; -+ case 2: -+ update_mode(mma, mma->mode, MMA7455L_GSELECT_2); -+ break; -+ default: -+ return -EINVAL; -+ break; -+ } -+ return count; -+ } -+ -+ return -EINVAL; -+} -+ -+static ssize_t write_level_threshold(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned long v; -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ if(strict_strtoul(buf, 10, &v) == 0) -+ { -+ if(v <= 0xFF) { -+ reg_write(mma, MMA7455L_REG_LDTH, v); -+ return count; -+ } else -+ return -EINVAL; -+ } -+ -+ return -EINVAL; -+} -+ -+static ssize_t write_calibration(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ int x, y, z; -+ struct mma7455l_info *mma = dev_get_drvdata(dev); -+ -+ if (sscanf(buf, "%d %d %d", &x, &y, &z) == 3) -+ { -+ mutex_lock(&mma->lock); -+ __reg_write_10(mma, MMA7455L_REG_XOFFL, MMA7455L_REG_XOFFH, x); -+ __reg_write_10(mma, MMA7455L_REG_YOFFL, MMA7455L_REG_YOFFH, y); -+ __reg_write_10(mma, MMA7455L_REG_ZOFFL, MMA7455L_REG_ZOFFH, z); -+ mutex_unlock(&mma->lock); -+ -+ return count; -+ } -+ -+ return -EINVAL; -+} -+ -+static DEVICE_ATTR(measure, S_IRUGO, show_measure, NULL); -+static DEVICE_ATTR(mode, S_IRUGO | S_IWUGO, show_mode, write_mode); -+static DEVICE_ATTR(gSelect, S_IRUGO | S_IWUGO, show_gSelect, write_gSelect); -+static DEVICE_ATTR(level_threshold, S_IRUGO | S_IWUGO, show_level_threshold, write_level_threshold); -+static DEVICE_ATTR(calibration, S_IRUGO | S_IWUGO, show_calibration, write_calibration); -+ -+static struct attribute *mma7455l_sysfs_entries[] = { -+ &dev_attr_measure.attr, -+ &dev_attr_mode.attr, -+ &dev_attr_gSelect.attr, -+ &dev_attr_level_threshold.attr, -+ &dev_attr_calibration.attr, -+ NULL -+}; -+ -+static struct attribute_group mma7455l_attr_group = { -+ .attrs = mma7455l_sysfs_entries, -+}; -+ -+/* input device handling and driver core interaction */ -+static int mma7455l_input_open(struct input_dev *inp) -+{ -+ struct mma7455l_info *mma = input_get_drvdata(inp); -+ if(mma->mode == MMA7455L_MODE_STANDBY) -+ update_mode(mma, MMA7455L_MODE_MEASUREMENT, mma->gSelect); -+ -+ return 0; -+} -+ -+static void mma7455l_input_close(struct input_dev *inp) -+{ -+ struct mma7455l_info *mma = input_get_drvdata(inp); -+ update_mode(mma, MMA7455L_MODE_STANDBY, MMA7455L_GSELECT_2); -+} -+ -+static int __devinit mma7455l_probe(struct spi_device *spi) -+{ -+ int rc; -+ struct mma7455l_info *mma; -+ struct mma7455l_platform_data *pdata = spi->dev.platform_data; -+ u_int8_t wai; -+ -+ mma = kzalloc(sizeof(*mma), GFP_KERNEL); -+ if (!mma) -+ return -ENOMEM; -+ -+ mutex_init(&mma->lock); -+ INIT_DELAYED_WORK(&mma->work, mma7455l_work); -+ mma->spi_dev = spi; -+ mma->flags = mma->working = 0; -+ -+ spi_set_drvdata(spi, mma); -+ -+ rc = spi_setup(spi); -+ if (rc < 0) { -+ printk(KERN_ERR "mma7455l error durign spi_setup of mma7455l driver\n"); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(mma); -+ return rc; -+ } -+ -+ wai = reg_read(mma, MMA7455L_REG_WHOAMI); -+ if (wai != MMA7455L_WHOAMI_MAGIC) { -+ printk(KERN_ERR "mma7455l unknown whoami signature 0x%02x\n", wai); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(mma); -+ return -ENODEV; -+ } -+ -+ rc = request_irq(mma->spi_dev->irq, mma7455l_interrupt, IRQF_TRIGGER_HIGH, -+ "mma7455l", mma); -+ if (rc < 0) { -+ dev_err(&spi->dev, "mma7455l error requesting IRQ %d\n", -+ mma->spi_dev->irq); -+ /* FIXME */ -+ return rc; -+ } -+ -+ rc = sysfs_create_group(&spi->dev.kobj, &mma7455l_attr_group); -+ if (rc) { -+ dev_err(&spi->dev, "error creating sysfs group\n"); -+ return rc; -+ } -+ -+ /* initialize input layer details */ -+ mma->input_dev = input_allocate_device(); -+ if (!mma->input_dev) { -+ dev_err(&spi->dev, "mma7455l Unable to allocate input device\n"); -+ /* FIXME */ -+ } -+ -+ set_bit(EV_ABS, mma->input_dev->evbit); -+ set_bit(ABS_X, mma->input_dev->absbit); -+ set_bit(ABS_Y, mma->input_dev->absbit); -+ set_bit(ABS_Z, mma->input_dev->absbit); -+ -+ input_set_drvdata(mma->input_dev, mma); -+ mma->input_dev->name = "MMA7455L"; -+ mma->input_dev->open = mma7455l_input_open; -+ mma->input_dev->close = mma7455l_input_close; -+ -+ rc = input_register_device(mma->input_dev); -+ if(!rc) -+ { -+ update_mode(mma, MMA7455L_MODE_STANDBY, MMA7455L_GSELECT_2); -+ -+ mutex_lock(&mma->lock); -+ __reg_write_10(mma, MMA7455L_REG_XOFFL, MMA7455L_REG_XOFFH, pdata->calibration_x); -+ __reg_write_10(mma, MMA7455L_REG_YOFFL, MMA7455L_REG_YOFFH, pdata->calibration_y); -+ __reg_write_10(mma, MMA7455L_REG_ZOFFL, MMA7455L_REG_ZOFFH, pdata->calibration_z); -+ mutex_unlock(&mma->lock); -+ -+ return 0; -+ } -+ -+ input_free_device(mma->input_dev); -+ return rc; -+} -+ -+static int __devexit mma7455l_remove(struct spi_device *spi) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(&spi->dev); -+ -+ sysfs_remove_group(&spi->dev.kobj, &mma7455l_attr_group); -+ input_unregister_device(mma->input_dev); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(mma); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int mma7455l_suspend(struct spi_device *spi, pm_message_t message) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(&spi->dev); -+ get_mode(mma, &mma->mode, &mma->gSelect); -+ set_mode(mma, MMA7455L_MODE_STANDBY, MMA7455L_GSELECT_2); -+ -+ return 0; -+} -+ -+static int mma7455l_resume(struct spi_device *spi) -+{ -+ struct mma7455l_info *mma = dev_get_drvdata(&spi->dev); -+ update_mode(mma, mma->mode, mma->gSelect); -+ -+ return 0; -+} -+#else -+#define mma7455l_suspend NULL -+#define mma7455l_resume NULL -+#endif -+ -+static struct spi_driver mma7455l_driver = { -+ .driver = { -+ .name = "mma7455l", -+ .owner = THIS_MODULE, -+ }, -+ -+ .probe = mma7455l_probe, -+ .remove = __devexit_p(mma7455l_remove), -+ .suspend = mma7455l_suspend, -+ .resume = mma7455l_resume, -+}; -+ -+static int __init mma7455l_init(void) -+{ -+ return spi_register_driver(&mma7455l_driver); -+} -+ -+static void __exit mma7455l_exit(void) -+{ -+ spi_unregister_driver(&mma7455l_driver); -+} -+ -+MODULE_AUTHOR("Gregoire Gentil "); -+MODULE_LICENSE("GPL"); -+ -+module_init(mma7455l_init); -+module_exit(mma7455l_exit); -diff --git a/include/linux/mma7455l.h b/include/linux/mma7455l.h -new file mode 100644 -index 0000000..12ab50a ---- /dev/null -+++ b/include/linux/mma7455l.h -@@ -0,0 +1,11 @@ -+#ifndef _LINUX_MMA7455L_H -+#define _LINUX_MMA7455L_H -+ -+struct mma7455l_platform_data { -+ /* Calibration offsets */ -+ s16 calibration_x; -+ s16 calibration_y; -+ s16 calibration_z; -+}; -+ -+#endif /* _LINUX_MMA7455L_H */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0003-bq27x00_battery-remove-error-message-output.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0003-bq27x00_battery-remove-error-message-output.patch deleted file mode 100644 index f8b307ee..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0003-bq27x00_battery-remove-error-message-output.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 6837800d92947d25e263bf041ebe7db4e804af68 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 11:41:17 +0100 -Subject: [PATCH 03/17] bq27x00_battery: remove error message output - ---- - drivers/power/bq27x00_battery.c | 5 ----- - 1 files changed, 0 insertions(+), 5 deletions(-) - -diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c -index 62bb981..6935bb6 100644 ---- a/drivers/power/bq27x00_battery.c -+++ b/drivers/power/bq27x00_battery.c -@@ -93,7 +93,6 @@ static int bq27x00_battery_temperature(struct bq27x00_device_info *di) - - ret = bq27x00_read(BQ27x00_REG_TEMP, &temp, 0, di); - if (ret) { -- dev_err(di->dev, "error reading temperature\n"); - return ret; - } - -@@ -111,7 +110,6 @@ static int bq27x00_battery_voltage(struct bq27x00_device_info *di) - - ret = bq27x00_read(BQ27x00_REG_VOLT, &volt, 0, di); - if (ret) { -- dev_err(di->dev, "error reading voltage\n"); - return ret; - } - -@@ -131,12 +129,10 @@ static int bq27x00_battery_current(struct bq27x00_device_info *di) - - ret = bq27x00_read(BQ27x00_REG_AI, &curr, 0, di); - if (ret) { -- dev_err(di->dev, "error reading current\n"); - return 0; - } - ret = bq27x00_read(BQ27x00_REG_FLAGS, &flags, 0, di); - if (ret < 0) { -- dev_err(di->dev, "error reading flags\n"); - return 0; - } - if ((flags & (1 << 7)) != 0) { -@@ -157,7 +153,6 @@ static int bq27x00_battery_rsoc(struct bq27x00_device_info *di) - - ret = bq27x00_read(BQ27x00_REG_RSOC, &rsoc, 1, di); - if (ret) { -- dev_err(di->dev, "error reading relative State-of-Charge\n"); - return ret; - } - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0004-bq27x00_battery-add-charged-gpio.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0004-bq27x00_battery-add-charged-gpio.patch deleted file mode 100644 index 759525f2..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0004-bq27x00_battery-add-charged-gpio.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 829d500667448b7ea9465615261a988adc3aa645 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 11:42:45 +0100 -Subject: [PATCH 04/17] bq27x00_battery: add charged gpio - ---- - drivers/power/bq27x00_battery.c | 21 +++++++++++++++++++++ - 1 files changed, 21 insertions(+), 0 deletions(-) - -diff --git a/drivers/power/bq27x00_battery.c b/drivers/power/bq27x00_battery.c -index 6935bb6..4b80f59 100644 ---- a/drivers/power/bq27x00_battery.c -+++ b/drivers/power/bq27x00_battery.c -@@ -28,6 +28,7 @@ - - #define DRIVER_VERSION "1.0.0" - -+#define BQ27x00_REG_MODE 0x00 - #define BQ27x00_REG_TEMP 0x06 - #define BQ27x00_REG_VOLT 0x08 - #define BQ27x00_REG_RSOC 0x0B /* Relative State-of-Charge */ -@@ -65,6 +66,7 @@ static enum power_supply_property bq27x00_battery_props[] = { - POWER_SUPPLY_PROP_CURRENT_NOW, - POWER_SUPPLY_PROP_CAPACITY, - POWER_SUPPLY_PROP_TEMP, -+ POWER_SUPPLY_PROP_ONLINE, - }; - - /* -@@ -83,6 +85,22 @@ static int bq27x00_read(u8 reg, int *rt_value, int b_single, - } - - /* -+ * Return the GPIO status (0 or 1) -+ * Or < 0 if something fails. -+ */ -+static int bq27x00_gpio(struct bq27x00_device_info *di) -+{ -+ int ret; -+ int gpio = 0; -+ -+ ret = bq27x00_read(BQ27x00_REG_MODE, &gpio, 0, di); -+ if (ret) -+ return ret; -+ -+ return (gpio & 0x40) >> 6; -+} -+ -+/* - * Return the battery temperature in Celsius degrees - * Or < 0 if something fails. - */ -@@ -184,6 +202,9 @@ static int bq27x00_battery_get_property(struct power_supply *psy, - case POWER_SUPPLY_PROP_TEMP: - val->intval = bq27x00_battery_temperature(di); - break; -+ case POWER_SUPPLY_PROP_ONLINE: -+ val->intval = bq27x00_gpio(di); -+ break; - default: - return -EINVAL; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0005-adf7846-add-more-debugging.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0005-adf7846-add-more-debugging.patch deleted file mode 100644 index f15e0a2e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0005-adf7846-add-more-debugging.patch +++ /dev/null @@ -1,99 +0,0 @@ -From e00ae0c0fa35b4b67bbc905581c2c7bde0e29901 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 13:50:38 +0100 -Subject: [PATCH 05/17] adf7846: add more debugging - ---- - drivers/input/touchscreen/ads7846.c | 73 +++++++++++++++++++++++++++++++++++ - 1 files changed, 73 insertions(+), 0 deletions(-) - -diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c -index 45287ab..ebdeeeb 100644 ---- a/drivers/input/touchscreen/ads7846.c -+++ b/drivers/input/touchscreen/ads7846.c -@@ -495,9 +495,82 @@ static ssize_t ads7846_disable_store(struct device *dev, - - static DEVICE_ATTR(disable, 0664, ads7846_disable_show, ads7846_disable_store); - -+static ssize_t show_debounce_max(struct device *dev, struct device_attribute *attr, char *buf) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ return sprintf(buf, "%u\n", ts->debounce_max); -+} -+ -+static ssize_t show_debounce_tol(struct device *dev, struct device_attribute *attr, char *buf) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ return sprintf(buf, "%u\n", ts->debounce_tol); -+} -+ -+static ssize_t show_debounce_rep(struct device *dev, struct device_attribute *attr, char *buf) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ return sprintf(buf, "%u\n", ts->debounce_rep); -+} -+ -+static ssize_t show_x_plate_ohms(struct device *dev, struct device_attribute *attr, char *buf) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ return sprintf(buf, "%u\n", ts->x_plate_ohms); -+} -+ -+static ssize_t write_debounce_max(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ unsigned long i; -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ ts->debounce_max = i; -+ return count; -+} -+ -+static ssize_t write_debounce_tol(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ unsigned long i; -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ ts->debounce_tol = i; -+ return count; -+} -+ -+static ssize_t write_debounce_rep(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ unsigned long i; -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ ts->debounce_rep = i; -+ return count; -+} -+ -+static ssize_t write_x_plate_ohms(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ unsigned long i; -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ ts->x_plate_ohms = i; -+ return count; -+} -+ -+static DEVICE_ATTR(debounce_max, S_IRUGO | S_IWUGO, show_debounce_max, write_debounce_max); -+static DEVICE_ATTR(debounce_tol, S_IRUGO | S_IWUGO, show_debounce_tol, write_debounce_tol); -+static DEVICE_ATTR(debounce_rep, S_IRUGO | S_IWUGO, show_debounce_rep, write_debounce_rep); -+static DEVICE_ATTR(x_plate_ohms, S_IRUGO | S_IWUGO, show_x_plate_ohms, write_x_plate_ohms); -+ - static struct attribute *ads784x_attributes[] = { - &dev_attr_pen_down.attr, - &dev_attr_disable.attr, -+ &dev_attr_debounce_max.attr, -+ &dev_attr_debounce_tol.attr, -+ &dev_attr_debounce_rep.attr, -+ &dev_attr_x_plate_ohms.attr, - NULL, - }; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0006-ads7846-read-max-mix-x-y-from-pdata.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0006-ads7846-read-max-mix-x-y-from-pdata.patch deleted file mode 100644 index 63a4ebbf..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0006-ads7846-read-max-mix-x-y-from-pdata.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5f227b8aa6083437e2907ca621159228a4a24d9a Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 13:50:45 +0100 -Subject: [PATCH 06/17] ads7846: read max/mix x/y from pdata - ---- - drivers/input/touchscreen/ads7846.c | 5 +++-- - 1 files changed, 3 insertions(+), 2 deletions(-) - -diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c -index ebdeeeb..56b0ffd 100644 ---- a/drivers/input/touchscreen/ads7846.c -+++ b/drivers/input/touchscreen/ads7846.c -@@ -604,6 +604,7 @@ static void ads7846_rx(void *ads) - { - struct ads7846 *ts = ads; - struct ads7846_packet *packet = ts->packet; -+ struct ads7846_platform_data *pdata = ts->spi->dev.platform_data; - unsigned Rt; - u16 x, y, z1, z2; - -@@ -674,8 +675,8 @@ static void ads7846_rx(void *ads) - if (ts->swap_xy) - swap(x, y); - -- input_report_abs(input, ABS_X, x); -- input_report_abs(input, ABS_Y, y); -+ input_report_abs(input, ABS_X, pdata->x_max - x + pdata->x_min); -+ input_report_abs(input, ABS_Y, pdata->y_max - y + pdata->y_min); - input_report_abs(input, ABS_PRESSURE, ts->pressure_max - Rt); - - input_sync(input); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0007-ads7846-add-settling-delay-to-pdata.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0007-ads7846-add-settling-delay-to-pdata.patch deleted file mode 100644 index a69c7836..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0007-ads7846-add-settling-delay-to-pdata.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 7330c695afad64eef62c525cb8e54913265a3b39 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 13:50:52 +0100 -Subject: [PATCH 07/17] ads7846: add settling delay to pdata - ---- - drivers/input/touchscreen/ads7846.c | 22 ++++++++++++++++++++++ - 1 files changed, 22 insertions(+), 0 deletions(-) - -diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c -index 56b0ffd..1d9f97c 100644 ---- a/drivers/input/touchscreen/ads7846.c -+++ b/drivers/input/touchscreen/ads7846.c -@@ -515,6 +515,26 @@ static ssize_t show_x_plate_ohms(struct device *dev, struct device_attribute *at - return sprintf(buf, "%u\n", ts->x_plate_ohms); - } - -+static ssize_t show_settle_delay_usecs(struct device *dev, struct device_attribute *attr, char *buf) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ struct ads7846_platform_data *pdata = ts->spi->dev.platform_data; -+ -+ return sprintf(buf, "%u\n", pdata->settle_delay_usecs); -+} -+ -+static ssize_t write_settle_delay_usecs(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -+ struct ads7846 *ts = dev_get_drvdata(dev); -+ struct ads7846_platform_data *pdata = ts->spi->dev.platform_data; -+ -+ unsigned long i; -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ pdata->settle_delay_usecs = i; -+ return count; -+} -+ - static ssize_t write_debounce_max(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct ads7846 *ts = dev_get_drvdata(dev); - unsigned long i; -@@ -563,6 +583,7 @@ static DEVICE_ATTR(debounce_max, S_IRUGO | S_IWUGO, show_debounce_max, write_deb - static DEVICE_ATTR(debounce_tol, S_IRUGO | S_IWUGO, show_debounce_tol, write_debounce_tol); - static DEVICE_ATTR(debounce_rep, S_IRUGO | S_IWUGO, show_debounce_rep, write_debounce_rep); - static DEVICE_ATTR(x_plate_ohms, S_IRUGO | S_IWUGO, show_x_plate_ohms, write_x_plate_ohms); -+static DEVICE_ATTR(settle_delay_usecs, S_IRUGO | S_IWUGO, show_settle_delay_usecs, write_settle_delay_usecs); - - static struct attribute *ads784x_attributes[] = { - &dev_attr_pen_down.attr, -@@ -571,6 +592,7 @@ static struct attribute *ads784x_attributes[] = { - &dev_attr_debounce_tol.attr, - &dev_attr_debounce_rep.attr, - &dev_attr_x_plate_ohms.attr, -+ &dev_attr_settle_delay_usecs.attr, - NULL, - }; - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0008-DSS2-OMAPFB-Translate-X-Y-coordinates-for-the-video-.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0008-DSS2-OMAPFB-Translate-X-Y-coordinates-for-the-video-.patch deleted file mode 100644 index 5d6ff3fb..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0008-DSS2-OMAPFB-Translate-X-Y-coordinates-for-the-video-.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 07396a332c4f3d6ed4ff498cb08d0338c98dc612 Mon Sep 17 00:00:00 2001 -From: Tim Yamin -Date: Mon, 20 Apr 2009 20:29:11 -0700 -Subject: [PATCH 08/17] DSS2: OMAPFB: Translate X/Y coordinates for the video planes when rotating. - -When rotating the video planes, translate the X/Y coordinates such that -a [0,0] from userspace always maps to the correct upper left corner of -the display. This patch assumes that you rotate plane 0 before rotating -plane 1. Patch also corrects the scaling parameters so that the video is -displayed in the correct orientation (vertically, instead of horizontally) -when rotating by 90 / 270 degrees. - -Signed-off-by: Tim Yamin ---- - drivers/video/omap2/dss/dispc.c | 16 ++++++++++++---- - drivers/video/omap2/dss/manager.c | 2 +- - drivers/video/omap2/dss/overlay.c | 19 ++++++++++++++----- - 3 files changed, 27 insertions(+), 10 deletions(-) - -diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c -index c6d5fc5..1b38c49 100644 ---- a/drivers/video/omap2/dss/dispc.c -+++ b/drivers/video/omap2/dss/dispc.c -@@ -1685,10 +1685,18 @@ static int _dispc_setup_plane(enum omap_plane plane, - _dispc_set_pic_size(plane, width, height); - - if (plane != OMAP_DSS_GFX) { -- _dispc_set_scaling(plane, width, height, -- out_width, out_height, -- ilace, five_taps, fieldmode); -- _dispc_set_vid_size(plane, out_width, out_height); -+ if (rotation == 1 || rotation == 3) { -+ _dispc_set_scaling(plane, width, height, -+ out_height, out_width, -+ ilace, five_taps, fieldmode); -+ _dispc_set_vid_size(plane, out_height, out_width); -+ } else { -+ _dispc_set_scaling(plane, width, height, -+ out_width, out_height, -+ ilace, five_taps, fieldmode); -+ _dispc_set_vid_size(plane, out_width, out_height); -+ } -+ - _dispc_set_vid_color_conv(plane, cconv); - } - -diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c -index 27d9c46..7c62dea 100644 ---- a/drivers/video/omap2/dss/manager.c -+++ b/drivers/video/omap2/dss/manager.c -@@ -702,7 +702,7 @@ static int configure_overlay(enum omap_plane plane) - u16 outw, outh; - u16 x, y, w, h; - u32 paddr; -- int r; -+ int r, pos_x = 0, pos_y = 0; - - DSSDBGF("%d", plane); - -diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c -index b7f9a73..0bc0592 100644 ---- a/drivers/video/omap2/dss/overlay.c -+++ b/drivers/video/omap2/dss/overlay.c -@@ -374,6 +374,20 @@ int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev) - outh = info->out_height; - } - -+ if ((ovl->supported_modes & info->color_mode) == 0) { -+ DSSERR("overlay doesn't support mode %d\n", info->color_mode); -+ return -EINVAL; -+ } -+ -+ if (ovl->id != OMAP_DSS_GFX && (info->rotation == 1 || -+ info->rotation == 3)) { -+ if(outw > dh || outh > dw) -+ return -EINVAL; -+ -+ /* If coordinates are invalid, they will be clipped later... */ -+ return 0; -+ } -+ - if (dw < info->pos_x + outw) { - DSSDBG("check_overlay failed 1: %d < %d + %d\n", - dw, info->pos_x, outw); -@@ -386,11 +400,6 @@ int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev) - return -EINVAL; - } - -- if ((ovl->supported_modes & info->color_mode) == 0) { -- DSSERR("overlay doesn't support mode %d\n", info->color_mode); -- return -EINVAL; -- } -- - return 0; - } - --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0009-DSS2-Fix-scaling-checks-when-rotation-is-90-or-270-d.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0009-DSS2-Fix-scaling-checks-when-rotation-is-90-or-270-d.patch deleted file mode 100644 index 51305984..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0009-DSS2-Fix-scaling-checks-when-rotation-is-90-or-270-d.patch +++ /dev/null @@ -1,52 +0,0 @@ -From fc2e9ddb93cb026ed10900d794dd1db11191dc24 Mon Sep 17 00:00:00 2001 -From: Tim Yamin -Date: Fri, 12 Mar 2010 13:57:38 +0100 -Subject: [PATCH 09/17] DSS2: Fix scaling checks when rotation is 90 or 270 degrees. - ---- - drivers/video/omap2/dss/dispc.c | 25 +++++++++++++++++++------ - 1 files changed, 19 insertions(+), 6 deletions(-) - -diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c -index 1b38c49..d648c08 100644 ---- a/drivers/video/omap2/dss/dispc.c -+++ b/drivers/video/omap2/dss/dispc.c -@@ -1563,16 +1563,29 @@ static int _dispc_setup_plane(enum omap_plane plane, - } - } else { - /* video plane */ -- -+ u8 error = 0; - unsigned long fclk = 0; - -- if (out_width < width / maxdownscale || -- out_width > width * 8) -- return -EINVAL; -+ if(rotation == 1 || rotation == 3) -+ { -+ if (out_width < height / maxdownscale || out_width > height * 8) -+ error = 1; -+ -+ if (out_height < width / maxdownscale || out_height > width * 8) -+ error = 1; -+ } else { -+ if (out_width < width / maxdownscale || out_width > width * 8) -+ error = 1; - -- if (out_height < height / maxdownscale || -- out_height > height * 8) -+ if (out_height < height / maxdownscale || out_height > height * 8) -+ error = 1; -+ } -+ -+ if(error != 0) -+ { -+ printk("DSS: Unable to down/up scale video plane\n"); - return -EINVAL; -+ } - - switch (color_mode) { - case OMAP_DSS_COLOR_RGBX32: --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0010-add-touchbook-hid-driver.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0010-add-touchbook-hid-driver.patch deleted file mode 100644 index aa3b359c..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0010-add-touchbook-hid-driver.patch +++ /dev/null @@ -1,339 +0,0 @@ -From 0f651f19bf9cfecbb76d6f0b251e3d8395f306b8 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 14:39:07 +0100 -Subject: [PATCH 10/17] add touchbook hid driver - ---- - drivers/hid/Kconfig | 7 ++ - drivers/hid/Makefile | 1 + - drivers/hid/hid-ai.c | 260 ++++++++++++++++++++++++++++++++++++++++++++++++ - drivers/hid/hid-core.c | 1 + - drivers/hid/hid-ids.h | 3 + - 5 files changed, 272 insertions(+), 0 deletions(-) - create mode 100644 drivers/hid/hid-ai.c - -diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig -index 24d90ea..3760565 100644 ---- a/drivers/hid/Kconfig -+++ b/drivers/hid/Kconfig -@@ -62,6 +62,13 @@ config HID_A4TECH - ---help--- - Support for A4 tech X5 and WOP-35 / Trust 450L mice. - -+config HID_AI -+ tristate "Always Innovating" if EMBEDDED -+ depends on USB_HID -+ default !EMBEDDED -+ ---help--- -+ Support for Always Innovating Touch Book. -+ - config HID_APPLE - tristate "Apple" if EMBEDDED - depends on (USB_HID || BT_HIDP) -diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile -index 0de2dff..1787952 100644 ---- a/drivers/hid/Makefile -+++ b/drivers/hid/Makefile -@@ -20,6 +20,7 @@ ifdef CONFIG_LOGIRUMBLEPAD2_FF - endif - - obj-$(CONFIG_HID_A4TECH) += hid-a4tech.o -+obj-$(CONFIG_HID_AI) += hid-ai.o - obj-$(CONFIG_HID_APPLE) += hid-apple.o - obj-$(CONFIG_HID_BELKIN) += hid-belkin.o - obj-$(CONFIG_HID_CHERRY) += hid-cherry.o -diff --git a/drivers/hid/hid-ai.c b/drivers/hid/hid-ai.c -new file mode 100644 -index 0000000..83aecaf ---- /dev/null -+++ b/drivers/hid/hid-ai.c -@@ -0,0 +1,260 @@ -+/* -+ * USB HID quirks support for the Always Innovating Touch Book -+ * Code borrowed from hid-apple.c -+ * -+ * Copyright (c) 2009 Tim Yamin -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the Free -+ * Software Foundation; either version 2 of the License, or (at your option) -+ * any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "hid-ids.h" -+ -+struct ai_sc { -+ unsigned long quirks; -+ unsigned int fn_on; -+ DECLARE_BITMAP(pressed_fn, KEY_CNT); -+}; -+ -+struct ai_key_translation { -+ u16 from; -+ u16 to; -+ u8 flags; -+}; -+ -+static struct ai_key_translation ai_fn_keys[] = { -+ { KEY_F6, KEY_BRIGHTNESSDOWN }, -+ { KEY_F7, KEY_BRIGHTNESSUP }, -+ -+ { KEY_F8, KEY_MUTE }, -+ { KEY_F9, KEY_VOLUMEDOWN }, -+ { KEY_F10, KEY_VOLUMEUP }, -+ -+ { KEY_UP, KEY_PAGEUP }, -+ { KEY_DOWN, KEY_PAGEDOWN }, -+ { } -+}; -+ -+extern unsigned int ai_revision; -+int swap_key = 0; -+ -+static struct ai_key_translation *ai_find_translation( -+ struct ai_key_translation *table, u16 from) -+{ -+ struct ai_key_translation *trans; -+ -+ /* Look for the translation */ -+ for (trans = table; trans->from; trans++) -+ if (trans->from == from) -+ return trans; -+ -+ return NULL; -+} -+ -+static int ai_event(struct hid_device *hid, struct hid_field *field, -+ struct hid_usage *usage, __s32 value) -+{ -+ int do_translate; -+ -+ struct input_dev *input = field->hidinput->input; -+ struct ai_sc *asc = hid_get_drvdata(hid); -+ struct ai_key_translation *trans; -+ -+ if (swap_key && usage->code == KEY_RIGHTSHIFT) { -+ input_event(input, usage->type, KEY_END, value); -+ return 1; -+ } -+ -+ if (swap_key && usage->code == KEY_END) { -+ input_event(input, usage->type, KEY_RIGHTSHIFT, value); -+ return 1; -+ } -+ -+ if (usage->code == KEY_POWER) { -+ asc->fn_on = !!value; -+ input_event(input, usage->type, usage->code, value); -+ return 1; -+ } -+ -+ trans = ai_find_translation(ai_fn_keys, usage->code); -+ if (trans) { -+ if (test_bit(usage->code, asc->pressed_fn)) -+ do_translate = 1; -+ else -+ do_translate = asc->fn_on; -+ -+ if (do_translate) { -+ if (value) -+ set_bit(usage->code, asc->pressed_fn); -+ else -+ clear_bit(usage->code, asc->pressed_fn); -+ -+ input_event(input, usage->type, trans->to, -+ value); -+ -+ return 1; -+ } -+ } -+ -+ return 0; -+} -+ -+static int ai_input_mapping(struct hid_device *hdev, struct hid_input *hi, -+ struct hid_field *field, struct hid_usage *usage, -+ unsigned long **bit, int *max) -+{ -+ struct ai_key_translation *trans; -+ -+ /* Enable all other keys */ -+ for (trans = ai_fn_keys; trans->from; trans++) -+ set_bit(trans->to, hi->input->keybit); -+ -+ return 0; -+} -+ -+static ssize_t show_swap_key(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return snprintf(buf, PAGE_SIZE, "%d\n", swap_key); -+} -+ -+static ssize_t store_swap_key(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ swap_key = simple_strtoul(buf, NULL, 0); -+ -+ if (swap_key != 0 && swap_key != 1) { -+ swap_key = 0; -+ return -EINVAL; -+ } -+ -+ return count; -+} -+ -+static struct device_attribute ai_hid_attrs[] = { -+ __ATTR(swap_key, S_IRUGO | S_IWUGO, show_swap_key, store_swap_key), -+}; -+ -+int ai_create_sysfs(struct hid_device *hdev) -+{ -+ int i; -+ int r; -+ -+ for (i = 0; i < ARRAY_SIZE(ai_hid_attrs); i++) { -+ r = device_create_file(&hdev->dev, -+ &ai_hid_attrs[i]); -+ -+ if (r) { -+ dev_err(&hdev->dev, "failed to create sysfs file\n"); -+ return r; -+ } -+ } -+ -+ return 0; -+} -+ -+void ai_remove_sysfs(struct hid_device *hdev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(ai_hid_attrs); i++) -+ device_remove_file(&hdev->dev, -+ &ai_hid_attrs[i]); -+} -+ -+static int ai_probe(struct hid_device *hdev, -+ const struct hid_device_id *id) -+{ -+ unsigned long quirks = id->driver_data; -+ struct ai_sc *asc; -+ unsigned int connect_mask = HID_CONNECT_DEFAULT; -+ int ret; -+ -+ asc = kzalloc(sizeof(*asc), GFP_KERNEL); -+ if (asc == NULL) { -+ dev_err(&hdev->dev, "can't alloc ai descriptor\n"); -+ return -ENOMEM; -+ } -+ -+ asc->quirks = quirks; -+ hid_set_drvdata(hdev, asc); -+ -+ ret = hid_parse(hdev); -+ if (ret) { -+ dev_err(&hdev->dev, "parse failed\n"); -+ goto err_free; -+ } -+ -+ ret = ai_create_sysfs(hdev); -+ if (ret) { -+ dev_err(&hdev->dev, "failed to create sysfs entries\n"); -+ goto err_free; -+ } -+ -+ swap_key = (ai_revision >= 4) ? 1 : 0; -+ -+ ret = hid_hw_start(hdev, connect_mask); -+ if (ret) { -+ dev_err(&hdev->dev, "hw start failed\n"); -+ goto err_free; -+ } -+ -+ return 0; -+err_free: -+ kfree(asc); -+ return ret; -+} -+ -+static void ai_remove(struct hid_device *hdev) -+{ -+ hid_hw_stop(hdev); -+ kfree(hid_get_drvdata(hdev)); -+ ai_remove_sysfs(hdev); -+} -+ -+static const struct hid_device_id ai_devices[] = { -+ { HID_USB_DEVICE(USB_VENDOR_ID_AI, USB_DEVICE_ID_AI_TOUCH_BOOK) }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(hid, ai_devices); -+ -+static struct hid_driver ai_driver = { -+ .name = "ai", -+ .id_table = ai_devices, -+ .probe = ai_probe, -+ .remove = ai_remove, -+ .event = ai_event, -+ .input_mapping = ai_input_mapping, -+}; -+ -+static int ai_init(void) -+{ -+ int ret; -+ -+ ret = hid_register_driver(&ai_driver); -+ if (ret) -+ printk(KERN_ERR "can't register ai driver\n"); -+ -+ return ret; -+} -+ -+static void ai_exit(void) -+{ -+ hid_unregister_driver(&ai_driver); -+} -+ -+module_init(ai_init); -+module_exit(ai_exit); -+MODULE_LICENSE("GPL"); -+HID_COMPAT_LOAD_DRIVER(ai); -diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c -index 80792d3..f6b5960 100644 ---- a/drivers/hid/hid-core.c -+++ b/drivers/hid/hid-core.c -@@ -1250,6 +1250,7 @@ EXPORT_SYMBOL_GPL(hid_disconnect); - static const struct hid_device_id hid_blacklist[] = { - { HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_WCP32PU) }, - { HID_USB_DEVICE(USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_X5_005D) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_AI, USB_DEVICE_ID_AI_TOUCH_BOOK) }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ATV_IRCONTROL) }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_IRCONTROL4) }, - { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MIGHTYMOUSE) }, -diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h -index 3839340..5a0127d 100644 ---- a/drivers/hid/hid-ids.h -+++ b/drivers/hid/hid-ids.h -@@ -54,6 +54,9 @@ - #define USB_VENDOR_ID_ALPS 0x0433 - #define USB_DEVICE_ID_IBM_GAMEPAD 0x1101 - -+#define USB_VENDOR_ID_AI 0xa110 -+#define USB_DEVICE_ID_AI_TOUCH_BOOK 0x0002 -+ - #define USB_VENDOR_ID_APPLE 0x05ac - #define USB_DEVICE_ID_APPLE_MIGHTYMOUSE 0x0304 - #define USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI 0x020e --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0011-Make-backlight-controls-accessible-to-users.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0011-Make-backlight-controls-accessible-to-users.patch deleted file mode 100644 index c6d36787..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0011-Make-backlight-controls-accessible-to-users.patch +++ /dev/null @@ -1,25 +0,0 @@ -From b46a494e0c02450e412db221d75446671b6ef511 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 14:41:05 +0100 -Subject: [PATCH 11/17] Make backlight controls accessible to users - ---- - drivers/video/backlight/backlight.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - -diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c -index 6615ac7..7898707 100644 ---- a/drivers/video/backlight/backlight.c -+++ b/drivers/video/backlight/backlight.c -@@ -228,7 +228,7 @@ static void bl_device_release(struct device *dev) - - static struct device_attribute bl_device_attributes[] = { - __ATTR(bl_power, 0644, backlight_show_power, backlight_store_power), -- __ATTR(brightness, 0644, backlight_show_brightness, -+ __ATTR(brightness, 0666, backlight_show_brightness, - backlight_store_brightness), - __ATTR(actual_brightness, 0444, backlight_show_actual_brightness, - NULL), --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0012-ads7846-don-t-error-out-when-there-s-no-pendown-gpio.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0012-ads7846-don-t-error-out-when-there-s-no-pendown-gpio.patch deleted file mode 100644 index 24fb9132..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0012-ads7846-don-t-error-out-when-there-s-no-pendown-gpio.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4c3ef06a333cf1f873a9a8de05af90959a5d1e68 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 15:04:58 +0100 -Subject: [PATCH 12/17] ads7846: don't error out when there's no pendown gpio - ---- - drivers/input/touchscreen/ads7846.c | 7 ------- - 1 files changed, 0 insertions(+), 7 deletions(-) - -diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c -index 1d9f97c..c72c3ae 100644 ---- a/drivers/input/touchscreen/ads7846.c -+++ b/drivers/input/touchscreen/ads7846.c -@@ -952,13 +952,6 @@ static int __devinit setup_pendown(struct spi_device *spi, struct ads7846 *ts) - return 0; - } - -- err = gpio_request(pdata->gpio_pendown, "ads7846_pendown"); -- if (err) { -- dev_err(&spi->dev, "failed to request pendown GPIO%d\n", -- pdata->gpio_pendown); -- return err; -- } -- - ts->gpio_pendown = pdata->gpio_pendown; - return 0; - } --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0013-ASoC-add-driver-for-omap3-touchbook.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0013-ASoC-add-driver-for-omap3-touchbook.patch deleted file mode 100644 index 2da7354e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0013-ASoC-add-driver-for-omap3-touchbook.patch +++ /dev/null @@ -1,350 +0,0 @@ -From 96ce6261efe4c194d9188e0f352803bcd92f1c59 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Wed, 31 Mar 2010 11:14:04 +0200 -Subject: [PATCH 13/17] ASoC: add driver for omap3-touchbook - ---- - sound/soc/omap/Kconfig | 8 + - sound/soc/omap/Makefile | 2 + - sound/soc/omap/omap3touchbook.c | 291 +++++++++++++++++++++++++++++++++++++++ - 3 files changed, 301 insertions(+), 0 deletions(-) - create mode 100644 sound/soc/omap/omap3touchbook.c - -diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig -index 61952aa..a7c06ab 100644 ---- a/sound/soc/omap/Kconfig -+++ b/sound/soc/omap/Kconfig -@@ -101,6 +101,14 @@ config SND_OMAP_SOC_OMAP3_BEAGLE - help - Say Y if you want to add support for SoC audio on the Beagleboard. - -+config SND_OMAP_SOC_OMAP3_TOUCHBOOK -+ tristate "SoC Audio support for OMAP3 Touch Book" -+ depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP3_TOUCHBOOK -+ select SND_OMAP_SOC_MCBSP -+ select SND_SOC_TWL4030 -+ help -+ Say Y if you want to add support for SoC audio on the Touch Book. -+ - config SND_OMAP_SOC_ZOOM2 - tristate "SoC Audio support for Zoom2" - depends on TWL4030_CORE && SND_OMAP_SOC && MACH_OMAP_ZOOM2 -diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile -index 19283e5..e3f172f 100644 ---- a/sound/soc/omap/Makefile -+++ b/sound/soc/omap/Makefile -@@ -16,6 +16,7 @@ snd-soc-am3517evm-objs := am3517evm.o - snd-soc-sdp3430-objs := sdp3430.o - snd-soc-omap3pandora-objs := omap3pandora.o - snd-soc-omap3beagle-objs := omap3beagle.o -+snd-soc-omap3touchbook-objs := omap3touchbook.o - snd-soc-zoom2-objs := zoom2.o - snd-soc-igep0020-objs := igep0020.o - -@@ -29,5 +30,6 @@ obj-$(CONFIG_SND_OMAP_SOC_AM3517EVM) += snd-soc-am3517evm.o - obj-$(CONFIG_SND_OMAP_SOC_SDP3430) += snd-soc-sdp3430.o - obj-$(CONFIG_SND_OMAP_SOC_OMAP3_PANDORA) += snd-soc-omap3pandora.o - obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o -+obj-$(CONFIG_SND_OMAP_SOC_OMAP3_TOUCHBOOK) += snd-soc-omap3touchbook.o - obj-$(CONFIG_SND_OMAP_SOC_ZOOM2) += snd-soc-zoom2.o - obj-$(CONFIG_SND_OMAP_SOC_IGEP0020) += snd-soc-igep0020.o -diff --git a/sound/soc/omap/omap3touchbook.c b/sound/soc/omap/omap3touchbook.c -new file mode 100644 -index 0000000..c5e6eaa ---- /dev/null -+++ b/sound/soc/omap/omap3touchbook.c -@@ -0,0 +1,291 @@ -+/* -+ * omap3touchbook.c -- SoC audio for Touch Book -+ * -+ * Copyright (C) 2009-2010 Always Innovating -+ * -+ * Author: Gregoire Gentil -+ * -+ * Based on: -+ * Author: Steve Sakoman -+ * Author: Misael Lopez Cruz -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA -+ * 02110-1301 USA -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "omap-mcbsp.h" -+#include "omap-pcm.h" -+#include "../codecs/twl4030.h" -+ -+static struct snd_soc_card snd_soc_omap3touchbook; -+ -+static int omap3touchbook_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; -+ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; -+ unsigned int fmt; -+ int ret; -+ -+ switch (params_channels(params)) { -+ case 2: /* Stereo I2S mode */ -+ fmt = SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBM_CFM; -+ break; -+ case 4: /* Four channel TDM mode */ -+ fmt = SND_SOC_DAIFMT_DSP_A | -+ SND_SOC_DAIFMT_IB_NF | -+ SND_SOC_DAIFMT_CBM_CFM; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* Set codec DAI configuration */ -+ ret = snd_soc_dai_set_fmt(codec_dai, fmt); -+ if (ret < 0) { -+ printk(KERN_ERR "can't set codec DAI configuration\n"); -+ return ret; -+ } -+ -+ /* Set cpu DAI configuration */ -+ ret = snd_soc_dai_set_fmt(cpu_dai, fmt); -+ if (ret < 0) { -+ printk(KERN_ERR "can't set cpu DAI configuration\n"); -+ return ret; -+ } -+ -+ /* Set the codec system clock for DAC and ADC */ -+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000, -+ SND_SOC_CLOCK_IN); -+ if (ret < 0) { -+ printk(KERN_ERR "can't set codec system clock\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static struct snd_soc_ops omap3touchbook_ops = { -+ .hw_params = omap3touchbook_hw_params, -+}; -+ -+/* Headset jack */ -+static struct snd_soc_jack hs_jack; -+ -+/* Headset jack detection DAPM pins */ -+static struct snd_soc_jack_pin hs_jack_pins[] = { -+ { -+ .pin = "Headset Stereo", -+ .mask = SND_JACK_HEADPHONE, -+ }, -+ { -+ .pin = "Headset Mic", -+ .mask = SND_JACK_HEADPHONE, -+ }, -+ { -+ .pin = "External Speakers", -+ .mask = SND_JACK_HEADPHONE, -+ .invert = 1, -+ }, -+}; -+ -+/* Headset jack detection gpios */ -+static struct snd_soc_jack_gpio hs_jack_gpios[] = { -+ { -+ .gpio = 56, -+ .name = "hsdet-gpio", -+ .report = SND_JACK_HEADSET, -+ .debounce_time = 200, -+ }, -+}; -+ -+/* omap3touchbook machine DAPM */ -+static const struct snd_soc_dapm_widget omap3touchbook_twl4030_dapm_widgets[] = { -+ SND_SOC_DAPM_SPK("External Speakers", NULL), -+ SND_SOC_DAPM_HP("Headset Stereo", NULL), -+ SND_SOC_DAPM_MIC("Headset Mic", NULL), -+ SND_SOC_DAPM_LINE("Line In", NULL), -+}; -+ -+static const struct snd_soc_dapm_route audio_map[] = { -+ /* External Speakers: HFL, HFR */ -+ {"External Speakers", NULL, "HFL"}, -+ {"External Speakers", NULL, "HFR"}, -+ -+ /* Headset Stereo: HSOL, HSOR */ -+ {"Headset Stereo", NULL, "HSOL"}, -+ {"Headset Stereo", NULL, "HSOR"}, -+ -+ /* Micro: HSMIC */ -+ {"HSMIC", NULL, "Headset Mic Bias"}, -+ {"Headset Mic Bias", NULL, "Headset Mic"}, -+ -+ /* Line In: AUXL, AUXR */ -+ {"AUXL", NULL, "Line In"}, -+ {"AUXR", NULL, "Line In"}, -+}; -+ -+static int omap3touchbook_twl4030_init(struct snd_soc_codec *codec) -+{ -+ int ret; -+ -+ /* Add omap3touchbook specific widgets */ -+ ret = snd_soc_dapm_new_controls(codec, omap3touchbook_twl4030_dapm_widgets, -+ ARRAY_SIZE(omap3touchbook_twl4030_dapm_widgets)); -+ if (ret) -+ return ret; -+ -+ /* Set up omap3touchbook specific audio path audio_map */ -+ snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); -+ -+ /* omap3touchbook connected pins */ -+ snd_soc_dapm_enable_pin(codec, "External Speakers"); -+ snd_soc_dapm_enable_pin(codec, "Headset Stereo"); -+ snd_soc_dapm_enable_pin(codec, "Headset Mic"); -+ snd_soc_dapm_enable_pin(codec, "Line In"); -+ -+ /* omap3touchbook not connected pins */ -+ snd_soc_dapm_nc_pin(codec, "CARKITMIC"); -+ snd_soc_dapm_nc_pin(codec, "MAINMIC"); -+ snd_soc_dapm_nc_pin(codec, "SUBMIC"); -+ snd_soc_dapm_nc_pin(codec, "DIGIMIC0"); -+ snd_soc_dapm_nc_pin(codec, "DIGIMIC1"); -+ snd_soc_dapm_nc_pin(codec, "OUTL"); -+ snd_soc_dapm_nc_pin(codec, "OUTR"); -+ snd_soc_dapm_nc_pin(codec, "EARPIECE"); -+ snd_soc_dapm_nc_pin(codec, "PREDRIVEL"); -+ snd_soc_dapm_nc_pin(codec, "PREDRIVER"); -+ snd_soc_dapm_nc_pin(codec, "CARKITL"); -+ snd_soc_dapm_nc_pin(codec, "CARKITR"); -+ snd_soc_dapm_nc_pin(codec, "VIBRA"); -+ -+ ret = snd_soc_dapm_sync(codec); -+ if (ret) -+ return ret; -+ -+ /* Headset jack detection */ -+ ret = snd_soc_jack_new(&snd_soc_omap3touchbook, "Headset Jack", -+ SND_JACK_HEADSET, &hs_jack); -+ if (ret) -+ return ret; -+ -+ ret = snd_soc_jack_add_pins(&hs_jack, ARRAY_SIZE(hs_jack_pins), -+ hs_jack_pins); -+ if (ret) -+ return ret; -+ -+ ret = snd_soc_jack_add_gpios(&hs_jack, ARRAY_SIZE(hs_jack_gpios), -+ hs_jack_gpios); -+ -+ return ret; -+} -+ -+/* Digital audio interface glue - connects codec <--> CPU */ -+static struct snd_soc_dai_link omap3touchbook_dai = { -+ .name = "TWL4030 I2S", -+ .stream_name = "TWL4030 Audio", -+ .cpu_dai = &omap_mcbsp_dai[0], -+ .codec_dai = &twl4030_dai[TWL4030_DAI_HIFI], -+ .init = omap3touchbook_twl4030_init, -+ .ops = &omap3touchbook_ops, -+}; -+ -+/* Audio machine driver */ -+static struct snd_soc_card snd_soc_omap3touchbook = { -+ .name = "omap3touchbook", -+ .platform = &omap_soc_platform, -+ .dai_link = &omap3touchbook_dai, -+ .num_links = 1, -+}; -+ -+/* twl4030 setup */ -+static struct twl4030_setup_data twl4030_setup = { -+ .ramp_delay_value = 3, -+ .sysclk = 26000, -+ .hs_extmute = 1, -+}; -+ -+/* Audio subsystem */ -+static struct snd_soc_device omap3touchbook_snd_devdata = { -+ .card = &snd_soc_omap3touchbook, -+ .codec_dev = &soc_codec_dev_twl4030, -+ .codec_data = &twl4030_setup, -+}; -+ -+static struct platform_device *omap3touchbook_snd_device; -+ -+static int __init omap3touchbook_soc_init(void) -+{ -+ int ret; -+ u8 pin_mux; -+ -+ if (!machine_is_touchbook()) { -+ pr_debug("Not Touch Book!\n"); -+ //return -ENODEV; -+ } -+ printk(KERN_INFO "Touch Book SoC init\n"); -+ -+ omap3touchbook_snd_device = platform_device_alloc("soc-audio", -1); -+ if (!omap3touchbook_snd_device) { -+ printk(KERN_ERR "Platform device allocation failed\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(omap3touchbook_snd_device, &omap3touchbook_snd_devdata); -+ omap3touchbook_snd_devdata.dev = &omap3touchbook_snd_device->dev; -+ *(unsigned int *)omap3touchbook_dai.cpu_dai->private_data = 1; /* McBSP2 */ -+ -+ ret = platform_device_add(omap3touchbook_snd_device); -+ if (ret) -+ goto err1; -+ -+ return 0; -+ -+err1: -+ printk(KERN_ERR "Unable to add platform device\n"); -+ platform_device_put(omap3touchbook_snd_device); -+ -+ return ret; -+} -+module_init(omap3touchbook_soc_init); -+ -+static void __exit omap3touchbook_soc_exit(void) -+{ -+ snd_soc_jack_free_gpios(&hs_jack, ARRAY_SIZE(hs_jack_gpios), -+ hs_jack_gpios); -+ -+ platform_device_unregister(omap3touchbook_snd_device); -+} -+module_exit(omap3touchbook_soc_exit); -+ -+MODULE_AUTHOR("Gregoire Gentil "); -+MODULE_LICENSE("GPL"); --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0014-backlight-add-PWM-support.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0014-backlight-add-PWM-support.patch deleted file mode 100644 index d517f072..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0014-backlight-add-PWM-support.patch +++ /dev/null @@ -1,126 +0,0 @@ -From cc8cb0d0731c7a0517653e65c754051a69f34c3e Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Wed, 31 Mar 2010 11:14:04 +0200 -Subject: [PATCH 14/17] backlight: add PWM support - ---- - drivers/video/backlight/backlight.c | 81 +++++++++++++++++++++++++++++++++++ - include/linux/backlight.h | 3 + - 2 files changed, 84 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c -index 7898707..615f40f 100644 ---- a/drivers/video/backlight/backlight.c -+++ b/drivers/video/backlight/backlight.c -@@ -226,6 +226,84 @@ static void bl_device_release(struct device *dev) - kfree(bd); - } - -+static ssize_t backlight_show_boost(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct backlight_device *bd = to_backlight_device(dev); -+ return sprintf(buf, "%u\n", bd->props.boost); -+} -+ -+static ssize_t backlight_store_boost(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned long i; -+ struct backlight_device *bd = to_backlight_device(dev); -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ mutex_lock(&bd->ops_lock); -+ if (bd->ops) -+ { -+ if (i) -+ bd->props.boost = 1; -+ else -+ bd->props.boost = 0; -+ backlight_update_status(bd); -+ } -+ mutex_unlock(&bd->ops_lock); -+ -+ return count; -+} -+ -+static ssize_t backlight_show_pwm_fq(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct backlight_device *bd = to_backlight_device(dev); -+ return sprintf(buf, "%u\n", bd->props.pwm_fq); -+} -+ -+static ssize_t backlight_store_pwm_fq(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned long i; -+ struct backlight_device *bd = to_backlight_device(dev); -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ mutex_lock(&bd->ops_lock); -+ if (bd->ops) -+ { -+ bd->props.pwm_fq = i; -+ backlight_update_status(bd); -+ } -+ mutex_unlock(&bd->ops_lock); -+ -+ return count; -+} -+ -+static ssize_t backlight_show_min_duty(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ struct backlight_device *bd = to_backlight_device(dev); -+ return sprintf(buf, "%u\n", bd->props.min_duty); -+} -+ -+static ssize_t backlight_store_min_duty(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned long i; -+ struct backlight_device *bd = to_backlight_device(dev); -+ -+ if (strict_strtoul(buf, 10, &i)) -+ return -EINVAL; -+ -+ mutex_lock(&bd->ops_lock); -+ if (bd->ops) -+ { -+ bd->props.min_duty = i; -+ backlight_update_status(bd); -+ } -+ mutex_unlock(&bd->ops_lock); -+ -+ return count; -+} -+ - static struct device_attribute bl_device_attributes[] = { - __ATTR(bl_power, 0644, backlight_show_power, backlight_store_power), - __ATTR(brightness, 0666, backlight_show_brightness, -@@ -233,6 +311,9 @@ static struct device_attribute bl_device_attributes[] = { - __ATTR(actual_brightness, 0444, backlight_show_actual_brightness, - NULL), - __ATTR(max_brightness, 0444, backlight_show_max_brightness, NULL), -+ __ATTR(boost, 0666, backlight_show_boost, backlight_store_boost), -+ __ATTR(pwm_fq, 0666, backlight_show_pwm_fq, backlight_store_pwm_fq), -+ __ATTR(min_duty, 0666, backlight_show_min_duty, backlight_store_min_duty), - __ATTR_NULL, - }; - -diff --git a/include/linux/backlight.h b/include/linux/backlight.h -index 0f5f578..f3a9b9f 100644 ---- a/include/linux/backlight.h -+++ b/include/linux/backlight.h -@@ -64,6 +64,9 @@ struct backlight_properties { - int fb_blank; - /* Flags used to signal drivers of state changes */ - /* Upper 4 bits are reserved for driver internal use */ -+ int boost; -+ int pwm_fq; -+ int min_duty; - unsigned int state; - - #define BL_CORE_SUSPENDED (1 << 0) /* backlight is suspended */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0015-Forward-port-TWL4030-BCI-driver-from-2.6.29-to-2.6.3.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0015-Forward-port-TWL4030-BCI-driver-from-2.6.29-to-2.6.3.patch deleted file mode 100644 index 562c459e..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0015-Forward-port-TWL4030-BCI-driver-from-2.6.29-to-2.6.3.patch +++ /dev/null @@ -1,1367 +0,0 @@ -From c3a08f3d696866508ef2b5e2fd065b8295b3e1a8 Mon Sep 17 00:00:00 2001 -From: Tim Yamin -Date: Sun, 9 May 2010 10:14:23 +0200 -Subject: [PATCH 15/17] Forward port TWL4030 BCI driver from 2.6.29 to 2.6.31 with AI enhancements. - -Signed-off-by: Tim Yamin ---- - drivers/power/Kconfig | 7 + - drivers/power/Makefile | 1 + - drivers/power/twl4030_bci_battery.c | 1307 +++++++++++++++++++++++++++++++++++ - include/linux/i2c/twl.h | 1 + - 4 files changed, 1316 insertions(+), 0 deletions(-) - create mode 100644 drivers/power/twl4030_bci_battery.c - -diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig -index d4b3d67..8345b3f 100644 ---- a/drivers/power/Kconfig -+++ b/drivers/power/Kconfig -@@ -124,4 +124,11 @@ config CHARGER_PCF50633 - help - Say Y to include support for NXP PCF50633 Main Battery Charger. - -+config TWL4030_BCI_BATTERY -+ tristate "OMAP TWL4030 BCI Battery driver" -+ depends on TWL4030_CORE && TWL4030_MADC -+ help -+ Support for OMAP TWL4030 BCI Battery driver. -+ This driver can give support for TWL4030 Battery Charge Interface. -+ - endif # POWER_SUPPLY -diff --git a/drivers/power/Makefile b/drivers/power/Makefile -index 573597c..7801da7 100644 ---- a/drivers/power/Makefile -+++ b/drivers/power/Makefile -@@ -31,3 +31,4 @@ obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o - obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o - obj-$(CONFIG_BATTERY_MAX17040) += max17040_battery.o - obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o -+obj-$(CONFIG_TWL4030_BCI_BATTERY) += twl4030_bci_battery.o -diff --git a/drivers/power/twl4030_bci_battery.c b/drivers/power/twl4030_bci_battery.c -new file mode 100644 -index 0000000..0876fc3 ---- /dev/null -+++ b/drivers/power/twl4030_bci_battery.c -@@ -0,0 +1,1307 @@ -+/* -+ * linux/drivers/power/twl4030_bci_battery.c -+ * -+ * OMAP2430/3430 BCI battery driver for Linux -+ * -+ * Copyright (C) 2008 Texas Instruments, Inc. -+ * Author: Texas Instruments, Inc. -+ * -+ * Copyright (C) 2010 Always Innovating -+ * Author: Tim Yamin -+ * -+ * This package is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -+ */ -+ -+/* Boot with automatic charge */ -+#define CHARGE_MODE 1 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define T2_BATTERY_VOLT 0x04 -+#define T2_BATTERY_TEMP 0x06 -+#define T2_BATTERY_CUR 0x08 -+ -+/* charger constants */ -+#define NO_PW_CONN 0 -+#define AC_PW_CONN 0x01 -+#define USB_PW_CONN 0x02 -+ -+/* TWL4030_MODULE_USB */ -+#define REG_POWER_CTRL 0x0AC -+#define OTG_EN 0x020 -+#define REG_PHY_CLK_CTRL 0x0FE -+#define REG_PHY_CLK_CTRL_STS 0x0FF -+#define PHY_DPLL_CLK 0x01 -+ -+#define REG_BCICTL1 0x023 -+#define REG_BCICTL2 0x024 -+#define CGAIN 0x020 -+#define ITHEN 0x010 -+#define ITHSENS 0x007 -+ -+/* Boot BCI flag bits */ -+#define BCIAUTOWEN 0x020 -+#define CONFIG_DONE 0x010 -+#define CVENAC 0x004 -+#define BCIAUTOUSB 0x002 -+#define BCIAUTOAC 0x001 -+#define BCIMSTAT_MASK 0x03F -+ -+/* Boot BCI register */ -+#define REG_BOOT_BCI 0x007 -+#define REG_CTRL1 0x00 -+#define REG_SW1SELECT_MSB 0x07 -+#define SW1_CH9_SEL 0x02 -+#define REG_CTRL_SW1 0x012 -+#define SW1_TRIGGER 0x020 -+#define EOC_SW1 0x002 -+#define REG_GPCH9 0x049 -+#define REG_STS_HW_CONDITIONS 0x0F -+#define STS_VBUS 0x080 -+#define STS_CHG 0x02 -+#define REG_BCIMSTATEC 0x02 -+#define REG_BCIMFSTS4 0x010 -+#define REG_BCIMFSTS2 0x00E -+#define REG_BCIMFSTS3 0x00F -+#define REG_BCIMFSTS1 0x001 -+#define USBFASTMCHG 0x004 -+#define BATSTSPCHG 0x004 -+#define BATSTSMCHG 0x040 -+#define VBATOV4 0x020 -+#define VBATOV3 0x010 -+#define VBATOV2 0x008 -+#define VBATOV1 0x004 -+#define REG_BB_CFG 0x012 -+#define BBCHEN 0x010 -+ -+/* GPBR */ -+#define REG_GPBR1 0x0c -+#define MADC_HFCLK_EN 0x80 -+#define DEFAULT_MADC_CLK_EN 0x10 -+ -+/* Power supply charge interrupt */ -+#define REG_PWR_ISR1 0x00 -+#define REG_PWR_IMR1 0x01 -+#define REG_PWR_EDR1 0x05 -+#define REG_PWR_SIH_CTRL 0x007 -+ -+#define USB_PRES 0x004 -+#define CHG_PRES 0x002 -+ -+#define USB_PRES_RISING 0x020 -+#define USB_PRES_FALLING 0x010 -+#define CHG_PRES_RISING 0x008 -+#define CHG_PRES_FALLING 0x004 -+#define AC_STATEC 0x20 -+#define COR 0x004 -+ -+/* interrupt status registers */ -+#define REG_BCIISR1A 0x0 -+#define REG_BCIISR2A 0x01 -+ -+/* Interrupt flags bits BCIISR1 */ -+#define BATSTS_ISR1 0x080 -+#define VBATLVL_ISR1 0x001 -+ -+/* Interrupt mask registers for int1*/ -+#define REG_BCIIMR1A 0x002 -+#define REG_BCIIMR2A 0x003 -+ -+ /* Interrupt masks for BCIIMR1 */ -+#define BATSTS_IMR1 0x080 -+#define VBATLVL_IMR1 0x001 -+ -+/* Interrupt edge detection register */ -+#define REG_BCIEDR1 0x00A -+#define REG_BCIEDR2 0x00B -+#define REG_BCIEDR3 0x00C -+ -+/* BCIEDR2 */ -+#define BATSTS_EDRRISIN 0x080 -+#define BATSTS_EDRFALLING 0x040 -+ -+/* BCIEDR3 */ -+#define VBATLVL_EDRRISIN 0x02 -+ -+/* BCIIREF1 */ -+#define REG_BCIIREF1 0x027 -+#define REG_BCIIREF2 0x028 -+ -+/* BCIMFTH1 */ -+#define REG_BCIMFTH1 0x016 -+ -+/* Key */ -+#define KEY_IIREF 0xE7 -+#define KEY_FTH1 0xD2 -+#define REG_BCIMFKEY 0x011 -+ -+/* Step size and prescaler ratio */ -+#define TEMP_STEP_SIZE 147 -+#define TEMP_PSR_R 100 -+ -+#define VOLT_STEP_SIZE 588 -+#define VOLT_PSR_R 100 -+ -+#define CURR_STEP_SIZE 147 -+#define CURR_PSR_R1 44 -+#define CURR_PSR_R2 80 -+ -+#define BK_VOLT_STEP_SIZE 441 -+#define BK_VOLT_PSR_R 100 -+ -+#define ENABLE 1 -+#define DISABLE 1 -+ -+struct twl4030_bci_device_info { -+ struct device *dev; -+ -+ unsigned long update_time; -+ int voltage_uV; -+ int bk_voltage_uV; -+ int current_uA; -+ int temp_C; -+ int charge_rsoc; -+ int charge_status; -+ -+ struct power_supply bat; -+ struct power_supply bk_bat; -+ struct delayed_work twl4030_bci_monitor_work; -+ struct delayed_work twl4030_bk_bci_monitor_work; -+ -+ struct twl4030_bci_platform_data *pdata; -+}; -+ -+static int usb_charger_flag; -+static int LVL_1, LVL_2, LVL_3, LVL_4; -+ -+static int read_bci_val(u8 reg_1); -+static inline int clear_n_set(u8 mod_no, u8 clear, u8 set, u8 reg); -+static int twl4030charger_presence(void); -+ -+/* -+ * Report and clear the charger presence event. -+ */ -+static inline int twl4030charger_presence_evt(void) -+{ -+ int ret; -+ u8 chg_sts, set = 0, clear = 0; -+ -+ /* read charger power supply status */ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &chg_sts, -+ REG_STS_HW_CONDITIONS); -+ if (ret) -+ return IRQ_NONE; -+ -+ if (chg_sts & STS_CHG) { /* If the AC charger have been connected */ -+ /* configuring falling edge detection for CHG_PRES */ -+ set = CHG_PRES_FALLING; -+ clear = CHG_PRES_RISING; -+ } else { /* If the AC charger have been disconnected */ -+ /* configuring rising edge detection for CHG_PRES */ -+ set = CHG_PRES_RISING; -+ clear = CHG_PRES_FALLING; -+ } -+ -+ /* Update the interrupt edge detection register */ -+ clear_n_set(TWL4030_MODULE_INT, clear, set, REG_PWR_EDR1); -+ -+ return 0; -+} -+ -+/* -+ * Interrupt service routine -+ * -+ * Attends to TWL 4030 power module interruptions events, specifically -+ * USB_PRES (USB charger presence) CHG_PRES (AC charger presence) events -+ * -+ */ -+static irqreturn_t twl4030charger_interrupt(int irq, void *_di) -+{ -+ struct twl4030_bci_device_info *di = _di; -+ -+#ifdef CONFIG_LOCKDEP -+ /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which -+ * we don't want and can't tolerate. Although it might be -+ * friendlier not to borrow this thread context... -+ */ -+ local_irq_enable(); -+#endif -+ -+ twl4030charger_presence_evt(); -+ power_supply_changed(&di->bat); -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * This function handles the twl4030 battery presence interrupt -+ */ -+static int twl4030battery_presence_evt(void) -+{ -+ int ret; -+ u8 batstsmchg, batstspchg; -+ -+ /* check for the battery presence in main charge*/ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ &batstsmchg, REG_BCIMFSTS3); -+ if (ret) -+ return ret; -+ -+ /* check for the battery presence in precharge */ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_PRECHARGE, -+ &batstspchg, REG_BCIMFSTS1); -+ if (ret) -+ return ret; -+ -+ /* -+ * REVISIT: Physically inserting/removing the batt -+ * does not seem to generate an int on 3430ES2 SDP. -+ */ -+ if ((batstspchg & BATSTSPCHG) || (batstsmchg & BATSTSMCHG)) { -+ /* In case of the battery insertion event */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, BATSTS_EDRRISIN, -+ BATSTS_EDRFALLING, REG_BCIEDR2); -+ if (ret) -+ return ret; -+ } else { -+ /* In case of the battery removal event */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, BATSTS_EDRFALLING, -+ BATSTS_EDRRISIN, REG_BCIEDR2); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* -+ * This function handles the twl4030 battery voltage level interrupt. -+ */ -+static int twl4030battery_level_evt(void) -+{ -+ int ret; -+ u8 mfst; -+ -+ /* checking for threshold event */ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ &mfst, REG_BCIMFSTS2); -+ if (ret) -+ return ret; -+ -+ /* REVISIT could use a bitmap */ -+ if (mfst & VBATOV4) { -+ LVL_4 = 1; -+ LVL_3 = 0; -+ LVL_2 = 0; -+ LVL_1 = 0; -+ } else if (mfst & VBATOV3) { -+ LVL_4 = 0; -+ LVL_3 = 1; -+ LVL_2 = 0; -+ LVL_1 = 0; -+ } else if (mfst & VBATOV2) { -+ LVL_4 = 0; -+ LVL_3 = 0; -+ LVL_2 = 1; -+ LVL_1 = 0; -+ } else { -+ LVL_4 = 0; -+ LVL_3 = 0; -+ LVL_2 = 0; -+ LVL_1 = 1; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Interrupt service routine -+ * -+ * Attends to BCI interruptions events, -+ * specifically BATSTS (battery connection and removal) -+ * VBATOV (main battery voltage threshold) events -+ * -+ */ -+static irqreturn_t twl4030battery_interrupt(int irq, void *_di) -+{ -+ u8 isr1a_val, isr2a_val, clear_2a, clear_1a; -+ int ret; -+ -+#ifdef CONFIG_LOCKDEP -+ /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which -+ * we don't want and can't tolerate. Although it might be -+ * friendlier not to borrow this thread context... -+ */ -+ local_irq_enable(); -+#endif -+ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_INTERRUPTS, &isr1a_val, -+ REG_BCIISR1A); -+ if (ret) -+ return IRQ_NONE; -+ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_INTERRUPTS, &isr2a_val, -+ REG_BCIISR2A); -+ if (ret) -+ return IRQ_NONE; -+ -+ clear_2a = (isr2a_val & VBATLVL_ISR1) ? (VBATLVL_ISR1) : 0; -+ clear_1a = (isr1a_val & BATSTS_ISR1) ? (BATSTS_ISR1) : 0; -+ -+ /* cleaning BCI interrupt status flags */ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, -+ clear_1a , REG_BCIISR1A); -+ if (ret) -+ return IRQ_NONE; -+ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, -+ clear_2a , REG_BCIISR2A); -+ if (ret) -+ return IRQ_NONE; -+ -+ /* battery connetion or removal event */ -+ if (isr1a_val & BATSTS_ISR1) -+ twl4030battery_presence_evt(); -+ /* battery voltage threshold event*/ -+ else if (isr2a_val & VBATLVL_ISR1) -+ twl4030battery_level_evt(); -+ else -+ return IRQ_NONE; -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Enable/Disable hardware battery level event notifications. -+ */ -+static int twl4030battery_hw_level_en(int enable) -+{ -+ int ret; -+ -+ if (enable) { -+ /* unmask VBATOV interrupt for INT1 */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, VBATLVL_IMR1, -+ 0, REG_BCIIMR2A); -+ if (ret) -+ return ret; -+ -+ /* configuring interrupt edge detection for VBATOv */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, 0, -+ VBATLVL_EDRRISIN, REG_BCIEDR3); -+ if (ret) -+ return ret; -+ } else { -+ /* mask VBATOV interrupt for INT1 */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, 0, -+ VBATLVL_IMR1, REG_BCIIMR2A); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Enable/disable hardware battery presence event notifications. -+ */ -+static int twl4030battery_hw_presence_en(int enable) -+{ -+ int ret; -+ -+ if (enable) { -+ /* unmask BATSTS interrupt for INT1 */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, BATSTS_IMR1, -+ 0, REG_BCIIMR1A); -+ if (ret) -+ return ret; -+ -+ /* configuring interrupt edge for BATSTS */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, 0, -+ BATSTS_EDRRISIN | BATSTS_EDRFALLING, REG_BCIEDR2); -+ if (ret) -+ return ret; -+ } else { -+ /* mask BATSTS interrupt for INT1 */ -+ ret = clear_n_set(TWL4030_MODULE_INTERRUPTS, 0, -+ BATSTS_IMR1, REG_BCIIMR1A); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Enable/Disable AC Charge funtionality. -+ */ -+static int twl4030charger_ac_en(int enable, int automatic) -+{ -+ int ret; -+ -+ if (enable) { -+ /* forcing the field BCIAUTOAC (BOOT_BCI[0) to 1 */ -+ if(!automatic) { -+ ret = clear_n_set(TWL4030_MODULE_PM_MASTER, BCIAUTOAC | CVENAC, -+ (CONFIG_DONE | BCIAUTOWEN), -+ REG_BOOT_BCI); -+ } else { -+ ret = clear_n_set(TWL4030_MODULE_PM_MASTER, 0, -+ (CONFIG_DONE | BCIAUTOWEN | BCIAUTOAC | CVENAC), -+ REG_BOOT_BCI); -+ } -+ if (ret) -+ return ret; -+ } else { -+ /* forcing the field BCIAUTOAC (BOOT_BCI[0) to 0*/ -+ ret = clear_n_set(TWL4030_MODULE_PM_MASTER, BCIAUTOAC, -+ (CONFIG_DONE | BCIAUTOWEN), -+ REG_BOOT_BCI); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Enable/Disable USB Charge funtionality. -+ */ -+int twl4030charger_usb_en(int enable) -+{ -+ u8 value; -+ int ret; -+ unsigned long timeout; -+ -+ if (enable) { -+ /* Check for USB charger conneted */ -+ ret = twl4030charger_presence(); -+ if (ret < 0) -+ return ret; -+ -+ if (!(ret & USB_PW_CONN)) -+ return -ENXIO; -+ -+ /* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */ -+ ret = clear_n_set(TWL4030_MODULE_PM_MASTER, 0, -+ (CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB), -+ REG_BOOT_BCI); -+ if (ret) -+ return ret; -+ -+ ret = clear_n_set(TWL4030_MODULE_USB, 0, PHY_DPLL_CLK, -+ REG_PHY_CLK_CTRL); -+ if (ret) -+ return ret; -+ -+ value = 0; -+ timeout = jiffies + msecs_to_jiffies(50); -+ -+ while ((!(value & PHY_DPLL_CLK)) && -+ time_before(jiffies, timeout)) { -+ udelay(10); -+ ret = twl_i2c_read_u8(TWL4030_MODULE_USB, &value, -+ REG_PHY_CLK_CTRL_STS); -+ if (ret) -+ return ret; -+ } -+ -+ /* OTG_EN (POWER_CTRL[5]) to 1 */ -+ ret = clear_n_set(TWL4030_MODULE_USB, 0, OTG_EN, -+ REG_POWER_CTRL); -+ if (ret) -+ return ret; -+ -+ mdelay(50); -+ -+ /* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */ -+ ret = clear_n_set(TWL4030_MODULE_MAIN_CHARGE, 0, -+ USBFASTMCHG, REG_BCIMFSTS4); -+ if (ret) -+ return ret; -+ } else { -+ twl4030charger_presence(); -+ ret = clear_n_set(TWL4030_MODULE_PM_MASTER, BCIAUTOUSB, -+ (CONFIG_DONE | BCIAUTOWEN), REG_BOOT_BCI); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Return battery temperature -+ * Or < 0 on failure. -+ */ -+static int twl4030battery_temperature(struct twl4030_bci_device_info *di) -+{ -+ u8 val; -+ int temp, curr, volt, res, ret; -+ -+ /* Is a temperature table specified? */ -+ if (!di->pdata->tblsize) -+ return 0; -+ -+ /* Getting and calculating the thermistor voltage */ -+ ret = read_bci_val(T2_BATTERY_TEMP); -+ if (ret < 0) -+ return ret; -+ -+ volt = (ret * TEMP_STEP_SIZE) / TEMP_PSR_R; -+ -+ /* Getting and calculating the supply current in micro ampers */ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &val, -+ REG_BCICTL2); -+ if (ret) -+ return 0; -+ -+ curr = ((val & ITHSENS) + 1) * 10; -+ -+ /* Getting and calculating the thermistor resistance in ohms*/ -+ res = volt * 1000 / curr; -+ -+ /*calculating temperature*/ -+ for (temp = 58; temp >= 0; temp--) { -+ int actual = di->pdata->battery_tmp_tbl[temp]; -+ if ((actual - res) >= 0) -+ break; -+ } -+ -+ /* Negative temperature */ -+ if (temp < 3) { -+ if (temp == 2) -+ temp = -1; -+ else if (temp == 1) -+ temp = -2; -+ else -+ temp = -3; -+ } -+ -+ return temp + 1; -+} -+ -+/* -+ * Return battery voltage -+ * Or < 0 on failure. -+ */ -+static int twl4030battery_voltage(void) -+{ -+ int volt = read_bci_val(T2_BATTERY_VOLT); -+ return (volt * VOLT_STEP_SIZE) / VOLT_PSR_R; -+} -+ -+/* -+ * Get latest battery voltage (using MADC) -+ * -+ * When the BCI is not charging, the BCI voltage registers are not -+ * updated and are 'frozen' but the data can be read through the -+ * MADC. -+ */ -+static int twl4030battery_voltage_madc(void) -+{ -+ struct twl4030_madc_request req; -+ -+ req.channels = (1 << 12); -+ req.do_avg = 0; -+ req.method = TWL4030_MADC_SW1; -+ req.active = 0; -+ req.func_cb = NULL; -+ twl4030_madc_conversion(&req); -+ -+ return (((int) req.rbuf[12]) * VOLT_STEP_SIZE) / VOLT_PSR_R; -+} -+ -+/* -+ * Return the battery current -+ * Or < 0 on failure. -+ */ -+static int twl4030battery_current(void) -+{ -+ int ret, curr = read_bci_val(T2_BATTERY_CUR); -+ u8 val; -+ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &val, -+ REG_BCICTL1); -+ if (ret) -+ return ret; -+ -+ if (val & CGAIN) /* slope of 0.44 mV/mA */ -+ return (curr * CURR_STEP_SIZE) / CURR_PSR_R1; -+ else /* slope of 0.88 mV/mA */ -+ return (curr * CURR_STEP_SIZE) / CURR_PSR_R2; -+} -+ -+/* -+ * Return the battery backup voltage -+ * Or < 0 on failure. -+ */ -+static int twl4030backupbatt_voltage(void) -+{ -+ struct twl4030_madc_request req; -+ int temp; -+ -+ req.channels = (1 << 9); -+ req.do_avg = 0; -+ req.method = TWL4030_MADC_SW1; -+ req.active = 0; -+ req.func_cb = NULL; -+ twl4030_madc_conversion(&req); -+ temp = (u16)req.rbuf[9]; -+ -+ return (temp * BK_VOLT_STEP_SIZE) / BK_VOLT_PSR_R; -+} -+ -+/* -+ * Returns an integer value, that means, -+ * NO_PW_CONN no power supply is connected -+ * AC_PW_CONN if the AC power supply is connected -+ * USB_PW_CONN if the USB power supply is connected -+ * AC_PW_CONN + USB_PW_CONN if USB and AC power supplies are both connected -+ * -+ * Or < 0 on failure. -+ */ -+static int twl4030charger_presence(void) -+{ -+ int ret; -+ u8 hwsts; -+ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &hwsts, -+ REG_STS_HW_CONDITIONS); -+ if (ret) { -+ pr_err("twl4030_bci: error reading STS_HW_CONDITIONS\n"); -+ return ret; -+ } -+ -+ ret = (hwsts & STS_CHG) ? AC_PW_CONN : NO_PW_CONN; -+ ret += (hwsts & STS_VBUS) ? USB_PW_CONN : NO_PW_CONN; -+ -+ if (ret & USB_PW_CONN) -+ usb_charger_flag = 1; -+ else -+ usb_charger_flag = 0; -+ -+ return ret; -+ -+} -+ -+/* -+ * Returns the main charge FSM status -+ * Or < 0 on failure. -+ */ -+static int twl4030bci_status(void) -+{ -+ int ret; -+ u8 status; -+ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, -+ &status, REG_BCIMSTATEC); -+ if (ret) { -+ pr_err("twl4030_bci: error reading BCIMSTATEC\n"); -+ return ret; -+ } -+ -+#ifdef DEBUG -+ printk("BCI DEBUG: BCIMSTATEC Charge state is 0x%x\n", status); -+#endif -+ return (int) (status & BCIMSTAT_MASK); -+} -+ -+static int read_bci_val(u8 reg) -+{ -+ int ret, temp; -+ u8 val; -+ -+ /* reading MSB */ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &val, -+ reg + 1); -+ if (ret) -+ return ret; -+ -+ temp = ((int)(val & 0x03)) << 8; -+ -+ /* reading LSB */ -+ ret = twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &val, -+ reg); -+ if (ret) -+ return ret; -+ -+ return temp | val; -+} -+ -+/* -+ * Settup the twl4030 BCI module to enable backup -+ * battery charging. -+ */ -+static int twl4030backupbatt_voltage_setup(void) -+{ -+ int ret; -+ -+ /* Starting backup batery charge */ -+ ret = clear_n_set(TWL4030_MODULE_PM_RECEIVER, 0, BBCHEN, -+ REG_BB_CFG); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+/* -+ * Settup the twl4030 BCI module to measure battery -+ * temperature -+ */ -+static int twl4030battery_temp_setup(void) -+{ -+#ifdef DEBUG -+ u8 i; -+#endif -+ u8 ret; -+ -+ /* Enabling thermistor current */ -+ ret = clear_n_set(TWL4030_MODULE_MAIN_CHARGE, 0, 0x1B, -+ REG_BCICTL1); -+ if (ret) -+ return ret; -+ -+#ifdef DEBUG -+ twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &ret, REG_BOOT_BCI); -+ printk("BCI DEBUG: BOOT_BCI Value is 0x%x\n", ret); -+ -+ twl_i2c_read_u8(TWL4030_MODULE_PM_MASTER, &ret, REG_STS_HW_CONDITIONS); -+ printk("BCI DEBUG: STS_HW_CONDITIONS Value is 0x%x\n", ret); -+ -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &ret, REG_BCICTL1); -+ printk("BCI DEBUG: BCICTL1 Value is 0x%x\n", ret); -+ -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &ret, REG_BCICTL2); -+ printk("BCI DEBUG: BCICTL2 Value is 0x%x\n", ret); -+ -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &ret, 0x0); -+ printk("BCI DEBUG: BCIMDEN Value is 0x%x\n", ret); -+ -+ twl_i2c_read_u8(TWL4030_MODULE_INTBR, &ret, REG_GPBR1); -+ printk("BCI DEBUG: GPBR1 Value is 0x%x\n", ret); -+ -+ for(i = 0x0; i <= 0x32; i++) -+ { -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &ret, i); -+ printk("BCI DEBUG: BCI 0x%x Value is 0x%x\n", i, ret); -+ } -+#endif -+ -+ return 0; -+} -+ -+/* -+ * Sets and clears bits on an given register on a given module -+ */ -+static inline int clear_n_set(u8 mod_no, u8 clear, u8 set, u8 reg) -+{ -+ int ret; -+ u8 val = 0; -+ -+ /* Gets the initial register value */ -+ ret = twl_i2c_read_u8(mod_no, &val, reg); -+ if (ret) -+ return ret; -+ /* Clearing all those bits to clear */ -+ val &= ~(clear); -+ -+ /* Setting all those bits to set */ -+ val |= set; -+ -+ /* Update the register */ -+ ret = twl_i2c_write_u8(mod_no, val, reg); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static enum power_supply_property twl4030_bci_battery_props[] = { -+ POWER_SUPPLY_PROP_STATUS, -+ POWER_SUPPLY_PROP_ONLINE, -+ POWER_SUPPLY_PROP_VOLTAGE_NOW, -+ POWER_SUPPLY_PROP_CURRENT_NOW, -+ POWER_SUPPLY_PROP_CAPACITY, -+ POWER_SUPPLY_PROP_TEMP, -+}; -+ -+static enum power_supply_property twl4030_bk_bci_battery_props[] = { -+ POWER_SUPPLY_PROP_VOLTAGE_NOW, -+}; -+ -+static void -+twl4030_bk_bci_battery_read_status(struct twl4030_bci_device_info *di) -+{ -+ di->bk_voltage_uV = twl4030backupbatt_voltage(); -+} -+ -+static void twl4030_bk_bci_battery_work(struct work_struct *work) -+{ -+ struct twl4030_bci_device_info *di = container_of(work, -+ struct twl4030_bci_device_info, -+ twl4030_bk_bci_monitor_work.work); -+ -+ if(!di->pdata->no_backup_battery) -+ twl4030_bk_bci_battery_read_status(di); -+ schedule_delayed_work(&di->twl4030_bk_bci_monitor_work, 500); -+} -+ -+static void twl4030_bci_battery_read_status(struct twl4030_bci_device_info *di) -+{ -+ if(di->charge_status != POWER_SUPPLY_STATUS_DISCHARGING) { -+ di->temp_C = twl4030battery_temperature(di); -+ di->voltage_uV = twl4030battery_voltage(); -+ di->current_uA = twl4030battery_current(); -+ } -+} -+ -+static void -+twl4030_bci_battery_update_status(struct twl4030_bci_device_info *di) -+{ -+ if (power_supply_am_i_supplied(&di->bat)) -+ di->charge_status = POWER_SUPPLY_STATUS_CHARGING; -+ else -+ di->charge_status = POWER_SUPPLY_STATUS_DISCHARGING; -+ twl4030_bci_battery_read_status(di); -+} -+ -+static void twl4030_bci_battery_work(struct work_struct *work) -+{ -+ struct twl4030_bci_device_info *di = container_of(work, -+ struct twl4030_bci_device_info, twl4030_bci_monitor_work.work); -+ -+ twl4030_bci_battery_update_status(di); -+ schedule_delayed_work(&di->twl4030_bci_monitor_work, 100); -+} -+ -+ -+#define to_twl4030_bci_device_info(x) container_of((x), \ -+ struct twl4030_bci_device_info, bat); -+ -+static void twl4030_bci_battery_external_power_changed(struct power_supply *psy) -+{ -+ struct twl4030_bci_device_info *di = to_twl4030_bci_device_info(psy); -+ -+ cancel_delayed_work(&di->twl4030_bci_monitor_work); -+ schedule_delayed_work(&di->twl4030_bci_monitor_work, 0); -+} -+ -+#define to_twl4030_bk_bci_device_info(x) container_of((x), \ -+ struct twl4030_bci_device_info, bk_bat); -+ -+static ssize_t -+show_charge_current(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ u8 ctl; -+ int ret = read_bci_val(REG_BCIIREF1) & 0x1FF; -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &ctl, REG_BCICTL1); -+ -+ if (ctl & CGAIN) -+ ret |= 0x200; -+ -+#ifdef DEBUG -+ /* Dump debug */ -+ twl4030battery_temp_setup(); -+#endif -+ -+ return sprintf(buf, "%d\n", ret); -+} -+ -+static ssize_t -+set_charge_current(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned long newCurrent; -+ int ret; -+ -+ ret = strict_strtoul(buf, 10, &newCurrent); -+ if (ret) -+ return -EINVAL; -+ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, KEY_IIREF, REG_BCIMFKEY); -+ if (ret) -+ return ret; -+ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, newCurrent & 0xff, REG_BCIIREF1); -+ if (ret) -+ return ret; -+ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, KEY_IIREF, REG_BCIMFKEY); -+ if (ret) -+ return ret; -+ -+ ret = twl_i2c_write_u8(TWL4030_MODULE_MAIN_CHARGE, (newCurrent >> 8) & 0x1, REG_BCIIREF2); -+ if (ret) -+ return ret; -+ -+ /* Set software-controlled charge */ -+ twl4030charger_ac_en(ENABLE, 0); -+ -+ /* Set CGAIN = 0 or 1 */ -+ if(newCurrent > 511) { -+ u8 tmp; -+ -+ /* Set CGAIN = 1 -- need to wait until automatic charge turns off */ -+ while(!ret) { -+ clear_n_set(TWL4030_MODULE_MAIN_CHARGE, 0, CGAIN | 0x1B, REG_BCICTL1); -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &tmp, REG_BCICTL1); -+ -+ ret = tmp & CGAIN; -+ if(!ret) -+ mdelay(50); -+ } -+ } else { -+ u8 tmp; -+ -+ /* Set CGAIN = 0 -- need to wait until automatic charge turns off */ -+ while(!ret) { -+ clear_n_set(TWL4030_MODULE_MAIN_CHARGE, CGAIN, 0x1B, REG_BCICTL1); -+ twl_i2c_read_u8(TWL4030_MODULE_MAIN_CHARGE, &tmp, REG_BCICTL1); -+ -+ ret = !(tmp & CGAIN); -+ if(!ret) -+ mdelay(50); -+ } -+ } -+ -+ /* Set automatic charge (CGAIN = 0/1 persists) */ -+ twl4030charger_ac_en(ENABLE, 1); -+ -+ return count; -+} -+ -+static ssize_t -+show_voltage(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "%d\n", twl4030battery_voltage_madc()); -+} -+ -+static DEVICE_ATTR(charge_current, S_IRUGO | S_IWUGO, show_charge_current, set_charge_current); -+static DEVICE_ATTR(voltage_now_madc, S_IRUGO, show_voltage, NULL); -+ -+static int twl4030_bk_bci_battery_get_property(struct power_supply *psy, -+ enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ struct twl4030_bci_device_info *di = to_twl4030_bk_bci_device_info(psy); -+ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_VOLTAGE_NOW: -+ val->intval = di->bk_voltage_uV; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int twl4030_bci_battery_get_property(struct power_supply *psy, -+ enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ struct twl4030_bci_device_info *di; -+ int status = 0; -+ -+ di = to_twl4030_bci_device_info(psy); -+ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_STATUS: -+ val->intval = di->charge_status; -+ return 0; -+ default: -+ break; -+ } -+ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_VOLTAGE_NOW: -+ { -+ /* Get latest data from MADC -- not done periodically by -+ worker as this is more expensive, so only do it when we -+ are actually asked for the data... */ -+ if(di->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) -+ val->intval = twl4030battery_voltage_madc(); -+ else -+ val->intval = di->voltage_uV; -+ -+ break; -+ } -+ case POWER_SUPPLY_PROP_CURRENT_NOW: -+ /* FIXME: Get from MADC */ -+ if(di->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) -+ val->intval = 0; -+ else -+ val->intval = di->current_uA; -+ break; -+ case POWER_SUPPLY_PROP_TEMP: -+ val->intval = di->temp_C; -+ break; -+ case POWER_SUPPLY_PROP_ONLINE: -+ status = twl4030bci_status(); -+ if ((status & AC_STATEC) == AC_STATEC) -+ val->intval = POWER_SUPPLY_TYPE_MAINS; -+ else if (usb_charger_flag) -+ val->intval = POWER_SUPPLY_TYPE_USB; -+ else -+ val->intval = 0; -+ break; -+ case POWER_SUPPLY_PROP_CAPACITY: -+ /* Get latest data from MADC -- not done periodically by -+ worker as this is more expensive, so only do it when we -+ are actually asked for the data... */ -+ if(di->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) -+ di->voltage_uV = twl4030battery_voltage_madc(); -+ -+ /* -+ * need to get the correct percentage value per the -+ * battery characteristics. Approx values for now. -+ */ -+ if (di->voltage_uV < 2894 || LVL_1) { -+ val->intval = 5; -+ LVL_1 = 0; -+ } else if ((di->voltage_uV < 3451 && di->voltage_uV > 2894) -+ || LVL_2) { -+ val->intval = 20; -+ LVL_2 = 0; -+ } else if ((di->voltage_uV < 3902 && di->voltage_uV > 3451) -+ || LVL_3) { -+ val->intval = 50; -+ LVL_3 = 0; -+ } else if ((di->voltage_uV < 3949 && di->voltage_uV > 3902) -+ || LVL_4) { -+ val->intval = 75; -+ LVL_4 = 0; -+ } else if (di->voltage_uV > 3949) -+ val->intval = 90; -+ break; -+ default: -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static char *twl4030_bci_supplied_to[] = { -+ "twl4030_bci_battery", -+}; -+ -+static int __init twl4030_bci_battery_probe(struct platform_device *pdev) -+{ -+ struct twl4030_bci_platform_data *pdata = pdev->dev.platform_data; -+ struct twl4030_bci_device_info *di; -+ int irq; -+ int ret; -+ -+ di = kzalloc(sizeof(*di), GFP_KERNEL); -+ if (!di) -+ return -ENOMEM; -+ -+ di->dev = &pdev->dev; -+ di->bat.name = "twl4030_bci_battery"; -+ di->bat.supplied_to = twl4030_bci_supplied_to; -+ di->bat.num_supplicants = ARRAY_SIZE(twl4030_bci_supplied_to); -+ di->bat.type = POWER_SUPPLY_TYPE_BATTERY; -+ di->bat.properties = twl4030_bci_battery_props; -+ di->bat.num_properties = ARRAY_SIZE(twl4030_bci_battery_props); -+ di->bat.get_property = twl4030_bci_battery_get_property; -+ di->bat.external_power_changed = -+ twl4030_bci_battery_external_power_changed; -+ -+ di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; -+ -+ di->bk_bat.name = "twl4030_bci_bk_battery"; -+ di->bk_bat.type = POWER_SUPPLY_TYPE_BATTERY; -+ di->bk_bat.properties = twl4030_bk_bci_battery_props; -+ di->bk_bat.num_properties = ARRAY_SIZE(twl4030_bk_bci_battery_props); -+ di->bk_bat.get_property = twl4030_bk_bci_battery_get_property; -+ di->bk_bat.external_power_changed = NULL; -+ di->pdata = pdata; -+ -+ /* Set up clocks */ -+ twl_i2c_write_u8(TWL4030_MODULE_INTBR, MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN, REG_GPBR1); -+ -+ twl4030charger_ac_en(ENABLE, CHARGE_MODE); -+ twl4030charger_usb_en(ENABLE); -+ twl4030battery_hw_level_en(ENABLE); -+ twl4030battery_hw_presence_en(ENABLE); -+ -+ platform_set_drvdata(pdev, di); -+ -+ /* settings for temperature sensing */ -+ ret = twl4030battery_temp_setup(); -+ if (ret) -+ goto temp_setup_fail; -+ -+ /* enabling GPCH09 for read back battery voltage */ -+ if(!di->pdata->no_backup_battery) -+ { -+ ret = twl4030backupbatt_voltage_setup(); -+ if (ret) -+ goto voltage_setup_fail; -+ } -+ -+ /* REVISIT do we need to request both IRQs ?? */ -+ -+ /* request BCI interruption */ -+ irq = platform_get_irq(pdev, 1); -+ ret = request_irq(irq, twl4030battery_interrupt, -+ 0, pdev->name, NULL); -+ if (ret) { -+ dev_dbg(&pdev->dev, "could not request irq %d, status %d\n", -+ irq, ret); -+ goto batt_irq_fail; -+ } -+ -+ /* request Power interruption */ -+ irq = platform_get_irq(pdev, 0); -+ ret = request_irq(irq, twl4030charger_interrupt, -+ 0, pdev->name, di); -+ -+ if (ret) { -+ dev_dbg(&pdev->dev, "could not request irq %d, status %d\n", -+ irq, ret); -+ goto chg_irq_fail; -+ } -+ -+ ret = power_supply_register(&pdev->dev, &di->bat); -+ if (ret) { -+ dev_dbg(&pdev->dev, "failed to register main battery\n"); -+ goto batt_failed; -+ } -+ -+ INIT_DELAYED_WORK_DEFERRABLE(&di->twl4030_bci_monitor_work, -+ twl4030_bci_battery_work); -+ schedule_delayed_work(&di->twl4030_bci_monitor_work, 0); -+ -+ if(!pdata->no_backup_battery) -+ { -+ ret = power_supply_register(&pdev->dev, &di->bk_bat); -+ if (ret) { -+ dev_dbg(&pdev->dev, "failed to register backup battery\n"); -+ goto bk_batt_failed; -+ } -+ } -+ -+ ret = device_create_file(di->bat.dev, &dev_attr_voltage_now_madc); -+ ret = device_create_file(di->bat.dev, &dev_attr_charge_current); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to create sysfs entries\n"); -+ goto bk_batt_failed; -+ } -+ -+ INIT_DELAYED_WORK_DEFERRABLE(&di->twl4030_bk_bci_monitor_work, -+ twl4030_bk_bci_battery_work); -+ schedule_delayed_work(&di->twl4030_bk_bci_monitor_work, 500); -+ -+ set_charge_current (NULL, NULL, "1023", 4); -+ return 0; -+ -+bk_batt_failed: -+ if(!pdata->no_backup_battery) -+ power_supply_unregister(&di->bat); -+batt_failed: -+ free_irq(irq, di); -+chg_irq_fail: -+ irq = platform_get_irq(pdev, 1); -+ free_irq(irq, NULL); -+batt_irq_fail: -+voltage_setup_fail: -+temp_setup_fail: -+ twl4030charger_ac_en(DISABLE, CHARGE_MODE); -+ twl4030charger_usb_en(DISABLE); -+ twl4030battery_hw_level_en(DISABLE); -+ twl4030battery_hw_presence_en(DISABLE); -+ kfree(di); -+ -+ return ret; -+} -+ -+static int __exit twl4030_bci_battery_remove(struct platform_device *pdev) -+{ -+ struct twl4030_bci_device_info *di = platform_get_drvdata(pdev); -+ int irq; -+ -+ twl4030charger_ac_en(DISABLE, CHARGE_MODE); -+ twl4030charger_usb_en(DISABLE); -+ twl4030battery_hw_level_en(DISABLE); -+ twl4030battery_hw_presence_en(DISABLE); -+ -+ irq = platform_get_irq(pdev, 0); -+ free_irq(irq, di); -+ -+ irq = platform_get_irq(pdev, 1); -+ free_irq(irq, NULL); -+ -+ flush_scheduled_work(); -+ power_supply_unregister(&di->bat); -+ power_supply_unregister(&di->bk_bat); -+ platform_set_drvdata(pdev, NULL); -+ kfree(di); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int twl4030_bci_battery_suspend(struct platform_device *pdev, -+ pm_message_t state) -+{ -+ struct twl4030_bci_device_info *di = platform_get_drvdata(pdev); -+ -+ di->charge_status = POWER_SUPPLY_STATUS_UNKNOWN; -+ cancel_delayed_work(&di->twl4030_bci_monitor_work); -+ cancel_delayed_work(&di->twl4030_bk_bci_monitor_work); -+ return 0; -+} -+ -+static int twl4030_bci_battery_resume(struct platform_device *pdev) -+{ -+ struct twl4030_bci_device_info *di = platform_get_drvdata(pdev); -+ -+ schedule_delayed_work(&di->twl4030_bci_monitor_work, 0); -+ schedule_delayed_work(&di->twl4030_bk_bci_monitor_work, 50); -+ return 0; -+} -+#else -+#define twl4030_bci_battery_suspend NULL -+#define twl4030_bci_battery_resume NULL -+#endif /* CONFIG_PM */ -+ -+static struct platform_driver twl4030_bci_battery_driver = { -+ .probe = twl4030_bci_battery_probe, -+ .remove = __exit_p(twl4030_bci_battery_remove), -+ .suspend = twl4030_bci_battery_suspend, -+ .resume = twl4030_bci_battery_resume, -+ .driver = { -+ .name = "twl4030_bci", -+ }, -+}; -+ -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:twl4030_bci"); -+MODULE_AUTHOR("Texas Instruments Inc"); -+ -+static int __init twl4030_battery_init(void) -+{ -+ return platform_driver_register(&twl4030_bci_battery_driver); -+} -+module_init(twl4030_battery_init); -+ -+static void __exit twl4030_battery_exit(void) -+{ -+ platform_driver_unregister(&twl4030_bci_battery_driver); -+} -+module_exit(twl4030_battery_exit); -+ -diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h -index d975c5b..a3470ce 100644 ---- a/include/linux/i2c/twl.h -+++ b/include/linux/i2c/twl.h -@@ -442,6 +442,7 @@ struct twl4030_clock_init_data { - struct twl4030_bci_platform_data { - int *battery_tmp_tbl; - unsigned int tblsize; -+ bool no_backup_battery; - }; - - /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0016-ARM-OMAP-omap3-touchbook-update-boardfile.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0016-ARM-OMAP-omap3-touchbook-update-boardfile.patch deleted file mode 100644 index 0dc58abf..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0016-ARM-OMAP-omap3-touchbook-update-boardfile.patch +++ /dev/null @@ -1,620 +0,0 @@ -From 67a87638586acaf7907f94d2f0d3b09190c23880 Mon Sep 17 00:00:00 2001 -From: Gregoire Gentil -Date: Fri, 12 Mar 2010 11:49:16 +0100 -Subject: [PATCH 16/17] ARM: OMAP: omap3-touchbook: update boardfile - ---- - arch/arm/mach-omap2/board-omap3touchbook.c | 417 +++++++++++++++++++++------- - 1 files changed, 322 insertions(+), 95 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c -index fc3e03c..c22a3e3 100644 ---- a/arch/arm/mach-omap2/board-omap3touchbook.c -+++ b/arch/arm/mach-omap2/board-omap3touchbook.c -@@ -1,7 +1,7 @@ - /* - * linux/arch/arm/mach-omap2/board-omap3touchbook.c - * -- * Copyright (C) 2009 Always Innovating -+ * Copyright (C) 2009-2010 Always Innovating - * - * Modified from mach-omap2/board-omap3beagleboard.c - * -@@ -33,6 +33,7 @@ - #include - - #include -+#include - - #include - #include -@@ -45,6 +46,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -60,18 +62,22 @@ - - #include - -+#include -+#include - - #define GPMC_CS0_BASE 0x60 - #define GPMC_CS_SIZE 0x30 - - #define NAND_BLOCK_SIZE SZ_128K - -+#define OMAP3_HJ_GPIO 56 - #define OMAP3_AC_GPIO 136 -+#define OMAP3_TS2_GPIO 154 - #define OMAP3_TS_GPIO 162 - #define TB_BL_PWM_TIMER 9 - #define TB_KILL_POWER_GPIO 168 - --unsigned long touchbook_revision; -+unsigned long ai_revision = 2; - - static struct mtd_partition omap3touchbook_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ -@@ -126,6 +132,103 @@ static struct platform_device omap3touchbook_nand_device = { - .resource = &omap3touchbook_nand_resource, - }; - -+static int touchbook_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->reset_gpio != -1) -+ gpio_set_value(dssdev->reset_gpio, 1); -+ -+ return 0; -+} -+ -+static void touchbook_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->reset_gpio != -1) -+ gpio_set_value(dssdev->reset_gpio, 0); -+} -+ -+static struct omap_dss_device touchbook_dvi_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "dvi", -+ .driver_name = "generic_panel", -+ .phy.dpi.data_lines = 24, -+ .reset_gpio = 176, -+ .platform_enable = touchbook_enable_dvi, -+ .platform_disable = touchbook_disable_dvi, -+}; -+ -+static int touchbook_panel_enable_tv(struct omap_dss_device *dssdev) -+{ -+#define ENABLE_VDAC_DEDICATED 0x03 -+#define ENABLE_VDAC_DEV_GRP 0x20 -+ -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ ENABLE_VDAC_DEDICATED, -+ TWL4030_VDAC_DEDICATED); -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, -+ ENABLE_VDAC_DEV_GRP, TWL4030_VDAC_DEV_GRP); -+ -+ return 0; -+} -+ -+static void touchbook_panel_disable_tv(struct omap_dss_device *dssdev) -+{ -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00, -+ TWL4030_VDAC_DEDICATED); -+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x00, -+ TWL4030_VDAC_DEV_GRP); -+} -+ -+static struct omap_dss_device touchbook_tv_device = { -+ .name = "tv", -+ .driver_name = "venc", -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -+ .platform_enable = touchbook_panel_enable_tv, -+ .platform_disable = touchbook_panel_disable_tv, -+}; -+ -+static struct omap_dss_device *touchbook_dss_devices[] = { -+ &touchbook_dvi_device, -+ &touchbook_tv_device, -+}; -+ -+static struct omap_dss_board_info touchbook_dss_data = { -+ .num_devices = ARRAY_SIZE(touchbook_dss_devices), -+ .devices = touchbook_dss_devices, -+ .default_device = &touchbook_dvi_device, -+}; -+ -+static struct platform_device touchbook_dss_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = &touchbook_dss_data, -+ }, -+}; -+ -+static struct regulator_consumer_supply touchbook_vdac_supply = { -+ .supply = "vdda_dac", -+ .dev = &touchbook_dss_device.dev, -+}; -+ -+static struct regulator_consumer_supply touchbook_vdvi_supply = { -+ .supply = "vdds_dsi", -+ .dev = &touchbook_dss_device.dev, -+}; -+ -+static void __init touchbook_display_init(void) -+{ -+ int r; -+ -+ r = gpio_request(touchbook_dvi_device.reset_gpio, "DVI reset"); -+ if (r < 0) { -+ printk(KERN_ERR "Unable to get DVI reset GPIO\n"); -+ return; -+ } -+ -+ gpio_direction_output(touchbook_dvi_device.reset_gpio, 0); -+} -+ - #include "sdram-micron-mt46h32m32lf-6.h" - - static struct twl4030_hsmmc_info mmc[] = { -@@ -137,15 +240,6 @@ static struct twl4030_hsmmc_info mmc[] = { - {} /* Terminator */ - }; - --static struct platform_device omap3_touchbook_lcd_device = { -- .name = "omap3touchbook_lcd", -- .id = -1, --}; -- --static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = { -- .ctrl_name = "internal", --}; -- - static struct regulator_consumer_supply touchbook_vmmc1_supply = { - .supply = "vmmc", - }; -@@ -177,6 +271,7 @@ static int touchbook_twl_gpio_setup(struct device *dev, - * power switch and overcurrent detect - */ - -+#if 0 - gpio_request(gpio + 1, "EHCI_nOC"); - gpio_direction_input(gpio + 1); - -@@ -187,6 +282,7 @@ static int touchbook_twl_gpio_setup(struct device *dev, - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; - -+#endif - return 0; - } - -@@ -201,16 +297,6 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = { - .setup = touchbook_twl_gpio_setup, - }; - --static struct regulator_consumer_supply touchbook_vdac_supply = { -- .supply = "vdac", -- .dev = &omap3_touchbook_lcd_device.dev, --}; -- --static struct regulator_consumer_supply touchbook_vdvi_supply = { -- .supply = "vdvi", -- .dev = &omap3_touchbook_lcd_device.dev, --}; -- - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ - static struct regulator_init_data touchbook_vmmc1 = { - .constraints = { -@@ -283,6 +369,15 @@ static struct twl4030_codec_data touchbook_codec_data = { - .audio = &touchbook_audio_data, - }; - -+static struct twl4030_bci_platform_data touchbook_bci_data = { -+ .tblsize = 0, -+ .no_backup_battery = 1, -+}; -+ -+static struct twl4030_madc_platform_data touchbook_madc_data = { -+ .irq_line = 1, -+}; -+ - static struct twl4030_platform_data touchbook_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, -@@ -291,10 +386,15 @@ static struct twl4030_platform_data touchbook_twldata = { - .usb = &touchbook_usb_data, - .gpio = &touchbook_gpio_data, - .codec = &touchbook_codec_data, -+ .madc = &touchbook_madc_data, - .vmmc1 = &touchbook_vmmc1, - .vsim = &touchbook_vsim, - .vdac = &touchbook_vdac, - .vpll2 = &touchbook_vpll2, -+ -+ /* TouchBook BCI */ -+ .bci = &touchbook_bci_data, -+ .madc = &touchbook_madc_data, - }; - - static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = { -@@ -310,10 +410,18 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("bq27200", 0x55), - }, -+ { -+ I2C_BOARD_INFO("chacha", 0x40), -+ .irq = OMAP_GPIO_IRQ(OMAP3_TS2_GPIO), -+ }, -+ { -+ I2C_BOARD_INFO("ds1307", 0x68), -+ }, - }; - - static int __init omap3_touchbook_i2c_init(void) - { -+ int ret; - /* Standard TouchBook bus */ - omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo, - ARRAY_SIZE(touchbook_i2c_boardinfo)); -@@ -322,53 +430,16 @@ static int __init omap3_touchbook_i2c_init(void) - omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo, - ARRAY_SIZE(touchBook_i2c_boardinfo)); - -- return 0; --} -- --static void __init omap3_ads7846_init(void) --{ -- if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) { -- printk(KERN_ERR "Failed to request GPIO %d for " -- "ads7846 pen down IRQ\n", OMAP3_TS_GPIO); -- return; -+ ret = gpio_request(OMAP3_TS2_GPIO, "chacha"); -+ if (ret < 0) { -+ printk(KERN_ERR "Failed to request GPIO %d for chacha IRQ\n", OMAP3_TS2_GPIO); -+ return 0; - } -+ gpio_direction_input(OMAP3_TS2_GPIO); - -- gpio_direction_input(OMAP3_TS_GPIO); -- omap_set_gpio_debounce(OMAP3_TS_GPIO, 1); -- omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa); -+ return 0; - } - --static struct ads7846_platform_data ads7846_config = { -- .x_min = 100, -- .y_min = 265, -- .x_max = 3950, -- .y_max = 3750, -- .x_plate_ohms = 40, -- .pressure_max = 255, -- .debounce_max = 10, -- .debounce_tol = 5, -- .debounce_rep = 1, -- .gpio_pendown = OMAP3_TS_GPIO, -- .keep_vref_on = 1, --}; -- --static struct omap2_mcspi_device_config ads7846_mcspi_config = { -- .turbo_mode = 0, -- .single_channel = 1, /* 0: slave, 1: master */ --}; -- --static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = { -- { -- .modalias = "ads7846", -- .bus_num = 4, -- .chip_select = 0, -- .max_speed_hz = 1500000, -- .controller_data = &ads7846_mcspi_config, -- .irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO), -- .platform_data = &ads7846_config, -- } --}; -- - static struct gpio_led gpio_leds[] = { - { - .name = "touchbook::usr0", -@@ -412,6 +483,7 @@ static struct gpio_keys_button gpio_buttons[] = { - .gpio = 183, - .desc = "power", - .wakeup = 1, -+ .active_low = 1, - }, - }; - -@@ -428,23 +500,8 @@ static struct platform_device keys_gpio = { - }, - }; - --static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = { -- { OMAP_TAG_LCD, &omap3_touchbook_lcd_config }, --}; -- --#ifdef CONFIG_OMAP_MUX --static struct omap_board_mux board_mux[] __initdata = { -- { .reg_offset = OMAP_MUX_TERMINATOR }, --}; --#else --#define board_mux NULL --#endif -- - static void __init omap3_touchbook_init_irq(void) - { -- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -- omap_board_config = omap3_touchbook_config; -- omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params, omap35x_mpu_rate_table, - omap35x_dsp_rate_table, omap35x_l3_rate_table); -@@ -456,9 +513,9 @@ static void __init omap3_touchbook_init_irq(void) - } - - static struct platform_device *omap3_touchbook_devices[] __initdata = { -- &omap3_touchbook_lcd_device, - &leds_gpio, - &keys_gpio, -+ &touchbook_dss_device, - }; - - static void __init omap3touchbook_flash_init(void) -@@ -500,7 +557,7 @@ static void __init omap3touchbook_flash_init(void) - } - } - --static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - - .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -@@ -512,6 +569,170 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .reset_gpio_port[2] = -EINVAL - }; - -+#ifdef CONFIG_OMAP_MUX -+static struct omap_board_mux board_mux[] __initdata = { -+ { .reg_offset = OMAP_MUX_TERMINATOR }, -+}; -+#else -+#define board_mux NULL -+#endif -+ -+static struct ads7846_platform_data ads7846_config = { -+ .x_min = 100, -+ .y_min = 265, -+ .x_max = 3950, -+ .y_max = 3750, -+ .x_plate_ohms = 40, -+ .pressure_max = 255, -+ .debounce_max = 10, -+ .debounce_tol = 5, -+ .debounce_rep = 1, -+ .gpio_pendown = OMAP3_TS_GPIO, -+ .keep_vref_on = 1, -+}; -+ -+static struct omap2_mcspi_device_config ads7846_mcspi_config = { -+ .turbo_mode = 0, -+ .single_channel = 1, /* 0: slave, 1: master */ -+}; -+ -+static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = { -+ { -+ .modalias = "ads7846", -+ .bus_num = 4, -+ .chip_select = 0, -+ .max_speed_hz = 1500000, -+ .controller_data = &ads7846_mcspi_config, -+ .irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO), -+ .platform_data = &ads7846_config, -+ } -+}; -+ -+static void __init omap3_ads7846_init(void) -+{ -+ if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) { -+ printk(KERN_ERR "Failed to request GPIO %d for " -+ "ads7846 pen down IRQ\n", OMAP3_TS_GPIO); -+ return; -+ } -+ -+ gpio_direction_input(OMAP3_TS_GPIO); -+ omap_set_gpio_debounce(OMAP3_TS_GPIO, 1); -+ omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa); -+} -+ -+static struct mma7455l_platform_data mma7455l_config = { -+ .calibration_x = -4, -+ .calibration_y = 28, -+ .calibration_z = -28, -+}; -+ -+static struct omap2_mcspi_device_config mma7455l_mcspi_config = { -+ .turbo_mode = 0, -+ .single_channel = 1, /* 0: slave, 1: master */ -+}; -+ -+static struct spi_board_info omap3_mma7455l_spi_board_info[] __initdata = { -+ { -+ .modalias = "mma7455l", -+ .bus_num = 3, -+ .chip_select = 0, -+ .max_speed_hz = 200000, -+ .irq = OMAP_GPIO_IRQ(OMAP3_AC_GPIO), -+ .controller_data = &mma7455l_mcspi_config, //(void *) 135, -+ .platform_data = &mma7455l_config, -+ } -+}; -+ -+static void __init omap3_mma7455l_init(void) -+{ -+ int ret; -+ -+ ret = gpio_request(OMAP3_AC_GPIO, "mma7455l"); -+ if (ret < 0) { -+ printk(KERN_ERR "Failed to request GPIO %d for mma7455l IRQ\n", OMAP3_AC_GPIO); -+ return; -+ } -+ -+ gpio_direction_input(OMAP3_AC_GPIO); -+} -+ -+static int touchbook_backlight_brightness = 50; -+static struct omap_dm_timer *touchbook_backlight_pwm; -+ -+static int touchbook_backlight_read(struct backlight_device *bd) -+{ -+ return touchbook_backlight_brightness; -+} -+ -+static int touchbook_backlight_update(struct backlight_device *bd) -+{ -+ int value = bd->props.brightness; -+ touchbook_backlight_brightness = value; -+ -+ /* Frequency calculation: -+ - For 200Hz PWM, you want to load -164 (=> -32768Hz / 200Hz). -+ - Minimum duty cycle for the backlight is 15%. -+ - You have (164*0.85) => ~140 levels of brightness. -+ */ -+ -+ /* Halve input brightness */ -+ if (!bd->props.boost) -+ value /= 2; -+ -+ /* For maximum brightness, just stop the timer... */ -+ if(value != bd->props.max_brightness) -+ { -+ /* Load the appropriate value for 200Hz PWM */ -+ u32 period = clk_get_rate(omap_dm_timer_get_fclk(touchbook_backlight_pwm)) / bd->props.pwm_fq; -+ -+ /* Minimum duty cycle is 15% */ -+ u32 minimum = (period * bd->props.min_duty) / 100; -+ u32 maximum = (period * 17) / 20; -+ -+ /* Work out match value */ -+ u32 match = (maximum * value) / 100; -+ -+ /* Start... */ -+ omap_dm_timer_set_load(touchbook_backlight_pwm, 1, 0xFFFFFFFF - period - 1); -+ omap_dm_timer_set_match(touchbook_backlight_pwm, 1, 0xFFFFFFFF - minimum - match); -+ omap_dm_timer_write_counter(touchbook_backlight_pwm, -1); -+ omap_dm_timer_start(touchbook_backlight_pwm); -+ } -+ else -+ omap_dm_timer_stop(touchbook_backlight_pwm); -+ -+ -+ return 0; -+} -+ -+static struct backlight_ops touchbook_backlight_properties = { -+ .get_brightness = touchbook_backlight_read, -+ .update_status = touchbook_backlight_update, -+}; -+ -+static void __init omap3_touchbook_backlight_init(void) -+{ -+ static struct backlight_device *bd; -+ bd = backlight_device_register("touchbook", NULL, NULL, &touchbook_backlight_properties); -+ -+ if(bd) -+ { -+ touchbook_backlight_pwm = omap_dm_timer_request_specific(TB_BL_PWM_TIMER); -+ omap_dm_timer_enable(touchbook_backlight_pwm); -+ omap_dm_timer_set_source(touchbook_backlight_pwm, OMAP_TIMER_SRC_SYS_CLK); -+ omap_dm_timer_set_pwm(touchbook_backlight_pwm, 1, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); -+ -+ bd->props.max_brightness = 100; -+ bd->props.brightness = touchbook_backlight_brightness; -+ bd->props.boost = 0; -+ bd->props.min_duty = 15; -+ bd->props.pwm_fq = 200; -+ } -+ -+ touchbook_backlight_update(bd); -+} -+ - static void omap3_touchbook_poweroff(void) - { - int r; -@@ -525,33 +746,26 @@ static void omap3_touchbook_poweroff(void) - gpio_direction_output(TB_KILL_POWER_GPIO, 0); - } - --static void __init early_touchbook_revision(char **p) -+static int __init ai_revision_instance(char *str) - { -- if (!*p) -- return; -+ if (!str) -+ return -EINVAL; -+ -+ ai_revision = simple_strtoul(str, NULL, 10); - -- strict_strtoul(*p, 10, &touchbook_revision); -+ return 0; - } --__early_param("tbr=", early_touchbook_revision); - - static void __init omap3_touchbook_init(void) - { - pm_power_off = omap3_touchbook_poweroff; - -+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap3_touchbook_i2c_init(); - platform_add_devices(omap3_touchbook_devices, - ARRAY_SIZE(omap3_touchbook_devices)); - omap_serial_init(); - -- omap_mux_init_gpio(170, OMAP_PIN_INPUT); -- gpio_request(176, "DVI_nPD"); -- /* REVISIT leave DVI powered down until it's needed ... */ -- gpio_direction_output(176, true); -- -- /* Touchscreen and accelerometer */ -- spi_register_board_info(omap3_ads7846_spi_board_info, -- ARRAY_SIZE(omap3_ads7846_spi_board_info)); -- omap3_ads7846_init(); - usb_musb_init(); - usb_ehci_init(&ehci_pdata); - omap3touchbook_flash_init(); -@@ -559,6 +773,17 @@ static void __init omap3_touchbook_init(void) - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); - omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -+ -+ touchbook_display_init(); -+ omap3_touchbook_backlight_init(); -+ -+ /* Touchscreen and accelerometer */ -+ spi_register_board_info(omap3_ads7846_spi_board_info, -+ ARRAY_SIZE(omap3_ads7846_spi_board_info)); -+ spi_register_board_info(omap3_mma7455l_spi_board_info, -+ ARRAY_SIZE(omap3_mma7455l_spi_board_info)); -+ omap3_ads7846_init(); -+ omap3_mma7455l_init(); - } - - static void __init omap3_touchbook_map_io(void) -@@ -567,6 +792,8 @@ static void __init omap3_touchbook_map_io(void) - omap2_map_common_io(); - } - -+early_param("air", ai_revision_instance); -+ - MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") - /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ - .phys_io = 0x48000000, --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0017-ARM-OMAP-add-800MHz-OPP-and-remove-125MHz-one.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0017-ARM-OMAP-add-800MHz-OPP-and-remove-125MHz-one.patch deleted file mode 100644 index 8a06ead4..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/0017-ARM-OMAP-add-800MHz-OPP-and-remove-125MHz-one.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 1f36c057ab83a5c5e8162094fb52022edd5ba9b8 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Tue, 4 May 2010 09:01:21 +0200 -Subject: [PATCH 17/17] ARM: OMAP: add 800MHz OPP and remove 125MHz one - ---- - arch/arm/mach-omap2/pm34xx.c | 6 ++++-- - 1 files changed, 4 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c -index d1cc528..42fbcdd 100644 ---- a/arch/arm/mach-omap2/pm34xx.c -+++ b/arch/arm/mach-omap2/pm34xx.c -@@ -120,7 +120,7 @@ static struct prm_setup_vc prm_setup = { - struct omap_opp omap35x_mpu_rate_table[] = { - {0, 0, 0}, - /*OPP1*/ -- {S125M, VDD1_OPP1, 0x1E}, -+// {S125M, VDD1_OPP1, 0x1E}, - /*OPP2*/ - {S250M, VDD1_OPP2, 0x26}, - /*OPP3*/ -@@ -131,12 +131,13 @@ struct omap_opp omap35x_mpu_rate_table[] = { - {S600M, VDD1_OPP5, 0x3C}, - /*OPP6*/ - {S720M, VDD1_OPP6, 0x3C}, -+ {S800M, VDD1_OPP6, 0x3F}, - }; - - struct omap_opp omap35x_dsp_rate_table[] = { - {0, 0, 0}, - /*OPP1*/ -- {S90M, VDD1_OPP1, 0x1E}, -+// {S90M, VDD1_OPP1, 0x1E}, - /*OPP2*/ - {S180M, VDD1_OPP2, 0x26}, - /*OPP3*/ -@@ -147,6 +148,7 @@ struct omap_opp omap35x_dsp_rate_table[] = { - {S430M, VDD1_OPP5, 0x3C}, - /*OPP5*/ - {S520M, VDD1_OPP6, 0x3C}, -+ {S600M, VDD1_OPP6, 0x3F}, - }; - - struct omap_opp omap35x_l3_rate_table[] = { --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/defconfig deleted file mode 100644 index 6f2b7bd9..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3-touchbook/defconfig +++ /dev/null @@ -1,3043 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Mon May 10 12:50:28 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=15 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=m -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_SLOW_WORK_DEBUG is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_INTEGRITY=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_UNLOCK is not set -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_UNLOCK is not set -# CONFIG_INLINE_READ_UNLOCK_BH is not set -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_UNLOCK is not set -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MBOX_FWK=m -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -# CONFIG_OMAP_PM_NOOP is not set -CONFIG_OMAP_PM_SRF=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -CONFIG_MACH_OMAP3_TOUCHBOOK=y -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_USER_L2_PLE is not set -# CONFIG_USER_PMON is not set -CONFIG_ARM_ERRATA_430973=y -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_VMSPLIT_3G is not set -CONFIG_VMSPLIT_2G=y -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0x80000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -# CONFIG_CPU_FREQ_DEBUG is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=m - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -# CONFIG_DEFAULT_BIC is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -# CONFIG_IPV6_PIMSM_V2 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=m -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -# CONFIG_NETFILTER_TPROXY is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=m -# CONFIG_NETFILTER_XT_TARGET_LED is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_DCCP=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_UDPLITE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=y - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_RDS is not set -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_BRIDGE=m -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m -# CONFIG_PHONET is not set -CONFIG_IEEE802154=m -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_IND=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -CONFIG_IRDA_ULTRA=y - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -CONFIG_IRDA_DEBUG=y - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -CONFIG_DONGLE=y -CONFIG_ESI_DONGLE=m -CONFIG_ACTISYS_DONGLE=m -CONFIG_TEKRAM_DONGLE=m -CONFIG_TOIM3232_DONGLE=m -CONFIG_LITELINK_DONGLE=m -CONFIG_MA600_DONGLE=m -CONFIG_GIRBIL_DONGLE=m -CONFIG_MCP2120_DONGLE=m -CONFIG_OLD_BELKIN_DONGLE=m -# CONFIG_ACT200L_DONGLE is not set -CONFIG_KINGSUN_DONGLE=m -CONFIG_KSDAZZLE_DONGLE=m -CONFIG_KS959_DONGLE=m - -# -# FIR device drivers -# -CONFIG_USB_IRDA=m -CONFIG_SIGMATEL_FIR=m -CONFIG_MCS_FIR=m -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -CONFIG_MAC80211_RC_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_NET_9P=m -# CONFIG_NET_9P_DEBUG is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_AD525X_DPOT is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -# CONFIG_ISL29003 is not set -# CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=y -# CONFIG_IWMC3200TOP is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -CONFIG_DM_UEVENT=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -# CONFIG_NET_ETHERNET is not set -CONFIG_MII=m -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_AT76C50X_USB is not set -CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -CONFIG_B43=m -# CONFIG_B43_SDIO is not set -CONFIG_B43_PHY_LP=y -CONFIG_B43_LEDS=y -CONFIG_B43_HWRNG=y -# CONFIG_B43_DEBUG is not set -# CONFIG_B43LEGACY is not set -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -# CONFIG_IWM is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -# CONFIG_LIBERTAS_SDIO is not set -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_SPI is not set -CONFIG_P54_LEDS=y -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800_LIB=m -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_HT=y -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -# CONFIG_WL12XX is not set -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# WiMAX Wireless Broadband devices -# -# CONFIG_WIMAX_I2400M_USB is not set -# CONFIG_WIMAX_I2400M_SDIO is not set - -# -# USB Network Adapters -# -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_CDCETHER=m -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=m -# CONFIG_USB_HSO is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -CONFIG_IEEE802154_DRIVERS=m -# CONFIG_IEEE802154_FAKEHARD is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOATM is not set -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -CONFIG_INPUT_POWERMATE=m -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -CONFIG_INPUT_MMA7455L=y - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -CONFIG_RAW_DRIVER=m -CONFIG_MAX_RAW_DEVS=256 -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -CONFIG_I2C_TINY_USB=m - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -CONFIG_BATTERY_BQ27x00=y -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_TWL4030_BCI_BATTERY=y -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_WATCHDOG=m - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -CONFIG_SSB=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -# CONFIG_SSB_SDIOHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set -CONFIG_TWL4030_CODEC=y -CONFIG_TWL4030_MADC=y -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_CUSTOMISE=y -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_DMA_SG=m -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -CONFIG_VIDEO_TVAUDIO=m -CONFIG_VIDEO_TDA7432=m -CONFIG_VIDEO_TDA9840=m -CONFIG_VIDEO_TDA9875=m -CONFIG_VIDEO_TEA6415C=m -CONFIG_VIDEO_TEA6420=m -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_CS5345=m -CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_M52790=m -CONFIG_VIDEO_TLV320AIC23B=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_WM8739=m -CONFIG_VIDEO_VP27SMPX=m - -# -# RDS decoders -# -CONFIG_VIDEO_SAA6588=m - -# -# Video decoders -# -CONFIG_VIDEO_ADV7180=m -CONFIG_VIDEO_BT819=m -CONFIG_VIDEO_BT856=m -CONFIG_VIDEO_BT866=m -CONFIG_VIDEO_KS0127=m -# CONFIG_VIDEO_OV7670 is not set -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_TCM825X=m -CONFIG_VIDEO_MT9P012=m -CONFIG_VIDEO_DW9710=m -# CONFIG_VIDEO_OV3640 is not set -CONFIG_VIDEO_IMX046=m -CONFIG_VIDEO_LV8093=m -CONFIG_VIDEO_SAA7110=m -CONFIG_VIDEO_SAA711X=m -CONFIG_VIDEO_SAA717X=m -CONFIG_VIDEO_SAA7191=m -CONFIG_VIDEO_TVP514X=m -CONFIG_VIDEO_TVP5150=m -CONFIG_VIDEO_VPX3220=m - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -CONFIG_VIDEO_SAA7127=m -CONFIG_VIDEO_SAA7185=m -CONFIG_VIDEO_ADV7170=m -CONFIG_VIDEO_ADV7175=m -CONFIG_VIDEO_THS7303=m -CONFIG_VIDEO_ADV7343=m - -# -# Video improvement chips -# -CONFIG_VIDEO_UPD64031A=m -CONFIG_VIDEO_UPD64083=m -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=m -CONFIG_VIDEO_VPSS_SYSTEM=m -# CONFIG_VIDEO_VPFE_CAPTURE is not set -CONFIG_VIDEO_OMAP2_VOUT=m -# CONFIG_VIDEO_OMAP3 is not set -# CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER is not set -# CONFIG_VIDEO_OMAP34XX_ISP_RESIZER is not set -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_TEF6862 is not set -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_FRIIO=m -CONFIG_DVB_USB_EC168=m -CONFIG_SMS_SIANO_MDTV=m - -# -# Siano module components -# -# CONFIG_SMS_USB_DRV is not set -# CONFIG_SMS_SDIO_DRV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_EC100=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_LGS8GL5=m -CONFIG_DAB=y -CONFIG_USB_DABUSB=m - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=18 -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -CONFIG_PANEL_SHARP_LQ043T1DG01=y -# CONFIG_PANEL_TAAL is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -CONFIG_LCD_PLATFORM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_LOGO is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=m -CONFIG_SND_RAWMIDI=m -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -# CONFIG_SND_PCM_OSS is not set -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -CONFIG_SND_VIRMIDI=m -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3_TOUCHBOOK=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=y -CONFIG_HID_AI=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -CONFIG_HID_TOPSEED=y -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_OXU210HP_HCD=y -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_U132_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -# CONFIG_USB_SERIAL_CP210X is not set -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m -CONFIG_USB_LED=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=m -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_VST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -CONFIG_USB_ZERO_HNPTEST=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -# CONFIG_USB_MASS_STORAGE is not set -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_GPIO_VBUS=y -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_TWL4030_USB=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_UNSAFE_RESUME=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=y -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -CONFIG_W35UND=m -CONFIG_PRISM2_USB=m -# CONFIG_ECHO is not set -CONFIG_OTUS=m -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -# CONFIG_RAMZSWAP is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_STRIP is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=m -CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=m -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=m -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_JFS_FS=m -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=m -# CONFIG_GFS2_FS_LOCKING_DLM is not set -CONFIG_OCFS2_FS=m -CONFIG_OCFS2_FS_O2CB=m -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -# CONFIG_OCFS2_DEBUG_FS is not set -# CONFIG_OCFS2_FS_POSIX_ACL is not set -CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=y -# CONFIG_CUSE is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=m -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -# CONFIG_ECRYPT_FS is not set -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DFS_UPCALL is not set -CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_NCP_FS=m -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_9P_FS=m - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3evm/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3evm/defconfig deleted file mode 100644 index 5508dc50..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/omap3evm/defconfig +++ /dev/null @@ -1,3088 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Wed Jul 28 15:05:34 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_SLOW_WORK_DEBUG is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -# CONFIG_INLINE_SPIN_UNLOCK is not set -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -# CONFIG_INLINE_READ_UNLOCK is not set -# CONFIG_INLINE_READ_UNLOCK_BH is not set -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -# CONFIG_INLINE_WRITE_UNLOCK is not set -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX=y -# CONFIG_OMAP_MUX_DEBUG is not set -CONFIG_OMAP_MUX_WARNINGS=y -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MBOX_FWK=m -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_LL_DEBUG_UART1=y -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -# CONFIG_OMAP_LL_DEBUG_UART3 is not set -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -# CONFIG_OMAP_PM_NOOP is not set -CONFIG_OMAP_PM_SRF=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -# CONFIG_MACH_OVERO is not set -CONFIG_MACH_OMAP3EVM=y -CONFIG_PMIC_TWL4030=y -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_USER_L2_PLE=y -CONFIG_USER_PMON=y -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_458693=y -CONFIG_ARM_ERRATA_460075=y -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -CONFIG_CPU_V7_SYSFS=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -CONFIG_CPU_FREQ_DEBUG=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -CONFIG_PM_RUNTIME=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -# CONFIG_DEFAULT_BIC is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -# CONFIG_IPV6_PIMSM_V2 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=m -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CT_PROTO_UDPLITE=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -# CONFIG_NETFILTER_TPROXY is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=m -# CONFIG_NETFILTER_XT_TARGET_LED is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_NF_NAT=m -CONFIG_NF_NAT_NEEDED=y -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PROTO_DCCP=m -CONFIG_NF_NAT_PROTO_GRE=m -CONFIG_NF_NAT_PROTO_UDPLITE=m -CONFIG_NF_NAT_PROTO_SCTP=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_NF_NAT_SIP=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_QUEUE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_TARGET_LOG=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration (EXPERIMENTAL) -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_CCID3_RTO=100 -CONFIG_IP_DCCP_TFRC_LIB=y - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -CONFIG_IP_SCTP=m -# CONFIG_SCTP_DBG_MSG is not set -# CONFIG_SCTP_DBG_OBJCNT is not set -# CONFIG_SCTP_HMAC_NONE is not set -# CONFIG_SCTP_HMAC_SHA1 is not set -CONFIG_SCTP_HMAC_MD5=y -# CONFIG_RDS is not set -CONFIG_TIPC=m -# CONFIG_TIPC_ADVANCED is not set -# CONFIG_TIPC_DEBUG is not set -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -# CONFIG_ATM_BR2684_IPFILTER is not set -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_BRIDGE=m -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -# CONFIG_DECNET is not set -CONFIG_LLC=m -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -CONFIG_WAN_ROUTER=m -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_CLS_IND=y -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=m -CONFIG_CAN_RAW=m -CONFIG_CAN_BCM=m - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=m -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_IRDA=m - -# -# IrDA protocols -# -CONFIG_IRLAN=m -CONFIG_IRNET=m -CONFIG_IRCOMM=m -CONFIG_IRDA_ULTRA=y - -# -# IrDA options -# -CONFIG_IRDA_CACHE_LAST_LSAP=y -CONFIG_IRDA_FAST_RR=y -CONFIG_IRDA_DEBUG=y - -# -# Infrared-port device drivers -# - -# -# SIR device drivers -# -CONFIG_IRTTY_SIR=m - -# -# Dongle support -# -CONFIG_DONGLE=y -CONFIG_ESI_DONGLE=m -CONFIG_ACTISYS_DONGLE=m -CONFIG_TEKRAM_DONGLE=m -CONFIG_TOIM3232_DONGLE=m -CONFIG_LITELINK_DONGLE=m -CONFIG_MA600_DONGLE=m -CONFIG_GIRBIL_DONGLE=m -CONFIG_MCP2120_DONGLE=m -CONFIG_OLD_BELKIN_DONGLE=m -# CONFIG_ACT200L_DONGLE is not set -CONFIG_KINGSUN_DONGLE=m -CONFIG_KSDAZZLE_DONGLE=m -CONFIG_KS959_DONGLE=m - -# -# FIR device drivers -# -CONFIG_USB_IRDA=m -CONFIG_SIGMATEL_FIR=m -CONFIG_MCS_FIR=m -CONFIG_BT=m -CONFIG_BT_L2CAP=m -CONFIG_BT_SCO=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -CONFIG_AF_RXRPC=m -# CONFIG_AF_RXRPC_DEBUG is not set -# CONFIG_RXKAD is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=y -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_WIMAX=m -CONFIG_WIMAX_DEBUG_LEVEL=8 -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_NET_9P=m -# CONFIG_NET_9P_DEBUG is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_OMAP_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -# CONFIG_MTD_ONENAND_GENERIC is not set -CONFIG_MTD_ONENAND_OMAP2=y -# CONFIG_MTD_ONENAND_OTP is not set -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -# CONFIG_MTD_ONENAND_SIM is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -CONFIG_MISC_DEVICES=y -# CONFIG_AD525X_DPOT is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -# CONFIG_ISL29003 is not set -# CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=m -CONFIG_IWMC3200TOP=m -# CONFIG_IWMC3200TOP_DEBUG is not set -# CONFIG_IWMC3200TOP_DEBUGFS is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -CONFIG_SCSI_ISCSI_ATTRS=m -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -# CONFIG_DM_UEVENT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_BONDING=m -CONFIG_MACVLAN=m -CONFIG_EQUALIZER=m -CONFIG_TUN=m -CONFIG_VETH=m -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -CONFIG_AT76C50X_USB=m -CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -CONFIG_B43=m -# CONFIG_B43_SDIO is not set -CONFIG_B43_PHY_LP=y -CONFIG_B43_LEDS=y -CONFIG_B43_HWRNG=y -# CONFIG_B43_DEBUG is not set -# CONFIG_B43LEGACY is not set -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -# CONFIG_IWM is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -# CONFIG_LIBERTAS_SDIO is not set -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_SPI is not set -CONFIG_P54_LEDS=y -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -# CONFIG_RT2800USB is not set -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -CONFIG_WL12XX=m -CONFIG_WL1251=m -CONFIG_WL1251_SPI=m -CONFIG_WL1251_SDIO=m -CONFIG_WL1271=m -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# WiMAX Wireless Broadband devices -# -CONFIG_WIMAX_I2400M=m -CONFIG_WIMAX_I2400M_USB=m -CONFIG_WIMAX_I2400M_SDIO=m -CONFIG_WIMAX_IWMC3200_SDIO=y -CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 - -# -# USB Network Adapters -# -CONFIG_USB_CATC=y -CONFIG_USB_KAWETH=y -CONFIG_USB_PEGASUS=y -CONFIG_USB_RTL8150=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=y -CONFIG_USB_NET_SMSC95XX=y -CONFIG_USB_NET_GL620A=y -CONFIG_USB_NET_NET1080=y -CONFIG_USB_NET_PLUSB=y -CONFIG_USB_NET_MCS7830=y -CONFIG_USB_NET_RNDIS_HOST=y -CONFIG_USB_NET_CDC_SUBSET=y -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=y -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -# CONFIG_WAN is not set -CONFIG_ATM_DRIVERS=y -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_TCP is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOATM is not set -CONFIG_PPPOL2TP=m -# CONFIG_SLIP is not set -CONFIG_SLHC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NETPOLL_TRAP=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -CONFIG_KEYBOARD_TWL4030=y -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_ATI_REMOTE is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=m -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -CONFIG_SSB=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -# CONFIG_SSB_SDIOHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_CODEC=y -# CONFIG_TWL4030_MADC is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_CUSTOMISE=y -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DVB=m -CONFIG_VIDEO_IR=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_IR_I2C=m - -# -# Encoders/decoders and other helper chips -# - -# -# Audio decoders -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA9875 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_OV7670 is not set -CONFIG_VIDEO_MT9V011=m -CONFIG_VIDEO_MT9V113=m -# CONFIG_VIDEO_TCM825X is not set -CONFIG_VIDEO_MT9P012=m -CONFIG_VIDEO_MT9T112=m -# CONFIG_VIDEO_DW9710 is not set -# CONFIG_VIDEO_OV3640 is not set -# CONFIG_VIDEO_IMX046 is not set -# CONFIG_VIDEO_LV8093 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set -CONFIG_VIDEO_TVP514X=y -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set - -# -# Video and audio decoders -# -CONFIG_VIDEO_CX25840=m - -# -# MPEG video encoders -# -CONFIG_VIDEO_CX2341X=m - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_ADV7343 is not set - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=y -# CONFIG_VIDEO_VPFE_CAPTURE is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -# CONFIG_USB_GL860 is not set -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -# CONFIG_USB_GSPCA_JEILINJ is not set -CONFIG_USB_GSPCA_MARS=m -# CONFIG_USB_GSPCA_MR97310A is not set -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -# CONFIG_USB_GSPCA_PAC7302 is not set -CONFIG_USB_GSPCA_PAC7311=m -# CONFIG_USB_GSPCA_SN9C20X is not set -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -CONFIG_USB_GSPCA_STK014=m -# CONFIG_USB_GSPCA_STV0680 is not set -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_CX231XX=m -# CONFIG_VIDEO_CX231XX_ALSA is not set -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_TEF6862 is not set -CONFIG_DVB_MAX_ADAPTERS=8 -CONFIG_DVB_DYNAMIC_MINORS=y -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AF9015=m -# CONFIG_DVB_USB_CE6230 is not set -# CONFIG_DVB_USB_FRIIO is not set -# CONFIG_DVB_USB_EC168 is not set -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX24116=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m -CONFIG_DVB_NXT200X=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_ISL6421=m -CONFIG_DVB_LGS8GL5=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=14 -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_USE_DSI_PLL=y -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C is not set -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -# CONFIG_PANEL_TAAL is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -CONFIG_SND_HRTIMER=m -CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_ARM is not set -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OMAP3EVM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -CONFIG_HID_TOPSEED=y -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_U132_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -# CONFIG_USB_MUSB_HOST is not set -# CONFIG_USB_MUSB_PERIPHERAL is not set -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -# CONFIG_USB_SERIAL_CP210X is not set -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -CONFIG_USB_SERIAL_SIEMENS_MPI=m -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_BERRY_CHARGE=m -CONFIG_USB_LED=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -# CONFIG_USB_IOWARRIOR is not set -CONFIG_USB_TEST=m -# CONFIG_USB_ISIGHTFW is not set -CONFIG_USB_VST=m -CONFIG_USB_ATM=m -CONFIG_USB_SPEEDTOUCH=m -CONFIG_USB_CXACRU=m -CONFIG_USB_UEAGLEATM=m -CONFIG_USB_XUSBATM=m -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -CONFIG_USB_ZERO_HNPTEST=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -# CONFIG_USB_MASS_STORAGE is not set -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -CONFIG_USB_GPIO_VBUS=y -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_TWL4030_USB=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_UNSAFE_RESUME=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=m - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=m -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -CONFIG_UIO=m -CONFIG_UIO_PDRV=m -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_USB_IP_COMMON is not set -CONFIG_W35UND=m -# CONFIG_PRISM2_USB is not set -CONFIG_ECHO=m -CONFIG_OTUS=m -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -CONFIG_RTL8192SU=m -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -# CONFIG_RAMZSWAP is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_STRIP is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_JFS_FS=m -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_XFS_FS=m -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=m -# CONFIG_GFS2_FS_LOCKING_DLM is not set -CONFIG_OCFS2_FS=m -CONFIG_OCFS2_FS_O2CB=m -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -# CONFIG_OCFS2_DEBUG_FS is not set -# CONFIG_OCFS2_FS_POSIX_ACL is not set -CONFIG_BTRFS_FS=m -# CONFIG_BTRFS_FS_POSIX_ACL is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -# CONFIG_CUSE is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=m -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -# CONFIG_ECRYPT_FS is not set -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -# CONFIG_ROMFS_BACKED_BY_MTD is not set -# CONFIG_ROMFS_BACKED_BY_BOTH is not set -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -# CONFIG_SMB_NLS_DEFAULT is not set -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DFS_UPCALL is not set -CONFIG_CIFS_EXPERIMENTAL=y -CONFIG_NCP_FS=m -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_9P_FS=m - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -CONFIG_MAC_PARTITION=y -CONFIG_MSDOS_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -# CONFIG_UNIXWARE_DISKLABEL is not set -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=y -CONFIG_DLM=m -# CONFIG_DLM_DEBUG is not set - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_DEBUG_PROC_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/overo/defconfig b/recipes-kernel/linux/linux-omap-psp-2.6.32/overo/defconfig deleted file mode 100644 index be4375e6..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/overo/defconfig +++ /dev/null @@ -1,2467 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32 -# Thu Mar 11 14:23:41 2010 -# -CONFIG_ARM=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ARCH_HAS_CPUFREQ=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_OPROFILE_ARMV7=y -CONFIG_VECTORS_BASE=0xffff0000 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=15 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -CONFIG_OPROFILE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_CLK=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -CONFIG_FREEZER=y - -# -# System Type -# -CONFIG_MMU=y -# CONFIG_ARCH_AAEC2000 is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_STMP3XXX is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP23XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_LOKI is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_PNX4008 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PC1XX is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_DAVINCI is not set -CONFIG_ARCH_OMAP=y -# CONFIG_ARCH_BCMRING is not set -# CONFIG_ARCH_U8500 is not set - -# -# TI OMAP Implementations -# -CONFIG_ARCH_OMAP_OTG=y -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -CONFIG_ARCH_OMAP3=y -# CONFIG_ARCH_OMAP4 is not set - -# -# OMAP Feature Selections -# -CONFIG_OMAP_SMARTREFLEX=y -# CONFIG_OMAP_SMARTREFLEX_TESTING is not set -# CONFIG_OMAP_RESET_CLOCKS is not set -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_MCBSP=y -CONFIG_OMAP_MBOX_FWK=m -CONFIG_OMAP_IOMMU=y -# CONFIG_OMAP_MPU_TIMER is not set -CONFIG_OMAP_32K_TIMER=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_DEBOBS is not set -CONFIG_OMAP_32K_TIMER_HZ=128 -CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set -# CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y -# CONFIG_OMAP_LL_DEBUG_NONE is not set -# CONFIG_OMAP_PM_NONE is not set -# CONFIG_OMAP_PM_NOOP is not set -CONFIG_OMAP_PM_SRF=y -CONFIG_ARCH_OMAP34XX=y -CONFIG_ARCH_OMAP3430=y -CONFIG_OMAP_PACKAGE_CBB=y - -# -# OMAP Board Type -# -# CONFIG_MACH_OMAP3_BEAGLE is not set -# CONFIG_MACH_OMAP_LDP is not set -CONFIG_MACH_OVERO=y -# CONFIG_MACH_OMAP3EVM is not set -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -# CONFIG_MACH_OMAP3_TOUCHBOOK is not set -# CONFIG_MACH_OMAP_3430SDP is not set -# CONFIG_MACH_NOKIA_RX51 is not set -# CONFIG_MACH_OMAP_ZOOM2 is not set -# CONFIG_MACH_OMAP_ZOOM3 is not set -# CONFIG_MACH_CM_T35 is not set -# CONFIG_MACH_IGEP0020 is not set -# CONFIG_MACH_OMAP_3630SDP is not set -# CONFIG_OMAP3_EMU is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_HAS_TLS_REG=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -CONFIG_COMMON_CLKDEV=y - -# -# Bus support -# -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -CONFIG_HZ=128 -# CONFIG_THUMB2_KERNEL is not set -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -# CONFIG_HIGHMEM is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_LEDS=y -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE=" debug " -# CONFIG_XIP_KERNEL is not set -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y - -# -# CPU Power Management -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_TABLE=y -CONFIG_CPU_FREQ_DEBUG=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_IDLE is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_HAVE_AOUT=y -CONFIG_BINFMT_AOUT=m -CONFIG_BINFMT_MISC=y - -# -# Power management options -# -CONFIG_PM=y -CONFIG_PM_DEBUG=y -# CONFIG_PM_VERBOSE is not set -CONFIG_CAN_PM_TRACE=y -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_SUSPEND_FREEZER=y -# CONFIG_APM_EMULATION is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_IPV6_SIT=m -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -# CONFIG_BT_MRVL is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=y -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_CFG80211_WEXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -CONFIG_LIB80211=m -CONFIG_LIB80211_CRYPT_WEP=m -CONFIG_LIB80211_CRYPT_CCMP=m -CONFIG_LIB80211_CRYPT_TKIP=m -# CONFIG_LIB80211_DEBUG is not set -CONFIG_MAC80211=y -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set -CONFIG_MAC80211_RC_DEFAULT="pid" -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -CONFIG_MTD_CONCAT=y -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -# CONFIG_MTD_NAND_GPIO is not set -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_PREFETCH=y -# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -CONFIG_MTD_UBI_GLUEBI=y - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_MG_DISK is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_EEPROM_93CX6=m -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=m -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CHR_DEV_SG=m -# CONFIG_CHR_DEV_SCH is not set -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_RAID6_PQ=m -# CONFIG_ASYNC_RAID6_TEST is not set -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -CONFIG_BLK_DEV_DM=m -# CONFIG_DM_DEBUG is not set -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_MIRROR=m -# CONFIG_DM_LOG_USERSPACE is not set -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_QL is not set -# CONFIG_DM_MULTIPATH_ST is not set -CONFIG_DM_DELAY=m -# CONFIG_DM_UEVENT is not set -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -CONFIG_TUN=m -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_TI_DAVINCI_EMAC is not set -# CONFIG_DM9000 is not set -CONFIG_ENC28J60=m -# CONFIG_ENC28J60_WRITEVERIFY is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_AT76C50X_USB is not set -CONFIG_USB_ZD1201=m -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_ATH_COMMON is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -# CONFIG_IWM is not set -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_USB=m -CONFIG_LIBERTAS_SDIO=m -# CONFIG_LIBERTAS_SPI is not set -CONFIG_LIBERTAS_DEBUG=y -CONFIG_P54_COMMON=m -CONFIG_P54_USB=m -# CONFIG_P54_SPI is not set -CONFIG_P54_LEDS=y -CONFIG_RT2X00=m -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -# CONFIG_RT2800USB is not set -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_DEBUG is not set -# CONFIG_WL12XX is not set -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_DM9601=m -# CONFIG_USB_NET_SMSC95XX is not set -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=m -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -CONFIG_PPP=m -# CONFIG_PPP_MULTILINK is not set -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -# CONFIG_PPPOL2TP is not set -# CONFIG_SLIP is not set -CONFIG_SLHC=m -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -CONFIG_INPUT_POLLDEV=m -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=m -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -CONFIG_I2C_OMAP=y -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -CONFIG_SPI_OMAP24XX=y -# CONFIG_SPI_XILINX is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -CONFIG_GPIO_TWL4030=y - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_GPIO_MC33880 is not set - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -CONFIG_POWER_SUPPLY=m -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_BQ27x00 is not set -# CONFIG_BATTERY_MAX17040 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_THERMAL is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_OMAP_WATCHDOG=y -# CONFIG_TWL4030_WATCHDOG is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -CONFIG_TWL4030_CORE=y -# CONFIG_TWL4030_POWER is not set -CONFIG_TWL4030_CODEC=y -CONFIG_TWL4030_MADC=y -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_MC13783 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_88PM8607 is not set -# CONFIG_AB4500_CORE is not set -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_TWL4030=y -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=y -CONFIG_VIDEOBUF_DMA_SG=y -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_VIDEO_TUNER=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -CONFIG_VIDEO_MSP3400=m -CONFIG_VIDEO_CS53L32A=m -CONFIG_VIDEO_WM8775=m -CONFIG_VIDEO_SAA711X=m -CONFIG_VIDEO_CX25840=m -CONFIG_VIDEO_CX2341X=m -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_AU0828 is not set -CONFIG_TI_MEDIA=y -CONFIG_VIDEO_VPSS_SYSTEM=m -# CONFIG_VIDEO_VPFE_CAPTURE is not set -CONFIG_VIDEO_OMAP2_VOUT=y -CONFIG_VIDEO_OMAP3=y -CONFIG_VIDEO_OMAP3_ISP=y -CONFIG_VIDEO_OMAP34XX_ISP_PREVIEWER=y -CONFIG_VIDEO_OMAP34XX_ISP_RESIZER=y -# CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -# CONFIG_USB_GL860 is not set -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -# CONFIG_USB_GSPCA_JEILINJ is not set -CONFIG_USB_GSPCA_MARS=m -# CONFIG_USB_GSPCA_MR97310A is not set -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_PAC207=m -# CONFIG_USB_GSPCA_PAC7302 is not set -CONFIG_USB_GSPCA_PAC7311=m -# CONFIG_USB_GSPCA_SN9C20X is not set -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -CONFIG_USB_GSPCA_STK014=m -# CONFIG_USB_GSPCA_STV0680 is not set -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -CONFIG_VIDEO_USBVISION=m -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -CONFIG_VIDEO_OVCAMCHIP=m -CONFIG_USB_W9968CF=m -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -# CONFIG_USB_ZC0301 is not set -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_USB_ZR364XX=m -# CONFIG_USB_STKWEBCAM is not set -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_I2C_SI4713 is not set -# CONFIG_RADIO_SI4713 is not set -# CONFIG_USB_DSBR is not set -# CONFIG_RADIO_SI470X is not set -# CONFIG_USB_MR800 is not set -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_TEF6862 is not set -CONFIG_DVB_MAX_ADAPTERS=8 -# CONFIG_DVB_DYNAMIC_MINORS is not set -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -# CONFIG_DVB_USB_DW2102 is not set -# CONFIG_DVB_USB_CINERGY_T2 is not set -# CONFIG_DVB_USB_ANYSEE is not set -# CONFIG_DVB_USB_DTV5100 is not set -# CONFIG_DVB_USB_AF9015 is not set -# CONFIG_DVB_USB_CE6230 is not set -# CONFIG_DVB_USB_FRIIO is not set -# CONFIG_DVB_USB_EC168 is not set -# CONFIG_SMS_SIANO_MDTV is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -# CONFIG_DVB_B2C2_FLEXCOP is not set - -# -# Supported DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_TDA826X=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -CONFIG_DVB_TDA10048=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_S5H1411=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_LNBP21=m -CONFIG_DVB_LGS8GL5=m -# CONFIG_DAB is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_OMAP2_VRAM=y -CONFIG_OMAP2_VRFB=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_VRAM_SIZE=0 -CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y -# CONFIG_OMAP2_DSS_RFBI is not set -CONFIG_OMAP2_DSS_VENC=y -CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO=y -# CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE is not set -# CONFIG_OMAP2_DSS_SDI is not set -# CONFIG_OMAP2_DSS_DSI is not set -# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_FB_OMAP2=y -CONFIG_FB_OMAP2_DEBUG_SUPPORT=y -# CONFIG_FB_OMAP2_FORCE_AUTO_UPDATE is not set -CONFIG_FB_OMAP2_NUM_FBS=3 - -# -# OMAP2/3 Display Device Drivers -# -CONFIG_PANEL_GENERIC=y -CONFIG_PANEL_LGPHILIPS_LB035Q02=y -CONFIG_PANEL_SAMSUNG_LTE430WQ_F0C=y -CONFIG_PANEL_SHARP_LS037V7DW01=y -# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -# CONFIG_LCD_PLATFORM is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=m -CONFIG_BACKLIGHT_GENERIC=m - -# -# Display device support -# -CONFIG_DISPLAY_SUPPORT=y - -# -# Display hardware drivers -# - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_SUN8x16 is not set -# CONFIG_FONT_SUN12x22 is not set -# CONFIG_FONT_10x18 is not set -# CONFIG_LOGO is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_JACK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_DEBUG=y -# CONFIG_SND_DEBUG_VERBOSE is not set -# CONFIG_SND_PCM_XRUN_DEBUG is not set -CONFIG_SND_RAWMIDI_SEQ=m -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_MCBSP=y -CONFIG_SND_OMAP_SOC_OVERO=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_TWL4030=y -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# Special HID drivers -# -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CHICONY=y -CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=y -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=y -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -# CONFIG_HID_NTRIG is not set -CONFIG_HID_PANTHERLORD=y -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_SOC=y - -# -# OMAP 343x high speed USB support -# -CONFIG_USB_MUSB_HOST=y -# CONFIG_USB_MUSB_PERIPHERAL is not set -# CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set -CONFIG_USB_MUSB_HDRC_HCD=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y -CONFIG_MUSB_USE_SYSTEM_DMA_RX=y -# CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_TI_CPPI41_DMA is not set -CONFIG_USB_MUSB_DEBUG=y - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_EZUSB=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_FUNSOFT=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MOTOROLA=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -# CONFIG_USB_SERIAL_QUALCOMM is not set -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_HP4X=m -CONFIG_USB_SERIAL_SAFE=m -# CONFIG_USB_SERIAL_SAFE_PADDED is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -# CONFIG_USB_SERIAL_SYMBOL is not set -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -# CONFIG_USB_BERRY_CHARGE is not set -CONFIG_USB_LED=m -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_SISUSBVGA_CON=y -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -CONFIG_USB_GADGET_OMAP=y -CONFIG_USB_OMAP=y -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_ETH_EEM is not set -# CONFIG_USB_GADGETFS is not set -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -# CONFIG_USB_MASS_STORAGE is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -# CONFIG_USB_G_MULTI is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_ISP1301_OMAP is not set -# CONFIG_USB_ULPI is not set -CONFIG_TWL4030_USB=y -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y - -# -# LED drivers -# -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_BD2802 is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_GPIO is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -CONFIG_RTC_DRV_TWL4030=y -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_PCF2123 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# CBUS support -# -# CONFIG_CBUS is not set - -# -# File systems -# -CONFIG_FS_JOURNAL_INFO=y -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m -# CONFIG_CUSE is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RTIME=y -CONFIG_JFFS2_RUBIN=y -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_XATTR is not set -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UBIFS_FS_DEBUG=y -CONFIG_UBIFS_FS_DEBUG_MSG_LVL=3 -# CONFIG_UBIFS_FS_DEBUG_CHKS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_ERRORS is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_OC_ETM is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=m -# CONFIG_CRYPTO_AUTHENC is not set -CONFIG_CRYPTO_TEST=m - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/recipes-kernel/linux/linux-omap-psp-2.6.32/porches.patch b/recipes-kernel/linux/linux-omap-psp-2.6.32/porches.patch deleted file mode 100644 index d631c6fe..00000000 --- a/recipes-kernel/linux/linux-omap-psp-2.6.32/porches.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 91dc9ee523ad7f2a09cabf8082396eca0ef68000 Mon Sep 17 00:00:00 2001 -From: Tasslehoff Kjappfot -Date: Wed, 8 Sep 2010 12:46:14 +0200 -Subject: [PATCH] OMAP: DSS2: OMAPFB: swap front and back porches for both hsync and vsync - -Framebuffer's left and right margins are relative to the active pixel -area. Front and back porches are relative to the sync area. - -Left margin was wrongly assigned to front porch (and right to back), -this patch fixes it. - -Signed-off-by: tasskjapp@gmail.com -Reviewed-by: Russ.Dill@gmail.com -Signed-off-by: Tomi Valkeinen ---- - drivers/video/omap2/omapfb/omapfb-main.c | 16 ++++++++-------- - 1 files changed, 8 insertions(+), 8 deletions(-) - -diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c -index 0fe87e0..4cb8355 100644 ---- a/drivers/video/omap2/omapfb/omapfb-main.c -+++ b/drivers/video/omap2/omapfb/omapfb-main.c -@@ -737,10 +737,10 @@ int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var) - var->pixclock = timings.pixel_clock != 0 ? - KHZ2PICOS(timings.pixel_clock) : - 0; -- var->left_margin = timings.hfp; -- var->right_margin = timings.hbp; -- var->upper_margin = timings.vfp; -- var->lower_margin = timings.vbp; -+ var->left_margin = timings.hbp; -+ var->right_margin = timings.hfp; -+ var->upper_margin = timings.vbp; -+ var->lower_margin = timings.vfp; - var->hsync_len = timings.hsw; - var->vsync_len = timings.vsw; - } else { -@@ -2019,10 +2019,10 @@ static int omapfb_mode_to_timings(const char *mode_str, - - if (r != 0) { - timings->pixel_clock = PICOS2KHZ(var.pixclock); -- timings->hfp = var.left_margin; -- timings->hbp = var.right_margin; -- timings->vfp = var.upper_margin; -- timings->vbp = var.lower_margin; -+ timings->hbp = var.left_margin; -+ timings->hfp = var.right_margin; -+ timings->vbp = var.upper_margin; -+ timings->vfp = var.lower_margin; - timings->hsw = var.hsync_len; - timings->vsw = var.vsync_len; - timings->x_res = var.xres; --- -1.6.6.1 - diff --git a/recipes-kernel/linux/linux-omap-psp_2.6.32.bb b/recipes-kernel/linux/linux-omap-psp_2.6.32.bb deleted file mode 100644 index 9f7c472c..00000000 --- a/recipes-kernel/linux/linux-omap-psp_2.6.32.bb +++ /dev/null @@ -1,213 +0,0 @@ -require multi-kernel.inc - -MULTI_CONFIG_BASE_SUFFIX = "" - -DESCRIPTION = "Linux kernel for OMAP processors" - -COMPATIBLE_MACHINE = "am3517-crane|beagleboard|omap3evm|am3517-evm|dm37x-evm|am37x-evm|omap3-touchbook|overo" - -# This is on the master branch -SRCREV = "5fc29e7b2a76a64a739f857858ef0b98294aa155" - -# The main PR is now using MACHINE_KERNEL_PR, for omap3 see conf/machine/include/omap3.inc -MACHINE_KERNEL_PR_append = "c+gitr${SRCREV}" - -SRC_URI += "git://arago-project.org/git/projects/linux-omap3.git;protocol=git;branch=master \ - file://0001-Revert-omap3-beagle-Fix-compile-time-errors.patch \ - file://0002-board-omap3touchbook-make-it-build-against-TI-linux-.patch \ - file://0003-ARM-OMAP-add-support-for-TCT-Zippy-to-Beagle-board-f.patch \ - file://0004-ARM-OMAP-Make-beagle-u-boot-partition-writable.patch \ - file://0005-board-omap3-beagle-add-DSS2-support.patch \ - file://0006-board-omap3beagle-prepare-for-DM3730-based-Beagleboa.patch \ - file://0007-ARM-OMAP-beagleboard-Add-infrastructure-to-do-fixups.patch \ - file://0008-ARM-OMAP-beagleboard-pre-export-GPIOs-to-userspace-w.patch \ - file://0009-ARM-OMAP-beagleboard-initialize-ds1307-and-eeprom-on.patch \ - file://0010-ARM-OMAP-update-beagleboard-defconfig.patch \ - file://0011-ASoC-enable-audio-capture-by-default-for-twl4030.patch \ - file://0012-MTD-NAND-omap2-proper-fix-for-subpage-read-ECC-error.patch \ - file://0013-OMAP3630-DSS2-Enable-Pre-Multiplied-Alpha-Support.patch \ - file://0014-DSS2-add-bootarg-for-selecting-svideo-or-composite-f.patch \ - file://0015-ISP-add-some-more-from-Leopard-imaging-patch.patch \ - file://0016-ARM-OMAP-Overo-Add-support-for-second-ethernet-port.patch \ - file://0017-drivers-net-smsc911x-return-ENODEV-if-device-is-not-.patch \ - file://0018-drivers-input-touchscreen-ads7846-return-ENODEV-if-d.patch \ - file://0019-drivers-mfd-add-twl4030-madc-driver.patch \ - file://0020-ARM-OMAP-Add-missing-twl4030-madc-header-file.patch \ - file://0021-ARM-OMAP-Add-twl4030-madc-support-to-Overo.patch \ - file://0022-ARM-OMAP-Add-twl4030-madc-support-to-Beagle.patch \ - file://0023-netdev-rt73usb-add-vendor-device-ID-for-Ceiva-Wirele.patch \ - file://0024-mmc-don-t-display-single-block-read-console-messages.patch \ - file://0025-ARM-OMAP2-mmc-twl4030-move-clock-input-selection-pri.patch \ - file://0026-board-overo-add-PM-code-and-sync-with-http-www.sakom.patch \ - file://0027-twl4030-madc-adjust-for-twl4030-twl-api-changes.patch \ - file://0028-OMAP-DSS2-Re-add-support-for-Samsung-lte430wq-f0c-pa.patch \ - file://0029-OMAP-DSS2-Add-support-for-LG-Philips-LB035Q02-panel.patch \ - file://0030-Fix-for-bus-width-which-improves-SD-card-s-peformanc.patch \ - file://0031-ARM-VFP-add-support-to-sync-the-VFP-state-of-the-cur.patch \ - file://0032-ARM-VFP-preserve-the-HW-context-when-calling-signal-.patch \ - file://0033-Switch-SGX-clocks-to-200MHz-on-DM37xx-OMAP36xx.patch \ - file://0034-modedb.c-add-proper-720p60-mode.patch \ - file://0035-RTC-add-support-for-backup-battery-recharge.patch \ - file://0036-ARM-Add-prompt-for-CONFIG_ALIGNMENT_TRAP.patch \ - file://0037-ARM-Print-warning-on-alignment-trap-in-kernel-mode.patch \ - file://0038-ARM-Expose-some-CPU-control-registers-via-sysfs.patch \ - file://0039-ARM-Add-option-to-allow-userspace-PLE-access.patch \ - file://0040-ARM-Add-option-to-allow-userspace-access-to-performa.patch \ - file://0041-ARM-Expose-some-PMON-registers-through-sysfs.patch \ - file://0042-musb-allow-host-io-without-gadget-module.patch \ - file://0043-MTD-silence-ecc-errors-on-mtdblock0.patch \ - file://0044-ARM-OMAP-beagle-every-known-beagle-except-revB-uses-.patch \ - file://0045-ARM-OMAP-beagle-add-support-for-beagleFPGA-expansion.patch \ - file://cam/0001-mt9t111-first-stab-at-merging-sensor-driver-based-on.patch \ - file://cam/0002-mt9t111-Fix-all-checkpatch-errors.patch \ - file://cam/0003-mt9t111-Pass-v4l2_int_device-data.patch \ - file://cam/0004-omap3beagle-Add-camera-support.patch \ - file://cam/0005-TEMP-omap3beagle-camera-Add-defconfig.patch \ - file://cam/0006-omap3beagle-camera-Add-support-for-regulators.patch \ - file://cam/0007-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch \ - file://cam/0008-omap3beagle-camera-Fix-null-pointer-dereference.patch \ - file://cam/0009-Revert-TEMP-omap3beagle-cam-Enable-OMAP_MUX.patch \ - file://cam/0010-omap3beagle-camera-Change-arch-late_initcall.patch \ - file://cam/0011-omap3beagle-camera-Move-i2c-registration-to-the-main.patch \ - file://cam/0012-ARM-OMAP3-make-camera-code-build-if-MT9T111-is-built.patch \ - file://cam/0013-DEBUG-omap3beagle-camera-Force-mode0-in-cam_xclka.patch \ - file://cam/0014-OMAP3-CLOCK-Add-capability-to-change-rate-of-dpll4_m.patch \ - file://cam/0015-Revert-DEBUG-omap3beagle-camera-Force-mode0-in-cam_x.patch \ - file://cam/0016-omap3beagle-camera-Fix-wrong-XCLKA-selection.patch \ - file://cam/0017-omap3isp-set-CAM_MCLK-to-172.8-MHz-allows-exact-9.6-.patch \ - file://cam/0018-Fix-Moved-MCLK-setting-to-the-board-file.patch \ - file://cam/0019-omap3isp-core-Do-smarter-MCLK-setting.patch \ - file://cam/0020-omap3beagle-camera-set-mclk-for-mt9t111.patch \ - file://cam/0021-mt9t111-Fix-max-supported-xclk.patch \ - file://cam/0022-omap3beagle-camera-Clarify-regulators-names.patch \ - file://cam/0023-omap3beagle-camera-Fix-powerup-sequence.patch \ - file://cam/0024-omap3beagle-camera-Change-vaux4-to-1.8v.patch \ - file://cam/0025-omap3beagle-camera-Rename-regulators-to-match-actual.patch \ - file://cam/0026-omap3beagle-camera-Complement-remainig-sensor-hw-con.patch \ - file://cam/0027-mt9t111-Fix-detect-function-retval-and-cleanup-print.patch \ - file://cam/0028-omap3beagle-camera-Set-padconf-settings-in-cam-init.patch \ - file://cam/0029-omap3beagle-camera-only-register-camera-driver-for-3.patch \ - file://cam/0030-WIP-mt9t111-Work-in-progress-for-camera-enablement.patch \ - file://cam/0031-BeagleXM-Cam-Add-support-for-MT9V113-VGA-Sensor.patch \ - file://cam/0032-MT9V113-Fixed-sensor-nitialization-issues.patch \ - file://cam/0033-mt9v113-Fix-wrong-active-widths.patch \ - file://cam/0034-omap3isp-Fix-Wrong-check-on-non-interlaced-sensor-on.patch \ - file://cam/0035-omap3isp-Fix-bad-YUV_BT-checks-in-datapath_config.patch \ - file://cam/0036-omap3isp-Set-vd_pol-to-0-by-default-on-all-cases.patch \ - file://cam/0037-omap3isp-ccdc-Set-datalines-to-10-for-YUV_SYNC.patch \ - file://cam/0038-omap3beagle-camera-Fix-parallel-i-f-settings.patch \ - file://cam/0039-omap3beagle-camera-Clean-up-Remove-unneccessary-code.patch \ - file://cam/0040-mt9v113-Clean-Up-Remove-unneccessary-code-printf.patch \ - file://cam/0041-MT9V113-Min-Max-clk-input-changed-as-per-the-spec.patch \ - file://cam/0042-omap3beagle-camera-Further-clode-cleanup.patch \ - file://cam/0043-mt9v113-Settings-from-Aptima-used-to-increase-FPS.patch \ - file://cam/0044-mt9v113-AE-param-tuned-to-get-28-30FPS.patch \ - file://cam/0045-omap3beagle-camera-Cleanup-of-boardfile.patch \ - file://cam/0046-omap3beagle-camera-Cleanup-regulator-usage.patch \ - file://cam/0047-omap3beagle-camera-Bring-back-mt9t111-support.patch \ - file://cam/0048-REMOVE-v4l2-Delete-MT9T111-sensor-driver.patch \ - file://cam/0049-V4L-DVB-13670-soc-camera-Add-mt9t112-camera-driver.patch \ - file://cam/0050-soc-camera-mt9t112-modify-exiting-conditions-from-st.patch \ - file://cam/0051-mt9t112-Migrate-from-soc_camera-to-v4l2-int-device.patch \ - file://cam/0052-mt9t112-Add-more-info-to-public-header.patch \ - file://cam/0053-mt9t112-Fix-null-pointer-kernel-bug.patch \ - file://cam/0054-DEBUG-omap3beagle-Add-MT9T112-to-defconfig.patch \ - file://cam/0055-omap3beagle-camera-Change-MT9T111-references-to-new-.patch \ - file://cam/0056-omap34xxcam-Fix-multi-pixel-format-negotiation.patch \ - file://cam/0057-SQUASH-omap3beagle-camera-Bring-back-mt9t111-support.patch \ - file://cam/0058-mt9t112-Do-init_camera-every-powerup.patch \ - file://cam/0059-omap3beagle-camera-Switch-flag-for-no-sensor-ISP.patch \ - file://cam/0060-mt9t112-Add-back-3MP-basesize.patch \ - file://cam/0061-mt9t112-Prepare-for-24MHz-EXTCLK-and-30-fps.patch \ - file://cam/0062-omap3beagle-camera-Prepare-24MHz-xclk-for-mt9t112.patch \ - file://cam/0063-mt9t112-Correct-register-settings-for-mt9t111-sensor.patch \ - file://cam/0064-mt9t112-Remove-smart-size-selection.patch \ - file://cam/0065-rtl8192su-remove-bogus-Kconfig-depend-on-PCI-and-add.patch \ - file://cam/0066-mt9t112-Add-Context-selection-to-configuration.patch \ - file://cam/0067-mt9t112-Disable-JPEG-in-Context-B.patch \ - file://cam/0068-mt9t112-Make-context-B-stream-unlimited-frames.patch \ - file://cam/0069-mt9t112-Fix-pll-p-dividers-abstraction.patch \ - file://cam/0070-mt9t112-Adjust-50-60Hz-flickering-settings.patch \ - file://cam/0071-mt9t112-Trigger-autofocus-at-the-end-of-context-swit.patch \ - file://cam/0072-omap3beagle-camera-Fix-dual-sensor-registration.patch \ - file://cam/0073-mt9v113-Fix-State-variable-handling.patch \ - file://cam/0074-Move-sensor-rest-to-after-applying-power.patch \ - file://cam/0075-omap3beagle-Add-camera-bootarg.patch \ - file://cam/5m03/0001-mt9p031-import-driver-from-https-github.com-Aptina-B.patch \ - file://0001-BeagleBoard-Adjust-USER-button-pin-for-xM.patch \ - file://0001-PSP-3.0.1.6-kernel-source-patched-with-OCF-Linux.patch \ - file://porches.patch \ - file://0001-cgroupfs-create-sys-fs-cgroup-to-mount-cgroupfs-on.patch \ - file://defconfig" - -SRC_URI_append_beagleboard = " file://logo_linux_clut224.ppm \ - file://beagleboard-xmc/0001-omap-Beagle-revision-detection.patch \ - file://beagleboard-xmc/0002-omap-Beagle-only-Cx-boards-use-pin-23-for-write-prot.patch \ - file://beagleboard-xmc/0003-omap-Beagle-no-gpio_wp-pin-connection-on-xM.patch \ - file://beagleboard-xmc/0004-omap3-beaglexm-fix-EHCI-power-up-GPIO-dir.patch \ - file://beagleboard-xmc/0005-omap3-beaglexm-fix-DVI-reset-GPIO.patch \ - file://beagleboard-xmc/0006-omap3-beaglexm-fix-power-on-of-DVI.patch \ - file://beagleboard-xmc/0007-beagleboard-hack-in-support-from-xM-rev-C.patch \ - file://beagleboard-xmc/0008-omap3-beagle-cleaned-up-board-revision-conditions.patch \ - file://cam/5m03/0002-board-omap3beagle-import-li5m03-driver-from-https-gi.patch \ -" - -SRC_URI_append_omap3-touchbook = " \ - file://0001-ARM-OMAP-add-spi-platform-devices.patch \ - file://0002-MMA7455L-accelerometer-driver.patch \ - file://0003-bq27x00_battery-remove-error-message-output.patch \ - file://0004-bq27x00_battery-add-charged-gpio.patch \ - file://0005-adf7846-add-more-debugging.patch \ - file://0006-ads7846-read-max-mix-x-y-from-pdata.patch \ - file://0007-ads7846-add-settling-delay-to-pdata.patch \ - file://0008-DSS2-OMAPFB-Translate-X-Y-coordinates-for-the-video-.patch \ - file://0009-DSS2-Fix-scaling-checks-when-rotation-is-90-or-270-d.patch \ - file://0010-add-touchbook-hid-driver.patch \ - file://0011-Make-backlight-controls-accessible-to-users.patch \ - file://0012-ads7846-don-t-error-out-when-there-s-no-pendown-gpio.patch \ - file://0013-ASoC-add-driver-for-omap3-touchbook.patch \ - file://0014-backlight-add-PWM-support.patch \ - file://0015-Forward-port-TWL4030-BCI-driver-from-2.6.29-to-2.6.3.patch \ - file://0016-ARM-OMAP-omap3-touchbook-update-boardfile.patch \ -" - -SRC_URI_append_am3517-crane = " \ - file://0001-Added-Crane-Board-support.patch \ - file://0001-OMAP3-craneboard-print-expansionboard-name-detected-.patch \ - file://0002-OMAP3-craneboard-add-support-for-TinCanTools-Trainer.patch \ -" - -addtask quiltfixup before do_patch after do_unpack -do_quiltfixup() { - rm ${S}/.pc -rf -} - -S = "${WORKDIR}/git" - -# Perf in 2.6.32 has broken perl handling, so disable it -do_compile_perf() { - : -} - -do_install_perf() { - : -} - -do_install_prepend() { - mkdir headerstash -p - cp include/linux/bounds.h headerstash/ - cp include/asm-arm/asm-offsets.h headerstash/ -} - -do_install_append() { - cp headerstash/bounds.h $kerneldir/include/linux/ - cp headerstash/asm-offsets.h $kerneldir/include/asm-arm/asm-offsets.h - rm -rf headerstash/ - - install -d ${D}/boot - install -m 0644 Documentation/arm/OMAP/DSS ${D}/boot/ -} - -PACKAGES =+ "omap-dss-doc" -FILES_omap-dss-doc = "/boot/DSS" -