diff --git a/recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch b/recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch new file mode 100644 index 00000000..4563a2ce --- /dev/null +++ b/recipes-bsp/u-boot/u-boot/2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch @@ -0,0 +1,30 @@ +From 7a3b3b04b1aed6a649d99396f914ec042968f924 Mon Sep 17 00:00:00 2001 +From: Chase Maupin +Date: Thu, 9 Feb 2012 13:09:27 -0600 +Subject: [PATCH] ddr_defs: change DDR timings for 15x15 EVM + +* For cold silicon the DDR timings need to be relaxed in order for + the device to boot with DDR at 266MHz +* Fix proposed by James Doublesin + +Signed-off-by: Chase Maupin +--- + arch/arm/include/asm/arch-ti81xx/ddr_defs.h | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/include/asm/arch-ti81xx/ddr_defs.h b/arch/arm/include/asm/arch-ti81xx/ddr_defs.h +index 6c4b422..0b7ffe7 100644 +--- a/arch/arm/include/asm/arch-ti81xx/ddr_defs.h ++++ b/arch/arm/include/asm/arch-ti81xx/ddr_defs.h +@@ -338,7 +338,7 @@ + #define DDR2_RD_DQS 0x40 + #define DDR2_PHY_FIFO_WE 0x56 + #else +-#define EMIF_READ_LATENCY 0x04 ++#define EMIF_READ_LATENCY 0x05 + #define EMIF_TIM1 0x0666B3D6 + #define EMIF_TIM2 0x143731DA + #define EMIF_TIM3 0x00000347 +-- +1.7.0.4 + diff --git a/recipes-bsp/u-boot/u-boot_2011.10rc.bb b/recipes-bsp/u-boot/u-boot_2011.10rc.bb index 74597f62..0102d15e 100644 --- a/recipes-bsp/u-boot/u-boot_2011.10rc.bb +++ b/recipes-bsp/u-boot/u-boot_2011.10rc.bb @@ -6,7 +6,7 @@ COMPATIBLE_MACHINE = "(ti33x)" DEFAULT_PREFERENCE_ti33x = "99" PV = "2011.09+git" -PR = "r25" +PR = "r26" # SPL build UBOOT_BINARY = "u-boot.img" @@ -23,6 +23,7 @@ SRC_URI = "git://arago-project.org/git/projects/u-boot-am33x.git;protocol=git;br file://2011.09git/0007-am335x_evm-switch-to-ext4.patch \ file://2011.09git/0008-HACK-am335x-evm-turn-d-cache-on-globally-turn-it-off.patch \ file://2011.09git/0009-am335x-evm-enable-i2c2-pinmux-for-beaglebone.patch \ + file://2011.09git/0001-ddr_defs-change-DDR-timings-for-15x15-EVM.patch \ " SRCREV = "f63b270e47f62f4d1a05b2001357e215966c6f5a"