LIC_FILES_CHECKSUM now calculates checksum on the copyright, skipping
the year which can change. The checksum contents itself have not changed
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Add the recipe for the video decoder driver.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Add the firmware packaging recipe for the video decoder
for J721E devices.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Restore max_leb_cnt so that the UBI/UBIFS fits into the board flash
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
* Update mdio register entries to use the full address
* For AM571x, remove the entries which are available after using DT overlay
Signed-off-by: Hongmei Gou <h-gou@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
* Add to the dependencies set in ti-pdk.bbclass so that we get tools
such as XDC.
* Set the edma3-lld path so the makefile can push it onto XDCPATH.
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Mahesh Radhakrishnan
Denys Dmytriyenko
Dan Murphy
Gowtham Tammana
Huang, David
Angela Stegmaier
Anand Balagopalakrishnan
Jacob Stiffler
Djordje Senicic
Gou, Hongmei
Jianzhong Xu
e-ruei1@ti.com