mirror of
https://git.yoctoproject.org/meta-ti
synced 2026-07-26 13:57:59 +00:00
Koen Kooi
257 lines
13 KiB
Diff
257 lines
13 KiB
Diff
From e96136d547a0de958c051e0ec6a0873f27a94537 Mon Sep 17 00:00:00 2001
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From: Benoit Cousson <b-cousson@ti.com>
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Date: Sat, 9 Jul 2011 19:15:04 -0600
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Subject: [PATCH 052/149] OMAP4: prcm: Fix errors in few defines name
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A couple of macros were wrongly changed during the _MOD to _INST
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rename done in the following commit:
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OMAP4: PRCM: rename _MOD macros to _INST
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cdb54c4457d68994da7c2e16907adfbfc130060d
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Fix them to their original name.
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Some CM and PRM instances were not well aligned. Align them.
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Remove one blank line in cm2_44xx.h to align the output with
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the other (cm1_44xx.h, prm44xx.h) files.
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Update header copyright date.
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Signed-off-by: Benoit Cousson <b-cousson@ti.com>
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Cc: Paul Walmsley <paul@pwsan.com>
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Cc: Rajendra Nayak <rnayak@ti.com>
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Signed-off-by: Paul Walmsley <paul@pwsan.com>
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---
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arch/arm/mach-omap2/cm1_44xx.h | 28 ++++++++++++++--------------
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arch/arm/mach-omap2/cm2_44xx.h | 23 +++++++++++------------
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arch/arm/mach-omap2/prm44xx.h | 22 +++++++++++-----------
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3 files changed, 36 insertions(+), 37 deletions(-)
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diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
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index e2d7a56..fc649f5 100644
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--- a/arch/arm/mach-omap2/cm1_44xx.h
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+++ b/arch/arm/mach-omap2/cm1_44xx.h
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@@ -1,7 +1,7 @@
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/*
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* OMAP44xx CM1 instance offset macros
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*
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- * Copyright (C) 2009-2010 Texas Instruments, Inc.
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+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley (paul@pwsan.com)
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@@ -41,9 +41,9 @@
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#define OMAP4430_CM1_INSTR_INST 0x0f00
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/* CM1 clockdomain register offsets (from instance start) */
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-#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
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-#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
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-#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
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+#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
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+#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
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+#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
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/* CM1 */
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@@ -82,8 +82,8 @@
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#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
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#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
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#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
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#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
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@@ -98,8 +98,8 @@
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#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
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#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
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#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
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#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
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@@ -116,8 +116,8 @@
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#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
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#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
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#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
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#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
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@@ -134,8 +134,8 @@
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#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
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#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
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#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
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#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
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@@ -154,8 +154,8 @@
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#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
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#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
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#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
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#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
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diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
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index aa47450..8036a16 100644
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--- a/arch/arm/mach-omap2/cm2_44xx.h
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+++ b/arch/arm/mach-omap2/cm2_44xx.h
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@@ -1,7 +1,7 @@
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/*
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* OMAP44xx CM2 instance offset macros
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*
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- * Copyright (C) 2009-2010 Texas Instruments, Inc.
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+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley (paul@pwsan.com)
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@@ -40,9 +40,9 @@
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#define OMAP4430_CM2_CAM_INST 0x1000
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#define OMAP4430_CM2_DSS_INST 0x1100
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#define OMAP4430_CM2_GFX_INST 0x1200
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-#define OMAP4430_CM2_L3INIT_INST 0x1300
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+#define OMAP4430_CM2_L3INIT_INST 0x1300
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#define OMAP4430_CM2_L4PER_INST 0x1400
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-#define OMAP4430_CM2_CEFUSE_INST 0x1600
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+#define OMAP4430_CM2_CEFUSE_INST 0x1600
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#define OMAP4430_CM2_RESTORE_INST 0x1e00
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#define OMAP4430_CM2_INSTR_INST 0x1f00
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@@ -65,7 +65,6 @@
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#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
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#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
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-
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/* CM2 */
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/* CM2.OCP_SOCKET_CM2 register offsets */
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@@ -121,8 +120,8 @@
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#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
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#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
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#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
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#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
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@@ -135,8 +134,8 @@
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#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
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#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
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#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
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#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
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@@ -151,8 +150,8 @@
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#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
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#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
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#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
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-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
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-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
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/* CM2.ALWAYS_ON_CM2 register offsets */
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#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
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@@ -227,8 +226,8 @@
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#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
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#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
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#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
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-#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528
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-#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
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+#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
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+#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
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#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
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#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
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#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
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diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
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index 67a0d3f..2aec8c8 100644
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--- a/arch/arm/mach-omap2/prm44xx.h
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+++ b/arch/arm/mach-omap2/prm44xx.h
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@@ -31,7 +31,7 @@
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#define OMAP4430_PRM_BASE 0x4a306000
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#define OMAP44XX_PRM_REGADDR(inst, reg) \
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- OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
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+ OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
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/* PRM instances */
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@@ -46,14 +46,14 @@
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#define OMAP4430_PRM_CAM_INST 0x1000
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#define OMAP4430_PRM_DSS_INST 0x1100
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#define OMAP4430_PRM_GFX_INST 0x1200
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-#define OMAP4430_PRM_L3INIT_INST 0x1300
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+#define OMAP4430_PRM_L3INIT_INST 0x1300
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#define OMAP4430_PRM_L4PER_INST 0x1400
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-#define OMAP4430_PRM_CEFUSE_INST 0x1600
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+#define OMAP4430_PRM_CEFUSE_INST 0x1600
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#define OMAP4430_PRM_WKUP_INST 0x1700
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#define OMAP4430_PRM_WKUP_CM_INST 0x1800
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#define OMAP4430_PRM_EMU_INST 0x1900
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-#define OMAP4430_PRM_EMU_CM_INST 0x1a00
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-#define OMAP4430_PRM_DEVICE_INST 0x1b00
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+#define OMAP4430_PRM_EMU_CM_INST 0x1a00
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+#define OMAP4430_PRM_DEVICE_INST 0x1b00
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#define OMAP4430_PRM_INSTR_INST 0x1f00
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/* PRM clockdomain register offsets (from instance start) */
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@@ -247,8 +247,8 @@
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#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
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#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
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#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
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-#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c
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-#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
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+#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
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+#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
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#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
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#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
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#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
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@@ -713,8 +713,8 @@
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#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
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#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
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#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
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-#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8
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-#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
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+#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
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+#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
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#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
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#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
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#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
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@@ -751,8 +751,8 @@
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#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
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#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
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#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
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-#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4
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-#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
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+#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
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+#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
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#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
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#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
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--
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1.7.2.5
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