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Koen Kooi
50 lines
1.4 KiB
Diff
50 lines
1.4 KiB
Diff
From dd1e35157bfd32303aaf87b1ec3f85d8dd1c0014 Mon Sep 17 00:00:00 2001
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From: Mans Rullgard <mans@mansr.com>
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Date: Tue, 10 Nov 2009 00:52:56 +0000
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Subject: [PATCH 40/45] ARM: Add option to allow userspace access to performance counters
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This adds an option to allow userspace access to the performance monitor
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registers of the Cortex-A8.
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Signed-off-by: Mans Rullgard <mans@mansr.com>
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---
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arch/arm/mm/Kconfig | 7 +++++++
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arch/arm/mm/proc-v7.S | 6 ++++++
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2 files changed, 13 insertions(+), 0 deletions(-)
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diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
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index 564ff7d..fda2e68 100644
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -793,3 +793,10 @@ config USER_L2_PLE
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help
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Enable userspace access to the L2 preload engine (PLE) available
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in Cortex-A series ARM processors.
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+
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+config USER_PMON
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+ bool "Enable userspace access to performance counters"
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+ depends on CPU_V7
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+ default n
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+ help
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+ Enable userpsace access to the performance monitor registers.
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diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
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index 3a28521..fec926a 100644
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--- a/arch/arm/mm/proc-v7.S
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+++ b/arch/arm/mm/proc-v7.S
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@@ -270,6 +270,12 @@ __v7_setup:
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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#endif
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+
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+#ifdef CONFIG_USER_PMON
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+ mov r0, #1
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+ mcr p15, 0, r0, c9, c14, 0
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+#endif
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+
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adr r5, v7_crval
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ldmia r5, {r5, r6}
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#ifdef CONFIG_CPU_ENDIAN_BE8
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--
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1.6.6.1
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