mirror of
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Koen Kooi
189ce92b4c
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
85 lines
2.8 KiB
Diff
85 lines
2.8 KiB
Diff
From 24791636a8052063d0f0ee3df30d8fce92e59398 Mon Sep 17 00:00:00 2001
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From: Joerg Roedel <joerg.roedel@amd.com>
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Date: Thu, 31 May 2012 17:38:11 +0200
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Subject: [PATCH 77/86] iommu/amd: Cache pdev pointer to root-bridge
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commit c1bf94ec1e12d76838ad485158aecf208ebd8fb9 upstream.
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At some point pci_get_bus_and_slot started to enable
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interrupts. Since this function is used in the
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amd_iommu_resume path it will enable interrupts on resume
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which causes a warning. The fix will use a cached pointer
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to the root-bridge to re-enable the IOMMU in case the BIOS
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is broken.
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Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
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---
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drivers/iommu/amd_iommu_init.c | 13 +++++--------
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drivers/iommu/amd_iommu_types.h | 3 +++
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2 files changed, 8 insertions(+), 8 deletions(-)
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diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
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index 20d5852..6269eb0 100644
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--- a/drivers/iommu/amd_iommu_init.c
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+++ b/drivers/iommu/amd_iommu_init.c
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@@ -943,6 +943,9 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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if (!iommu->dev)
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return 1;
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+ iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
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+ PCI_DEVFN(0, 0));
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+
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iommu->cap_ptr = h->cap_ptr;
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iommu->pci_seg = h->pci_seg;
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iommu->mmio_phys = h->mmio_phys;
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@@ -1225,20 +1228,16 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
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{
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int i, j;
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u32 ioc_feature_control;
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- struct pci_dev *pdev = NULL;
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+ struct pci_dev *pdev = iommu->root_pdev;
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/* RD890 BIOSes may not have completely reconfigured the iommu */
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- if (!is_rd890_iommu(iommu->dev))
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+ if (!is_rd890_iommu(iommu->dev) || !pdev)
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return;
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/*
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* First, we need to ensure that the iommu is enabled. This is
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* controlled by a register in the northbridge
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*/
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- pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
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-
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- if (!pdev)
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- return;
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/* Select Northbridge indirect register 0x75 and enable writing */
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pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
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@@ -1248,8 +1247,6 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
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if (!(ioc_feature_control & 0x1))
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pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
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- pci_dev_put(pdev);
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-
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/* Restore the iommu BAR */
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pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
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iommu->stored_addr_lo);
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diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
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index 5b9c507..40ab83b 100644
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--- a/drivers/iommu/amd_iommu_types.h
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+++ b/drivers/iommu/amd_iommu_types.h
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@@ -385,6 +385,9 @@ struct amd_iommu {
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/* Pointer to PCI device of this IOMMU */
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struct pci_dev *dev;
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+ /* Cache pdev to root device for resume quirks */
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+ struct pci_dev *root_pdev;
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+
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/* physical address of MMIO space */
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u64 mmio_phys;
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/* virtual address of MMIO space */
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--
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1.7.9.5
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