mirror of
https://git.yoctoproject.org/meta-ti
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Koen Kooi
89 lines
3.3 KiB
Diff
89 lines
3.3 KiB
Diff
From 3ef45618e396f3d9abb12fb4ef1c4462ccca6fd3 Mon Sep 17 00:00:00 2001
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From: Benoit Cousson <b-cousson@ti.com>
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Date: Sun, 10 Jul 2011 05:56:32 -0600
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Subject: [PATCH 086/149] OMAP4: cm: Add two new APIs for modulemode control
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In OMAP4, a new programming model based on module control instead
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of clock control was introduced.
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Expose two APIs to allow the upper layer (omap_hwmod) to control
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the module mode independently of the parent clocks management.
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Signed-off-by: Benoit Cousson <b-cousson@ti.com>
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Cc: Paul Walmsley <paul@pwsan.com>
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Cc: Rajendra Nayak <rnayak@ti.com>
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[paul@pwsan.com: renamed 'omap4_cm_' fns to 'omap4_cminst_'; cleaned up
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kerneldoc]
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Signed-off-by: Paul Walmsley <paul@pwsan.com>
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---
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arch/arm/mach-omap2/cminst44xx.c | 40 ++++++++++++++++++++++++++++++++++++++
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arch/arm/mach-omap2/cminst44xx.h | 5 ++++
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2 files changed, 45 insertions(+), 0 deletions(-)
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diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
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index 0fe3f14..eb2a472 100644
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--- a/arch/arm/mach-omap2/cminst44xx.c
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+++ b/arch/arm/mach-omap2/cminst44xx.c
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@@ -309,3 +309,43 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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+
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+/**
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+ * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
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+ * @mode: Module mode (SW or HW)
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+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
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+ * @inst: CM instance register offset (*_INST macro)
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+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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+ *
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+ * No return value.
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+ */
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+void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs)
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+{
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+ u32 v;
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+
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+ v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
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+ v &= ~OMAP4430_MODULEMODE_MASK;
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+ v |= mode << OMAP4430_MODULEMODE_SHIFT;
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+ omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
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+}
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+
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+/**
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+ * omap4_cminst_module_disable - Disable the module inside CLKCTRL
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+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
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+ * @inst: CM instance register offset (*_INST macro)
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+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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+ *
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+ * No return value.
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+ */
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+void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs)
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+{
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+ u32 v;
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+
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+ v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
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+ v &= ~OMAP4430_MODULEMODE_MASK;
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+ omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
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+}
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diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
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index a985400..f2ea645 100644
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--- a/arch/arm/mach-omap2/cminst44xx.h
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+++ b/arch/arm/mach-omap2/cminst44xx.h
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@@ -20,6 +20,11 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
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extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
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extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
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+extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs);
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+extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs);
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+
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/*
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* In an ideal world, we would not export these low-level functions,
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* but this will probably take some time to fix properly
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--
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1.7.2.5
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