mirror of
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Koen Kooi
8f1fc028be
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
211 lines
7.0 KiB
Diff
211 lines
7.0 KiB
Diff
From cf5db5477d8d43f02f4511f3835ab4bec0dcc27c Mon Sep 17 00:00:00 2001
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From: Richard Watts <rrw@kynesim.co.uk>
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Date: Mon, 20 Feb 2012 17:58:26 +0000
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Subject: [PATCH] Fix sprz319 erratum 2.1
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There is an erratum in DM3730 which results in the
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EHCI USB PLL (DPLL5) not updating sufficiently frequently; this
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leads to USB PHY clock drift and once the clock has drifted far
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enough, the PHY's ULPI interface stops responding and USB
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drops out. This is manifested on a Beagle xM by having the attached
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SMSC9514 report 'Cannot enable port 2. Maybe the USB cable is bad?'
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or similar.
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The fix is to carefully adjust your DPLL5 settings so as to
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keep the PHY clock as close as possible to 120MHz over the long
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term; TI SPRZ319e gives a table of such settings and this patch
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applies that table to systems with a 13MHz or a 26MHz clock,
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thus fixing the issue (inasfar as it can be fixed) on Beagle xM
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and Overo Firestorm.
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Signed-off-by: Richard Watts <rrw@kynesim.co.uk>
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---
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arch/arm/mach-omap2/clkt_clksel.c | 15 ++++++++
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arch/arm/mach-omap2/clock.h | 7 ++++
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arch/arm/mach-omap2/clock3xxx.c | 65 +++++++++++++++++++++++++++++----
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arch/arm/mach-omap2/clock3xxx.h | 1 +
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arch/arm/mach-omap2/clock3xxx_data.c | 2 +-
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arch/arm/mach-omap2/dpll3xxx.c | 2 +-
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6 files changed, 82 insertions(+), 10 deletions(-)
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diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
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index e25364d..e378fe7 100644
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--- a/arch/arm/mach-omap2/clkt_clksel.c
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+++ b/arch/arm/mach-omap2/clkt_clksel.c
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@@ -460,6 +460,21 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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return 0;
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}
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+int omap2_clksel_force_divisor(struct clk *clk, int new_div)
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+{
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+ u32 field_val;
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+
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+ field_val = _divisor_to_clksel(clk, new_div);
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+ if (field_val == ~0)
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+ return -EINVAL;
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+
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+ _write_clksel_reg(clk, field_val);
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+
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+ clk->rate = clk->parent->rate / new_div;
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+
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+ return 0;
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+}
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+
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/*
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* Clksel parent setting function - not passed in struct clk function
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* pointer - instead, the OMAP clock code currently assumes that any
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diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
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index 8bad1c6..ac3d367 100644
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--- a/arch/arm/mach-omap2/clock.h
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+++ b/arch/arm/mach-omap2/clock.h
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@@ -61,6 +61,12 @@ void omap3_dpll_allow_idle(struct clk *clk);
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void omap3_dpll_deny_idle(struct clk *clk);
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u32 omap3_dpll_autoidle_read(struct clk *clk);
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
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+#if CONFIG_ARCH_OMAP3
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+int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel);
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+/* If you are using this function and not on OMAP3, you are
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+ * Doing It Wrong(tm), so there is no stub.
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+ */
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+#endif
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int omap3_noncore_dpll_enable(struct clk *clk);
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void omap3_noncore_dpll_disable(struct clk *clk);
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int omap4_dpllmx_gatectrl_read(struct clk *clk);
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@@ -84,6 +90,7 @@ unsigned long omap2_clksel_recalc(struct clk *clk);
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long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
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+int omap2_clksel_force_divisor(struct clk *clk, int new_div);
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/* clkt_iclk.c public functions */
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extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
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diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
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index 952c3e0..d5be086 100644
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--- a/arch/arm/mach-omap2/clock3xxx.c
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+++ b/arch/arm/mach-omap2/clock3xxx.c
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@@ -40,6 +40,60 @@
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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+struct dpll_settings {
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+ int rate, m, n, f;
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+};
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+
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+
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+static int omap3_dpll5_apply_erratum21(struct clk *clk, struct clk *dpll5_m2)
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+{
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+ struct clk *sys_clk;
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+ int i, rv;
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+ static const struct dpll_settings precomputed[] = {
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+ /* From DM3730 errata (sprz319e), table 36
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+ * +1 is because the values in the table are register values;
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+ * dpll_program() will subtract one from what we give it,
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+ * so ...
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+ */
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+ { 13000000, 443+1, 5+1, 8 },
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+ { 26000000, 443+1, 11+1, 8 }
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+ };
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+
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+ sys_clk = clk_get(NULL, "sys_ck");
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+
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+ for (i = 0 ; i < (sizeof(precomputed)/sizeof(struct dpll_settings)) ;
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+ ++i) {
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+ const struct dpll_settings *d = &precomputed[i];
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+ if (sys_clk->rate == d->rate) {
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+ rv = omap3_noncore_dpll_program(clk, d->m , d->n, 0);
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+ if (rv)
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+ return 1;
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+ rv = omap2_clksel_force_divisor(dpll5_m2 , d->f);
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+ return 1;
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+ }
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+ }
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+ return 0;
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+}
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+
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+int omap3_dpll5_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ struct clk *dpll5_m2;
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+ int rv;
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+ dpll5_m2 = clk_get(NULL, "dpll5_m2_ck");
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+
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+ if (cpu_is_omap3630() && rate == DPLL5_FREQ_FOR_USBHOST &&
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+ omap3_dpll5_apply_erratum21(clk, dpll5_m2)) {
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+ return 1;
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+ }
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+ rv = omap3_noncore_dpll_set_rate(clk, rate);
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+ if (rv)
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+ goto out;
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+ rv = clk_set_rate(dpll5_m2, rate);
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+
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+out:
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+ return rv;
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+}
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+
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int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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{
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/*
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@@ -59,19 +113,14 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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void __init omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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- struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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- clk_enable(dpll5_clk);
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- /* Program dpll5_m2_clk divider for no division */
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- dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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- clk_enable(dpll5_m2_clk);
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- clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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+ /* dpll5_m2_ck is now (grottily!) handled by dpll5_clk's set routine,
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+ * to cope with an erratum on DM3730
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+ */
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- clk_disable(dpll5_m2_clk);
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- clk_disable(dpll5_clk);
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return;
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}
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diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
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index 8bbeeaf..0ede513 100644
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--- a/arch/arm/mach-omap2/clock3xxx.h
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+++ b/arch/arm/mach-omap2/clock3xxx.h
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@@ -10,6 +10,7 @@
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int omap3xxx_clk_init(void);
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int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
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+int omap3_dpll5_set_rate(struct clk *clk, unsigned long rate);
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int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
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void omap3_clk_lock_dpll5(void);
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diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
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index ffd55b1..dcd7bdc 100644
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--- a/arch/arm/mach-omap2/clock3xxx_data.c
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+++ b/arch/arm/mach-omap2/clock3xxx_data.c
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@@ -942,7 +942,7 @@ static struct clk dpll5_ck = {
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.parent = &sys_ck,
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.dpll_data = &dpll5_dd,
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.round_rate = &omap2_dpll_round_rate,
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- .set_rate = &omap3_noncore_dpll_set_rate,
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+ .set_rate = &omap3_dpll5_set_rate,
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.clkdm_name = "dpll5_clkdm",
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.recalc = &omap3_dpll_recalc,
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};
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diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
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index f77022b..1909cd0 100644
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--- a/arch/arm/mach-omap2/dpll3xxx.c
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+++ b/arch/arm/mach-omap2/dpll3xxx.c
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@@ -291,7 +291,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
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* Program the DPLL with the supplied M, N values, and wait for the DPLL to
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* lock.. Returns -EINVAL upon error, or 0 upon success.
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*/
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-static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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+int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
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{
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struct dpll_data *dd = clk->dpll_data;
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u8 dco, sd_div;
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--
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1.7.2.5
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