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Koen Kooi
2177f80076
Duplicate patches between PSP and 3.2.17 have been dropped from the 3.2.17 series Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
53 lines
2.1 KiB
Diff
53 lines
2.1 KiB
Diff
From c0d0663f26ba8ed987704a454a360b1a5997e1d7 Mon Sep 17 00:00:00 2001
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From: Archit Taneja <archit@ti.com>
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Date: Thu, 19 Apr 2012 17:39:16 +0530
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Subject: [PATCH 02/56] ARM: OMAP: Revert "ARM: OMAP: ctrl: Fix CONTROL_DSIPHY
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register fields"
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commit 08ca7444f589bedf9ad5d82883e5d0754852d73b upstream.
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This reverts commit 46f8c3c7e95c0d30d95911e7975ddc4f93b3e237.
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The commit above swapped the DSI1_PPID and DSI2_PPID register fields in
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CONTROL_DSIPHY to be in sync with the newer public OMAP TRMs(after version V).
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With this commit, contention errors were reported on DSI lanes some OMAP4 SDPs.
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After probing the DSI lanes on OMAP4 SDP, it was seen that setting bits in the
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DSI2_PPID field was pulling up voltage on DSI1 lanes, and DSI1_PPID field was
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pulling up voltage on DSI2 lanes.
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This proves that the current version of OMAP4 TRM is incorrect, swap the
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position of register fields according to the older TRM versions as they were
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correct.
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Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Signed-off-by: Archit Taneja <archit@ti.com>
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Signed-off-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
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---
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.../include/mach/ctrl_module_pad_core_44xx.h | 8 ++++----
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1 files changed, 4 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
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index 1e2d332..c88420d 100644
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--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
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+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
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@@ -941,10 +941,10 @@
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#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
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#define OMAP4_DSI1_LANEENABLE_SHIFT 24
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#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
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-#define OMAP4_DSI2_PIPD_SHIFT 19
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-#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
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-#define OMAP4_DSI1_PIPD_SHIFT 14
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-#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
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+#define OMAP4_DSI1_PIPD_SHIFT 19
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+#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
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+#define OMAP4_DSI2_PIPD_SHIFT 14
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+#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
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/* CONTROL_MCBSPLP */
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#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
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--
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1.7.7.6
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