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4e18d70247
This patchset is managed in https://github.com/beagleboard/kernel/tree/beagleboard-3.2 by Robert Nelson and myself. Tested on beagleboard-xM/Angstrom Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
57 lines
2.1 KiB
Diff
57 lines
2.1 KiB
Diff
From 65f1ea963900225224754f674e8907248262a46b Mon Sep 17 00:00:00 2001
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From: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Date: Fri, 16 Dec 2011 16:09:12 -0800
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Subject: [PATCH 4/6] ARM: OMAP4: clock: Add CPU local timer clock node
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Local timer clock is sourced from the CPU clock and hence changes
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along with CPU clock. These per CPU local timers are used as
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clock-events, so they need to be reconfigured on CPU frequency
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change as part of CPUfreq governor.
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Newly introduced clockevents_reconfigure() needs to know the
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twd clock-rate. Provide a clock-node to make clk_get_rate() work
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for TWD.
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Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Cc: Paul Walmsley <paul@pwsan.com>
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Cc: Kevin Hilman <khilman@ti.com>
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[paul@pwsan.com: renamed clock node to 'mpu_periphclk' to indicate that this
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is the Cortex-A9 MPCore subsystem clock PERIPHCLK (DDI 0407G); moved
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clock and clkdev entries to match the autogenerated script output]
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Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Signed-off-by: Tony Lindgren <tony@atomide.com>
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---
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arch/arm/mach-omap2/clock44xx_data.c | 9 +++++++++
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1 files changed, 9 insertions(+), 0 deletions(-)
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diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
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index 0798a80..730097e 100644
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--- a/arch/arm/mach-omap2/clock44xx_data.c
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+++ b/arch/arm/mach-omap2/clock44xx_data.c
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@@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = {
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{ .parent = NULL },
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};
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+static struct clk mpu_periphclk = {
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+ .name = "mpu_periphclk",
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+ .parent = &dpll_mpu_ck,
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+ .ops = &clkops_null,
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+ .fixed_div = 2,
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+ .recalc = &omap_fixed_divisor_recalc,
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+};
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+
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static struct clk ocp_abe_iclk = {
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.name = "ocp_abe_iclk",
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.parent = &aess_fclk,
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@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
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CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
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CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
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CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
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+ CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
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CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
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CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
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CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
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--
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1.7.7.4
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