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Koen Kooi
df83a59b6b
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Denys Dmytriyenko <denys@ti.com>
336 lines
10 KiB
Diff
336 lines
10 KiB
Diff
From 6b090d4fbcfaaa71f311f47019e622a794b0fca4 Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Mon, 30 Jul 2012 19:42:10 +0100
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Subject: [PATCH 50/70] ARM: Fix undefined instruction exception handling
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commit 15ac49b65024f55c4371a53214879a9c77c4fbf9 upstream.
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While trying to get a v3.5 kernel booted on the cubox, I noticed that
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VFP does not work correctly with VFP bounce handling. This is because
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of the confusion over 16-bit vs 32-bit instructions, and where PC is
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supposed to point to.
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The rule is that FP handlers are entered with regs->ARM_pc pointing at
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the _next_ instruction to be executed. However, if the exception is
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not handled, regs->ARM_pc points at the faulting instruction.
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This is easy for ARM mode, because we know that the next instruction and
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previous instructions are separated by four bytes. This is not true of
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Thumb2 though.
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Since all FP instructions are 32-bit in Thumb2, it makes things easy.
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We just need to select the appropriate adjustment. Do this by moving
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the adjustment out of do_undefinstr() into the assembly code, as only
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the assembly code knows whether it's dealing with a 32-bit or 16-bit
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instruction.
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Acked-by: Will Deacon <will.deacon@arm.com>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
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---
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arch/arm/kernel/entry-armv.S | 111 +++++++++++++++++++++++++++---------------
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arch/arm/kernel/traps.c | 8 ---
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arch/arm/vfp/entry.S | 16 +++---
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arch/arm/vfp/vfphw.S | 19 ++++---
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4 files changed, 92 insertions(+), 62 deletions(-)
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diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
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index 3a456c6..bc084a1 100644
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--- a/arch/arm/kernel/entry-armv.S
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+++ b/arch/arm/kernel/entry-armv.S
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@@ -241,6 +241,19 @@ svc_preempt:
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b 1b
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#endif
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+__und_fault:
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+ @ Correct the PC such that it is pointing at the instruction
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+ @ which caused the fault. If the faulting instruction was ARM
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+ @ the PC will be pointing at the next instruction, and have to
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+ @ subtract 4. Otherwise, it is Thumb, and the PC will be
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+ @ pointing at the second half of the Thumb instruction. We
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+ @ have to subtract 2.
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+ ldr r2, [r0, #S_PC]
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+ sub r2, r2, r1
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+ str r2, [r0, #S_PC]
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+ b do_undefinstr
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+ENDPROC(__und_fault)
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+
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.align 5
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__und_svc:
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#ifdef CONFIG_KPROBES
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@@ -258,25 +271,32 @@ __und_svc:
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@
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@ r0 - instruction
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@
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-#ifndef CONFIG_THUMB2_KERNEL
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+#ifndef CONFIG_THUMB2_KERNEL
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ldr r0, [r4, #-4]
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#else
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+ mov r1, #2
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ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
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cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
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- ldrhhs r9, [r4] @ bottom 16 bits
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- orrhs r0, r9, r0, lsl #16
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+ blo __und_svc_fault
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+ ldrh r9, [r4] @ bottom 16 bits
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+ add r4, r4, #2
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+ str r4, [sp, #S_PC]
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+ orr r0, r9, r0, lsl #16
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#endif
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- adr r9, BSYM(1f)
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+ adr r9, BSYM(__und_svc_finish)
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mov r2, r4
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bl call_fpe
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+ mov r1, #4 @ PC correction to apply
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+__und_svc_fault:
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mov r0, sp @ struct pt_regs *regs
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- bl do_undefinstr
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+ bl __und_fault
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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-1: disable_irq_notrace
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+__und_svc_finish:
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+ disable_irq_notrace
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@
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@ restore SPSR and restart the instruction
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@@ -420,25 +440,33 @@ __und_usr:
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mov r2, r4
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mov r3, r5
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+ @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
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+ @ faulting instruction depending on Thumb mode.
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+ @ r3 = regs->ARM_cpsr
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@
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- @ fall through to the emulation code, which returns using r9 if
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- @ it has emulated the instruction, or the more conventional lr
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- @ if we are to treat this as a real undefined instruction
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- @
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- @ r0 - instruction
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+ @ The emulation code returns using r9 if it has emulated the
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+ @ instruction, or the more conventional lr if we are to treat
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+ @ this as a real undefined instruction
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@
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adr r9, BSYM(ret_from_exception)
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- adr lr, BSYM(__und_usr_unknown)
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+
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tst r3, #PSR_T_BIT @ Thumb mode?
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- itet eq @ explicit IT needed for the 1f label
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- subeq r4, r2, #4 @ ARM instr at LR - 4
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- subne r4, r2, #2 @ Thumb instr at LR - 2
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-1: ldreqt r0, [r4]
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+ bne __und_usr_thumb
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+ sub r4, r2, #4 @ ARM instr at LR - 4
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+1: ldrt r0, [r4]
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#ifdef CONFIG_CPU_ENDIAN_BE8
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- reveq r0, r0 @ little endian instruction
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+ rev r0, r0 @ little endian instruction
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#endif
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- beq call_fpe
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+ @ r0 = 32-bit ARM instruction which caused the exception
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+ @ r2 = PC value for the following instruction (:= regs->ARM_pc)
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+ @ r4 = PC value for the faulting instruction
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+ @ lr = 32-bit undefined instruction function
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+ adr lr, BSYM(__und_usr_fault_32)
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+ b call_fpe
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+
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+__und_usr_thumb:
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@ Thumb instruction
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+ sub r4, r2, #2 @ First half of thumb instr at LR - 2
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#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
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/*
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* Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
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@@ -452,7 +480,7 @@ __und_usr:
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ldr r5, .LCcpu_architecture
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ldr r5, [r5]
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cmp r5, #CPU_ARCH_ARMv7
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- blo __und_usr_unknown
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+ blo __und_usr_fault_16 @ 16bit undefined instruction
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/*
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* The following code won't get run unless the running CPU really is v7, so
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* coding round the lack of ldrht on older arches is pointless. Temporarily
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@@ -460,15 +488,18 @@ __und_usr:
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*/
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.arch armv6t2
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#endif
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-2:
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- ARM( ldrht r5, [r4], #2 )
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- THUMB( ldrht r5, [r4] )
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- THUMB( add r4, r4, #2 )
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+2: ldrht r5, [r4]
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cmp r5, #0xe800 @ 32bit instruction if xx != 0
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- blo __und_usr_unknown
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-3: ldrht r0, [r4]
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+ blo __und_usr_fault_16 @ 16bit undefined instruction
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+3: ldrht r0, [r2]
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add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
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+ str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
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orr r0, r0, r5, lsl #16
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+ adr lr, BSYM(__und_usr_fault_32)
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+ @ r0 = the two 16-bit Thumb instructions which caused the exception
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+ @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
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+ @ r4 = PC value for the first 16-bit Thumb instruction
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+ @ lr = 32bit undefined instruction function
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#if __LINUX_ARM_ARCH__ < 7
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/* If the target arch was overridden, change it back: */
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@@ -479,17 +510,13 @@ __und_usr:
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#endif
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#endif /* __LINUX_ARM_ARCH__ < 7 */
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#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
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- b __und_usr_unknown
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+ b __und_usr_fault_16
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#endif
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- UNWIND(.fnend )
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+ UNWIND(.fnend)
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ENDPROC(__und_usr)
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- @
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- @ fallthrough to call_fpe
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- @
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-
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/*
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- * The out of line fixup for the ldrt above.
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+ * The out of line fixup for the ldrt instructions above.
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*/
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.pushsection .fixup, "ax"
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4: mov pc, r9
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@@ -520,11 +547,12 @@ ENDPROC(__und_usr)
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* NEON handler code.
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*
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* Emulators may wish to make use of the following registers:
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- * r0 = instruction opcode.
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- * r2 = PC+4
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+ * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
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+ * r2 = PC value to resume execution after successful emulation
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* r9 = normal "successful" return address
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- * r10 = this threads thread_info structure.
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+ * r10 = this threads thread_info structure
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* lr = unrecognised instruction return address
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+ * IRQs disabled, FIQs enabled.
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*/
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@
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@ Fall-through from Thumb-2 __und_usr
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@@ -659,12 +687,17 @@ ENTRY(no_fp)
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mov pc, lr
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ENDPROC(no_fp)
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-__und_usr_unknown:
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- enable_irq
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+__und_usr_fault_32:
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+ mov r1, #4
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+ b 1f
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+__und_usr_fault_16:
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+ mov r1, #2
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+1: enable_irq
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mov r0, sp
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adr lr, BSYM(ret_from_exception)
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- b do_undefinstr
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-ENDPROC(__und_usr_unknown)
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+ b __und_fault
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+ENDPROC(__und_usr_fault_32)
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+ENDPROC(__und_usr_fault_16)
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.align 5
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__pabt_usr:
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diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
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index 160cb16..8380bd1 100644
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--- a/arch/arm/kernel/traps.c
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+++ b/arch/arm/kernel/traps.c
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@@ -362,18 +362,10 @@ static int call_undef_hook(struct pt_regs *regs, unsigned int instr)
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asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
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{
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- unsigned int correction = thumb_mode(regs) ? 2 : 4;
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unsigned int instr;
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siginfo_t info;
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void __user *pc;
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- /*
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- * According to the ARM ARM, PC is 2 or 4 bytes ahead,
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- * depending whether we're in Thumb mode or not.
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- * Correct this offset.
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- */
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- regs->ARM_pc -= correction;
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-
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pc = (void __user *)instruction_pointer(regs);
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if (processor_mode(regs) == SVC_MODE) {
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diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
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index 4fa9903..cc926c9 100644
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--- a/arch/arm/vfp/entry.S
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+++ b/arch/arm/vfp/entry.S
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@@ -7,18 +7,20 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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- *
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- * Basic entry code, called from the kernel's undefined instruction trap.
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- * r0 = faulted instruction
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- * r5 = faulted PC+4
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- * r9 = successful return
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- * r10 = thread_info structure
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- * lr = failure return
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*/
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#include <asm/thread_info.h>
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#include <asm/vfpmacros.h>
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#include "../kernel/entry-header.S"
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+@ VFP entry point.
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+@
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+@ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
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+@ r2 = PC value to resume execution after successful emulation
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+@ r9 = normal "successful" return address
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+@ r10 = this threads thread_info structure
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+@ lr = unrecognised instruction return address
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+@ IRQs disabled.
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+@
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ENTRY(do_vfp)
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#ifdef CONFIG_PREEMPT
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
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index 2d30c7f..3a0efaa 100644
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--- a/arch/arm/vfp/vfphw.S
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+++ b/arch/arm/vfp/vfphw.S
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@@ -61,13 +61,13 @@
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@ VFP hardware support entry point.
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@
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-@ r0 = faulted instruction
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-@ r2 = faulted PC+4
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-@ r9 = successful return
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+@ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
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+@ r2 = PC value to resume execution after successful emulation
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+@ r9 = normal "successful" return address
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@ r10 = vfp_state union
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@ r11 = CPU number
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-@ lr = failure return
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-
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+@ lr = unrecognised instruction return address
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+@ IRQs enabled.
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ENTRY(vfp_support_entry)
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DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
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@@ -161,9 +161,12 @@ vfp_hw_state_valid:
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@ exception before retrying branch
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@ out before setting an FPEXC that
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@ stops us reading stuff
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- VFPFMXR FPEXC, r1 @ restore FPEXC last
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- sub r2, r2, #4
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- str r2, [sp, #S_PC] @ retry the instruction
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+ VFPFMXR FPEXC, r1 @ Restore FPEXC last
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+ sub r2, r2, #4 @ Retry current instruction - if Thumb
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+ str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
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+ @ else it's one 32-bit instruction, so
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+ @ always subtract 4 from the following
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+ @ instruction address.
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#ifdef CONFIG_PREEMPT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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--
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1.7.7.6
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