Major layout change to the packages directory

Having one monolithic packages directory makes it hard to find things and is generally overwhelming. This commit splits it into several logical sections roughly based on function, recipes.txt gives more information about the classifications used. The opportunity is also used to switch from "packages" to "recipes" as used in OpenEmbedded as the term "packages" can be confusing to people and has many different meanings. Not all recipes have been classified yet, this is just a first pass at separating things out. Some packages are moved to meta-extras as they're no longer actively used or maintained. Signed-off-by: Richard Purdie <rpurdie@linux.intel.com>
2026-07-15 15:37:03 +00:00 · 2010-08-27 15:14:24 +01:00
parent da49de6885
commit 29d6678fd5
2534 changed files with 19 additions and 206 deletions
@@ -0,0 +1,16 @@
+---
+ arch/arm/kernel/vmlinux.lds.S |    1 +
+ 1 file changed, 1 insertion(+)
+
+Index: linux-2.6.22/arch/arm/kernel/vmlinux.lds.S
+===================================================================
+--- linux-2.6.22.orig/arch/arm/kernel/vmlinux.lds.S	2007-09-11 18:32:29.000000000 +0200
+++ linux-2.6.22/arch/arm/kernel/vmlinux.lds.S	2007-09-11 18:33:42.000000000 +0200
+@@ -94,6 +94,7 @@
+ 			TEXT_TEXT
+ 			SCHED_TEXT
+ 			LOCK_TEXT
+			*(.note.*)
+ #ifdef CONFIG_MMU
+ 			*(.fixup)
+ #endif
@@ -0,0 +1,25 @@
+From e566813cedb9f91724597df45c11075023a7b589 Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 18:58:27 -0400
+Subject: [PATCH] cm-x270-match-type
+
+---
+ arch/arm/boot/compressed/head-xscale.S |    5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
+index 73c5d9e..dc89459 100644
+--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
+@@ -53,3 +53,8 @@ __XScale_start:
+ 		str	r1, [r0, #0x18]
+ #endif
+ 
+#if defined(CONFIG_MACH_ARMCORE)
+		mov r7, #(MACH_TYPE_ARMCORE & 0xFF00)
+		add r7, r7, #(MACH_TYPE_ARMCORE & 0xFF)
+#endif
+
+-- 
+1.5.1.6
+
@@ -0,0 +1,186 @@
+From f260d5fa4c99cd7df949e6408af59807f8ccf224 Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 18:59:39 -0400
+Subject: [PATCH] cm-x270-ide
+
+---
+ drivers/ide/Kconfig           |    8 +++
+ drivers/ide/arm/Makefile      |    1 +
+ drivers/ide/arm/cm-x270-ide.c |  135 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 144 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/ide/arm/cm-x270-ide.c
+
+diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
+index b1a9b81..7de4155 100644
+--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
+@@ -864,6 +864,14 @@ config BLK_DEV_IDE_BAST
+ 	  Say Y here if you want to support the onboard IDE channels on the
+ 	  Simtec BAST or the Thorcom VR1000
+ 
+config BLK_DEV_IDE_CM_X270
+	tristate "CompuLab CM-X270 IDE support"
+	depends on ARM && (MACH_ARMCORE)
+	help
+	  Say Y here if you want to support the onboard IDE channels on the
+	  CompuLab CM-X270 module
+
+
+ config BLK_DEV_GAYLE
+ 	bool "Amiga Gayle IDE interface support"
+ 	depends on AMIGA
+diff --git a/drivers/ide/arm/Makefile b/drivers/ide/arm/Makefile
+index 6a78f07..e5cadb7 100644
+--- a/drivers/ide/arm/Makefile
+++ b/drivers/ide/arm/Makefile
+@@ -2,5 +2,6 @@
+ obj-$(CONFIG_BLK_DEV_IDE_ICSIDE)	+= icside.o
+ obj-$(CONFIG_BLK_DEV_IDE_RAPIDE)	+= rapide.o
+ obj-$(CONFIG_BLK_DEV_IDE_BAST)		+= bast-ide.o
+obj-$(CONFIG_BLK_DEV_IDE_CM_X270)	+= cm-x270-ide.o
+ 
+ EXTRA_CFLAGS	:= -Idrivers/ide
+diff --git a/drivers/ide/arm/cm-x270-ide.c b/drivers/ide/arm/cm-x270-ide.c
+new file mode 100644
+index 0000000..a8b15aa
+--- /dev/null
+++ b/drivers/ide/arm/cm-x270-ide.c
+@@ -0,0 +1,135 @@
+/* linux/drivers/ide/arm/cm-x270-ide.c
+ *
+ * Copyright (c) 2006 CompuLab, Ltd
+ *  Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on linux/drivers/ide/arm/bast-ide.c
+ * Copyright (c) 2003-2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/ide.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/io.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/cm-x270.h>
+
+#define CMX270_SB270_IDECS0_VIRT (CMX270_IDE104_VIRT + (1<<24) + (1<<25))
+#define CMX270_SB270_IDECS1_VIRT (CMX270_IDE104_VIRT + (1<<25))
+#define CMX270_ATX_IDECS0_VIRT (CMX270_IDE104_VIRT + (1<<25))
+#define CMX270_ATX_IDECS1_VIRT (CMX270_IDE104_VIRT + (1<<25) + (1<<22))
+
+/* list of registered interfaces */
+static ide_hwif_t *ifs[1];
+
+static int __init
+cmx270_ide_register(unsigned int base, unsigned int aux, int irq,
+		 ide_hwif_t **hwif)
+{
+	hw_regs_t hw;
+
+	memset(&hw, 0, sizeof(hw));
+
+	if(!base || !aux) return -EINVAL;
+
+	printk(KERN_DEBUG "%s: base = %08x, aux = %08x\n", __FUNCTION__,
+	       base, aux);
+
+        /* Different mappings for local bus IDE and PCMCIA IDE */
+	if(base == CMX270_SB270_IDECS0_VIRT) {
+		hw.io_ports[IDE_DATA_OFFSET] = base + 0;
+		hw.io_ports[IDE_ERROR_OFFSET] = base + (0x1<<3);
+		hw.io_ports[IDE_NSECTOR_OFFSET]= base + (0x2<<3);
+		hw.io_ports[IDE_SECTOR_OFFSET]= base + (0x3<<3);
+		hw.io_ports[IDE_LCYL_OFFSET]= base + (0x4<<3);
+		hw.io_ports[IDE_HCYL_OFFSET]= base + (0x5<<3);
+		hw.io_ports[IDE_SELECT_OFFSET]=	base + (0x6<<3);
+		hw.io_ports[IDE_STATUS_OFFSET]=	base + (0x7<<3);
+		hw.io_ports[IDE_CONTROL_OFFSET] = aux+(0x6<<3);
+	}
+	else if (base == CMX270_ATX_IDECS0_VIRT) { /* atx base */
+		hw.io_ports[IDE_DATA_OFFSET] = base + 0;
+		hw.io_ports[IDE_ERROR_OFFSET] =	base + 8;
+		hw.io_ports[IDE_NSECTOR_OFFSET]= base + 2;
+		hw.io_ports[IDE_SECTOR_OFFSET]= base + 10;
+		hw.io_ports[IDE_LCYL_OFFSET]= base + 4;
+		hw.io_ports[IDE_HCYL_OFFSET]= base + 12;
+		hw.io_ports[IDE_SELECT_OFFSET]= base + 6; //6;
+		hw.io_ports[IDE_STATUS_OFFSET]= base + 14;
+		hw.io_ports[IDE_CONTROL_OFFSET] = (aux+0x6);
+	} else {
+		printk(KERN_DEBUG "%s: registering wrong IDE i/f\n", __FUNCTION__);
+		hw.io_ports[IDE_DATA_OFFSET] = base + 8;
+		hw.io_ports[IDE_ERROR_OFFSET] = base + 13;
+		hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
+		hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
+		hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
+		hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
+		hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
+		hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
+		hw.io_ports[IDE_CONTROL_OFFSET] = aux;
+	}
+	
+	hw.irq = irq;
+
+	return ide_register_hw(&hw, hwif);
+}
+
+static int __init cmx270_ide_init(void)
+{
+	int retval = 0;
+
+	if (!(machine_is_armcore()))
+		goto out;
+
+	printk("CM-X270: initializing IDE interface\n");
+
+	MSC1 = 0x7ffc7ff4;
+
+	/* Interrupts on rising edge: lines are inverted before they get to
+           the PXA */
+	pxa_gpio_mode(IRQ_TO_GPIO(CMX270_IDE_IRQ));
+
+	/* try SB-X270 */
+	set_irq_type(CMX270_IDE_IRQ, IRQ_TYPE_EDGE_RISING);
+	retval = cmx270_ide_register(CMX270_SB270_IDECS0_VIRT,
+				 CMX270_SB270_IDECS1_VIRT,
+				 CMX270_IDE_IRQ, &ifs[0]);
+	if (retval >= 0) {
+		printk(KERN_DEBUG "%s: found IDE interface on SB-X270\n",
+		       __FUNCTION__);
+		goto out;
+	}
+
+	/* SB-X270 detection failed, try ATX */
+	set_irq_type(CMX270_IDE_IRQ, IRQ_TYPE_EDGE_FALLING);
+	retval = cmx270_ide_register(CMX270_ATX_IDECS0_VIRT,
+				 CMX270_ATX_IDECS1_VIRT,
+				 CMX270_IDE_IRQ, &ifs[0]);
+
+	if ( retval >= 0 ) {
+		printk(KERN_DEBUG "%s: found IDE interface on ATX\n",
+		       __FUNCTION__);
+		goto out;
+	}
+
+  out:
+	return retval;
+}
+
+module_init(cmx270_ide_init);
+
+MODULE_AUTHOR("CompuLab");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CompuLab CM-X270 IDE driver");
+-- 
+1.5.1.6
+
@@ -0,0 +1,496 @@
+From 1306abec905df1ff5cf2b1d91ac0d94d18d96c5b Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 19:00:07 -0400
+Subject: [PATCH] cm-x270-it8152
+
+---
+ arch/arm/common/Makefile          |    1 +
+ arch/arm/common/it8152.c          |  272 +++++++++++++++++++++++++++++++++++++
+ arch/arm/kernel/bios32.c          |   28 ++++-
+ include/asm-arm/hardware/it8152.h |  104 ++++++++++++++
+ include/asm-arm/pci.h             |    7 +
+ include/linux/pci_ids.h           |    1 +
+ 6 files changed, 410 insertions(+), 3 deletions(-)
+ create mode 100644 arch/arm/common/it8152.c
+ create mode 100644 include/asm-arm/hardware/it8152.h
+
+diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
+index e1289a2..3d0b9fa 100644
+--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
+@@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM)	+= sharpsl_pm.o
+ obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o
+ obj-$(CONFIG_ARCH_IXP2000)	+= uengine.o
+ obj-$(CONFIG_ARCH_IXP23XX)	+= uengine.o
+obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
+diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
+new file mode 100644
+index 0000000..8563610
+--- /dev/null
+++ b/arch/arm/common/it8152.c
+@@ -0,0 +1,272 @@
+/*
+ * arch/arm/common/it8152.c: PCI functions for IT8152
+ *
+ * Compulab Ltd, 2002-2006
+ *
+ * The DMA bouncing is taken from arch/arm/mach-ixp4xx/common-pci.c
+ * (see this file for respective copyrights)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ptrace.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <asm/mach/map.h>
+
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/mach/pci.h>
+#include <asm/hardware/it8152.h>
+
+#define MAX_SLOTS		21
+
+static unsigned long
+it8152_pci_dev_base_address(struct pci_bus *bus, unsigned int devfn)
+{
+	unsigned long addr = 0;
+
+	if (bus->number == 0) {
+			if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
+				addr = (devfn << 8);
+	} else
+		addr = (bus->number << 16) | (devfn << 8);
+
+	return addr;
+}
+
+static int
+it8152_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+		    int size, u32 *value)
+{
+	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
+	u32 v;
+	int shift;
+
+#ifdef CONFIG_MACH_ARMCORE
+	if(devfn!=0) IT8152_GPIO_GPLR=0x00;
+#endif	
+	shift = (where & 3);
+
+	IT8152_PCI_CFG_ADDR = (addr + where);
+	v = (IT8152_PCI_CFG_DATA  >> (8 * (shift)));	
+
+	*value = v;
+
+#ifdef CONFIG_MACH_ARMCORE
+	if(devfn!=0) IT8152_GPIO_GPLR=0x20;
+#endif	
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int
+it8152_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+		     int size, u32 value)
+{
+	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
+	u32 v, vtemp, mask=0;
+	int shift;
+
+#ifdef CONFIG_MACH_ARMCORE
+	if(devfn!=0) IT8152_GPIO_GPLR=0x00;
+#endif
+
+	if(size==1) mask=0xff;
+	if(size==2) mask=0xffff;
+
+	shift = (where & 3);
+
+	IT8152_PCI_CFG_ADDR = addr + where;
+	vtemp = IT8152_PCI_CFG_DATA;
+
+	if(mask) vtemp &= ~(mask << (8 * shift));
+	else vtemp = 0;
+
+	v = (value << (8 * shift));
+	IT8152_PCI_CFG_ADDR = addr + where;
+	IT8152_PCI_CFG_DATA  = (v | vtemp);
+
+#ifdef CONFIG_MACH_ARMCORE
+	if(devfn!=0) IT8152_GPIO_GPLR=0x20;
+#endif
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops it8152_ops = {
+	.read = it8152_pci_read_config,
+	.write = it8152_pci_write_config,
+};
+
+static struct resource it8152_io = {
+	.name	= "IT8152 PCI I/O region",
+	.flags	= IORESOURCE_IO,
+};
+
+static struct resource it8152_mem1 = {
+	.name	= "First IT8152 PCI memory region",
+	.start	= 0x10000000,
+	.end	= 0x13e00000,
+	.flags	= IORESOURCE_MEM,
+};
+
+/*
+ * The following functions are needed for DMA bouncing.
+ * ITE8152 chip can addrees up to 64MByte, so all the devices
+ * connected to ITE8152 (PCI and USB) should have limited DMA window
+ */
+
+/*
+ * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
+ * other devices.
+ */
+static int it8152_pci_platform_notify(struct device *dev)
+{
+	if ( dev->bus == &pci_bus_type ) {
+		if ( dev->dma_mask )
+			*dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
+		dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
+		dmabounce_register_dev(dev, 2048, 4096);
+	}
+	return 0;
+}
+
+static int it8152_pci_platform_notify_remove(struct device *dev)
+{
+	if ( dev->bus == &pci_bus_type ) {
+		dmabounce_unregister_dev(dev);
+	}
+	return 0;
+}
+
+int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+{
+	dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
+		__FUNCTION__, dma_addr, size);
+	return (dev->bus == &pci_bus_type ) && 
+		((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
+}
+
+/*
+ * Only first 64MB of memory can be accessed via PCI.
+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
+ * This is really ugly and we need a better way of specifying
+ * DMA-capable regions of memory.
+ */
+void __init it8152_adjust_zones(int node, unsigned long *zone_size,
+	unsigned long *zhole_size)
+{
+	unsigned int sz = SZ_64M >> PAGE_SHIFT;
+
+	/*
+	 * Only adjust if > 64M on current system
+	 */
+	if (node || (zone_size[0] <= sz))
+		return;
+
+	zone_size[1] = zone_size[0] - sz;
+	zone_size[0] = sz;
+	zhole_size[1] = zhole_size[0];
+	zhole_size[0] = 0;
+}
+
+/*
+ * We override these so we properly do dmabounce otherwise drivers
+ * are able to set the dma_mask to 0xffffffff and we can no longer
+ * trap bounces. :(
+ *
+ * We just return true on everyhing except for < 64MB in which case 
+ * we will fail miseralby and die since we can't handle that case.
+ */
+int
+pci_set_dma_mask(struct pci_dev *dev, u64 mask)
+{
+	printk(KERN_INFO "===> %s: %s %x\n", __FUNCTION__, dev->dev.bus_id, mask);
+	if (mask >= PHYS_OFFSET + SZ_64M - 1 )
+		return 0;
+
+	return -EIO;
+}
+    
+int
+pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
+{
+	printk(KERN_INFO "===> %s: %s %x\n", __FUNCTION__, dev->dev.bus_id, mask);
+	if (mask >= PHYS_OFFSET + SZ_64M - 1 )
+		return 0;
+
+	return -EIO;
+}
+
+EXPORT_SYMBOL(pci_set_dma_mask);
+EXPORT_SYMBOL(pci_set_consistent_dma_mask);
+
+
+int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
+{
+	it8152_io.start = IT8152_IO_BASE + 0x12000;
+ 	it8152_io.end	= IT8152_IO_BASE + 0x100000;
+
+	if (request_resource(&ioport_resource, &it8152_io)) {
+		printk(KERN_ERR "PCI: unable to allocate IO region\n");
+		return -EBUSY;
+	}
+	if (request_resource(&iomem_resource, &it8152_mem1)) {
+		printk(KERN_ERR "PCI: unable to allocate memory region\n");
+		return -EBUSY;
+	}
+
+	sys->resource[0] = &it8152_io;
+	sys->resource[1] = &it8152_mem1;
+
+	if (platform_notify || platform_notify_remove) {
+		printk(KERN_ERR "PCI: Can't use platform_notify\n");
+		return -EBUSY;
+	}
+
+	platform_notify = it8152_pci_platform_notify;
+	platform_notify_remove = it8152_pci_platform_notify_remove;
+
+	return 1;  
+}
+			  
+/*
+ * If we set up a device for bus mastering, we need to check the latency
+ * timer as we don't have even crappy BIOSes to set it properly.
+ * The implementation is from arch/i386/pci/i386.c
+ */
+unsigned int pcibios_max_latency = 255;
+
+void pcibios_set_master(struct pci_dev *dev)
+{
+	u8 lat;
+
+	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
+	if (lat < 16)
+		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
+	else if (lat > pcibios_max_latency)
+		lat = pcibios_max_latency;
+	else
+		return;
+	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+}
+
+
+struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	return pci_scan_bus(nr, &it8152_ops, sys);
+}
+
+diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
+index 240c448..d8d2352 100644
+--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
+@@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
+ 
+static void __init pci_fixup_it8152(struct pci_dev *dev) 
+{
+	int i;
+	/* fixup for ITE 8152 devices */
+	/* FIXME: add defines for class 0x68000 and 0x80103 */
+	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
+	    dev->class == 0x68000 ||
+	    dev->class == 0x80103) {
+		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+			dev->resource[i].start = 0;
+			dev->resource[i].end   = 0;
+			dev->resource[i].flags = 0;
+		}
+	}
+}	
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
+
+
+
+ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
+ {
+ 	if (debug_pci)
+@@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
+  */
+ static inline int pdev_bad_for_parity(struct pci_dev *dev)
+ {
+-	return (dev->vendor == PCI_VENDOR_ID_INTERG &&
+-		(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
+-		 dev->device == PCI_DEVICE_ID_INTERG_2010));
+	return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
+		 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
+		  dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
+		(dev->vendor == PCI_VENDOR_ID_ITE &&
+		 dev->device == PCI_DEVICE_ID_ITE_8152));
+
+ }
+ 
+ /*
+diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h
+new file mode 100644
+index 0000000..d28210d
+--- /dev/null
+++ b/include/asm-arm/hardware/it8152.h
+@@ -0,0 +1,104 @@
+/*
+ *  arch/arm/mach-pxa/it8152.h
+ *
+ *  Compulab Ltd., 2006
+ *
+ *  ITE 8152 companion chip definitions
+ */
+
+
+/* #define CMX270_IT8152_VIRT		(CMX270_VIRT_BASE) */
+
+
+extern unsigned long it8152_base_address;
+
+#define IT8152_IO_BASE			(it8152_base_address + 0x03e00000)
+#define IT8152_CFGREG_BASE		(it8152_base_address + 0x03f00000)
+
+/* #define IRQ_GPIO_IT8152_IRQ		IRQ_GPIO(GPIO_IT8152_IRQ) */
+
+#define IT8152_SHORT_IO(x)		(*((volatile unsigned short *)(IT8152_CFGREG_BASE+(x))))
+#define IT8152_LONG_IO(x)		(*((volatile unsigned long *)(IT8152_CFGREG_BASE+(x))))
+
+
+#define IT8152_PCI_MEMBASE		(*((volatile unsigned long *)(it8152_base_address)))
+/* #define IT8152_PCI_IOBASE		(*((volatile unsigned long *)(it8152_base_address + 0x3e00000))) */
+
+#define IT8152_PCI_IACK			(*((volatile unsigned long *)(it8152_base_address + 0x3f00808)))
+#define IT8152_PCI_CFG_ADDR		(*((volatile unsigned long *)(it8152_base_address + 0x3f00800)))
+#define IT8152_PCI_CFG_DATA		(*((volatile unsigned long *)(it8152_base_address + 0x3f00804)))
+
+#define IT_BUSNUM_SHF                   16
+#define IT_DEVNUM_SHF                   11
+#define IT_FUNCNUM_SHF                  8
+#define IT_REGNUM_SHF                   2
+
+/* Power management & PLL registers */
+#define IT8152_PMPLL_DSR		IT8152_LONG_IO(0x00)
+#define IT8152_PMPLL_DSSR		IT8152_LONG_IO(0x04)
+#define IT8152_PMPLL_PLLCR		IT8152_LONG_IO(0x20)
+#define IT8152_PMPLL_MFSR		IT8152_LONG_IO(0x24)
+
+/* Memory controller */
+#define IT8152_MC_REG_OFFSET		0x100
+
+#define IT8152_MC_SDCR			IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x00)
+#define IT8152_MC_PCICR			IT8152_LONG_IO(IT8152_MC_REG_OFFSET + 0x04)
+
+/* Interrupt related definitions */
+#define IT8152_INTC_REG_OFFSET		0x300
+
+#define IT8152_INTC_LDCNIRR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x00)
+#define IT8152_INTC_LDPNIRR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x04)
+#define IT8152_INTC_LDCNIMR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x08)
+#define IT8152_INTC_LDPNIMR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x0C)
+#define IT8152_INTC_LDNITR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x10)
+#define IT8152_INTC_LDNIAR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x14)
+#define IT8152_INTC_LPCNIRR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x20)
+#define IT8152_INTC_LPPNIRR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x24)
+#define IT8152_INTC_LPCNIMR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x28)
+#define IT8152_INTC_LPPNIMR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x2C)
+#define IT8152_INTC_LPNITR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x30)
+#define IT8152_INTC_LPNIAR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x34)
+#define IT8152_INTC_PDCNIRR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x40)
+#define IT8152_INTC_PDPNIRR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x44)
+#define IT8152_INTC_PDCNIMR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x48)
+#define IT8152_INTC_PDPNIMR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x4C)
+#define IT8152_INTC_PDNITR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x50)
+#define IT8152_INTC_PDNIAR		IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0x54)
+#define IT8152_INTC_INTC_TYPER	IT8152_LONG_IO(IT8152_INTC_REG_OFFSET + 0xFC)
+
+#define IT8152_UART_BASE		IT8152_LONG_IO(0x200)
+
+#define IT8152_GPIO_REG_OFFSET		0x500
+
+#define IT8152_GPIO_GPLR		IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET)
+#define IT8152_GPIO_GPCR12		IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x04)
+#define IT8152_GPIO_GPCR34		IT8152_LONG_IO(IT8152_GPIO_REG_OFFSET + 0x08)
+
+
+/* Interrupt bit definitions */
+#define PCISERR_BIT		(1<<14)
+#define H2PTADR_BIT		(1<<13)
+#define H2PMAR_BIT		(1<<12)
+#define PCI_INTD_BIT	(1<<11)
+#define PCI_INTC_BIT	(1<<10)
+#define PCI_INTB_BIT	(1<<9)
+#define PCI_INTA_BIT	(1<<8)
+#define CDMA_INT_BIT	(1<<2)
+#define USB_INT_BIT		(1<<1)
+#define AUDIO_INT_BIT	(1<<0)
+
+/* IT8152 UART */
+#define ITESER_BIT		(1<<5)
+
+
+
+
+
+
+
+
+
+ 
+
+diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
+index f21abd4..2cf30bf 100644
+--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
+@@ -8,10 +8,17 @@
+ 
+ #define pcibios_scan_all_fns(a, b)	0
+ 
+#ifdef CONFIG_PCI_HOST_ITE8152
+/* ITE bridge requires setting latency timer to avoid early bus access
+   termination by PIC bus mater devices
+*/
+extern void pcibios_set_master(struct pci_dev *dev);
+#else
+ static inline void pcibios_set_master(struct pci_dev *dev)
+ {
+ 	/* No special bus mastering setup handling */
+ }
+#endif
+ 
+ static inline void pcibios_penalize_isa_irq(int irq, int active)
+ {
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 5b1c999..b4c81d5 100644
+--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
+@@ -1650,6 +1650,7 @@
+ #define PCI_DEVICE_ID_ITE_8211		0x8211
+ #define PCI_DEVICE_ID_ITE_8212		0x8212
+ #define PCI_DEVICE_ID_ITE_8213		0x8213
+#define PCI_DEVICE_ID_ITE_8152		0x8152
+ #define PCI_DEVICE_ID_ITE_8872		0x8872
+ #define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
+ 
+-- 
+1.5.1.6
+
@@ -0,0 +1,228 @@
+From 338653da8f8afcdf8afc7e8a5a0104d5083597cc Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 19:01:27 -0400
+Subject: [PATCH] cm-x270-pcmcia
+
+---
+ drivers/pcmcia/Makefile         |    1 +
+ drivers/pcmcia/pxa2xx_cm_x270.c |  198 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 199 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/pcmcia/pxa2xx_cm_x270.c
+
+diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
+index 4276965..353d5b7 100644
+--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
+@@ -69,4 +69,5 @@ sa1100_cs-$(CONFIG_SA1100_SIMPAD)		+= sa1100_simpad.o
+ pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK)		+= pxa2xx_lubbock.o sa1111_generic.o
+ pxa2xx_cs-$(CONFIG_MACH_MAINSTONE)		+= pxa2xx_mainstone.o
+ pxa2xx_cs-$(CONFIG_PXA_SHARPSL)			+= pxa2xx_sharpsl.o
+pxa2xx_cs-$(CONFIG_MACH_ARMCORE)               += pxa2xx_cm_x270.o
+ 
+diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
+new file mode 100644
+index 0000000..25e369f
+--- /dev/null
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
+@@ -0,0 +1,198 @@
+/*
+ * linux/drivers/pcmcia/pxa/pxa_armcore.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Compulab Ltd., 2003
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+
+#include <pcmcia/ss.h>
+#include <asm/delay.h>
+#include <asm/hardware.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/cm-x270.h>
+
+#include "soc_common.h"
+
+
+static struct pcmcia_irqs irqs[] = {
+       { 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
+       { 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
+};
+
+
+static int
+cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
+{
+       int return_val=0;
+
+       GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
+               GPIO_bit(GPIO49_nPWE) |
+               GPIO_bit(GPIO50_nPIOR) |
+               GPIO_bit(GPIO51_nPIOW) |
+               GPIO_bit(GPIO85_nPCE_1) |
+               GPIO_bit(GPIO54_nPCE_2);
+
+       pxa_gpio_mode(GPIO48_nPOE_MD);
+       pxa_gpio_mode(GPIO49_nPWE_MD);
+       pxa_gpio_mode(GPIO50_nPIOR_MD);
+       pxa_gpio_mode(GPIO51_nPIOW_MD);
+       pxa_gpio_mode(GPIO85_nPCE_1_MD);
+       pxa_gpio_mode(GPIO54_nPCE_2_MD);
+       //pxa_gpio_mode(GPIO79_pSKTSEL_MD); /* REVISIT: s/b dependent on num sockets (on ATX base not routed)*/
+       pxa_gpio_mode(GPIO55_nPREG_MD);
+       pxa_gpio_mode(GPIO56_nPWAIT_MD);
+       pxa_gpio_mode(GPIO57_nIOIS16_MD);
+
+       // Reset signal
+       GPDR(GPIO53_nPCE_2) |= GPIO_bit(GPIO53_nPCE_2);
+       GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+
+       GPDR(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID));
+       GPDR(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID));
+
+       set_irq_type(PCMCIA_S0_CD_VALID, IRQ_TYPE_EDGE_BOTH);
+       set_irq_type(PCMCIA_S1_CD_VALID, IRQ_TYPE_EDGE_BOTH);
+
+       //irq's for slots:
+       GPDR(IRQ_TO_GPIO(PCMCIA_S0_RDYINT)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S0_RDYINT));
+       GPDR(IRQ_TO_GPIO(PCMCIA_S1_RDYINT)) &= ~GPIO_bit(IRQ_TO_GPIO(PCMCIA_S1_RDYINT));
+
+       set_irq_type(PCMCIA_S0_RDYINT, IRQ_TYPE_EDGE_FALLING);
+       set_irq_type(PCMCIA_S1_RDYINT, IRQ_TYPE_EDGE_FALLING);
+
+       skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
+       return_val = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
+
+       return return_val;
+}
+
+
+static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
+{
+       soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
+
+       set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQ_TYPE_NONE);
+       set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQ_TYPE_NONE);
+
+       set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQ_TYPE_NONE);
+       set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQ_TYPE_NONE);
+}
+
+
+static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
+                                   struct pcmcia_state *state)
+{
+
+       state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0;
+       state->ready  = (PCC_READY(skt->nr) == 0) ? 0 : 1;
+       state->bvd1   = 1;
+       state->bvd2   = 1;
+       state->vs_3v  = 0;
+       state->vs_Xv  = 0;
+       state->wrprot = 0;  /* not available */
+
+}
+
+
+static int
+cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
+                                      const socket_state_t *state)
+{
+
+       GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+       pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
+       //pxa_gpio_mode(GPIO79_pSKTSEL_MD | GPIO_OUT); /* For 2-socket mode */
+
+       switch(skt->nr){
+           case 0:
+                       if(state->flags & SS_RESET) {
+                               //GPCR(GPIO79_pSKTSEL) = GPIO_bit(GPIO79_pSKTSEL); /* For 2-socket mode */
+                               //udelay(1);
+                               GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                               GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                               udelay(10);
+                               GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                               GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                       }
+                   break;
+               case 1:
+                       if(state->flags & SS_RESET) {
+                               //GPCR(GPIO79_pSKTSEL) = GPIO_bit(GPIO79_pSKTSEL); /* For 2-socket mode */
+                               //udelay(1);
+                               GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                               GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                               udelay(10);
+                               GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
+                               GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
+                       }
+                   break;
+       }
+
+       pxa_gpio_mode(GPIO49_nPWE_MD);
+       //pxa_gpio_mode(GPIO79_pSKTSEL_MD); /* For 2-socket mode */
+
+
+       return 0;
+}
+
+static void cmx270_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
+{
+}
+
+static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
+{
+}
+
+
+static struct pcmcia_low_level cmx270_pcmcia_ops = {
+       .owner                  = THIS_MODULE,
+       .hw_init                = cmx270_pcmcia_hw_init,
+       .hw_shutdown            = cmx270_pcmcia_shutdown,
+       .socket_state           = cmx270_pcmcia_socket_state,
+       .configure_socket       = cmx270_pcmcia_configure_socket,
+       .socket_init            = cmx270_pcmcia_socket_init,
+       .socket_suspend         = cmx270_pcmcia_socket_suspend,
+       .nr                     = 2,
+};
+
+static struct platform_device *cmx270_pcmcia_device;
+
+static int __init cmx270_pcmcia_init(void)
+{
+       int ret;
+
+       cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
+
+       if (!cmx270_pcmcia_device)
+               return -ENOMEM;
+
+       cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops;
+
+       printk ("Registering cm-x270 PCMCIA interface.\n");
+       ret = platform_device_add(cmx270_pcmcia_device);
+
+       if (ret)
+               platform_device_put(cmx270_pcmcia_device);
+
+       return ret;
+}
+
+static void __exit cmx270_pcmcia_exit(void)
+{
+       platform_device_unregister(cmx270_pcmcia_device);
+}
+
+module_init(cmx270_pcmcia_init);
+module_exit(cmx270_pcmcia_exit);
+
+MODULE_LICENSE("GPL");
+-- 
+1.5.1.6
+
@@ -0,0 +1,80 @@
+From ca4508b1266109208f62e986b51397ce2788e255 Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 19:01:50 -0400
+Subject: [PATCH] ramdisk_load
+
+---
+ arch/arm/mach-pxa/cm-x270.c        |    6 ++++++
+ include/asm-arm/arch-pxa/cm-x270.h |    2 ++
+ init/initramfs.c                   |   16 ++++++++++++++++
+ 3 files changed, 24 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
+index 88b080d..c6ec489 100644
+--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
+@@ -308,6 +308,12 @@ static struct map_desc cmx270_io_desc[] __initdata = {
+ 		.length		= PXA_CS_SIZE,
+ 		.type		= MT_DEVICE
+ 	},
+	[2] = { /* NOR flash */
+		.virtual	= CMX270_FLASH_VIRT,
+		.pfn		= __phys_to_pfn(PXA_CS0_PHYS),
+		.length		= (8<<20), /* up to 8 MByte flash */
+		.type		= MT_DEVICE
+	},
+ };
+ 
+ /*
+diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
+index 24613a5..aad152e 100644
+--- a/include/asm-arm/arch-pxa/cm-x270.h
+++ b/include/asm-arm/arch-pxa/cm-x270.h
+@@ -20,7 +20,9 @@
+ 
+ #define CMX270_IT8152_VIRT		(CMX270_VIRT_BASE)
+ #define CMX270_IDE104_VIRT		(CMX270_IT8152_VIRT + PXA_CS_SIZE)
+#define CMX270_FLASH_VIRT		(CMX270_IDE104_VIRT + PXA_CS_SIZE)
+ 
+#define CMX270_FLASH_RAMDISK_VIRT	(CMX270_FLASH_VIRT + 0x1c0000)
+ 
+ /* GPIO related definitions */
+ #define GPIO_IT8152_IRQ			(22)
+diff --git a/init/initramfs.c b/init/initramfs.c
+index 00eff7a..0ecd40b 100644
+--- a/init/initramfs.c
+++ b/init/initramfs.c
+@@ -7,6 +7,9 @@
+ #include <linux/string.h>
+ #include <linux/syscalls.h>
+ 
+// HACK for compulab cm-x270
+#include <asm/arch/cm-x270.h>
+
+ static __initdata char *message;
+ static void __init error(char *x)
+ {
+@@ -550,7 +553,20 @@ static int __init populate_rootfs(void)
+ #ifdef CONFIG_BLK_DEV_INITRD
+ 	if (initrd_start) {
+ #ifdef CONFIG_BLK_DEV_RAM
+ 
+		/* hack to make initramfs work because the 
+		 * compulab BL does not zero out the 
+		 * initrd memory.  This only seems to affect loading
+		 * initramfs (cpio.gz) archives.  Does not seem to 
+		 * affect ramdisks.
+		 */
+ 		int initrd_size = *(int *)(CMX270_FLASH_RAMDISK_VIRT);
+ 		int fd;
+
+ 		initrd_end = initrd_start + initrd_size;
+ 		//printk("CLIFF: initrd_start = 0x%x\n", initrd_start);
+ 		//printk("CLIFF: initrd_end = 0x%x\n", initrd_end);
+
+ 		printk(KERN_INFO "checking if image is initramfs...");
+ 		err = unpack_to_rootfs((char *)initrd_start,
+ 			initrd_end - initrd_start, 1);
+-- 
+1.5.1.6
+
@@ -0,0 +1,36 @@
+From 26638b93f7479dc597a58e2e2b2832c6ff4c8f7b Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 19:02:55 -0400
+Subject: [PATCH] mmcsd_large_cards-r0
+
+---
+ drivers/mmc/card/block.c |    6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
+index 540ff4b..1f8d67d 100644
+--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
+@@ -403,6 +403,7 @@ static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+ {
+ 	struct mmc_blk_data *md;
+ 	int devidx, ret;
+	unsigned long cap;
+ 
+ 	devidx = find_first_zero_bit(dev_use, MMC_NUM_MINORS);
+ 	if (devidx >= MMC_NUM_MINORS)
+@@ -467,6 +468,11 @@ static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+ 
+ 	sprintf(md->disk->disk_name, "mmcblk%d", devidx);
+ 
+	if (card->csd.read_blkbits > 9)
+		md->block_bits = 9;
+	else
+		md->block_bits = card->csd.read_blkbits;
+
+ 	blk_queue_hardsect_size(md->queue.queue, 1 << md->block_bits);
+ 
+ 	if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
+-- 
+1.5.1.6
+
@@ -0,0 +1,25 @@
+From e1a243564a40d7542a62d4684f2e6ce0b95fa267 Mon Sep 17 00:00:00 2001
+From: Cliff Brake <cbrake@happy.dev.bec-systems.com>
+Date: Fri, 20 Jul 2007 19:04:12 -0400
+Subject: [PATCH] cm-x270-nand-simplify-name
+
+---
+ drivers/mtd/nand/cmx270_nand.c |    2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c
+index cb663ef..3654ce4 100644
+--- a/drivers/mtd/nand/cmx270_nand.c
+++ b/drivers/mtd/nand/cmx270_nand.c
+@@ -191,6 +191,8 @@ static int cmx270_init(void)
+ 	cmx270_nand_mtd->owner = THIS_MODULE;
+ 	cmx270_nand_mtd->priv = this;
+ 
+	cmx270_nand_mtd->name = "cm-x270-nand";
+
+ 	/* insert callbacks */
+ 	this->IO_ADDR_R = cmx270_nand_io;
+ 	this->IO_ADDR_W = cmx270_nand_io;
+-- 
+1.5.1.6
+
@@ -0,0 +1,13 @@
+Index: linux-2.6.23/arch/arm/mach-pxa/cm-x270.c
+===================================================================
+--- linux-2.6.23.orig/arch/arm/mach-pxa/cm-x270.c	2008-02-14 20:32:28.000000000 +0000
+++ linux-2.6.23/arch/arm/mach-pxa/cm-x270.c	2008-02-14 20:27:55.000000000 +0000
+@@ -383,7 +383,7 @@
+ 
+ static struct pxafb_mode_info generic_crt_640x480_mode = {
+ 	.pixclock	= 38461,
+-	.bpp		= 8,
+	.bpp		= 16,
+ 	.xres		= 640,
+ 	.yres		= 480,
+ 	.hsync_len	= 63,
@@ -0,0 +1,40 @@
+Index: linux-2.6.23/arch/arm/mach-pxa/em-x270-pm.c
+===================================================================
+--- linux-2.6.23.orig/arch/arm/mach-pxa/em-x270-pm.c	2008-02-21 14:30:06.000000000 +0000
+++ linux-2.6.23/arch/arm/mach-pxa/em-x270-pm.c	2008-02-21 14:59:24.000000000 +0000
+@@ -461,6 +461,9 @@
+ 			else {
+ 				val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+ 			}
+		} 
+		else {
+			val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+ 		}
+ 	}
+ 	else {
+@@ -547,8 +550,9 @@
+ 		pr_debug("%s: MODEL = %s\n", __FUNCTION__, val->strval);
+ 		break;
+ 	default: break;
+		 return -1;
+ 	}
+-	
+
+ 	return 0;
+ }
+ 
+Index: linux-2.6.23/drivers/power/em_x270_battery.c
+===================================================================
+--- linux-2.6.23.orig/drivers/power/em_x270_battery.c	2008-02-21 12:21:53.000000000 +0000
+++ linux-2.6.23/drivers/power/em_x270_battery.c	2008-02-21 15:00:51.000000000 +0000
+@@ -418,8 +418,9 @@
+ 		pr_debug("%s: MODEL = %s\n", __FUNCTION__, val->strval);
+ 		break;
+ 	default: break;
+		return -1;
+ 	}
+-	
+
+ 	return 0;
+ }
+