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class-recipe: add support for loongarch64

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(From OE-Core rev: ec88f703f753efcbad5c077d866a5dc44ad54db0)

Signed-off-by: Jialing Zhang <zhangjialing@loongson.cn>
Signed-off-by: Qizheng Zhu <zhuqizheng@loongson.cn>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Jialing Zhang
2023-03-22 09:34:03 +08:00
committed by Richard Purdie
parent 23212c8c44
commit 46186808bd
3 changed files with 15 additions and 1 deletions
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meta/classes-recipe/libc-package.bbclass
+2 -1
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@@ -268,7 +268,8 @@ python package_do_split_gconvs () {
"riscv32": " --uint32-align=4 --little-endian ", \ "riscv32": " --uint32-align=4 --little-endian ", \
"i586": " --uint32-align=4 --little-endian ", \ "i586": " --uint32-align=4 --little-endian ", \
"i686": " --uint32-align=4 --little-endian ", \ "i686": " --uint32-align=4 --little-endian ", \
"x86_64": " --uint32-align=4 --little-endian " } "x86_64": " --uint32-align=4 --little-endian ", \
"loongarch64": " --uint32-align=4 --little-endian " }
if target_arch in locale_arch_options: if target_arch in locale_arch_options:
localedef_opts = locale_arch_options[target_arch] localedef_opts = locale_arch_options[target_arch]
meta/classes-recipe/meson-routines.bbclass
+2
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@@ -23,6 +23,8 @@ def meson_cpu_family(var, d):
return 'arm' return 'arm'
elif arch == 'aarch64_be': elif arch == 'aarch64_be':
return 'aarch64' return 'aarch64'
elif arch == 'loongarch64':
return 'loongarch64'
elif arch == 'mipsel': elif arch == 'mipsel':
return 'mips' return 'mips'
elif arch == 'mips64el': elif arch == 'mips64el':
meta/classes-recipe/rust-target-config.bbclass
+11
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@@ -245,6 +245,14 @@ TARGET_POINTER_WIDTH[riscv64gc] = "64"
TARGET_C_INT_WIDTH[riscv64gc] = "64" TARGET_C_INT_WIDTH[riscv64gc] = "64"
MAX_ATOMIC_WIDTH[riscv64gc] = "64" MAX_ATOMIC_WIDTH[riscv64gc] = "64"
## loongarch64-unknown-linux-{gnu, musl}
DATA_LAYOUT[loongarch64] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
TARGET_ENDIAN[loongarch64] = "little"
TARGET_POINTER_WIDTH[loongarch64] = "64"
TARGET_C_INT_WIDTH[loongarch64] = "32"
MAX_ATOMIC_WIDTH[loongarch64] = "64"
FEATURES[loongarch64] = "+d"
# Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something # Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something
# rust's internals won't choke on. # rust's internals won't choke on.
def arch_to_rust_target_arch(arch): def arch_to_rust_target_arch(arch):
@@ -288,6 +296,7 @@ def llvm_cpu(d):
trans['mips64el'] = "mips64" trans['mips64el'] = "mips64"
trans['riscv64'] = "generic-rv64" trans['riscv64'] = "generic-rv64"
trans['riscv32'] = "generic-rv32" trans['riscv32'] = "generic-rv32"
trans['loongarch64'] = "la464"
if target in ["mips", "mipsel", "powerpc"]: if target in ["mips", "mipsel", "powerpc"]:
feat = frozenset(d.getVar('TUNE_FEATURES').split()) feat = frozenset(d.getVar('TUNE_FEATURES').split())
@@ -367,6 +376,8 @@ def rust_gen_target(d, thing, wd, arch):
tspec['llvm-abiname'] = "lp64d" tspec['llvm-abiname'] = "lp64d"
if "riscv32" in tspec['llvm-target']: if "riscv32" in tspec['llvm-target']:
tspec['llvm-abiname'] = "ilp32d" tspec['llvm-abiname'] = "ilp32d"
if "loongarch64" in tspec['llvm-target']:
tspec['llvm-abiname'] = "lp64d"
tspec['vendor'] = "unknown" tspec['vendor'] = "unknown"
tspec['target-family'] = "unix" tspec['target-family'] = "unix"
tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix) tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix)