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gcc: Security fix for CVE-2019-15847
Affects <= 9.2.0 Dropped Changelog changes (From OE-Core rev: a579b111349fd9ad91b2d40a51f194fd25af723a) Signed-off-by: Armin Kuster <akuster@mvista.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Armin Kuster
committed by
Richard Purdie
Richard Purdie
parent
1b9559de4b
commit
4802bed8ce
@@ -75,6 +75,9 @@ SRC_URI = "\
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file://0042-PR-debug-86964.patch \
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file://0042-PR-debug-86964.patch \
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file://0043-PR85434-Prevent-spilling-of-stack-protector-guard-s-.patch \
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file://0043-PR85434-Prevent-spilling-of-stack-protector-guard-s-.patch \
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file://CVE-2019-14250.patch \
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file://CVE-2019-14250.patch \
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file://CVE-2019-15847_p1.patch \
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file://CVE-2019-15847_p2.patch \
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file://CVE-2019-15847_p3.patch \
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"
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"
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SRC_URI[md5sum] = "65b210b4bfe7e060051f799e0f994896"
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SRC_URI[md5sum] = "65b210b4bfe7e060051f799e0f994896"
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SRC_URI[sha256sum] = "64baadfe6cc0f4947a84cb12d7f0dfaf45bb58b7e92461639596c21e02d97d2c"
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SRC_URI[sha256sum] = "64baadfe6cc0f4947a84cb12d7f0dfaf45bb58b7e92461639596c21e02d97d2c"
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@@ -0,0 +1,521 @@
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From baf7c861e1cc523425029dcf81467f16c734fbd5 Mon Sep 17 00:00:00 2001
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From: segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Fri, 30 Aug 2019 14:13:51 +0000
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Subject: [PATCH 1/3] Backport from trunk 2019-08-22 Segher Boessenkool
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<segher@kernel.crashing.org>
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* config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
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UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to...
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* config/rs6000/rs6000.md (unspec): ... here.
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* config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb,
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*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
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cmpeqb, *cmpeqb_internal): Delete, move to...
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* config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb,
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*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
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cmpeqb, *cmpeqb_internal): ... here.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-8-branch@275180 138bc75d-0d04-0410-961f-82ee72b054a4
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Upstream-Status: Backport
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CVE: CVE-2019-14847 p1
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Affects <= 9.2.0
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Dropped Changelog changes
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Signed-off-by: Armin Kuster <akuster@mvista.com>
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---
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gcc/config/rs6000/altivec.md | 223 ------------------------------------------
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gcc/config/rs6000/rs6000.md | 224 +++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 239 insertions(+), 223 deletions(-)
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Index: gcc-8.3.0/gcc/config/rs6000/altivec.md
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===================================================================
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--- gcc-8.3.0.orig/gcc/config/rs6000/altivec.md
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+++ gcc-8.3.0/gcc/config/rs6000/altivec.md
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@@ -80,9 +80,6 @@
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UNSPEC_VUPKHPX
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UNSPEC_VUPKLPX
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UNSPEC_CONVERT_4F32_8I16
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- UNSPEC_DARN
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- UNSPEC_DARN_32
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- UNSPEC_DARN_RAW
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UNSPEC_DST
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UNSPEC_DSTT
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UNSPEC_DSTST
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@@ -161,9 +158,6 @@
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UNSPEC_BCDADD
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UNSPEC_BCDSUB
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UNSPEC_BCD_OVERFLOW
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- UNSPEC_CMPRB
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- UNSPEC_CMPRB2
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- UNSPEC_CMPEQB
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UNSPEC_VRLMI
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UNSPEC_VRLNM
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])
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@@ -4317,223 +4311,6 @@
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[(set_attr "length" "4")
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(set_attr "type" "vecsimple")])
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-(define_insn "darn_32"
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- [(set (match_operand:SI 0 "register_operand" "=r")
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- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
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- "TARGET_P9_MISC"
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- "darn %0,0"
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- [(set_attr "type" "integer")])
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-
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-(define_insn "darn_raw"
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- [(set (match_operand:DI 0 "register_operand" "=r")
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- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
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- "TARGET_P9_MISC && TARGET_64BIT"
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- "darn %0,2"
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- [(set_attr "type" "integer")])
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-
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-(define_insn "darn"
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- [(set (match_operand:DI 0 "register_operand" "=r")
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- (unspec:DI [(const_int 0)] UNSPEC_DARN))]
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- "TARGET_P9_MISC && TARGET_64BIT"
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- "darn %0,1"
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- [(set_attr "type" "integer")])
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-
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-;; Test byte within range.
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-;;
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the range specified by operand 2.
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-;; The bytes of operand 2 are organized as xx:xx:hi:lo.
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-;;
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-;; Return in target register operand 0 a value of 1 if lo <= vv and
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-;; vv <= hi. Otherwise, set register operand 0 to 0.
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-;;
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-;; Though the instructions to which this expansion maps operate on
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-;; 64-bit registers, the current implementation only operates on
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-;; SI-mode operands as the high-order bits provide no information
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-;; that is not already available in the low-order bits. To avoid the
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-;; costs of data widening operations, future enhancements might allow
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-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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-(define_expand "cmprb"
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- [(set (match_dup 3)
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB))
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- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_dup 3)
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 3)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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-{
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- operands[3] = gen_reg_rtx (CCmode);
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-})
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-
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the range specified by operand 2.
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-;; The bytes of operand 2 are organized as xx:xx:hi:lo.
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-;;
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-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
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-;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
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-;; 3 bits of the target CR register are all set to 0.
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-(define_insn "*cmprb_internal"
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- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB))]
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- "TARGET_P9_MISC"
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- "cmprb %0,0,%1,%2"
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- [(set_attr "type" "logical")])
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-
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-;; Set operand 0 register to -1 if the LT bit (0x8) of condition
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-;; register operand 1 is on. Otherwise, set operand 0 register to 1
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-;; if the GT bit (0x4) of condition register operand 1 is on.
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-;; Otherwise, set operand 0 to 0. Note that the result stored into
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-;; register operand 0 is non-zero iff either the LT or GT bits are on
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-;; within condition register operand 1.
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-(define_insn "setb_signed"
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- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 1)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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- "setb %0,%1"
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- [(set_attr "type" "logical")])
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-
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-(define_insn "setb_unsigned"
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- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gtu (match_dup 1)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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- "setb %0,%1"
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- [(set_attr "type" "logical")])
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-
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-;; Test byte within two ranges.
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-;;
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the range specified by operand 2.
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-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
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-;;
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-;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
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-;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
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-;; operand 0 to 0.
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-;;
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-;; Though the instructions to which this expansion maps operate on
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-;; 64-bit registers, the current implementation only operates on
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-;; SI-mode operands as the high-order bits provide no information
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-;; that is not already available in the low-order bits. To avoid the
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-;; costs of data widening operations, future enhancements might allow
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-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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-(define_expand "cmprb2"
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- [(set (match_dup 3)
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB2))
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- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
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- (if_then_else:SI (lt (match_dup 3)
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- (const_int 0))
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- (const_int -1)
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- (if_then_else (gt (match_dup 3)
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- (const_int 0))
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- (const_int 1)
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- (const_int 0))))]
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- "TARGET_P9_MISC"
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-{
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- operands[3] = gen_reg_rtx (CCmode);
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-})
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-
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the ranges specified by operand 2.
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-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
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-;;
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-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
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-;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
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-;; Otherwise, set the GT bit to 0. The other 3 bits of the target
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-;; CR register are all set to 0.
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-(define_insn "*cmprb2_internal"
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- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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- (match_operand:SI 2 "gpc_reg_operand" "r")]
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- UNSPEC_CMPRB2))]
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- "TARGET_P9_MISC"
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- "cmprb %0,1,%1,%2"
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- [(set_attr "type" "logical")])
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-
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-;; Test byte membership within set of 8 bytes.
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-;;
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-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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-;; represents a byte whose value is ignored in this context and
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-;; vv, the least significant byte, holds the byte value that is to
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-;; be tested for membership within the set specified by operand 2.
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-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
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-;;
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-;; Return in target register operand 0 a value of 1 if vv equals one
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-;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
|
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|
-;; register operand 0 to 0. Note that the 8 byte values held within
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-;; operand 2 need not be unique.
|
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-;;
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|
-;; Though the instructions to which this expansion maps operate on
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-;; 64-bit registers, the current implementation requires that operands
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|
-;; 0 and 1 have mode SI as the high-order bits provide no information
|
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|
-;; that is not already available in the low-order bits. To avoid the
|
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|
-;; costs of data widening operations, future enhancements might allow
|
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|
-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||||
|
-(define_expand "cmpeqb"
|
||||||
|
- [(set (match_dup 3)
|
||||||
|
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
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- (match_operand:DI 2 "gpc_reg_operand" "r")]
|
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- UNSPEC_CMPEQB))
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- (set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
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- (if_then_else:SI (lt (match_dup 3)
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- (const_int 0))
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- (const_int -1)
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||||||
|
- (if_then_else (gt (match_dup 3)
|
||||||
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- (const_int 0))
|
||||||
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- (const_int 1)
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||||||
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- (const_int 0))))]
|
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|
- "TARGET_P9_MISC && TARGET_64BIT"
|
||||||
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-{
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||||||
|
- operands[3] = gen_reg_rtx (CCmode);
|
||||||
|
-})
|
||||||
|
-
|
||||||
|
-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
-;; represents a byte whose value is ignored in this context and
|
||||||
|
-;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
-;; be tested for membership within the set specified by operand 2.
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||||||
|
-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||||
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-;;
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||||||
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-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
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||||||
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-;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
|
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-;; set the GT bit to zero. The other 3 bits of the target CR register
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-;; are all set to 0.
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-(define_insn "*cmpeqb_internal"
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||||||
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- [(set (match_operand:CC 0 "cc_reg_operand" "=y")
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||||||
|
- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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||||||
|
- (match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||||
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- UNSPEC_CMPEQB))]
|
||||||
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- "TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
- "cmpeqb %0,%1,%2"
|
||||||
|
- [(set_attr "type" "logical")])
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||||||
|
-
|
||||||
|
(define_expand "bcd<bcd_add_sub>_<code>"
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||||||
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[(parallel [(set (reg:CCFP CR6_REGNO)
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||||||
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(compare:CCFP
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|
Index: gcc-8.3.0/gcc/config/rs6000/rs6000.md
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|
===================================================================
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||||||
|
--- gcc-8.3.0.orig/gcc/config/rs6000/rs6000.md
|
||||||
|
+++ gcc-8.3.0/gcc/config/rs6000/rs6000.md
|
||||||
|
@@ -136,6 +136,12 @@
|
||||||
|
UNSPEC_LSQ
|
||||||
|
UNSPEC_FUSION_GPR
|
||||||
|
UNSPEC_STACK_CHECK
|
||||||
|
+ UNSPEC_DARN
|
||||||
|
+ UNSPEC_DARN_32
|
||||||
|
+ UNSPEC_DARN_RAW
|
||||||
|
+ UNSPEC_CMPRB
|
||||||
|
+ UNSPEC_CMPRB2
|
||||||
|
+ UNSPEC_CMPEQB
|
||||||
|
UNSPEC_FUSION_P9
|
||||||
|
UNSPEC_FUSION_ADDIS
|
||||||
|
UNSPEC_ADD_ROUND_TO_ODD
|
||||||
|
@@ -14597,7 +14603,225 @@
|
||||||
|
"xscmpuqp %0,%1,%2"
|
||||||
|
[(set_attr "type" "veccmp")
|
||||||
|
(set_attr "size" "128")])
|
||||||
|
+
|
||||||
|
+;; Miscellaneous ISA 3.0 (power9) instructions
|
||||||
|
+
|
||||||
|
+(define_insn "darn_32"
|
||||||
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
+ (unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+ "darn %0,0"
|
||||||
|
+ [(set_attr "type" "integer")])
|
||||||
|
+
|
||||||
|
+(define_insn "darn_raw"
|
||||||
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
+ (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
|
||||||
|
+ "TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
+ "darn %0,2"
|
||||||
|
+ [(set_attr "type" "integer")])
|
||||||
|
+
|
||||||
|
+(define_insn "darn"
|
||||||
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
+ (unspec:DI [(const_int 0)] UNSPEC_DARN))]
|
||||||
|
+ "TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
+ "darn %0,1"
|
||||||
|
+ [(set_attr "type" "integer")])
|
||||||
|
|
||||||
|
+;; Test byte within range.
|
||||||
|
+;;
|
||||||
|
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
+;; represents a byte whose value is ignored in this context and
|
||||||
|
+;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
+;; be tested for membership within the range specified by operand 2.
|
||||||
|
+;; The bytes of operand 2 are organized as xx:xx:hi:lo.
|
||||||
|
+;;
|
||||||
|
+;; Return in target register operand 0 a value of 1 if lo <= vv and
|
||||||
|
+;; vv <= hi. Otherwise, set register operand 0 to 0.
|
||||||
|
+;;
|
||||||
|
+;; Though the instructions to which this expansion maps operate on
|
||||||
|
+;; 64-bit registers, the current implementation only operates on
|
||||||
|
+;; SI-mode operands as the high-order bits provide no information
|
||||||
|
+;; that is not already available in the low-order bits. To avoid the
|
||||||
|
+;; costs of data widening operations, future enhancements might allow
|
||||||
|
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||||
|
+(define_expand "cmprb"
|
||||||
|
+ [(set (match_dup 3)
|
||||||
|
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||||
|
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||||
|
+ UNSPEC_CMPRB))
|
||||||
|
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||||
|
+ (if_then_else:SI (lt (match_dup 3)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int -1)
|
||||||
|
+ (if_then_else (gt (match_dup 3)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int 1)
|
||||||
|
+ (const_int 0))))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+{
|
||||||
|
+ operands[3] = gen_reg_rtx (CCmode);
|
||||||
|
+})
|
||||||
|
+
|
||||||
|
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
+;; represents a byte whose value is ignored in this context and
|
||||||
|
+;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
+;; be tested for membership within the range specified by operand 2.
|
||||||
|
+;; The bytes of operand 2 are organized as xx:xx:hi:lo.
|
||||||
|
+;;
|
||||||
|
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
|
||||||
|
+;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
|
||||||
|
+;; 3 bits of the target CR register are all set to 0.
|
||||||
|
+(define_insn "*cmprb_internal"
|
||||||
|
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||||
|
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||||
|
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||||
|
+ UNSPEC_CMPRB))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+ "cmprb %0,0,%1,%2"
|
||||||
|
+ [(set_attr "type" "logical")])
|
||||||
|
+
|
||||||
|
+;; Set operand 0 register to -1 if the LT bit (0x8) of condition
|
||||||
|
+;; register operand 1 is on. Otherwise, set operand 0 register to 1
|
||||||
|
+;; if the GT bit (0x4) of condition register operand 1 is on.
|
||||||
|
+;; Otherwise, set operand 0 to 0. Note that the result stored into
|
||||||
|
+;; register operand 0 is non-zero iff either the LT or GT bits are on
|
||||||
|
+;; within condition register operand 1.
|
||||||
|
+(define_insn "setb_signed"
|
||||||
|
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||||
|
+ (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int -1)
|
||||||
|
+ (if_then_else (gt (match_dup 1)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int 1)
|
||||||
|
+ (const_int 0))))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+ "setb %0,%1"
|
||||||
|
+ [(set_attr "type" "logical")])
|
||||||
|
+
|
||||||
|
+(define_insn "setb_unsigned"
|
||||||
|
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||||
|
+ (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int -1)
|
||||||
|
+ (if_then_else (gtu (match_dup 1)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int 1)
|
||||||
|
+ (const_int 0))))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+ "setb %0,%1"
|
||||||
|
+ [(set_attr "type" "logical")])
|
||||||
|
+
|
||||||
|
+;; Test byte within two ranges.
|
||||||
|
+;;
|
||||||
|
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
+;; represents a byte whose value is ignored in this context and
|
||||||
|
+;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
+;; be tested for membership within the range specified by operand 2.
|
||||||
|
+;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
|
||||||
|
+;;
|
||||||
|
+;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
|
||||||
|
+;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
|
||||||
|
+;; operand 0 to 0.
|
||||||
|
+;;
|
||||||
|
+;; Though the instructions to which this expansion maps operate on
|
||||||
|
+;; 64-bit registers, the current implementation only operates on
|
||||||
|
+;; SI-mode operands as the high-order bits provide no information
|
||||||
|
+;; that is not already available in the low-order bits. To avoid the
|
||||||
|
+;; costs of data widening operations, future enhancements might allow
|
||||||
|
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||||
|
+(define_expand "cmprb2"
|
||||||
|
+ [(set (match_dup 3)
|
||||||
|
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||||
|
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||||
|
+ UNSPEC_CMPRB2))
|
||||||
|
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||||
|
+ (if_then_else:SI (lt (match_dup 3)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int -1)
|
||||||
|
+ (if_then_else (gt (match_dup 3)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int 1)
|
||||||
|
+ (const_int 0))))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+{
|
||||||
|
+ operands[3] = gen_reg_rtx (CCmode);
|
||||||
|
+})
|
||||||
|
+
|
||||||
|
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
+;; represents a byte whose value is ignored in this context and
|
||||||
|
+;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
+;; be tested for membership within the ranges specified by operand 2.
|
||||||
|
+;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
|
||||||
|
+;;
|
||||||
|
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
|
||||||
|
+;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
|
||||||
|
+;; Otherwise, set the GT bit to 0. The other 3 bits of the target
|
||||||
|
+;; CR register are all set to 0.
|
||||||
|
+(define_insn "*cmprb2_internal"
|
||||||
|
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||||
|
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||||
|
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||||
|
+ UNSPEC_CMPRB2))]
|
||||||
|
+ "TARGET_P9_MISC"
|
||||||
|
+ "cmprb %0,1,%1,%2"
|
||||||
|
+ [(set_attr "type" "logical")])
|
||||||
|
+
|
||||||
|
+;; Test byte membership within set of 8 bytes.
|
||||||
|
+;;
|
||||||
|
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
+;; represents a byte whose value is ignored in this context and
|
||||||
|
+;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
+;; be tested for membership within the set specified by operand 2.
|
||||||
|
+;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||||
|
+;;
|
||||||
|
+;; Return in target register operand 0 a value of 1 if vv equals one
|
||||||
|
+;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
|
||||||
|
+;; register operand 0 to 0. Note that the 8 byte values held within
|
||||||
|
+;; operand 2 need not be unique.
|
||||||
|
+;;
|
||||||
|
+;; Though the instructions to which this expansion maps operate on
|
||||||
|
+;; 64-bit registers, the current implementation requires that operands
|
||||||
|
+;; 0 and 1 have mode SI as the high-order bits provide no information
|
||||||
|
+;; that is not already available in the low-order bits. To avoid the
|
||||||
|
+;; costs of data widening operations, future enhancements might allow
|
||||||
|
+;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||||
|
+(define_expand "cmpeqb"
|
||||||
|
+ [(set (match_dup 3)
|
||||||
|
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||||
|
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||||
|
+ UNSPEC_CMPEQB))
|
||||||
|
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||||
|
+ (if_then_else:SI (lt (match_dup 3)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int -1)
|
||||||
|
+ (if_then_else (gt (match_dup 3)
|
||||||
|
+ (const_int 0))
|
||||||
|
+ (const_int 1)
|
||||||
|
+ (const_int 0))))]
|
||||||
|
+ "TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
+{
|
||||||
|
+ operands[3] = gen_reg_rtx (CCmode);
|
||||||
|
+})
|
||||||
|
+
|
||||||
|
+;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||||
|
+;; represents a byte whose value is ignored in this context and
|
||||||
|
+;; vv, the least significant byte, holds the byte value that is to
|
||||||
|
+;; be tested for membership within the set specified by operand 2.
|
||||||
|
+;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||||
|
+;;
|
||||||
|
+;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
|
||||||
|
+;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
|
||||||
|
+;; set the GT bit to zero. The other 3 bits of the target CR register
|
||||||
|
+;; are all set to 0.
|
||||||
|
+(define_insn "*cmpeqb_internal"
|
||||||
|
+ [(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||||
|
+ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||||
|
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||||
|
+ UNSPEC_CMPEQB))]
|
||||||
|
+ "TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
+ "cmpeqb %0,%1,%2"
|
||||||
|
+ [(set_attr "type" "logical")])
|
||||||
|
|
||||||
|
|
||||||
|
(include "sync.md")
|
||||||
@@ -0,0 +1,77 @@
|
|||||||
|
From 2d7749ba418adde9536baf0d16d50a072b5841de Mon Sep 17 00:00:00 2001
|
||||||
|
From: segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4>
|
||||||
|
Date: Fri, 30 Aug 2019 14:15:39 +0000
|
||||||
|
Subject: [PATCH 2/3] Backport from trunk 2019-08-22 Segher Boessenkool
|
||||||
|
<segher@kernel.crashing.org>
|
||||||
|
|
||||||
|
PR target/91481
|
||||||
|
* config/rs6000/rs6000.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
|
||||||
|
and UNSPEC_DARN_RAW.
|
||||||
|
(unspecv): New enumerator values UNSPECV_DARN, UNSPECV_DARN_32, and
|
||||||
|
UNSPECV_DARN_RAW.
|
||||||
|
(darn_32): Use an unspec_volatile, and UNSPECV_DARN_32.
|
||||||
|
(darn_raw): Use an unspec_volatile, and UNSPECV_DARN_RAW.
|
||||||
|
(darn): Use an unspec_volatile, and UNSPECV_DARN.
|
||||||
|
|
||||||
|
|
||||||
|
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-8-branch@275181 138bc75d-0d04-0410-961f-82ee72b054a4
|
||||||
|
|
||||||
|
Upstream-Status: Backport
|
||||||
|
CVE: CVE-2019-14847 p2
|
||||||
|
Affects <= 9.2.0
|
||||||
|
Dropped Change log changes
|
||||||
|
Signed-off-by: Armin Kuster <akuster@mvista.com>
|
||||||
|
|
||||||
|
---
|
||||||
|
gcc/config/rs6000/rs6000.md | 12 ++++++------
|
||||||
|
2 files changed, 20 insertions(+), 6 deletions(-)
|
||||||
|
|
||||||
|
Index: gcc-8.3.0/gcc/config/rs6000/rs6000.md
|
||||||
|
===================================================================
|
||||||
|
--- gcc-8.3.0.orig/gcc/config/rs6000/rs6000.md
|
||||||
|
+++ gcc-8.3.0/gcc/config/rs6000/rs6000.md
|
||||||
|
@@ -136,9 +136,6 @@
|
||||||
|
UNSPEC_LSQ
|
||||||
|
UNSPEC_FUSION_GPR
|
||||||
|
UNSPEC_STACK_CHECK
|
||||||
|
- UNSPEC_DARN
|
||||||
|
- UNSPEC_DARN_32
|
||||||
|
- UNSPEC_DARN_RAW
|
||||||
|
UNSPEC_CMPRB
|
||||||
|
UNSPEC_CMPRB2
|
||||||
|
UNSPEC_CMPEQB
|
||||||
|
@@ -168,6 +165,9 @@
|
||||||
|
UNSPECV_EH_RR ; eh_reg_restore
|
||||||
|
UNSPECV_ISYNC ; isync instruction
|
||||||
|
UNSPECV_MFTB ; move from time base
|
||||||
|
+ UNSPECV_DARN ; darn 1 (deliver a random number)
|
||||||
|
+ UNSPECV_DARN_32 ; darn 2
|
||||||
|
+ UNSPECV_DARN_RAW ; darn 0
|
||||||
|
UNSPECV_NLGR ; non-local goto receiver
|
||||||
|
UNSPECV_MFFS ; Move from FPSCR
|
||||||
|
UNSPECV_MTFSF ; Move to FPSCR Fields
|
||||||
|
@@ -14608,21 +14608,21 @@
|
||||||
|
|
||||||
|
(define_insn "darn_32"
|
||||||
|
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
|
||||||
|
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
|
||||||
|
"TARGET_P9_MISC"
|
||||||
|
"darn %0,0"
|
||||||
|
[(set_attr "type" "integer")])
|
||||||
|
|
||||||
|
(define_insn "darn_raw"
|
||||||
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
|
||||||
|
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
|
||||||
|
"TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
"darn %0,2"
|
||||||
|
[(set_attr "type" "integer")])
|
||||||
|
|
||||||
|
(define_insn "darn"
|
||||||
|
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||||
|
- (unspec:DI [(const_int 0)] UNSPEC_DARN))]
|
||||||
|
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
|
||||||
|
"TARGET_P9_MISC && TARGET_64BIT"
|
||||||
|
"darn %0,1"
|
||||||
|
[(set_attr "type" "integer")])
|
||||||
@@ -0,0 +1,45 @@
|
|||||||
|
From 5f8cd14f8966f11e8ed10a4c7e35dc01fffe54d8 Mon Sep 17 00:00:00 2001
|
||||||
|
From: segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4>
|
||||||
|
Date: Fri, 30 Aug 2019 14:17:20 +0000
|
||||||
|
Subject: [PATCH 3/3] Backport from trunk 2019-08-23 Segher Boessenkool
|
||||||
|
<segher@kernel.crashing.org>
|
||||||
|
|
||||||
|
gcc/testsuite/
|
||||||
|
PR target/91481
|
||||||
|
* gcc.target/powerpc/darn-3.c: New testcase.
|
||||||
|
|
||||||
|
|
||||||
|
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-8-branch@275182 138bc75d-0d04-0410-961f-82ee72b054a4
|
||||||
|
|
||||||
|
Upstream-Status: Backport
|
||||||
|
CVE: CVE-2019-14847 p3
|
||||||
|
Affects <= 9.2.0
|
||||||
|
Dropped Change log changes
|
||||||
|
Signed-off-by: Armin Kuster <akuster@mvista.com>
|
||||||
|
|
||||||
|
---
|
||||||
|
gcc/testsuite/gcc.target/powerpc/darn-3.c | 16 ++++++++++++++++
|
||||||
|
2 files changed, 25 insertions(+)
|
||||||
|
create mode 100644 gcc/testsuite/gcc.target/powerpc/darn-3.c
|
||||||
|
|
||||||
|
Index: gcc-8.3.0/gcc/testsuite/gcc.target/powerpc/darn-3.c
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null
|
||||||
|
+++ gcc-8.3.0/gcc/testsuite/gcc.target/powerpc/darn-3.c
|
||||||
|
@@ -0,0 +1,16 @@
|
||||||
|
+/* { dg-do compile { target { powerpc*-*-* } } } */
|
||||||
|
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
|
||||||
|
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
|
||||||
|
+
|
||||||
|
+static int darn32(void) { return __builtin_darn_32(); }
|
||||||
|
+
|
||||||
|
+int four(void)
|
||||||
|
+{
|
||||||
|
+ int sum = 0;
|
||||||
|
+ int i;
|
||||||
|
+ for (i = 0; i < 4; i++)
|
||||||
|
+ sum += darn32();
|
||||||
|
+ return sum;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+/* { dg-final { scan-assembler-times {(?n)\mdarn .*,0\M} 4 } } */
|
||||||
Reference in New Issue
Block a user