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linux-omap2-git: Sync with OE.dev, add fixes to compile correctly with gcc 4.3.1
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@5009 311d38ba-8fff-0310-9ca6-ca027cbcb966
This commit is contained in:
Richard Purdie
@@ -0,0 +1,303 @@
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TWL4030: use *_SIH_CTRL.COR bit to determine whether to read or write ISR to clear
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From: Paul Walmsley <paul@pwsan.com>
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TWL4030 interrupt status register bits can be cleared in one of two ways:
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either by reading from the register, or by writing a 1 to the
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appropriate bit(s) in the register. This behavior can be altered at any
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time by the <twlmodule>_SIH_CTRL.COR register bit ("clear-on-read").
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The TWL4030 TRM is deeply confused as to whether COR=1 means that the
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registers are cleared on reads, or cleared on writes. Peter De
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Schrijver <peter.de-schrijver> confirms that COR=1 means that the registers
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are cleared on read.
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So, for each TWL4030 SIH, check the value of the *_SIH_CTRL.COR bit, and if
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it is 1, use reads to clear the ISRs; if it is 0, use writes.
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Also, use WARN_ON() to warn if the read/write failed, and don't skip
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the rest of the initialization on failure either.
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Thanks to Peter for his help with this patch.
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Signed-off-by: Paul Walmsley <paul@pwsan.com>
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---
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drivers/i2c/chips/twl4030-core.c | 183 ++++++++++++++++++++++----------------
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1 files changed, 106 insertions(+), 77 deletions(-)
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diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
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index 9d93524..eae0634 100644
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--- a/drivers/i2c/chips/twl4030-core.c
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+++ b/drivers/i2c/chips/twl4030-core.c
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@@ -133,6 +133,16 @@
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/* on I2C-1 for 2430SDP */
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#define CONFIG_I2C_TWL4030_ID 1
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+/* SIH_CTRL registers */
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+#define TWL4030_INT_PWR_SIH_CTRL 0x07
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+#define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d
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+#define TWL4030_MADC_MADC_SIH_CTRL 0x67
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+#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
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+#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d
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+
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+#define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
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+
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+
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/* Helper functions */
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static int
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twl4030_detect_client(struct i2c_adapter *adapter, unsigned char sid);
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@@ -712,13 +722,61 @@ static int power_companion_init(void)
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return e;
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}
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+/**
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+ * twl4030_i2c_clear_isr - clear TWL4030 SIH ISR regs via read + write
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+ * @mod_no: TWL4030 module number
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+ * @reg: register index to clear
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+ * @cor: value of the <module>_SIH_CTRL.COR bit (1 or 0)
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+ *
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+ * Either reads (cor == 1) or writes (cor == 0) to a TWL4030 interrupt
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+ * status register to ensure that any prior interrupts are cleared.
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+ * Returns the status from the I2C read operation.
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+ */
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+static int twl4030_i2c_clear_isr(u8 mod_no, u8 reg, u8 cor)
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+{
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+ u8 tmp;
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+
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+ return (cor) ? twl4030_i2c_read_u8(mod_no, &tmp, reg) :
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+ twl4030_i2c_write_u8(mod_no, 0xff, reg);
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+}
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+
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+/**
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+ * twl4030_read_cor_bit - are TWL module ISRs cleared by reads or writes?
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+ * @mod_no: TWL4030 module number
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+ * @reg: register index to clear
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+ *
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+ * Returns 1 if the TWL4030 SIH interrupt status registers (ISRs) for
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+ * the specified TWL module are cleared by reads, or 0 if cleared by
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+ * writes.
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+ */
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+static int twl4030_read_cor_bit(u8 mod_no, u8 reg)
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+{
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+ u8 tmp = 0;
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+
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+ WARN_ON(twl4030_i2c_read_u8(mod_no, &tmp, reg) < 0);
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+
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+ tmp &= TWL4030_SIH_CTRL_COR_MASK;
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+ tmp >>= __ffs(TWL4030_SIH_CTRL_COR_MASK);
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+
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+ return tmp;
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+}
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+
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static void twl_init_irq(void)
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{
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int i = 0;
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int res = 0;
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+ int cor;
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char *msg = "Unable to register interrupt subsystem";
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unsigned int irq_num;
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+ /*
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+ * For each TWL4030 module with ISR/IMR registers, mask all
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+ * interrupts and then clear any existing interrupt status bits,
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+ * since we initially do not have any TWL4030 module interrupt
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+ * handlers present.
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+ */
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+
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+
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/* PWR_IMR1 */
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res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1);
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if (res < 0) {
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@@ -734,20 +792,18 @@ static void twl_init_irq(void)
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}
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/* Clear off any other pending interrupts on power */
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+
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+ /* Are PWR interrupt status bits cleared by reads or writes? */
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+ cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
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+ TWL4030_INT_PWR_SIH_CTRL);
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+ WARN_ON(cor < 0);
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+
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/* PWR_ISR1 */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x00);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0);
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/* PWR_ISR2 */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x02);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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- /* POWER HACK (END) */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0);
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+
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/* Slave address 0x4A */
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/* BCIIMR1A */
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@@ -778,33 +834,22 @@ static void twl_init_irq(void)
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return;
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}
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+ /* Are BCI interrupt status bits cleared by reads or writes? */
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+ cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
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+ TWL4030_INTERRUPTS_BCISIHCTRL);
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+ WARN_ON(cor < 0);
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+
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/* BCIISR1A */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x0);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0);
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/* BCIISR2A */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x1);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0);
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/* BCIISR1B */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0);
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/* BCIISR2B */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x5);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0);
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/* MAD C */
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/* MADC_IMR1 */
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@@ -821,19 +866,16 @@ static void twl_init_irq(void)
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return;
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}
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+ /* Are MADC interrupt status bits cleared by reads or writes? */
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+ cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
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+ TWL4030_MADC_MADC_SIH_CTRL);
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+ WARN_ON(cor < 0);
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+
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/* MADC_ISR1 */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x61);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0);
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/* MADC_ISR2 */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x63);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0);
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/* key Pad */
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/* KEYPAD - IMR1 */
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@@ -842,12 +884,15 @@ static void twl_init_irq(void)
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pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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return;
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}
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- {
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- u8 clear;
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- /* Clear ISR */
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- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11);
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- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11);
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- }
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+
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+ /* Are keypad interrupt status bits cleared by reads or writes? */
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+ cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
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+ TWL4030_KEYPAD_KEYP_SIH_CTRL);
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+ WARN_ON(cor < 0);
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+
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+ /* KEYPAD - ISR1 */
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+ /* XXX does this still need to be done twice for some reason? */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
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/* KEYPAD - IMR2 */
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res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x14));
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@@ -856,6 +901,9 @@ static void twl_init_irq(void)
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return;
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}
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+ /* KEYPAD - ISR2 */
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
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+
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/* Slave address 0x49 */
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/* GPIO_IMR1A */
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res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1C));
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@@ -899,47 +947,28 @@ static void twl_init_irq(void)
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return;
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}
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+ /* Are GPIO interrupt status bits cleared by reads or writes? */
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+ cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
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+ TWL4030_GPIO_GPIO_SIH_CTRL);
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+ WARN_ON(cor < 0);
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+
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/* GPIO_ISR1A */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x19);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0);
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/* GPIO_ISR2A */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1a);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0);
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/* GPIO_ISR3A */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1b);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0);
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/* GPIO_ISR1B */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1f);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0);
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/* GPIO_ISR2B */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x20);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0);
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/* GPIO_ISR3B */
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- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x21);
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- if (res < 0) {
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- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
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- return;
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- }
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+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0);
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/* install an irq handler for each of the PIH modules */
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for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
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