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binutils: Fix octeon3 disassembly patch

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The structure has apparently changed, and there was a missing
setting.  This corrects a segfault when disassembling code.

(From OE-Core rev: 2e8f1ffe3a8d7740b0ac68eefbba3fe28f7ba6d4)

Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Mark Hatle
2015-10-20 10:54:33 -05:00
committed by Richard Purdie
parent fc45deac89
commit fd4f4d299e
1 changed files with 1 additions and 1 deletions
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meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch
+1 -1
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@@ -229,7 +229,7 @@ Index: git/opcodes/mips-dis.c
+ { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, + { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3,
+ ISA_MIPS64R2 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, + ISA_MIPS64R2 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64,
+ mips_cp0_names_numeric, + mips_cp0_names_numeric,
+ NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
+ +
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR, 0, ISA_MIPS64 | INSN_XLR, 0,