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hardware watchdog
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c09fd31457
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@@ -82,6 +82,7 @@ class GPIO(object):
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# clock for delay). So, do not create two or more instances of DMAGPIO.
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class DMAGPIO(DMAProto):
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_DMA_CONTROL_BLOCK_SIZE = 32
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_DMA_CHANNEL = 4
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def __init__(self):
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""" Create object which control GPIO pins via DMA(Direct Memory
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@@ -93,7 +94,7 @@ class DMAGPIO(DMAProto):
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otherwise memory will be unlocked and it could be overwritten by
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operating system.
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"""
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super(DMAGPIO, self).__init__(30 * 1024 * 1024, 4)
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super(DMAGPIO, self).__init__(30 * 1024 * 1024, self._DMA_CHANNEL)
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self.__current_address = 0
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# get helpers registers, this class uses PWM module to create precise
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@@ -259,6 +260,7 @@ class DMAPWM(DMAProto):
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_DMA_CONTROL_BLOCK_SIZE = 32
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_DMA_DATA_OFFSET = 24
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_TOTAL_NUMBER_OF_BLOCKS = 256
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_DMA_CHANNEL = 14
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def __init__(self):
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""" Initialise PWM. PWM has 8 bit resolution and fixed frequency
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@@ -273,7 +275,8 @@ class DMAPWM(DMAProto):
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Cycles in info field of control blocks.
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"""
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super(DMAPWM, self).__init__(self._TOTAL_NUMBER_OF_BLOCKS
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* self._DMA_CONTROL_BLOCK_SIZE, 14)
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* self._DMA_CONTROL_BLOCK_SIZE,
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self._DMA_CHANNEL)
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self._clear_pins = dict()
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# first control block always set pins
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self.__add_control_block(0, GPIO_SET_OFFSET)
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@@ -356,6 +359,57 @@ class DMAPWM(DMAProto):
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assert len(self._clear_pins) == 0
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class DMAWatchdog(DMAProto):
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_DMA_CONTROL_BLOCK_SIZE = 32
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_DMA_CHANNEL = 13
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_DMA_BLOCKS = 2047
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def __init__(self):
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""" Initialize hardware watchdog timer.
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"""
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super(DMAWatchdog, self).__init__(self._DMA_CONTROL_BLOCK_SIZE
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* (self._DMA_BLOCKS + 1),
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self._DMA_CHANNEL)
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def start(self):
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""" Arm watchdog for ~15 seconds. If watchdog wasn't fed in 15 seconds,
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GPIO pins 0-29 will be switched to input to prevent any output from
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them.
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"""
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data = ()
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ba = self._phys_memory.get_bus_address()
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# first blocks is just a delay
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for _ in range(0, self._DMA_BLOCKS):
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data += (
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DMA_TI_NO_WIDE_BURSTS | DMA_DEST_IGNORE | DMA_TI_WAIT_RESP
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| DMA_TI_WAITS(31),
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ba + 24, ba + 28, 65535,
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0, ba + self._DMA_CONTROL_BLOCK_SIZE, 0, 0
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)
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ba += self._DMA_CONTROL_BLOCK_SIZE
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# The last block writes zero(switch to input state) in GPIO's FSEL
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# register in normal operating, should never be called, until watchdog
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# timeout is reached.
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data += (
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DMA_TI_NO_WIDE_BURSTS | DMA_TI_WAIT_RESP | DMA_TI_DEST_INC,
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ba + 24, PHYSICAL_GPIO_BUS + GPIO_FSEL_OFFSET, 12,
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0, 0, 0, 0
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)
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self._phys_memory.write(0, str(len(data)) + "I", data)
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super(DMAWatchdog, self)._run_dma()
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def stop(self):
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""" Disarm watchdog.
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"""
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super(DMAWatchdog, self)._stop_dma()
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def feed(self):
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""" Feed watchdog, restart waiting loop from the very beginning.
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"""
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self._dma.write_int(self._DMA_CHANNEL_ADDRESS + DMA_NEXTCONBK,
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self._phys_memory.get_bus_address())
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# for testing purpose
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def main():
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pin = 21
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