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refactoring
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@@ -57,32 +57,18 @@ DMA_CS_END = 1 << 1
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DMA_CS_ACTIVE = 1 << 0
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DMA_TI_PER_MAP_PWM = 5
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DMA_TI_PER_MAP_PCM = 2
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def DMA_TI_PER_MAP(x):
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return x << 16
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def DMA_TI_TXFR_LEN_YLENGTH(y):
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return (y & 0x3fff) << 16
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def DMA_TI_TXFR_LEN_XLENGTH(x):
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return x & 0xffff
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def DMA_TI_STRIDE_D_STRIDE(x):
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return (x & 0xffff) << 16
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def DMA_TI_STRIDE_S_STRIDE(x):
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return x & 0xffff
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def DMA_CS_PRIORITY(x):
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return (x & 0xf) << 16
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def DMA_CS_PANIC_PRIORITY(x):
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return (x & 0xf) << 20
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DMA_TI_PER_MAP = (lambda x: x << 16)
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DMA_TI_TXFR_LEN_YLENGTH = (lambda y: (y & 0x3fff) << 16)
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DMA_TI_TXFR_LEN_XLENGTH = (lambda x: x & 0xffff)
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DMA_TI_STRIDE_D_STRIDE = (lambda x: (x & 0xffff) << 16)
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DMA_TI_STRIDE_S_STRIDE = (lambda x: x & 0xffff)
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DMA_CS_PRIORITY = (lambda x: (x & 0xf) << 16)
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DMA_CS_PANIC_PRIORITY = (lambda x: (x & 0xf) << 20)
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# hardware PWM controller registers
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PWM_BASE = 0x0020C000
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PHYSICAL_PWM_BUS = 0x7E000000 + PWM_BASE
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PWM_CTL= 0x00
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PWM_CTL = 0x00
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PWM_DMAC = 0x08
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PWM_RNG1 = 0x10
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PWM_RNG2 = 0x20
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@@ -95,12 +81,8 @@ PWM_CTL_CLRF = 1 << 6
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PWM_CTL_USEF1 = 1 << 5
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PWM_CTL_USEF2 = 1 << 13
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PWM_DMAC_ENAB = 1 << 31
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def PWM_DMAC_PANIC(x):
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return x << 8
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def PWM_DMAC_DREQ(x):
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return x
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PWM_DMAC_PANIC = (lambda x: x << 8)
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PWM_DMAC_DREQ = (lambda x: x)
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# clock manager module
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CM_BASE = 0x00101000
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@@ -113,14 +95,13 @@ CM_CNTL_ENABLE = 1 << 4
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CM_CNTL_BUSY = 1 << 7
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CM_SRC_OSC = 1 # 19.2 MHz
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CM_SRC_PLLC = 5 # 1000 MHz
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CM_SRC_PLLD = 6 # 500 MHz
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CM_SRC_HDMI = 7 # 216 MHz
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def CM_DIV_VALUE(x):
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return x << 12
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CM_SRC_PLLD = 6 # 500 MHz
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CM_SRC_HDMI = 7 # 216 MHz
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CM_DIV_VALUE = (lambda x: x << 12)
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class PhysicalMemory(object):
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# noinspection PyArgumentList,PyArgumentList
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def __init__(self, phys_address, size=PAGE_SIZE):
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""" Create object which maps physical memory to Python's mmap object.
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:param phys_address: based address of physical memory
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@@ -128,14 +109,14 @@ class PhysicalMemory(object):
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self._size = size
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phys_address -= phys_address % PAGE_SIZE
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fd = self._open_dev("/dev/mem")
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self._rmap = mmap.mmap(fd, size, flags=mmap.MAP_SHARED,
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prot=mmap.PROT_READ | mmap.PROT_WRITE,
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offset=phys_address)
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self._memmap = mmap.mmap(fd, size, flags=mmap.MAP_SHARED,
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prot=mmap.PROT_READ | mmap.PROT_WRITE,
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offset=phys_address)
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self._close_dev(fd)
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atexit.register(self.cleanup)
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def cleanup(self):
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self._rmap.close()
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self._memmap.close()
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@staticmethod
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def _open_dev(name):
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@@ -149,13 +130,13 @@ class PhysicalMemory(object):
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os.close(fd)
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def write_int(self, address, int_value):
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ctypes.c_uint32.from_buffer(self._rmap, address).value = int_value
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ctypes.c_uint32.from_buffer(self._memmap, address).value = int_value
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def write(self, address, fmt, data):
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struct.pack_into(fmt, self._rmap, address, *data)
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struct.pack_into(fmt, self._memmap, address, *data)
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def read_int(self, address):
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return ctypes.c_uint32.from_buffer(self._rmap, address).value
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return ctypes.c_uint32.from_buffer(self._memmap, address).value
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def get_size(self):
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return self._size
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@@ -177,8 +158,8 @@ class CMAPhysicalMemory(PhysicalMemory):
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if self._handle == 0:
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raise OSError("No memory to allocate with /dev/vcio")
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# lock memory
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self._busmem = self._send_data(0x3000d, [self._handle])
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if self._busmem == 0:
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self._bus_memory = self._send_data(0x3000d, [self._handle])
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if self._bus_memory == 0:
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# memory should be freed in __del__
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raise OSError("Failed to lock memory with /dev/vcio")
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# print("allocate {} at {} (bus {})".format(size,
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@@ -206,10 +187,10 @@ class CMAPhysicalMemory(PhysicalMemory):
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return data[5]
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def get_bus_address(self):
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return self._busmem
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return self._bus_memory
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def get_phys_address(self):
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return self._busmem & ~0xc0000000
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return self._bus_memory & ~0xc0000000
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class DMAProto(object):
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@@ -219,7 +200,7 @@ class DMAProto(object):
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"""
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self._DMA_CHANNEL = dma_channel
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# allocate buffer for control blocks
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self._physmem = CMAPhysicalMemory(memory_size)
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self._phys_memory = CMAPhysicalMemory(memory_size)
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# prepare dma registers memory map
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self._dma = PhysicalMemory(PERI_BASE + DMA_BASE)
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@@ -228,7 +209,8 @@ class DMAProto(object):
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"""
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address = 0x100 * self._DMA_CHANNEL
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self._dma.write_int(address + DMA_CS, DMA_CS_END)
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self._dma.write_int(address + DMA_CONBLK_AD, self._physmem.get_bus_address())
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self._dma.write_int(address + DMA_CONBLK_AD,
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self._phys_memory.get_bus_address())
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cs = DMA_CS_PRIORITY(7) | DMA_CS_PANIC_PRIORITY(7) | DMA_CS_DISDEBUG
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self._dma.write_int(address + DMA_CS, cs)
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cs |= DMA_CS_ACTIVE
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