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patch du noyau pour la pengwyn

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BENOIT Vincent
2023-02-14 07:42:13 +00:00
parent c42cbb991a
commit 20607eed67
6 changed files with 451 additions and 40 deletions
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recipes-kernel/dts/files/am335x-pengwyn.dts
+38 -30
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@@ -69,9 +69,9 @@
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) /* spi0_d0_mosi, external pullup */
AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) /* spi0_d1_miso */
AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) /* spi0_d1_miso */
AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) /* external pullup */
>;
};
@@ -285,13 +285,6 @@
status = "okay";
};
//&uart1 {
// pinctrl-names = "default";
// pinctrl-0 = <&uart1_pins>;
//
// status = "disabled";
//};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -338,29 +331,35 @@
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; /* SPI0_CS0 */
status = "okay";
//ti,pindir-do-out-d1-in;
status = "disabled";
ti,pindir-d0-out-d1-in;
ti,spi-num-cs = <1>;
interrupt-parent = <&intc>;
interrupt = <65>;
dmas = <&edma 16
&edma 17
&edma 18
&edma 19>;
dma-names = "tx0", "rx0", "tx1", "rx1";
/*
spidev@0 {
tpm@0 {
// number of cells required to define a chip select address on the SPI bus.
#address-cells = <1>;
// should be zero
#size-cells = <0>;
// name of SPI bus controller following generic names recommended practice
compatible = "infineon,slb9670";
spi-max-frequency = <3200000>;
reg = <0>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <1>;
};
*/
slb9670@0 {
// number of cells required to define a chip select address on the SPI bus.
//#address-cells = <1>;
// should be zero
//#size-cells = <0>;
// name of SPI bus controller following generic names recommended practice
compatible = "infineon,slb9670";
spi-max-frequency = <32000000>;
reg = <0>;
//num-cs = <1>;
//gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
//status = "okay";
};
};
&spi1 {
@@ -368,16 +367,25 @@
pinctrl-0 = <&spi1_pins>;
cs-gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; /* SPI1_CS0 */
status = "okay";
//ti,pindir-do-out-d1-in;
ti,pindir-d0-out-d1-in;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&intc>;
interrupt = <125>;
dmas = <&edma 42
&edma 43
&edma 44
&edma 45>;
dma-names = "tx0", "rx0", "tx1", "rx1";
slb9670@0 {
// number of cells required to define a chip select address on the SPI bus.
//#address-cells = <1>;
#address-cells = <1>;
// should be zero
//#size-cells = <0>;
#size-cells = <0>;
// name of SPI bus controller following generic names recommended practice
compatible = "infineon,slb9670";
spi-max-frequency = <33000000>;
spi-max-frequency = <10000000>;
reg = <0>;
};