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arm-bsp/firmware-image-juno: remove dependency on Linaro firmware archive
The Juno firmware recipe currently depends on the juno-latest-oe-uboot.zip archive hosted on Linaro. That archive is no longer available, making the recipe impossible to build from scratch. Replace the archive dependency with the individual firmware files required to recreate the original directory layout. The recipe now assembles the firmware tree during do_install(), generating the small board-specific differences where appropriate. The original archive contained duplicate copies of mbb_v151.ebf, io_b118.bit, and tapid.arm under the HBI0262B/C/D directories. The only meaningful differences between those directories are the PMS firmware filename and references to it, so the recipe generates the board-specific files with sed rather than storing duplicate copies. Similarly, the SITE1 images.txt files only differ in the referenced DTB, so those are generated from a common template. Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Jon Mason
@@ -12,19 +12,27 @@ PACKAGE_ARCH = "${MACHINE_ARCH}"
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COMPATIBLE_MACHINE = "juno"
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LINARO_RELEASE = "19.06"
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SRC_URI = "http://releases.linaro.org/members/arm/platforms/${LINARO_RELEASE}/juno-latest-oe-uboot.zip;subdir=${S} \
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file://images-r0.txt \
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file://images-r1.txt \
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file://images-r2.txt \
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SRC_URI = " \
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file://mbb_v151.ebf \
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file://io_b118.bit \
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file://tapid.arm \
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file://pms_v103.bin \
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file://pms_v104.bin \
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file://pms_v105.bin \
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file://mb-board.txt \
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file://site1-HBI0262B-board.txt \
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file://site1-HBI0262C-board.txt \
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file://site1-HBI0262D-board.txt \
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file://site1-images.txt \
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file://hdlcdclk.dat \
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file://startup.nsh \
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file://selftest \
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file://config.txt \
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file://uEnv.txt \
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"
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SRC_URI[md5sum] = "01b662b81fa409d55ff298238ad24003"
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SRC_URI[sha256sum] = "b8a3909bb3bc4350a8771b863193a3e33b358e2a727624a77c9ecf13516cec82"
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FIRMWARE_DIR = "juno-firmware-${LINARO_RELEASE}"
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S = "${UNPACKDIR}/${FIRMWARE_DIR}"
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FIRMWARE_DIR = "juno-firmware"
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S = "${UNPACKDIR}"
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inherit deploy nopackages
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@@ -34,23 +42,63 @@ do_compile[noexec] = "1"
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# The ${D} is used as a temporary directory and we don't generate any
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# packages for this recipe.
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do_install() {
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cp -a ${S} ${D}/
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install -d ${D}/${FIRMWARE_DIR}/
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cp -f ${UNPACKDIR}/config.txt ${D}/${FIRMWARE_DIR}/
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# Files in the MB directory are mostly the same, except for the PMS file and references to the PMS file by name
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install -d ${D}/${FIRMWARE_DIR}/MB/HBI0262B/
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cp -f ${UNPACKDIR}/mbb_v151.ebf ${D}/${FIRMWARE_DIR}/MB/HBI0262B/
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cp -f ${UNPACKDIR}/io_b118.bit ${D}/${FIRMWARE_DIR}/MB/HBI0262B/
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cp -f ${UNPACKDIR}/tapid.arm ${D}/${FIRMWARE_DIR}/MB/HBI0262B/
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cp -f ${UNPACKDIR}/pms_v103.bin ${D}/${FIRMWARE_DIR}/MB/HBI0262B/
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cp -f ${UNPACKDIR}/mb-board.txt ${D}/${FIRMWARE_DIR}/MB/HBI0262B/board.txt
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install -d ${D}/${FIRMWARE_DIR}/MB/HBI0262C/
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cp -f ${UNPACKDIR}/mbb_v151.ebf ${D}/${FIRMWARE_DIR}/MB/HBI0262C/
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cp -f ${UNPACKDIR}/io_b118.bit ${D}/${FIRMWARE_DIR}/MB/HBI0262C/
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cp -f ${UNPACKDIR}/tapid.arm ${D}/${FIRMWARE_DIR}/MB/HBI0262C/
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cp -f ${UNPACKDIR}/pms_v104.bin ${D}/${FIRMWARE_DIR}/MB/HBI0262C/
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sed 's/pms_v103/pms_v104/g' ${UNPACKDIR}/mb-board.txt > ${D}/${FIRMWARE_DIR}/MB/HBI0262C/board.txt
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install -d ${D}/${FIRMWARE_DIR}/MB/HBI0262D/
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cp -f ${UNPACKDIR}/mbb_v151.ebf ${D}/${FIRMWARE_DIR}/MB/HBI0262D/
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cp -f ${UNPACKDIR}/io_b118.bit ${D}/${FIRMWARE_DIR}/MB/HBI0262D/
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cp -f ${UNPACKDIR}/tapid.arm ${D}/${FIRMWARE_DIR}/MB/HBI0262D/
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cp -f ${UNPACKDIR}/pms_v105.bin ${D}/${FIRMWARE_DIR}/MB/HBI0262D/
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sed 's/pms_v103/pms_v105/g' ${UNPACKDIR}/mb-board.txt > ${D}/${FIRMWARE_DIR}/MB/HBI0262D/board.txt
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# The SITE1 image files are mostly the same except for the DTB they reference
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install -d ${D}/${FIRMWARE_DIR}/SITE1/HBI0262B/
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cp -f ${UNPACKDIR}/site1-HBI0262B-board.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262B/board.txt
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cp -f ${UNPACKDIR}/site1-images.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262B/images.txt
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install -d ${D}/${FIRMWARE_DIR}/SITE1/HBI0262C/
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cp -f ${UNPACKDIR}/site1-HBI0262C-board.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262C/board.txt
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sed 's/juno\.dtb/juno-r1.dtb/g' ${UNPACKDIR}/site1-images.txt > ${D}/${FIRMWARE_DIR}/SITE1/HBI0262C/images.txt
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install -d ${D}/${FIRMWARE_DIR}/SITE1/HBI0262D/
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cp -f ${UNPACKDIR}/site1-HBI0262D-board.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262D/board.txt
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sed 's/juno\.dtb/juno-r2.dtb/g' ${UNPACKDIR}/site1-images.txt > ${D}/${FIRMWARE_DIR}/SITE1/HBI0262D/images.txt
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# The files in SOFTWARE are listed in the SITE1 board.txt file by name
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install -d ${D}/${FIRMWARE_DIR}/SOFTWARE/
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cp -f ${RECIPE_SYSROOT}/firmware/trusted-firmware-a/fip.bin \
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${D}/${FIRMWARE_DIR}/SOFTWARE/fip.bin
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cp -f ${RECIPE_SYSROOT}/firmware/trusted-firmware-a/bl1.bin \
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${D}/${FIRMWARE_DIR}/SOFTWARE/bl1.bin
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cp -f ${RECIPE_SYSROOT}/firmware/trusted-firmware-a/fip.bin \
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${D}/${FIRMWARE_DIR}/SOFTWARE/fip.bin
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cp -f ${UNPACKDIR}/hdlcdclk.dat ${D}/${FIRMWARE_DIR}/SOFTWARE/
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cp -f ${RECIPE_SYSROOT}/firmware/scp-firmware/scp_romfw_bypass.bin \
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${D}/${FIRMWARE_DIR}/SOFTWARE/scp_bl1.bin
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cp -f ${UNPACKDIR}/startup.nsh ${D}/${FIRMWARE_DIR}/SOFTWARE/
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cp -f ${UNPACKDIR}/selftest ${D}/${FIRMWARE_DIR}/SOFTWARE/
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dd if=/dev/zero of="${D}/${FIRMWARE_DIR}/SOFTWARE/blank.img" bs=1024 count=192 status=none
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# u-boot environment file
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cp -f ${UNPACKDIR}/uEnv.txt ${D}/${FIRMWARE_DIR}/SOFTWARE/
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# Juno images list file
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cp -f ${UNPACKDIR}/images-r0.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262B/images.txt
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cp -f ${UNPACKDIR}/images-r1.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262C/images.txt
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cp -f ${UNPACKDIR}/images-r2.txt ${D}/${FIRMWARE_DIR}/SITE1/HBI0262D/images.txt
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}
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do_deploy() {
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@@ -0,0 +1,28 @@
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TITLE: V2M-Juno Configuration File
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[CONFIGURATION]
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AUTORUN: TRUE ;Auto Run from power on
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TESTMENU: FALSE ;MB Peripheral Test Menu
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UPDATE: FALSE ;Force JTAG and FPGA update to DBs
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VERIFY: FALSE ;Force FPGA verify to DBs
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DVIMODE: VGA ;VGA or SVGA or XGA or SXGA or UXGA
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MBLOG: FALSE ;LOG MB MICRO in run mode FALSE/UART0/UART1
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DBLOG: FALSE ;LOG DB MICRO in run mode FALSE/UART1 (when MBLOG is not UART1)
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USERSWITCH: 00000000 ;UserSwitch[7:0] in binary
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CONFSWITCH: 00000000 ;Configuration Switch[7:0] in binary, Core[0:1] Cluster[2]
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ASSERTNPOR: TRUE ;External resets assert nPOR
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WDTRESET: RESETMB ;Watchdog reset options NONE/RESETMB/RESETDB
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PCIMASTER: DB1 ;Port Failover DB1/SL3
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MASTERSITE: DB1 ;Boot Master DB1/SL3
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REMOTE: NONE ;Selects remote command via USB or FTP NONE/USB/FTP
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MCCMACADDRESS: 0xFFFFFFFFFFFF ;MCC MAC Address (must be even MAC address)
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SMCMACADDRESS: 0xFFFFFFFFFFFF ;SMC MAC Address
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HOSTNAME: V2M-JUNO-A2 ;Host name for FTP [15 characters max]
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Binary file not shown.
@@ -1,71 +0,0 @@
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TITLE: Versatile Express Images Configuration File
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[IMAGES]
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TOTALIMAGES: 10 ;Number of Images (Max: 32)
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NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR0ADDRESS: 0x00000000 ;Image Flash Address
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NOR0FILE: \SOFTWARE\fip.bin ;Image File Name
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NOR0LOAD: 00000000 ;Image Load Address
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NOR0ENTRY: 00000000 ;Image Entry Point
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NOR1UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR1ADDRESS: 0x03EC0000 ;Image Flash Address
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NOR1FILE: \SOFTWARE\bl1.bin ;Image File Name
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NOR1LOAD: 00000000 ;Image Load Address
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NOR1ENTRY: 00000000 ;Image Entry Point
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NOR2UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR2ADDRESS: 0x00500000 ;Image Flash Address
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NOR2FILE: \SOFTWARE\Image ;Image File Name
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NOR2NAME: norkern ;Rename kernel to norkern
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NOR2LOAD: 00000000 ;Image Load Address
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NOR2ENTRY: 00000000 ;Image Entry Point
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NOR3UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR3ADDRESS: 0x03000000 ;Image Flash Address
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NOR3FILE: \SOFTWARE\juno-r1.dtb ;Image File Name
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NOR3NAME: board.dtb ;Specify target filename to preserve file extension
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NOR3LOAD: 00000000 ;Image Load Address
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NOR3ENTRY: 00000000 ;Image Entry Point
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NOR4UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR4ADDRESS: 0x030C0000 ;Image Flash Address
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NOR4FILE: \SOFTWARE\hdlcdclk.dat ;Image File Name
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NOR4LOAD: 00000000 ;Image Load Address
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NOR4ENTRY: 00000000 ;Image Entry Point
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NOR5UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR5ADDRESS: 0x03E40000 ;Image Flash Address
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NOR5FILE: \SOFTWARE\scp_bl1.bin ;Image File Name
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NOR5LOAD: 00000000 ;Image Load Address
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NOR5ENTRY: 00000000 ;Image Entry Point
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NOR6UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR6ADDRESS: 0x0BF00000 ;Image Flash Address
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NOR6FILE: \SOFTWARE\startup.nsh ;Image File Name
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NOR6NAME: startup.nsh
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NOR6LOAD: 00000000 ;Image Load Address
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NOR6ENTRY: 00000000 ;Image Entry Point
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NOR7UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR7ADDRESS: 0x0BFC0000 ;Image Flash Address
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NOR7FILE: \SOFTWARE\blank.img ;Image File Name
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NOR7NAME: BOOTENV
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NOR7LOAD: 00000000 ;Image Load Address
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NOR7ENTRY: 00000000 ;Image Entry Point
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NOR8UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR8ADDRESS: 0x03100000 ;Image Flash Address
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NOR8FILE: \SOFTWARE\selftest ;Image File Name
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NOR8LOAD: 00000000 ;Image Load Address
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NOR8ENTRY: 00000000 ;Image Entry Point
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NOR9UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR9ADDRESS: 0x03180000 ;Image Flash Address
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NOR9NAME: uEnv.txt
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NOR9FILE: \SOFTWARE\uEnv.txt ;Image File Name
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NOR9LOAD: 00000000 ;Image Load Address
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NOR9ENTRY: 00000000 ;Image Entry Point
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@@ -1,71 +0,0 @@
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TITLE: Versatile Express Images Configuration File
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[IMAGES]
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TOTALIMAGES: 10 ;Number of Images (Max: 32)
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NOR0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR0ADDRESS: 0x00000000 ;Image Flash Address
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NOR0FILE: \SOFTWARE\fip.bin ;Image File Name
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NOR0LOAD: 00000000 ;Image Load Address
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NOR0ENTRY: 00000000 ;Image Entry Point
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NOR1UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR1ADDRESS: 0x03EC0000 ;Image Flash Address
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NOR1FILE: \SOFTWARE\bl1.bin ;Image File Name
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NOR1LOAD: 00000000 ;Image Load Address
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NOR1ENTRY: 00000000 ;Image Entry Point
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NOR2UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR2ADDRESS: 0x00500000 ;Image Flash Address
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NOR2FILE: \SOFTWARE\Image ;Image File Name
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NOR2NAME: norkern ;Rename kernel to norkern
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NOR2LOAD: 00000000 ;Image Load Address
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NOR2ENTRY: 00000000 ;Image Entry Point
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NOR3UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR3ADDRESS: 0x03000000 ;Image Flash Address
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NOR3FILE: \SOFTWARE\juno-r2.dtb ;Image File Name
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NOR3NAME: board.dtb ;Specify target filename to preserve file extension
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NOR3LOAD: 00000000 ;Image Load Address
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NOR3ENTRY: 00000000 ;Image Entry Point
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NOR4UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR4ADDRESS: 0x030C0000 ;Image Flash Address
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NOR4FILE: \SOFTWARE\hdlcdclk.dat ;Image File Name
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NOR4LOAD: 00000000 ;Image Load Address
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NOR4ENTRY: 00000000 ;Image Entry Point
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NOR5UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR5ADDRESS: 0x03E40000 ;Image Flash Address
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NOR5FILE: \SOFTWARE\scp_bl1.bin ;Image File Name
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NOR5LOAD: 00000000 ;Image Load Address
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NOR5ENTRY: 00000000 ;Image Entry Point
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NOR6UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR6ADDRESS: 0x0BF00000 ;Image Flash Address
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NOR6FILE: \SOFTWARE\startup.nsh ;Image File Name
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NOR6NAME: startup.nsh
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NOR6LOAD: 00000000 ;Image Load Address
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NOR6ENTRY: 00000000 ;Image Entry Point
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NOR7UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR7ADDRESS: 0x0BFC0000 ;Image Flash Address
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NOR7FILE: \SOFTWARE\blank.img ;Image File Name
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NOR7NAME: BOOTENV
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NOR7LOAD: 00000000 ;Image Load Address
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NOR7ENTRY: 00000000 ;Image Entry Point
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NOR8UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR8ADDRESS: 0x03100000 ;Image Flash Address
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NOR8FILE: \SOFTWARE\selftest ;Image File Name
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NOR8LOAD: 00000000 ;Image Load Address
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NOR8ENTRY: 00000000 ;Image Entry Point
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NOR9UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
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NOR9ADDRESS: 0x03180000 ;Image Flash Address
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NOR9NAME: uEnv.txt
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NOR9FILE: \SOFTWARE\uEnv.txt ;Image File Name
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NOR9LOAD: 00000000 ;Image Load Address
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NOR9ENTRY: 00000000 ;Image Entry Point
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Binary file not shown.
@@ -0,0 +1,26 @@
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BOARD: HBI0262
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TITLE: MotherBoard Configuration File
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[MCCS]
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MBBIOS: mbb_v151.ebf ;MB BIOS IMAGE
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[FPGAS]
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MBIOFPGA: io_b118.bit ;MB IOFPGA
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[PMIC]
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MBPMIC: pms_v103.bin ;MB PMIC
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[OSCCLKS]
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TOTALOSCCLKS: 11
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OSC0: 50.0 ;OSC0 Juno SYSREFCLK (System clock)
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OSC1: 50.0 ;OSC1 Juno AONREFCLK (Always On)
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OSC2: 50.0 ;OSC2 Juno PXLREFCLK (HS pixel clock)
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OSC3: 47.5 ;OSC3 Juno PXCLKIN (LS pixel clock)
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OSC4: 2.11 ;OSC4 Juno I2SCLK (Audio)
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OSC5: 50.0 ;OSC5 Juno SMCMCLK (Static memory)
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OSC6: 50.0 ;OSC6 Juno CA53 REF_CLK (RSVD)
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OSC7: 50.0 ;OSC7 Juno CA57 REF_CLK (RSVD)
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OSC8: 50.0 ;OSC8 Juno GPU REF_CLK (RSVD)
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OSC9: 30.0 ;OSC9 IOFPGA BOOT (RSVD)
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OSC10: 24.0 ;OSC10 IOFPGA UART (RSVD)
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OSC11: 7.37 ;OSC11 Juno UARTCLK (UART clock)
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Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,22 @@
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BOARD: HBI0262
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TITLE: V2M-Juno DevChip Configuration File
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[SCC REGISTERS]
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TOTALSCCS: 12 ;Total Number of SCC registers
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SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
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SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
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SCC: 0x100 0x003F1000 ;A57 PLL Register 0 (800MHz)
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SCC: 0x104 0x0001F300 ;A57 PLL Register 1
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SCC: 0x108 0x00371000 ;A53 PLL Register 0 (700MHz)
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SCC: 0x10C 0x0001B300 ;A53 PLL Register 1
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SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
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SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
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SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
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SCC: 0x0FC 0xABE40000 ;BL0 entry point
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SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
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;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
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;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
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SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
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;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
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;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
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@@ -0,0 +1,24 @@
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BOARD: HBI0262
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TITLE: V2M-Juno DevChip Configuration File
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[SCC REGISTERS]
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TOTALSCCS: 13 ;Total Number of SCC registers
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SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
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SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
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SCC: 0x100 0x003F1000 ;A57 PLL Register 0 (800MHz)
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SCC: 0x104 0x0001F300 ;A57 PLL Register 1
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SCC: 0x108 0x00331000 ;A53 PLL Register 0 (650MHz)
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SCC: 0x10C 0x00019300 ;A53 PLL Register 1
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SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
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SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
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SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
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SCC: 0x0FC 0xABE40000 ;BL0 entry point
|
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SCC: 0xA14 0x00000000 ;PCLKDBG_CONTROL DIV=1
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||||
|
||||
SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
|
||||
;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
|
||||
;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
|
||||
SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
|
||||
;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
|
||||
;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
BOARD: HBI0262
|
||||
TITLE: V2M-Juno DevChip Configuration File
|
||||
|
||||
[SCC REGISTERS]
|
||||
TOTALSCCS: 13 ;Total Number of SCC registers
|
||||
SCC: 0x054 0x0007FFFE ;Enable non-secure DMA operations
|
||||
SCC: 0x05C 0x00FE001E ;Enable default GPU Texture Formats
|
||||
SCC: 0x100 0x00271000 ;A72 PLL Register 0 (1000MHz)
|
||||
SCC: 0x104 0x00013100 ;A72 PLL Register 1
|
||||
SCC: 0x108 0x003F1000 ;A53 PLL Register 0 (800MHz)
|
||||
SCC: 0x10C 0x0001F300 ;A53 PLL Register 1
|
||||
SCC: 0x118 0x003F1000 ;SYS PLL Register 0 (1600MHz)
|
||||
SCC: 0x11C 0x0001F100 ;SYS PLL Register 1
|
||||
SCC: 0x0F8 0x0BEC0000 ;BL1 entry point
|
||||
SCC: 0x0FC 0xABE40000 ;BL0 entry point
|
||||
|
||||
SCC: 0xA14 0x00000000 ;PCLKDBG_CONTROL DIV=1
|
||||
|
||||
SCC: 0x00C 0x000000C2 ;Clock Control, TMIF2XCLK, Register 0xC1 = default
|
||||
;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
|
||||
;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
|
||||
SCC: 0x010 0x000000C2 ;Clock Control, TSIF2XCLK, Register 0xC1 = default
|
||||
;[3:0] CLKSEL : 0 Output gated, 1 AON_REF_CLK, 2 SYSCLK
|
||||
;[7:4] CLKDIV : Clock divider -1 (0 give a division of 1)
|
||||
@@ -0,0 +1,4 @@
|
||||
echo -off
|
||||
echo Juno startup.nsh from NOR flash
|
||||
echo Example command to start the kernel:
|
||||
echo norkern dtb=board.dtb initrd=ramdisk.img console=ttyAMA0,115200n8 root=/dev/sda2 rw rootwait earlyprintk=pl011,0x7ff80000 debug user_debug=31 androidboot.hardware=juno loglevel=9 sky2.mac_address=0xAA,0xBB,0xCC,0xDD,0xEE,0xFF
|
||||
@@ -0,0 +1,97 @@
|
||||
# ARM TAP controller IR register lengths file
|
||||
#
|
||||
# Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This file contains a definition of the devices names, ID codes, ID code mask
|
||||
# and IR lengths for devices used on ARM boards. This file is read by the
|
||||
# progcards_usb.exe program and used to determine if a device ID is valid and
|
||||
# the corresponding IR length. A device that is not recognized will be display
|
||||
# as 'UNKOWN' and device details should be added to this file.
|
||||
#
|
||||
# DEVICE NAME ID CODE ID MASK IR LENGTH
|
||||
# ------------- ---------- ---------- ---------
|
||||
|
||||
# XILINX PLDs
|
||||
|
||||
XC9572 0x09504093 0x0FFFFFFF 8
|
||||
XC9536XL 0x29602093 0x0FFFFFFF 8
|
||||
XC9572XL 0x09604093 0x0FFFFFFF 8
|
||||
XC95288XL 0x09616093 0x0FFFFFFF 8
|
||||
XCR3256XL 0xF494FFFF 0x0FFF8001 4
|
||||
XC4036XLA 0x00224093 0x00FFFFFF 3
|
||||
XC4062XLA 0x00230093 0x00FFFFFF 3
|
||||
XC4085XLA 0x00238093 0x00FFFFFF 3
|
||||
XC2C32A 0x06E1C093 0x0FFF0FFF 8
|
||||
XC2C64A 0x06E5D093 0x0FFF0FFF 8
|
||||
XC2C128 0x06D8A093 0x0FFF0FFF 8
|
||||
XC2C256 0x16D4c093 0x0FFF0FFF 8
|
||||
XC2C384 0x06D5C093 0x0FFF0FFF 8
|
||||
|
||||
# XILINX FPGAs
|
||||
|
||||
XCV600 0x10630093 0x00FFFFFF 5
|
||||
XCV600E 0x90A30093 0x00FFFFFF 5
|
||||
XCV1000 0x40640093 0x0FFFFFFF 5
|
||||
XCV2000E 0xF0A50093 0x0FFFFFFF 5
|
||||
XC2V2000 0x01038093 0x0FFFFFFF 6
|
||||
XC2V6000 0x31060093 0x0FFFFFFF 6
|
||||
XC2V8000 0x01070093 0x0FFFFFFF 6
|
||||
XC4VLX40 0x316A4093 0x0FFFFFFF 10
|
||||
XC4VLX160 0x01718093 0x0FFFFFFF 10
|
||||
XC4VLX200 0x01734093 0x0FFFFFFF 10
|
||||
XC5VLX50T 0x02A96093 0x0FFFFFFF 10
|
||||
XC5VLX110 0x228D6093 0x0FFFFFFF 10
|
||||
XC5VLX330 0x2295C093 0x0FFFFFFF 10
|
||||
XC2S200E 0x20A1C093 0x0FFFFFFF 5
|
||||
XC2S300E 0x90A20093 0x0FFFFFFF 5
|
||||
XC3S200A 0x02218093 0x0FFFFFFF 6
|
||||
XC3S4000 0x01448093 0x0FFFFFFF 6
|
||||
XC6SLX45 0x04008093 0x0FFFFFFF 6
|
||||
|
||||
# ARM
|
||||
|
||||
ARM7TDMI 0x3F0F0F0F 0xFFFFFFFF 4
|
||||
ARM7TDMI-r4 0x40700F0F 0xFFFFFFFF 4
|
||||
ARM720T 0x0F0F0F0F 0xFFFFFFFF 4
|
||||
ARM920T 0x10920F0F 0xFFFFFFFF 4
|
||||
ARM926EJ-S 0x07926F0F 0xFFFFFFFF 4
|
||||
ARM940T 0x1F0F0F0F 0xFFFFFFFF 4
|
||||
ARM10200 0x00A20F0F 0xFFFFFFFF 4
|
||||
ARMFLASH 0x0F0E5F2F 0xFFFFFFFF 5
|
||||
ARMDBT 0x00000F0F 0xFFFFFFFF 5
|
||||
PWP926EJ-S_BS2 0x0F21FF0F 0xFFFFFFFF 2
|
||||
ARM_BS2_ 0x0F203F0F 0xFFFFFFFF 2
|
||||
ARM1136J-Sr0_BS2 0x0F21DF0F 0xFFFFFFFF 2
|
||||
ARM11MPCore_BS5 0x17536021 0xFFFFFFFF 5
|
||||
PXP1176JZF_BS2 0x0F2258EF 0xFFFFFFFF 2
|
||||
CORTEXA8 0x0F423477 0xFFFFFFFF 4
|
||||
CORTEXA9 0x08226021 0xFFFFFFFF 4
|
||||
|
||||
# ALTERA
|
||||
|
||||
EPM3032A 0x170320DD 0xFFFFFFFF 10
|
||||
EPM7256AE 0x172560DD 0xFFFFFFFF 10
|
||||
EPM7512AE 0x175120DD 0xFFFFFFFF 10
|
||||
EPM1270 0x020A30DD 0xFFFFFFFF 10
|
||||
EP20K1000E 0x090000DD 0xFFFFFFFF 10
|
||||
EP2S180F 0x020960DD 0xFFFFFFFF 10
|
||||
|
||||
# Misc
|
||||
|
||||
ispClock5520 0x00150043 0xFFFFFFFF 8
|
||||
ispClock5620 0x00160043 0xFFFFFFFF 8
|
||||
ispClock5610V 0x00161043 0xFFFFFFFF 8
|
||||
ispClock5610AV 0x00166043 0xFFFFFFFF 8
|
||||
ISSP 0x0F0F0F0F 0x0FFFFFFF 5
|
||||
Mali200 0x10400477 0xFFFFFFFF 2
|
||||
PLX6520 0x3197839B 0xFFFFFFFF 5
|
||||
PLX8114 0x21FB239B 0xFFFFFFFF 5
|
||||
PLX8518 0x1214639B 0xFFFFFFFF 5
|
||||
PLX8518 0x4214639B 0xFFFFFFFF 5
|
||||
|
||||
STM32TMC 0x16410041 0x0FFF0FFF 5
|
||||
STM32CM3 0x3BA00477 0x0FFFFFFF 4
|
||||
IDT89HPES32H8 0x08035067 0xFFFFFFFF 6
|
||||
IDT89H16NT16 0x28090067 0xFFFFFFFF 6
|
||||
NX5000_BYPASS 0x14951185 0xFFFFFFFF 4
|
||||
NX5000_FC1152 0x03387589 0xFFFFFFFF 4
|
||||
Reference in New Issue
Block a user