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arm-bsp/optee-os:corstone1000: Add Cortex-A320 support
Update the OP-TEE OS build logic to detect `MACHINE_FEATURES` and append the appropriate `arm64-platform-cpuarch` value to `EXTRA_OEMAKE`, instead of hard-coding `cortex-a35`. This change ensures that when `MACHINE_FEATURES` includes `cortexa320`, the OP-TEE build receives the matching `core-arch` flag, while maintaining `cortex-a35` as the default. The new Corstone-1000 variant with Cortex-A320 replaces the original GIC-400 (v2) interrupt controller with a GIC-600, which is architecturally compliant with GICv3. Since OP-TEE already provides a generic GICv3 driver, only minimal platform changes are needed to expose the updated register map and initialize the GICv3 interface. Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com> Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Hugues KAMBA MPIANA
committed by
Jon Mason
Jon Mason
parent
b6b1a81f5e
commit
0faf5c4d37
@@ -0,0 +1,143 @@
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From 4a8fa965a39879d98eac1626c4c756043985726d Mon Sep 17 00:00:00 2001
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From: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
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Date: Tue, 11 Nov 2025 08:09:40 +0000
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Subject: [PATCH] plat-corstone1000: Add Cortex-A320 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
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(default) assignment so users can override it (for example to
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cortex-a320) via the make command line.
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The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
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When arm64-platform-cpuarch is set to cortex-a320, switch to
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-march=armv9.2-a.
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The new Corstone-1000 variant with Cortex-A320 replaces the original
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GIC-400 (v2) interrupt controller with a GIC-600, which is
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architecturally compliant with GICv3. Since OP-TEE already provides
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a generic GICv3 driver, only minimal platform changes are needed
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to expose the updated register map and initialize the GICv3 interface.
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**Changes introduced**
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* When `cortex-a320` is selected:
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* Force `CFG_ARM_GICV3=y`.
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* Introduce `CFG_CORSTONE1000_CORTEX_A320` to guard
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Cortex-A320–specific code.
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* Map the Redistributor region (`GICR_BASE`).
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* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
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* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
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* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
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the Cortex-A35 + GIC-400 variant continues to build unchanged.
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Upstream-Status: Submitted (https://github.com/OP-TEE/optee_os/pull/7627)
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Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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---
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core/arch/arm/plat-corstone1000/conf.mk | 11 ++++++++++-
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core/arch/arm/plat-corstone1000/main.c | 11 ++++++++++-
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.../arm/plat-corstone1000/platform_config.h | 19 +++++++++++++++++--
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3 files changed, 37 insertions(+), 4 deletions(-)
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diff --git a/core/arch/arm/plat-corstone1000/conf.mk b/core/arch/arm/plat-corstone1000/conf.mk
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index 86b8d8480..147b6972f 100644
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--- a/core/arch/arm/plat-corstone1000/conf.mk
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+++ b/core/arch/arm/plat-corstone1000/conf.mk
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@@ -23,9 +23,18 @@ $(call force,CFG_PL011,y)
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$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
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$(call force,CFG_ARM64_core,y)
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-arm64-platform-cpuarch := cortex-a35
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+# Default CPU core for Corstone1000 platform; override for other cores (e.g. cortex-a320)
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+arm64-platform-cpuarch ?= cortex-a35
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+
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+ifeq ($(arm64-platform-cpuarch),cortex-a320)
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+arm64-platform-cflags += -march=armv9.2-a
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+arm64-platform-aflags += -march=armv9.2-a
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+$(call force,CFG_ARM_GICV3,y)
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+$(call force,CFG_CORSTONE1000_CORTEX_A320,y)
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+else
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arm64-platform-cflags += -mcpu=$(arm64-platform-cpuarch)
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arm64-platform-aflags += -mcpu=$(arm64-platform-cpuarch)
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+endif
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CFG_WITH_STATS ?= y
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CFG_WITH_ARM_TRUSTED_FW ?= y
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diff --git a/core/arch/arm/plat-corstone1000/main.c b/core/arch/arm/plat-corstone1000/main.c
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index 9e1482a7b..fd2dd888c 100644
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--- a/core/arch/arm/plat-corstone1000/main.c
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+++ b/core/arch/arm/plat-corstone1000/main.c
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: BSD-2-Clause
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/*
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- * Copyright (c) 2022, Arm Limited
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+ * Copyright (c) 2022, 2025, Arm Limited
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*/
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#include <console.h>
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@@ -18,11 +18,20 @@ register_ddr(DRAM0_BASE, DRAM0_SIZE);
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
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+
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+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
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+register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_REDIST_REG_SIZE);
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+#else
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
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+#endif
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void boot_primary_init_intc(void)
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{
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+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
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+ gic_init_v3(0, GICD_BASE, GICR_BASE);
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+#else
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gic_init(GICC_BASE, GICD_BASE);
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+#endif
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}
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void boot_secondary_init_intc(void)
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diff --git a/core/arch/arm/plat-corstone1000/platform_config.h b/core/arch/arm/plat-corstone1000/platform_config.h
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index f59c93a14..600b2c02e 100644
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--- a/core/arch/arm/plat-corstone1000/platform_config.h
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+++ b/core/arch/arm/plat-corstone1000/platform_config.h
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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- * Copyright (c) 2022, Arm Limited
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+ * Copyright (c) 2022, 2025 Arm Limited
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*/
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#ifndef PLATFORM_CONFIG_H
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@@ -20,11 +20,26 @@
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#define DRAM0_BASE 0x80000000
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#define DRAM0_SIZE CFG_DDR_SIZE
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+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
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+#define GICR_SIZE_PER_CORE 0x20000
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+#define GIC_REDIST_REG_SIZE (GICR_SIZE_PER_CORE * CFG_TEE_CORE_NB_CORE)
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+#endif
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+
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+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
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+/* Corstone-1000 with Cortex-A320 uses GIC-v3 which supports GICR */
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+#define GICD_OFFSET 0x00000
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+#define GICR_OFFSET 0x40000
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+#else
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#define GICD_OFFSET 0x10000
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#define GICC_OFFSET 0x2F000
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+#endif
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-#define GICD_BASE (GIC_BASE + GICD_OFFSET)
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+#if defined(CFG_CORSTONE1000_CORTEX_A320) && defined(CFG_ARM_GICV3)
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+#define GICR_BASE (GIC_BASE + GICR_OFFSET)
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+#else
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#define GICC_BASE (GIC_BASE + GICC_OFFSET)
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+#endif
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+#define GICD_BASE (GIC_BASE + GICD_OFFSET)
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#define UART_BAUDRATE 115200
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#define CONSOLE_BAUDRATE UART_BAUDRATE
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--
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2.50.1
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@@ -1,5 +1,9 @@
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FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/corstone1000:"
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SRC_URI:append = " \
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file://0001-plat-corstone1000-Add-Cortex-A320-support.patch \
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"
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COMPATIBLE_MACHINE = "corstone1000"
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OPTEEMACHINE = "corstone1000"
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@@ -14,3 +18,8 @@ EXTRA_OEMAKE += " CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y"
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EXTRA_OEMAKE += " CFG_WITH_SP=y"
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EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' CFG_TEE_CORE_NB_CORE=4', '', d)}"
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# Override OP-TEE OS ARM64 core architecture based on MACHINE_FEATURES
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CPUARCH = "cortex-a35"
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CPUARCH:cortexa320 = "cortex-a320"
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EXTRA_OEMAKE:append:corstone1000 = " arm64-platform-cpuarch=${CPUARCH}"
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