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arm-bsp/trusted-firmware-m: corstone1000: Drive NPU reset via ext sys ctrl
- Derive host base addresses from offsets and add ext sys reset bitfields - Deassert CPUWAIT with a bitmask - Enable ext sys boot handling for Corstone1000 with Cortex-A320 - Add the new downstream TF‑M patches to the recipe Signed-off-by: Michael Safwat <michael.safwat@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Michael Safwat
committed by
Jon Mason
Jon Mason
parent
d987a59458
commit
2318956135
+111
@@ -0,0 +1,111 @@
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From 37cac6c86f10340382ff950e5e0323f2efbe5ed3 Mon Sep 17 00:00:00 2001
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From: Michael Safwat <michael.safwat@arm.com>
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Date: Wed, 8 Apr 2026 13:02:47 +0100
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Subject: [PATCH 1/2] plat: cs1k: Derive host base addresses from offsets
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Define explicit host register offsets and compute base addresses
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from the common host address space base. This keeps the map
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consistent, and also makes it easy to relocate all addresses if the
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base addresses change.
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Define External System Reset Control bitfields and use them to
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de-assert CPUWAIT when booting the external system, so we can touch
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only the bit of interest instead of zeroing the whole register.
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Change-Id: Id228351926fc846d28d5bf4e4180a995057154b1
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Signed-off-by: Michael Safwat <michael.safwat@arm.com>
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Upstream-Status: Backport [d73cc1dbc2eb72af02de740926f7b3c889bbac4b]
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---
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.../Device/Include/platform_base_address.h | 52 ++++++++++++++-----
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.../arm/corstone1000/tfm_hal_multi_core.c | 5 +-
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2 files changed, 41 insertions(+), 16 deletions(-)
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diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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index 3908d69bc..62ee7d049 100644
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--- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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+++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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@@ -68,23 +68,49 @@
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/* Host base addresses from the SE perspective - partial list, only the ones
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* required by the SE are defined here */
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#define CORSTONE1000_HOST_ADDRESS_SPACE_BASE (0x60000000U) /* Host Address Space */
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-#define CORSTONE1000_HOST_BIR_BASE (0x60000000U) /* Boot Instruction Register */
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-#define CORSTONE1000_HOST_TRUSTED_RAM_BASE (0x62000000U) /* Secure RAM */
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-#define CORSTONE1000_HOST_XNVM_BASE (0x68000000U) /* XNVM */
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-#define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE (0x7A010000U) /* Host SCB */
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-#define CORSTONE1000_EXT_SYS_RESET_REG (0x7A010310U) /* external system (cortex-M3) */
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-#define CORSTONE1000_HOST_FIREWALL_BASE (0x7A800000U) /* Host Firewall */
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-#define CORSTONE1000_HOST_INT_APBCOM_BASE (0x7B900000U) /* Internal APBCOM */
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-#define CORSTONE1000_HOST_FPGA_SCC_REGISTERS (0x80000000U) /* FPGA SCC Registers */
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-#define CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP (0x80010000U) /* SE Flash */
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-#define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE (0x80050000U) /* AXI QSPI Controller */
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-#define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH (0x90010000U) /* AXI QSPI Controller for SE FLash */
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-#define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE (0xA0000000U) /* 1.5 GB DDR */
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+/* Registers offsets - partial list, only the ones
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+ * required by the SE are defined here */
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+#define CORSTONE1000_HOST_BIR_OFFSET (0x00000000U)
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+#define CORSTONE1000_HOST_CVM_OFFSET (0x02000000U)
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+#define CORSTONE1000_HOST_XNVM_OFFSET (0x08000000U)
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+#define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE_OFFSET (0x1A010000U)
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+#define CORSTONE1000_HOST_EXT_SYS0_RST_CTRL_OFFSET (0x310U)
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+#define CORSTONE1000_HOST_FIREWALL_BASE_OFFSET (0x1A800000U)
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+#define CORSTONE1000_HOST_INT_APBCOM_BASE_OFFSET (0x1B900000U)
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+/* The below offsets have been derived from the reserved section.*/
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+#define CORSTONE1000_HOST_FPGA_SCC_REGISTERS_OFFSET (0x20000000U)
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+#define CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP_OFFSET (0x20010000U)
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+#define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_OFFSET (0x20050000U)
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+#define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH_OFFSET (0x30010000U)
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+#define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE_OFFSET (0x40000000U)
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+#define CORSTONE1000_HOST_DSU_120T_BASE_OFFSET (0x60910000U)
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+
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+/* Register Addresses */
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+#define CORSTONE1000_HOST_BIR_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_BIR_OFFSET) /* Boot Instruction Register */
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+#define CORSTONE1000_HOST_TRUSTED_RAM_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_CVM_OFFSET) /* On-chip Volatile Memory */
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+#define CORSTONE1000_HOST_XNVM_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_XNVM_OFFSET) /* eXecute-in-place Non-volatile Memory */
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+#define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE_OFFSET) /* Security Control Bits */
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+#define CORSTONE1000_EXT_SYS_RESET_REG (CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE + CORSTONE1000_HOST_EXT_SYS0_RST_CTRL_OFFSET) /* External System (Cortex-M3) */
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+#define CORSTONE1000_HOST_FIREWALL_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_FIREWALL_BASE_OFFSET) /* System Firewall */
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+#define CORSTONE1000_HOST_INT_APBCOM_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_INT_APBCOM_BASE_OFFSET) /* Internal Advanced Peripheral Bus Communication */
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+#define CORSTONE1000_HOST_FPGA_SCC_REGISTERS (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_FPGA_SCC_REGISTERS_OFFSET) /* FPGA Serial Communication Controller Registers */
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+#define CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP_OFFSET) /* Secure Enclave Flash */
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+#define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_OFFSET) /* AXI QSPI Controller */
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+#define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH_OFFSET) /* AXI QSPI Controller for SE FLash */
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+#define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_DRAM_UEFI_CAPSULE_OFFSET) /* DDR RAM (1.5 GB) */
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#ifdef CORSTONE1000_DSU_120T
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-#define CORSTONE1000_HOST_DSU_120T_BASE (0xC0910000U) /* DSU-120T PPU */
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+#define CORSTONE1000_HOST_DSU_120T_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_DSU_120T_BASE_OFFSET) /* DynamIQ Shared Unit-120 Power Policy Units */
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#endif
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+/* Bit definition for External System Reset Control register */
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+#define CORSTONE1000_EXT_SYS_RESET_REG_CPUWAIT_Pos (0U) // CPU Wait Control. 0b0 - External System's CPUWAIT signal is de-asserted. 0b1 - External System's CPUWAIT signal is asserted.
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+#define CORSTONE1000_EXT_SYS_RESET_REG_CPUWAIT_Msk (0x1UL << CORSTONE1000_EXT_SYS_RESET_REG_CPUWAIT_Pos) // 1 bit
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+#define CORSTONE1000_EXT_SYS_RESET_REG_RST_REQ_Pos (1U) // Reset Request for External System. 0b0 - No Reset Requested. 0b1 - Reset Requested.
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+#define CORSTONE1000_EXT_SYS_RESET_REG_RST_REQ_Msk (0x1UL << CORSTONE1000_EXT_SYS_RESET_REG_RST_REQ_Pos) // 1 bit
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+#define CORSTONE1000_EXT_SYS_RESET_REG_Reserved_Pos (2U) // Reserved.
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+#define CORSTONE1000_EXT_SYS_RESET_REG_Reserved_Msk (0x3FFFFFFFUL << CORSTONE1000_EXT_SYS_RESET_REG_Reserved_Pos) // 30 bits
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+
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/* Map Component definitions to Corstone definitions */
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#define CC3XX_BASE_S CORSTONE1000_CRYPTO_ACCELERATOR_BASE
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diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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index 9a785bfa0..76360b507 100644
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--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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@@ -26,12 +26,11 @@
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#define AA64nAA32_MASK (1 << 3)
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#ifdef EXTERNAL_SYSTEM_SUPPORT
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-void tfm_external_system_boot()
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+void tfm_external_system_boot(void)
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{
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volatile uint32_t *ext_sys_reset_ctl_reg = (uint32_t *)(CORSTONE1000_EXT_SYS_RESET_REG);
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- /* de-assert CPU_WAIT signal*/
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- *ext_sys_reset_ctl_reg = 0x0;
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+ *ext_sys_reset_ctl_reg &= ~(CORSTONE1000_EXT_SYS_RESET_REG_CPUWAIT_Msk);
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}
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#endif
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--
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2.43.0
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+75
@@ -0,0 +1,75 @@
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From 334e5513db08f6ebdd7e59429849d442b7b43446 Mon Sep 17 00:00:00 2001
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From: Michael Safwat <michael.safwat@arm.com>
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Date: Thu, 19 Mar 2026 11:12:19 +0000
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Subject: [PATCH 2/2] plat: cs1k: Drive NPU via external system reset control
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On Corstone-1000 with Cortex-A320, the NPU reset was previously tied
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to the host boot flow, so the NPU was powered on when the Secure
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Enclave powered on the host. Now the NPU is tied to the External
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System Reset Control register to control the power state.
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Reuse the existing external-system boot control mechanism for NPU.
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Change-Id: I74f9d57e8cbe5cb38db352d706885f9a37db0183
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Signed-off-by: Michael Safwat <michael.safwat@arm.com>
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Upstream-Status: Backport [6010d3b509e51cf10a711596e7d6058bde1568dc]
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---
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platform/ext/target/arm/corstone1000/CMakeLists.txt | 5 +++++
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.../arm/corstone1000/Device/Include/platform_base_address.h | 2 +-
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platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c | 4 ++--
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3 files changed, 8 insertions(+), 3 deletions(-)
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diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
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index e543c4b6b..739a6a086 100644
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--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
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+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
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@@ -484,6 +484,11 @@ if (CORSTONE1000_CORTEX_A320)
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PUBLIC
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CORSTONE1000_CORTEX_A320
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)
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+
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+ target_compile_definitions(platform_s
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+ PUBLIC
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+ CORSTONE1000_CORTEX_A320
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+ )
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endif()
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#========================= tfm_adac ============================================#
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diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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index 62ee7d049..631592b34 100644
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--- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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+++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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@@ -91,7 +91,7 @@
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#define CORSTONE1000_HOST_TRUSTED_RAM_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_CVM_OFFSET) /* On-chip Volatile Memory */
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#define CORSTONE1000_HOST_XNVM_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_XNVM_OFFSET) /* eXecute-in-place Non-volatile Memory */
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#define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE_OFFSET) /* Security Control Bits */
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-#define CORSTONE1000_EXT_SYS_RESET_REG (CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE + CORSTONE1000_HOST_EXT_SYS0_RST_CTRL_OFFSET) /* External System (Cortex-M3) */
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+#define CORSTONE1000_EXT_SYS_RESET_REG (CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE + CORSTONE1000_HOST_EXT_SYS0_RST_CTRL_OFFSET) /* External System (Cortex-M3/NPU) */
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#define CORSTONE1000_HOST_FIREWALL_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_FIREWALL_BASE_OFFSET) /* System Firewall */
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#define CORSTONE1000_HOST_INT_APBCOM_BASE (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_INT_APBCOM_BASE_OFFSET) /* Internal Advanced Peripheral Bus Communication */
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#define CORSTONE1000_HOST_FPGA_SCC_REGISTERS (CORSTONE1000_HOST_ADDRESS_SPACE_BASE + CORSTONE1000_HOST_FPGA_SCC_REGISTERS_OFFSET) /* FPGA Serial Communication Controller Registers */
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diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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index 76360b507..ff65228bf 100644
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--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
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@@ -25,7 +25,7 @@
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#define AA64nAA32_MASK (1 << 3)
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-#ifdef EXTERNAL_SYSTEM_SUPPORT
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+#if defined(EXTERNAL_SYSTEM_SUPPORT) || defined(CORSTONE1000_CORTEX_A320)
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void tfm_external_system_boot(void)
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{
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volatile uint32_t *ext_sys_reset_ctl_reg = (uint32_t *)(CORSTONE1000_EXT_SYS_RESET_REG);
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@@ -123,7 +123,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
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#endif
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#endif
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-#ifdef EXTERNAL_SYSTEM_SUPPORT
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+#if defined(EXTERNAL_SYSTEM_SUPPORT) || defined(CORSTONE1000_CORTEX_A320)
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/*release EXT SYS out of reset*/
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tfm_external_system_boot();
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#endif
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--
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2.43.0
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@@ -75,6 +75,8 @@ SRC_URI:append:corstone1000 = " \
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file://0041-plat-cs1k-Changed-to-use-new-GPT-library.patch \
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file://0042-plat-cs1k-Move-variable-from-stack-to-data.patch \
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file://0043-plat-cs1k-Create-and-remove-FWU-image-partitions.patch \
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file://0044-plat-cs1k-Derive-host-base-addresses-from-offsets.patch \
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file://0045-plat-cs1k-Drive-NPU-via-external-system-reset-contro.patch \
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"
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SRCREV_tfm-psa-adac:corstone1000 = "f2809ae231be33a1afcd7714f40756c67d846c88"
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