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arm-bsp/u-boot: cs1k: Align Ethos-U85 DT with in-tree driver
Align the Corstone1000 Ethos-U85 device tree to match the upstream bindings used by the in-tree Ethos-U DRM accel driver. - Rework the Corstone1000 U-Boot patch to replace the legacy arm,ethosu-direct node with an upstream-style Ethos-U85 node (arm,ethos-u85), add the required clocks/clock-names, and switch the SRAM description to mmio-sram. - Drop meta-ethos specific properties (reserved-memory/dma-ranges, /region-cfgs/mem-config) from the U-Boot DT. - Enable required kernel options for the in-tree driver and SRAM provider: - CONFIG_SRAM - CONFIG_DRM - CONFIG_DRM_ACCEL - CONFIG_DRM_ACCEL_ARM_ETHOSU Signed-off-by: Michael Safwat <michael.safwat@arm.com> Signed-off-by: Frazer Carsley <frazer.carsley@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Michael Safwat
committed by
Jon Mason
Jon Mason
parent
c2258d460f
commit
2c81c14c5b
@@ -1,4 +1,4 @@
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From 9f95097d9b2d9b1360b5c105161509ea9a5b198d Mon Sep 17 00:00:00 2001
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From da23886f3b38812c60a4597db129ab96df74bb99 Mon Sep 17 00:00:00 2001
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From: Frazer Carsley <frazer.carsley@arm.com>
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Date: Wed, 25 Feb 2026 14:28:08 +0000
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Subject: [PATCH] corstone1000-a320: Add Corstone1000 board variant
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@@ -22,13 +22,9 @@ compatibility with Cortex-A35 and GIC-400.
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* Add `/ethosu@1a050000` node describing the NPU register block at
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`0x1A050000`.
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* Introduce associated reserved memory regions:
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* `ethosu_sram@02400000`: 2 MiB on-chip SRAM (`no-map`).
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* `ethosu_reserved@A0000000`: 32 MiB DDR carve-out
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(`shared-dma-pool`).
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* Connect memory regions through `memory-region` and `sram` phandles.
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* Add `dma-ranges`, interrupt spec, `region-cfgs`, `cs-region`, and
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`ethosu-mem-config` for full driver support.
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* `ethosu_sram@02400000`: 2 MiB on-chip SRAM.
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* Fully compliant with upstream bindings.
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**GIC-700 support**
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* Add full GICv3 node.
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@@ -41,20 +37,22 @@ These updates align the Corstone-1000 platform with Arm’s latest
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Cortex-A320 and Ethos-U85 configurations and ensure proper interrupt
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and memory mapping for both secure and non-secure domains.
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Upstream-Status: Inappropriate [Unsupported ethosu device-tree nodes, denied by maintainers (https://lore.kernel.org/all/20251127154752.589691-1-frazer.carsley@arm.com/)]
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Upstream-Status: Pending [Strong dependency on previous patches that
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should be upstreamed first]
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Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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Signed-off-by: Michael Safwat <michael.safwat@arm.com>
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---
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arch/arm/Kconfig | 1 +
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arch/arm/dts/corstone1000-a320-fvp.dts | 51 ++++
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arch/arm/dts/corstone1000-a320.dtsi | 237 ++++++++++++++++++
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arch/arm/dts/corstone1000-a320-fvp.dts | 51 +++++
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arch/arm/dts/corstone1000-a320.dtsi | 208 ++++++++++++++++++
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arch/arm/include/asm/armv8/cpu.h | 3 +
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board/armltd/corstone1000-a320/Kconfig | 12 +
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board/armltd/corstone1000-a320/MAINTAINERS | 7 +
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board/armltd/corstone1000/corstone1000.c | 6 +-
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configs/corstone1000-a320_defconfig | 89 +++++++
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configs/corstone1000-a320_defconfig | 89 ++++++++
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.../arm/arm,corstone1000-a320.yml | 31 +++
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9 files changed, 434 insertions(+), 3 deletions(-)
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9 files changed, 405 insertions(+), 3 deletions(-)
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create mode 100644 arch/arm/dts/corstone1000-a320-fvp.dts
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create mode 100644 arch/arm/dts/corstone1000-a320.dtsi
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create mode 100644 board/armltd/corstone1000-a320/Kconfig
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@@ -133,10 +131,10 @@ index 00000000000..c01c629e0ca
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+};
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diff --git a/arch/arm/dts/corstone1000-a320.dtsi b/arch/arm/dts/corstone1000-a320.dtsi
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new file mode 100644
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index 00000000000..28424db77bb
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index 00000000000..6715e15ec37
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--- /dev/null
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+++ b/arch/arm/dts/corstone1000-a320.dtsi
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@@ -0,0 +1,237 @@
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@@ -0,0 +1,208 @@
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+// SPDX-License-Identifier: GPL-2.0 or MIT
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+/*
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+ * Copyright 2026, Arm Limited and/or its affiliates <open-source-office@arm.com>
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@@ -260,42 +258,26 @@ index 00000000000..28424db77bb
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+ method = "smc";
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+ };
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+
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+ ethosu: ethosu@1A050000 {
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+ compatible = "arm,ethosu-direct";
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+ ethosu_sram: ethosu_sram@02400000 {
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+ compatible = "mmio-sram";
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+ reg = <0x02400000 0x200000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ };
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+
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+ ethosu@1A050000 {
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+ compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85";
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+
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+ // Base address and size of NPU registers
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+ reg = <0x1A050000 0x4000>;
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+
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+ memory-region = <ðosu_reserved>;
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+ sram = <ðosu_sram>;
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+
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+ // Address mappings to translate between bus addresses (NPU) and physical host CPU addresses
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+ dma-ranges = <0x02400000 0x02400000 0x200000>,
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+ <0xA0000000 0xA0000000 0x02000000>;
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+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ interrupts = <0 16 4>;
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+ interrupt-names = "irq";
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+
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+ // Memory region configuration
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+ region-cfgs = <3 3 0 3 3 3 3 3>;
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+
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+ // Memory regions used for the command stream
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+ cs-region = <2>;
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+
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+ // Memory interface configuration for Ethos-U85
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+ ethosu_mem_config {
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+ compatible = "arm,ethosu-mem-config";
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+ // <beats outstanding_read outstanding_write>
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+ sram = <0 64 32>;
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+ ext = <1 64 32>;
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+ // <mem_domain mem_type axi_port>
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+ configs = <0 0 0>,
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+ <0 0 0>,
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+ <0 0 1>,
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+ <0 0 1>;
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+ };
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+ clocks = <&uartclk>, <&refclk100mhz>;
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+ clock-names = "core", "apb";
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+ };
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+
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+ soc {
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@@ -361,19 +343,6 @@ index 00000000000..28424db77bb
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+ };
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+};
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+
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+&{/reserved-memory} {
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+ ethosu_sram: ethosu_sram@02400000 {
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+ reg = <0x02400000 0x200000>;
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+ no-map;
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+ };
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+
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+ ethosu_reserved: ethosu_reserved@A0000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0xA0000000 0x02000000>;
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+ no-map;
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+ };
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+};
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+
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diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
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index e906fdf1bf1..1ae679f7119 100644
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--- a/arch/arm/include/asm/armv8/cpu.h
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@@ -0,0 +1,4 @@
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CONFIG_SRAM=y
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CONFIG_DRM=y
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CONFIG_DRM_ACCEL=y
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CONFIG_DRM_ACCEL_ARM_ETHOSU=y
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@@ -65,6 +65,7 @@ KMACHINE:corstone1000:cortexa320 = "corstone1000-a320"
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LINUX_KERNEL_TYPE:corstone1000:cortexa320 = "standard"
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SRC_URI:append:corstone1000:cortexa320 = " \
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file://defconfig \
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file://ethosu.cfg \
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"
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# Default kernel features not needed for Corstone-1000 with
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