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arm-bsp/trusted-firmware-m: corstone1000: Enable host firewall in FVP
Enables host firewall and mpu setup for FVP. It also fixes secure-ram configuration and disable access rights to secure ram from both normal world for both mps3 and fvp. Signed-off-by: Emekcan Aras <emekcan.aras@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Emekcan Aras
Jon Mason
+177
@@ -0,0 +1,177 @@
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From 1410dc5504d60219279581b1cf6442f81551cfe7 Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Wed, 3 Apr 2024 13:37:40 +0100
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Subject: [PATCH] Platform: Corstone1000: Enable host firewall in FVP
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Enables host firewall and mpu setup for FVP. It also fixes secure-ram
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configuration and disable access rights to secure ram from both normal world
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for both mps3 and fvp.
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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Upstream-Status: Pending [Not submitted to upstream yet]
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---
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.../Device/Include/platform_base_address.h | 2 +-
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.../arm/corstone1000/bl1/boot_hal_bl1_1.c | 42 ++++---------------
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.../arm/corstone1000/bl2/flash_map_bl2.c | 2 +-
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3 files changed, 11 insertions(+), 35 deletions(-)
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diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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index 416f0ebcd..101cad9e7 100644
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--- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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+++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
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@@ -67,7 +67,7 @@
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* required by the SE are defined here */
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#define CORSTONE1000_HOST_ADDRESS_SPACE_BASE (0x60000000U) /* Host Address Space */
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#define CORSTONE1000_HOST_BIR_BASE (0x60000000U) /* Boot Instruction Register */
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-#define CORSTONE1000_HOST_SHARED_RAM_BASE (0x62000000U) /* Shared RAM */
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+#define CORSTONE1000_HOST_TRUSTED_RAM_BASE (0x62000000U) /* Secure RAM */
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#define CORSTONE1000_HOST_XNVM_BASE (0x68000000U) /* XNVM */
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#define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE (0x7A010000U) /* Host SCB */
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#define CORSTONE1000_EXT_SYS_RESET_REG (0x7A010310U) /* external system (cortex-M3) */
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diff --git a/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c b/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
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index a5fee66af..7988c2392 100644
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--- a/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
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+++ b/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
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@@ -35,7 +35,7 @@ REGION_DECLARE(Image$$, ER_DATA, $$Base)[];
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REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[];
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#define HOST_ADDRESS_SPACE_BASE 0x00000000
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-#define HOST_SHARED_RAM_BASE 0x02000000
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+#define HOST_TRUSTED_RAM_BASE 0x02000000
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#define HOST_XNVM_BASE 0x08000000
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#define HOST_BASE_SYSTEM_CONTROL_BASE 0x1A010000
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#define HOST_FIREWALL_BASE 0x1A800000
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@@ -347,7 +347,7 @@ static void setup_host_firewall(void)
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fc_pe_enable();
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- /* CVM - Shared RAM */
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+ /* CVM - Secure RAM */
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fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_CVM);
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fc_disable_bypass();
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fc_pe_disable();
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@@ -355,15 +355,12 @@ static void setup_host_firewall(void)
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fc_select_region(1);
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fc_disable_regions();
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fc_disable_mpe(RGN_MPE0);
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- fc_prog_rgn(RGN_SIZE_4MB, HOST_SHARED_RAM_BASE);
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+ fc_prog_rgn(RGN_SIZE_4MB, HOST_TRUSTED_RAM_BASE);
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fc_init_mpl(RGN_MPE0);
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mpl_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_SECURE_READ_MASK |
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RGN_MPL_SECURE_WRITE_MASK |
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- RGN_MPL_SECURE_EXECUTE_MASK |
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- RGN_MPL_NONSECURE_READ_MASK |
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- RGN_MPL_NONSECURE_WRITE_MASK |
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- RGN_MPL_NONSECURE_EXECUTE_MASK);
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+ RGN_MPL_SECURE_EXECUTE_MASK);
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fc_enable_mpl(RGN_MPE0, mpl_rights);
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fc_disable_mpl(RGN_MPE0, ~mpl_rights);
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@@ -398,7 +395,9 @@ static void setup_host_firewall(void)
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fc_pe_enable();
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- /* Host Expansion Master 0 */
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+#if !(PLATFORM_IS_FVP)
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+ /* Host Expansion Master 0 (Due to the difference in the models only
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+ * programming this for MPS3) */
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fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_EXPMST0);
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fc_disable_bypass();
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fc_pe_disable();
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@@ -433,7 +432,6 @@ static void setup_host_firewall(void)
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fc_enable_regions();
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fc_rgn_lock();
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-#if !(PLATFORM_IS_FVP)
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fc_select_region(3);
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fc_disable_regions();
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fc_disable_mpe(RGN_MPE0);
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@@ -461,16 +459,14 @@ static void setup_host_firewall(void)
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fc_enable_mpe(RGN_MPE0);
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fc_enable_regions();
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fc_rgn_lock();
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-#endif
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fc_pe_enable();
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- /* Host Expansion Master 0 */
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+ /* Host Expansion Master 1*/
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fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_EXPMST1);
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fc_disable_bypass();
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fc_pe_disable();
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-#if !(PLATFORM_IS_FVP)
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fc_select_region(1);
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fc_disable_regions();
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fc_disable_mpe(RGN_MPE0);
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@@ -484,22 +480,6 @@ static void setup_host_firewall(void)
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fc_enable_mpe(RGN_MPE0);
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fc_enable_regions();
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fc_rgn_lock();
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-#else
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- fc_select_region(1);
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- fc_disable_regions();
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- fc_disable_mpe(RGN_MPE0);
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- fc_prog_rgn(RGN_SIZE_8MB, HOST_SE_SECURE_FLASH_BASE_FVP);
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- fc_init_mpl(RGN_MPE0);
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-
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- mpl_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_SECURE_READ_MASK |
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- RGN_MPL_SECURE_WRITE_MASK);
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-
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- fc_enable_mpl(RGN_MPE0, mpl_rights);
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- fc_enable_mpe(RGN_MPE0);
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- fc_enable_regions();
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- fc_rgn_lock();
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-#endif
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-
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fc_pe_enable();
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/* Always ON Host Peripherals */
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@@ -527,7 +507,6 @@ static void setup_host_firewall(void)
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}
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fc_pe_enable();
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-
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/* Host System Peripherals */
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fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_SYSPERIPH);
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fc_disable_bypass();
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@@ -553,6 +532,7 @@ static void setup_host_firewall(void)
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}
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fc_pe_enable();
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+#endif
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/* Host System Peripherals */
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fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_DBGPERIPH);
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@@ -592,13 +572,9 @@ int32_t boot_platform_init(void)
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if (result != ARM_DRIVER_OK) {
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return 1;
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}
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-#if !(PLATFORM_IS_FVP)
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setup_mpu();
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-#endif
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setup_se_firewall();
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-#if !(PLATFORM_IS_FVP)
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setup_host_firewall();
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-#endif
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#if defined(TFM_BL1_LOGGING) || defined(TEST_BL1_1) || defined(TEST_BL1_2)
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stdio_init();
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diff --git a/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c b/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c
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index 2b1cdfa19..06cc3f0f5 100644
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--- a/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c
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+++ b/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c
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@@ -70,7 +70,7 @@ int boot_get_image_exec_ram_info(uint32_t image_id,
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rc = 0;
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}
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else if (image_id == 1 || image_id == 2) {
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- (*exec_ram_start) = CORSTONE1000_HOST_SHARED_RAM_BASE;
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+ (*exec_ram_start) = CORSTONE1000_HOST_TRUSTED_RAM_BASE;
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(*exec_ram_size) = 0x20000000U;
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rc = 0;
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}
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--
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2.25.1
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@@ -40,6 +40,7 @@ SRC_URI:append:corstone1000 = " \
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file://0005-platform-corstone1000-fix-synchronization-issue-on-o.patch \
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file://0006-Platform-Corstone1000-skip-the-first-nv-counter.patch \
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file://0007-platform-corstone1000-add-unique-guid-for-mps3.patch \
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file://0008-Platform-Corstone1000-Enable-host-firewall-in-FVP.patch \
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"
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# TF-M ships patches for external dependencies that needs to be applied
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