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arm-bsp/tc: enable tracing in Total Compute
Enable coresight components in the config and also port the patches which were upstreamed in later version of the linux kernel. Change-Id: I27983abd5f2945328f7465cc1b2af4f8e848b69b Signed-off-by: Davidson K <davidson.kumaresan@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Davidson K
Jon Mason
@@ -5,3 +5,4 @@ kconf non-hardware tc/gralloc.cfg
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kconf non-hardware tc/mali.cfg
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kconf non-hardware tc/tee.cfg
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kconf non-hardware tc/virtio.cfg
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kconf non-hardware tc/autofdo.cfg
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@@ -0,0 +1,3 @@
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CONFIG_CORESIGHT=y
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CONFIG_CORESIGHT_SOURCE_ETM4X=y
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CONFIG_CORESIGHT_TRBE=y
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@@ -220,5 +220,7 @@ SRC_URI:append:tc = " \
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file://0018-optee-add-a-FF-A-memory-pool.patch \
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file://0019-optee-add-FF-A-support.patch \
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file://0021-arm_ffa-add-support-for-FFA-v1.1.patch \
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file://0022-coresight-etm4x-Save-restore-TRFCR_EL1.patch \
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file://0023-coresight-etm4x-Use-Trace-Filtering-controls-dynamic.patch \
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"
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KERNEL_FEATURES:append:tc = " bsp/arm-platforms/tc.scc"
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+181
@@ -0,0 +1,181 @@
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From 7150eac72ee0c2c7da03f53a90a871c3d6d4e538 Mon Sep 17 00:00:00 2001
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From: Suzuki K Poulose <suzuki.poulose@arm.com>
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Date: Tue, 14 Sep 2021 11:26:32 +0100
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Subject: [PATCH 1/2] coresight: etm4x: Save restore TRFCR_EL1
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When the CPU enters a low power mode, the TRFCR_EL1 contents could be
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reset. Thus we need to save/restore the TRFCR_EL1 along with the ETM4x
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registers to allow the tracing.
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The TRFCR related helpers are in a new header file, as we need to use
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them for TRBE in the later patches.
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Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
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Cc: Anshuman Khandual <anshuman.khandual@arm.com>
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Cc: Mike Leach <mike.leach@linaro.org>
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Cc: Leo Yan <leo.yan@linaro.org>
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Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
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Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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Link: https://lore.kernel.org/r/20210914102641.1852544-2-suzuki.poulose@arm.com
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[Fixed cosmetic details]
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Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=937d3f58cacf377cab7c32e475e1ffa91d611dce]
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Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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---
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.../coresight/coresight-etm4x-core.c | 43 +++++++++++++------
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drivers/hwtracing/coresight/coresight-etm4x.h | 2 +
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.../coresight/coresight-self-hosted-trace.h | 24 +++++++++++
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3 files changed, 57 insertions(+), 12 deletions(-)
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create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h
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diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
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index 90827077d2f9..b78080d169f8 100644
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--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
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+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
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@@ -39,6 +39,7 @@
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#include "coresight-etm4x.h"
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#include "coresight-etm-perf.h"
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+#include "coresight-self-hosted-trace.h"
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static int boot_enable;
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module_param(boot_enable, int, 0444);
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@@ -990,7 +991,7 @@ static void cpu_enable_tracing(struct etmv4_drvdata *drvdata)
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if (is_kernel_in_hyp_mode())
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trfcr |= TRFCR_EL2_CX;
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- write_sysreg_s(trfcr, SYS_TRFCR_EL1);
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+ write_trfcr(trfcr);
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}
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static void etm4_init_arch_data(void *info)
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@@ -1528,7 +1529,7 @@ static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
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drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
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}
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-static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
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+static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
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{
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int i, ret = 0;
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struct etmv4_save_state *state;
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@@ -1667,7 +1668,23 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
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return ret;
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}
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-static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
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+static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
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+{
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+ int ret = 0;
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+
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+ /* Save the TRFCR irrespective of whether the ETM is ON */
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+ if (drvdata->trfc)
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+ drvdata->save_trfcr = read_trfcr();
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+ /*
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+ * Save and restore the ETM Trace registers only if
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+ * the ETM is active.
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+ */
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+ if (local_read(&drvdata->mode) && drvdata->save_state)
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+ ret = __etm4_cpu_save(drvdata);
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+ return ret;
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+}
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+
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+static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
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{
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int i;
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struct etmv4_save_state *state = drvdata->save_state;
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@@ -1763,6 +1780,14 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
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etm4_cs_lock(drvdata, csa);
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}
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+static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
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+{
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+ if (drvdata->trfc)
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+ write_trfcr(drvdata->save_trfcr);
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+ if (drvdata->state_needs_restore)
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+ __etm4_cpu_restore(drvdata);
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+}
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+
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static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
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void *v)
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{
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@@ -1774,23 +1799,17 @@ static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
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drvdata = etmdrvdata[cpu];
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- if (!drvdata->save_state)
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- return NOTIFY_OK;
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-
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if (WARN_ON_ONCE(drvdata->cpu != cpu))
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return NOTIFY_BAD;
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switch (cmd) {
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case CPU_PM_ENTER:
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- /* save the state if self-hosted coresight is in use */
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- if (local_read(&drvdata->mode))
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- if (etm4_cpu_save(drvdata))
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- return NOTIFY_BAD;
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+ if (etm4_cpu_save(drvdata))
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+ return NOTIFY_BAD;
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break;
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case CPU_PM_EXIT:
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case CPU_PM_ENTER_FAILED:
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- if (drvdata->state_needs_restore)
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- etm4_cpu_restore(drvdata);
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+ etm4_cpu_restore(drvdata);
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break;
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default:
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return NOTIFY_DONE;
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diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
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index e5b79bdb9851..82cba16b73a6 100644
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--- a/drivers/hwtracing/coresight/coresight-etm4x.h
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+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
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@@ -921,6 +921,7 @@ struct etmv4_save_state {
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* @lpoverride: If the implementation can support low-power state over.
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* @trfc: If the implementation supports Arm v8.4 trace filter controls.
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* @config: structure holding configuration parameters.
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+ * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event.
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* @save_state: State to be preserved across power loss
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* @state_needs_restore: True when there is context to restore after PM exit
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* @skip_power_up: Indicates if an implementation can skip powering up
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@@ -973,6 +974,7 @@ struct etmv4_drvdata {
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bool lpoverride;
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bool trfc;
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struct etmv4_config config;
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+ u64 save_trfcr;
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struct etmv4_save_state *save_state;
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bool state_needs_restore;
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bool skip_power_up;
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diff --git a/drivers/hwtracing/coresight/coresight-self-hosted-trace.h b/drivers/hwtracing/coresight/coresight-self-hosted-trace.h
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new file mode 100644
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index 000000000000..303d71911870
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--- /dev/null
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+++ b/drivers/hwtracing/coresight/coresight-self-hosted-trace.h
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@@ -0,0 +1,24 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Arm v8 Self-Hosted trace support.
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+ *
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+ * Copyright (C) 2021 ARM Ltd.
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+ */
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+
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+#ifndef __CORESIGHT_SELF_HOSTED_TRACE_H
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+#define __CORESIGHT_SELF_HOSTED_TRACE_H
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+
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+#include <asm/sysreg.h>
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+
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+static inline u64 read_trfcr(void)
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+{
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+ return read_sysreg_s(SYS_TRFCR_EL1);
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+}
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+
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+static inline void write_trfcr(u64 val)
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+{
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+ write_sysreg_s(val, SYS_TRFCR_EL1);
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+ isb();
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+}
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+
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+#endif /* __CORESIGHT_SELF_HOSTED_TRACE_H */
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--
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2.34.1
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+227
@@ -0,0 +1,227 @@
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From 55228b0522bfb7d945019a8931742ab9b063b6c9 Mon Sep 17 00:00:00 2001
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From: Suzuki K Poulose <suzuki.poulose@arm.com>
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Date: Tue, 14 Sep 2021 11:26:33 +0100
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Subject: [PATCH 2/2] coresight: etm4x: Use Trace Filtering controls
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dynamically
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The Trace Filtering support (FEAT_TRF) ensures that the ETM
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can be prohibited from generating any trace for a given EL.
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This is much stricter knob, than the TRCVICTLR exception level
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masks, which doesn't prevent the ETM from generating Context
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packets for an "excluded" EL. At the moment, we do a onetime
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enable trace at user and kernel and leave it untouched for the
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kernel life time. This implies that the ETM could potentially
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generate trace packets containing the kernel addresses, and
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thus leaking the kernel virtual address in the trace.
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This patch makes the switch dynamic, by honoring the filters
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set by the user and enforcing them in the TRFCR controls.
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We also rename the cpu_enable_tracing() appropriately to
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cpu_detect_trace_filtering() and the drvdata member
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trfc => trfcr to indicate the "value" of the TRFCR_EL1.
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Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
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Cc: Al Grant <al.grant@arm.com>
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Cc: Mike Leach <mike.leach@linaro.org>
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Cc: Leo Yan <leo.yan@linaro.org>
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Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
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Link: https://lore.kernel.org/r/20210914102641.1852544-3-suzuki.poulose@arm.com
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Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Upstream-Status: Backport [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f6fd1aa8cc147b111af1a833574487a87237dc0]
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Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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---
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.../coresight/coresight-etm4x-core.c | 63 ++++++++++++++-----
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drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++-
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.../coresight/coresight-self-hosted-trace.h | 7 +++
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3 files changed, 59 insertions(+), 18 deletions(-)
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diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
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index b78080d169f8..b804d4413b43 100644
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--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
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+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
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@@ -237,6 +237,45 @@ struct etm4_enable_arg {
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int rc;
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};
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+/*
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+ * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
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+ * When the CPU supports FEAT_TRF, we could move the ETM to a trace
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+ * prohibited state by filtering the Exception levels via TRFCR_EL1.
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+ */
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+static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
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+{
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+ /* If the CPU doesn't support FEAT_TRF, nothing to do */
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+ if (!drvdata->trfcr)
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+ return;
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+ cpu_prohibit_trace();
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+}
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+
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+/*
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+ * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
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+ * as configured by the drvdata->config.mode for the current
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+ * session. Even though we have TRCVICTLR bits to filter the
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+ * trace in the ELs, it doesn't prevent the ETM from generating
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+ * a packet (e.g, TraceInfo) that might contain the addresses from
|
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+ * the excluded levels. Thus we use the additional controls provided
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+ * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
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+ * is generated for the excluded ELs.
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+ */
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+static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
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+{
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+ u64 trfcr = drvdata->trfcr;
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+
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+ /* If the CPU doesn't support FEAT_TRF, nothing to do */
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+ if (!trfcr)
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+ return;
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+
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+ if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
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+ trfcr &= ~TRFCR_ELx_ExTRE;
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+ if (drvdata->config.mode & ETM_MODE_EXCL_USER)
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+ trfcr &= ~TRFCR_ELx_E0TRE;
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+
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+ write_trfcr(trfcr);
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+}
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+
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#ifdef CONFIG_ETM4X_IMPDEF_FEATURE
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#define HISI_HIP08_AMBA_ID 0x000b6d01
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@@ -441,6 +480,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
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if (etm4x_is_ete(drvdata))
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etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
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+ etm4x_allow_trace(drvdata);
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/* Enable the trace unit */
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etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
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@@ -724,7 +764,6 @@ static int etm4_enable(struct coresight_device *csdev,
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static void etm4_disable_hw(void *info)
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{
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u32 control;
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- u64 trfcr;
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struct etmv4_drvdata *drvdata = info;
|
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struct etmv4_config *config = &drvdata->config;
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struct coresight_device *csdev = drvdata->csdev;
|
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@@ -751,12 +790,7 @@ static void etm4_disable_hw(void *info)
|
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* If the CPU supports v8.4 Trace filter Control,
|
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* set the ETM to trace prohibited region.
|
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*/
|
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- if (drvdata->trfc) {
|
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- trfcr = read_sysreg_s(SYS_TRFCR_EL1);
|
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- write_sysreg_s(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE),
|
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- SYS_TRFCR_EL1);
|
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- isb();
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- }
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+ etm4x_prohibit_trace(drvdata);
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/*
|
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* Make sure everything completes before disabling, as recommended
|
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* by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
|
||||
@@ -772,9 +806,6 @@ static void etm4_disable_hw(void *info)
|
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if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
|
||||
dev_err(etm_dev,
|
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"timeout while waiting for PM stable Trace Status\n");
|
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- if (drvdata->trfc)
|
||||
- write_sysreg_s(trfcr, SYS_TRFCR_EL1);
|
||||
-
|
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/* read the status of the single shot comparators */
|
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for (i = 0; i < drvdata->nr_ss_cmp; i++) {
|
||||
config->ss_status[i] =
|
||||
@@ -969,15 +1000,15 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
|
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return false;
|
||||
}
|
||||
|
||||
-static void cpu_enable_tracing(struct etmv4_drvdata *drvdata)
|
||||
+static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
|
||||
{
|
||||
u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
|
||||
u64 trfcr;
|
||||
|
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+ drvdata->trfcr = 0;
|
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if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
|
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return;
|
||||
|
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- drvdata->trfc = true;
|
||||
/*
|
||||
* If the CPU supports v8.4 SelfHosted Tracing, enable
|
||||
* tracing at the kernel EL and EL0, forcing to use the
|
||||
@@ -991,7 +1022,7 @@ static void cpu_enable_tracing(struct etmv4_drvdata *drvdata)
|
||||
if (is_kernel_in_hyp_mode())
|
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trfcr |= TRFCR_EL2_CX;
|
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- write_trfcr(trfcr);
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+ drvdata->trfcr = trfcr;
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}
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static void etm4_init_arch_data(void *info)
|
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@@ -1177,7 +1208,7 @@ static void etm4_init_arch_data(void *info)
|
||||
/* NUMCNTR, bits[30:28] number of counters available for tracing */
|
||||
drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
|
||||
etm4_cs_lock(drvdata, csa);
|
||||
- cpu_enable_tracing(drvdata);
|
||||
+ cpu_detect_trace_filtering(drvdata);
|
||||
}
|
||||
|
||||
static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
|
||||
@@ -1673,7 +1704,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
|
||||
int ret = 0;
|
||||
|
||||
/* Save the TRFCR irrespective of whether the ETM is ON */
|
||||
- if (drvdata->trfc)
|
||||
+ if (drvdata->trfcr)
|
||||
drvdata->save_trfcr = read_trfcr();
|
||||
/*
|
||||
* Save and restore the ETM Trace registers only if
|
||||
@@ -1782,7 +1813,7 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
|
||||
|
||||
static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
|
||||
{
|
||||
- if (drvdata->trfc)
|
||||
+ if (drvdata->trfcr)
|
||||
write_trfcr(drvdata->save_trfcr);
|
||||
if (drvdata->state_needs_restore)
|
||||
__etm4_cpu_restore(drvdata);
|
||||
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
|
||||
index 82cba16b73a6..3c4d69b096ca 100644
|
||||
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
|
||||
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
|
||||
@@ -919,7 +919,10 @@ struct etmv4_save_state {
|
||||
* @nooverflow: Indicate if overflow prevention is supported.
|
||||
* @atbtrig: If the implementation can support ATB triggers
|
||||
* @lpoverride: If the implementation can support low-power state over.
|
||||
- * @trfc: If the implementation supports Arm v8.4 trace filter controls.
|
||||
+ * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
|
||||
+ * allows tracing at all ELs. We don't want to compute this
|
||||
+ * at runtime, due to the additional setting of TRFCR_CX when
|
||||
+ * in EL2. Otherwise, 0.
|
||||
* @config: structure holding configuration parameters.
|
||||
* @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event.
|
||||
* @save_state: State to be preserved across power loss
|
||||
@@ -972,7 +975,7 @@ struct etmv4_drvdata {
|
||||
bool nooverflow;
|
||||
bool atbtrig;
|
||||
bool lpoverride;
|
||||
- bool trfc;
|
||||
+ u64 trfcr;
|
||||
struct etmv4_config config;
|
||||
u64 save_trfcr;
|
||||
struct etmv4_save_state *save_state;
|
||||
diff --git a/drivers/hwtracing/coresight/coresight-self-hosted-trace.h b/drivers/hwtracing/coresight/coresight-self-hosted-trace.h
|
||||
index 303d71911870..23f05df3f173 100644
|
||||
--- a/drivers/hwtracing/coresight/coresight-self-hosted-trace.h
|
||||
+++ b/drivers/hwtracing/coresight/coresight-self-hosted-trace.h
|
||||
@@ -21,4 +21,11 @@ static inline void write_trfcr(u64 val)
|
||||
isb();
|
||||
}
|
||||
|
||||
+static inline void cpu_prohibit_trace(void)
|
||||
+{
|
||||
+ u64 trfcr = read_trfcr();
|
||||
+
|
||||
+ /* Prohibit tracing at EL0 & the kernel EL */
|
||||
+ write_trfcr(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE));
|
||||
+}
|
||||
#endif /* __CORESIGHT_SELF_HOSTED_TRACE_H */
|
||||
--
|
||||
2.34.1
|
||||
|
||||
Reference in New Issue
Block a user