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arm-bsp/u-boot: enabling the generic timer for Corstone-500

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This commit updates the ARMv7 generic timer driver by configuring
and enabling the timer.

Change-Id: I1fc1df83f40e28869d8dd41ff7b202f6fa177a1f
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Signed-off-by: Ross Burton <ross.burton@arm.com>
This commit is contained in:
Abdellatif El Khlifi
2020-11-13 16:31:34 +00:00
committed by Ross Burton
parent 390aa6e354
commit 39ae13d44e
2 changed files with 35 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
meta-arm-bsp/recipes-bsp/u-boot/u-boot-2020.07/corstone500/0001-armv7-add-mmio-timer.patch → meta-arm-bsp/recipes-bsp/u-boot/u-boot-2020.07/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch
+34 -14
View File
@@ -1,21 +1,33 @@
From 4449a6c2de38bdeb09e3158f6d9318812966243a Mon Sep 17 00:00:00 2001
Upstream-Status: Pending [Not submitted to upstream yet]
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
From b6879fc62b5ec01e3c87c2772d3a5e0f51c35f1c Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Wed, 18 Dec 2019 21:52:34 +0000
Subject: [PATCH 1/2] armv7: add mmio timer
Subject: [PATCH] armv7: adding generic timer access through MMIO
This timer can be used by u-boot when arch-timer is not available in
core, for example, Cortex-A5.
This driver enables the ARMv7 generic timer.
The access to the timer registers is through memory mapping (MMIO).
This driver can be used by u-boot to access to the timer through MMIO
when arch_timer is not available in the core (access using system
instructions not possible), for example, in case of Cortex-A5.
This driver configures and enables the generic timer at
the u-boot initcall level (timer_init) before u-boot relocation.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/mmio_timer.c | 56 +++++++++++++++++++++++++++++++++
arch/arm/cpu/armv7/mmio_timer.c | 64 +++++++++++++++++++++++++++++++++
scripts/config_whitelist.txt | 1 +
3 files changed, 58 insertions(+)
3 files changed, 66 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mmio_timer.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 8c955d0d5284..82af9c031277 100644
index 8c955d0d52..82af9c0312 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o
@@ -28,10 +40,10 @@ index 8c955d0d5284..82af9c031277 100644
obj-y += s5p-common/
diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c
new file mode 100644
index 000000000000..5d6f66172398
index 0000000000..82ff3937b6
--- /dev/null
+++ b/arch/arm/cpu/armv7/mmio_timer.c
@@ -0,0 +1,56 @@
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
@@ -47,22 +59,30 @@ index 000000000000..5d6f66172398
+
+#define CNTCTLBASE 0x1a020000UL
+#define CNTREADBASE 0x1a030000UL
+#define CNTEN (1 << 0)
+#define CNTFCREQ (1 << 8)
+
+static inline uint32_t mmio_read32(uintptr_t addr)
+{
+ return *(volatile uint32_t*)addr;
+}
+
+static inline void mmio_write32(uintptr_t addr, uint32_t data)
+{
+ *(volatile uint32_t*)addr = data;
+}
+
+int timer_init(void)
+{
+ gd->arch.timer_rate_hz = mmio_read32(CNTCTLBASE);
+
+ gd->arch.timer_rate_hz = COUNTER_FREQUENCY / CONFIG_SYS_HZ; /* calculating the frequency in ms */
+ mmio_write32(CNTCTLBASE + 0x20, COUNTER_FREQUENCY); /* configuring CNTFID0 register: setting the base frequency */
+ mmio_write32(CNTCTLBASE, CNTFCREQ | CNTEN); /* configuring CNTCR register: enabling the generic counter and selecting the first frequency entry */
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ return ((mmio_read32(CNTCTLBASE + 0x4) << 32) |
+ return ((mmio_read32(CNTREADBASE + 0x4) << 32) |
+ mmio_read32(CNTREADBASE));
+}
+
@@ -89,7 +109,7 @@ index 000000000000..5d6f66172398
+ return gd->arch.timer_rate_hz;
+}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 916768f361d9..c8fd8c6e355a 100644
index 916768f361..c8fd8c6e35 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3075,6 +3075,7 @@ CONFIG_SYS_MMC_U_BOOT_DST
@@ -101,5 +121,5 @@ index 916768f361d9..c8fd8c6e355a 100644
CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_MONITOR_BASE_EARLY
--
2.28.0
2.17.1
meta-arm-bsp/recipes-bsp/u-boot/u-boot_2020.07.bbappend
+1 -1
View File
@@ -9,7 +9,7 @@ FILESEXTRAPATHS_prepend_foundation-armv8 = "${THIS_DIR}/${BP}/fvp-common:"
# Corstone-500 MACHINE
#
SRC_URI_append_corstone500 = " \
file://0001-armv7-add-mmio-timer.patch \
file://0001-armv7-adding-generic-timer-access-through-MMIO.patch \
file://0002-board-arm-add-corstone500-board.patch"
#