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arm-bsp/u-boot: corstone500: bump to 2022.10
Rebase corstone500 u-boot patches to 2022.10 version. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Rui Miguel Silva
committed by
Jon Mason
Jon Mason
parent
a7d911310e
commit
3f35573acb
@@ -26,7 +26,7 @@ SERIAL_CONSOLES = "115200;ttyAMA0"
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UBOOT_MACHINE = "corstone500_defconfig"
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UBOOT_IMAGE_ENTRYPOINT = "0x84000000"
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UBOOT_IMAGE_LOADADDRESS = "0x84000000"
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PREFERRED_VERSION_u-boot ?= "2022.07"
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PREFERRED_VERSION_u-boot ?= "2022.10"
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# making sure EXTRA_IMAGEDEPENDS will be used while creating the image
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WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}"
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+4
-4
@@ -1,4 +1,4 @@
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From d75d794785419592ba49046165d19a6ec9488b2d Mon Sep 17 00:00:00 2001
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From 787a802afb8c05fcb5117c1cbb612c51554aad24 Mon Sep 17 00:00:00 2001
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From: Rui Miguel Silva <rui.silva@linaro.org>
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Date: Wed, 18 Dec 2019 21:52:34 +0000
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Subject: [PATCH 1/2] armv7: adding generic timer access through MMIO
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@@ -124,10 +124,10 @@ index 000000000000..edd806e06e42
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+ return gd->arch.timer_rate_hz;
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+}
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diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
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index c61df4fb1c9b..cfb1c68b6297 100644
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index f505722f6b04..e0df0026c985 100644
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--- a/scripts/config_whitelist.txt
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+++ b/scripts/config_whitelist.txt
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@@ -1253,6 +1253,7 @@ CONFIG_SYS_MMC_U_BOOT_DST
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@@ -900,6 +900,7 @@ CONFIG_SYS_MMC_U_BOOT_DST
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CONFIG_SYS_MMC_U_BOOT_OFFS
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CONFIG_SYS_MMC_U_BOOT_SIZE
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CONFIG_SYS_MMC_U_BOOT_START
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@@ -136,5 +136,5 @@ index c61df4fb1c9b..cfb1c68b6297 100644
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CONFIG_SYS_MONITOR_SEC
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CONFIG_SYS_MOR_VAL
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--
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2.37.1
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2.38.1
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+23
-33
@@ -1,4 +1,4 @@
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From 3566cf4ab79ca78acd69cfb87e74587394e5aeb2 Mon Sep 17 00:00:00 2001
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From 70cf3f7498e98a98b21804f577f3b850018894da Mon Sep 17 00:00:00 2001
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From: Rui Miguel Silva <rui.silva@linaro.org>
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Date: Wed, 8 Jan 2020 09:48:11 +0000
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Subject: [PATCH 2/2] board: arm: add corstone500 board
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@@ -10,19 +10,15 @@ Add support for the Arm corstone500 platform, with a cortex-a5
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chip, add the default configuration, initialization and
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makefile for this system.
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Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
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%% original patch: 0002-board-arm-add-corstone500-board.patch
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Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
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---
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arch/arm/Kconfig | 10 +++
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board/armltd/corstone500/Kconfig | 12 +++
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board/armltd/corstone500/Makefile | 8 ++
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board/armltd/corstone500/corstone500.c | 48 +++++++++++
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configs/corstone500_defconfig | 40 +++++++++
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include/configs/corstone500.h | 109 +++++++++++++++++++++++++
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6 files changed, 227 insertions(+)
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board/armltd/corstone500/corstone500.c | 48 ++++++++++++
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configs/corstone500_defconfig | 41 ++++++++++
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include/configs/corstone500.h | 102 +++++++++++++++++++++++++
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6 files changed, 221 insertions(+)
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create mode 100644 board/armltd/corstone500/Kconfig
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create mode 100644 board/armltd/corstone500/Makefile
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create mode 100644 board/armltd/corstone500/corstone500.c
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@@ -30,12 +26,12 @@ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
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create mode 100644 include/configs/corstone500.h
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diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
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index 9898c7d68e1b..8c60ed39712e 100644
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index 82cd456f51f1..a925e7759ee8 100644
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -718,6 +718,15 @@ config ARCH_BCMSTB
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This enables support for Broadcom ARM-based set-top box
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chipsets, including the 7445 family of chips.
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@@ -1349,6 +1349,15 @@ config TARGET_CORSTONE1000
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select PL01X_SERIAL
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select DM
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+config TARGET_CORSTONE500
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+ bool "Support Corstone500"
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@@ -46,10 +42,10 @@ index 9898c7d68e1b..8c60ed39712e 100644
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+ This enables support for Corstone500 ARM which is a
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+ Cortex-A5 system
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+
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config TARGET_VEXPRESS_CA9X4
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bool "Support vexpress_ca9x4"
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select CPU_V7A
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@@ -2299,6 +2308,7 @@ source "board/bosch/shc/Kconfig"
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config TARGET_TOTAL_COMPUTE
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bool "Support Total Compute Platform"
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select ARM64
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@@ -2302,6 +2311,7 @@ source "board/bosch/shc/Kconfig"
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source "board/bosch/guardian/Kconfig"
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source "board/Marvell/octeontx/Kconfig"
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source "board/Marvell/octeontx2/Kconfig"
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@@ -145,22 +141,24 @@ index 000000000000..e878f5c6a521
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+
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diff --git a/configs/corstone500_defconfig b/configs/corstone500_defconfig
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new file mode 100644
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index 000000000000..d3161a4b40d8
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index 000000000000..e475cbe7e40d
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--- /dev/null
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+++ b/configs/corstone500_defconfig
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@@ -0,0 +1,40 @@
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@@ -0,0 +1,41 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_TARGET_CORSTONE500=y
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+CONFIG_SYS_TEXT_BASE=0x88000000
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+CONFIG_SYS_MALLOC_LEN=0x840000
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+CONFIG_SYS_MALLOC_F_LEN=0x2000
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_SYS_MEMTEST_START=0x80000000
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+CONFIG_SYS_MEMTEST_END=0xff000000
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+CONFIG_ENV_SIZE=0x40000
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+CONFIG_SYS_PROMPT="corstone500# "
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+CONFIG_IDENT_STRING=" corstone500 aarch32"
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+CONFIG_SYS_LOAD_ADDR=0x90000000
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+CONFIG_SYS_MEMTEST_START=0x80000000
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+CONFIG_SYS_MEMTEST_END=0xff000000
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+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
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+CONFIG_SUPPORT_RAW_INITRD=y
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+CONFIG_BOOTDELAY=1
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+CONFIG_USE_BOOTARGS=y
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@@ -168,7 +166,6 @@ index 000000000000..d3161a4b40d8
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+# CONFIG_DISPLAY_CPUINFO is not set
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+# CONFIG_DISPLAY_BOARDINFO is not set
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+CONFIG_HUSH_PARSER=y
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+CONFIG_SYS_PROMPT="corstone500# "
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+# CONFIG_CMD_CONSOLE is not set
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+CONFIG_CMD_BOOTZ=y
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+# CONFIG_CMD_XIMG is not set
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@@ -191,10 +188,10 @@ index 000000000000..d3161a4b40d8
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+CONFIG_OF_LIBFDT=y
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diff --git a/include/configs/corstone500.h b/include/configs/corstone500.h
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new file mode 100644
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index 000000000000..93c397d2f515
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index 000000000000..416f5fa4399d
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--- /dev/null
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+++ b/include/configs/corstone500.h
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@@ -0,0 +1,109 @@
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@@ -0,0 +1,102 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * (C) Copyright 2022 ARM Limited
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@@ -208,8 +205,6 @@ index 000000000000..93c397d2f515
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+#ifndef __CORSTONE500_H
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+#define __CORSTONE500_H
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+
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+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
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+
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+/* Generic Timer Definitions */
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+#define CONFIG_SYS_HZ_CLOCK 7500000
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+#define CONFIG_SYS_HZ 1000
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@@ -285,12 +280,7 @@ index 000000000000..93c397d2f515
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+ "bootz $kernel_addr $initrd_addr:0x800000 $fdt_addr"
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+
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+/* Monitor Command Prompt */
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+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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+#define CONFIG_SYS_MAXARGS 64 /* max command args */
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+
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+#define CONFIG_SYS_FLASH_BASE 0x80000000
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+/* 256 x 256KiB sectors */
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+#define CONFIG_SYS_MAX_FLASH_SECT 256
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+/* Store environment at top of flash */
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+#define CONFIG_ENV_ADDR 0x0a7c0000
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+#define CONFIG_ENV_SECT_SIZE 0x0040000
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@@ -305,5 +295,5 @@ index 000000000000..93c397d2f515
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+#define CONFIG_ENV_IS_IN_FLASH 1
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+#endif
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--
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2.37.1
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2.38.1
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