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arm-bsp/trusted-firmware-a: Upgrade Corstone1000 to TF-A v2.11

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Update the preferred version of TrustedFirmware-A for Cortsone-1000
from 2.10.x to 2.11.x to benefit from the latest fixes and improvements
as well as to reduce the number of out-of-tree patches.

As a result of updating the version:
* Remove no longer required out-of-tree patches
* Update the numbering of the remaining out-of-tree patches

Additionally remove unnecessary white spaces in modified BitBake files.

Signed-off-by: Bence Balogh <bence.balogh@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Bence Balogh
2024-07-05 18:06:20 +02:00
committed by Jon Mason
parent 0ec9dedc00
commit 45cc1d2e2c
7 changed files with 25 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
meta-arm-bsp/conf/machine/include/corstone1000.inc
View File

@@ -7,7 +7,7 @@ PREFERRED_VERSION_trusted-firmware-m ?= "2.0.%"
# TF-A
TFA_PLATFORM = "corstone1000"
PREFERRED_VERSION_trusted-firmware-a ?= "2.10.%"
PREFERRED_VERSION_trusted-firmware-a ?= "2.11.%"
PREFERRED_VERSION_tf-a-tests ?= "2.10.%"
TFA_BL2_BINARY = "bl2-corstone1000.bin"

0
meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch → meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch
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54
meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-spmd-remove-EL3-interrupt-registration.patch
View File

@@ -1,54 +0,0 @@
From 684b8f88238f522b52eb102485762e02e6b1671a Mon Sep 17 00:00:00 2001
From: Emekcan Aras <Emekcan.Aras@arm.com>
Date: Fri, 23 Feb 2024 13:17:59 +0000
Subject: [PATCH] fix(spmd): remove EL3 interrupt registration
This configuration should not be done for corstone1000 and similar
platforms. GICv2 systems only support EL3 interrupts and can have SEL1 component
as SPMC.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Upstream-Status: Inappropriate [Discussions of fixing this in a better way is ongoing in upstream]
---
services/std_svc/spmd/spmd_main.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 066571e9b..313f05bf3 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -580,30 +580,6 @@ static int spmd_spmc_init(void *pm_addr)
panic();
}
- /*
- * Permit configurations where the SPM resides at S-EL1/2 and upon a
- * Group0 interrupt triggering while the normal world runs, the
- * interrupt is routed either through the EHF or directly to the SPMD:
- *
- * EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD
- * for handling by spmd_group0_interrupt_handler_nwd.
- *
- * EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF.
- *
- */
-#if (EL3_EXCEPTION_HANDLING == 0)
- /*
- * Register an interrupt handler routing Group0 interrupts to SPMD
- * while the NWd is running.
- */
- rc = register_interrupt_type_handler(INTR_TYPE_EL3,
- spmd_group0_interrupt_handler_nwd,
- flags);
- if (rc != 0) {
- panic();
- }
-#endif
-
return 0;
}
--
2.25.1

0
meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-fix-corstone1000-clean-the-cache-and-disable-interru.patch → meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch
View File

33
meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch → meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch
View File

@@ -1,4 +1,4 @@
From bd975fbcff8886b3d3ed3268d7b6fa41bd7fba2d Mon Sep 17 00:00:00 2001
From dcc9cf5111c41edc691f007bd97548d96f5efddb Mon Sep 17 00:00:00 2001
From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Date: Thu, 9 May 2024 16:59:34 +0000
Subject: [PATCH] feat(corstone1000): add multicore support for fvp
@@ -13,8 +13,8 @@ Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
.../common/corstone1000_helpers.S | 26 +++++++++++
.../corstone1000/common/corstone1000_pm.c | 43 ++++++++++++++++++-
.../common/include/platform_def.h | 15 ++++++-
plat/arm/board/corstone1000/platform.mk | 8 ++++
4 files changed, 90 insertions(+), 2 deletions(-)
plat/arm/board/corstone1000/platform.mk | 7 +++
4 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
index cbe27c3b5..90dc4fee6 100644
@@ -56,10 +56,10 @@ index cbe27c3b5..90dc4fee6 100644
/* ---------------------------------------------------------------------
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index 4b0a791e7..9cd384e18 100644
index a52e945bf..979243317 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -24,10 +24,51 @@ static void __dead2 corstone1000_system_reset(void)
@@ -33,10 +33,51 @@ static void __dead2 corstone1000_system_reset(void)
wfi();
}
}
@@ -80,7 +80,7 @@ index 4b0a791e7..9cd384e18 100644
+{
+ int core_index = plat_core_pos_by_mpidr(mpidr);
+ uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE;
+
+ /* Validate the core index */
+ if ((core_index < 0) || (core_index > PLATFORM_CORE_COUNT)) {
+ return PSCI_E_INVALID_PARAMS;
@@ -91,7 +91,7 @@ index 4b0a791e7..9cd384e18 100644
+
+ return PSCI_E_SUCCESS;
+}
+
+void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ (void)target_state;
@@ -113,10 +113,10 @@ index 4b0a791e7..9cd384e18 100644
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 35bb6ad5c..56e124f96 100644
index b9a1d43df..c4839ccf3 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -251,7 +251,20 @@
@@ -249,7 +249,20 @@
*/
#define ARM_LOCAL_STATE_OFF U(2)
@@ -139,11 +139,11 @@ index 35bb6ad5c..56e124f96 100644
#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE)
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
index dcd0df844..71b7f324c 100644
index fd08803e8..45092ace9 100644
--- a/plat/arm/board/corstone1000/platform.mk
+++ b/plat/arm/board/corstone1000/platform.mk
@@ -31,6 +31,14 @@ override NEED_BL31 := yes
NEED_BL32 := yes
@@ -31,6 +31,13 @@ override NEED_BL31 := yes
NEED_BL32 ?= yes
override NEED_BL33 := yes
+ENABLE_MULTICORE := 0
@@ -153,10 +153,9 @@ index dcd0df844..71b7f324c 100644
+endif
+endif
+
+
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
# Add CORSTONE1000_WITH_BL32 as a preprocessor define (-D option)
ifeq (${NEED_BL32},yes)
$(eval $(call add_define,CORSTONE1000_WITH_BL32))
--
2.34.1
2.25.1

0
meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0007-feat-corstone1000-include-platform-header-file.patch → meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-include-platform-header-file.patch
View File

17
meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc
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@@ -6,11 +6,10 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
SRC_URI:append = " \
file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \
file://0002-fix-corstone1000-pass-spsr-value-explicitly.patch \
file://0003-fix-spmd-remove-EL3-interrupt-registration.patch \
file://0004-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \
file://0005-fix-corstone1000-clean-the-cache-and-disable-interru.patch \
file://0006-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \
file://0007-feat-corstone1000-include-platform-header-file.patch \
file://0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \
file://0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch \
file://0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \
file://0006-feat-corstone1000-include-platform-header-file.patch \
"
TFA_DEBUG = "1"
@@ -27,13 +26,13 @@ TFA_SPMD_SPM_AT_SEL2 = "0"
# BL2 loads BL32 (optee). So, optee needs to be built first:
DEPENDS += "optee-os"
# Note: Regarding the build option: LOG_LEVEL.
# Note: Regarding the build option: LOG_LEVEL.
# There seems to be an issue when setting it
# to 50 (LOG_LEVEL_VERBOSE), where the kernel
# to 50 (LOG_LEVEL_VERBOSE), where the kernel
# tee driver sends yielding requests to OP-TEE
# at a faster pace than OP-TEE processes them,
# as the processing time is consumed by logging
# in TF-A. When this issue occurs, booting halts
# as the processing time is consumed by logging
# in TF-A. When this issue occurs, booting halts
# as soon as optee driver starts initialization.
# Therefore, it's not currently recommended to
# set LOG_LEVEL to 50 at all.