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arm-bsp/optee-os: N1SDP support for optee-os 3.19
From: Emekcan <emekcan.aras@arm.com> Adds build configuration to support optee-os 3.19 for N1SDP. Also, it patches optee-os to support external DT for N1SDP. Signed-off-by: Emekcan <emekcan.aras@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Emekcan Aras
Jon Mason
@@ -0,0 +1,44 @@
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Upstream-Status: Pending [Not submitted to upstream yet]
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Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
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From 1a9aeedda58228893add545e49d2d6cd4c316b4f Mon Sep 17 00:00:00 2001
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From: Emekcan <emekcan.aras@arm.com>
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Date: Tue, 13 Dec 2022 13:45:06 +0000
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Subject: [PATCH] plat-n1sdp: add external device tree base and size
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Adds external device tree address and size. It also
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register this physical memory so optee can read the device tree.
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---
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core/arch/arm/plat-n1sdp/main.c | 1 +
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core/arch/arm/plat-n1sdp/platform_config.h | 3 +++
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2 files changed, 4 insertions(+)
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diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c
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index bb951ce6b..ab76f60c6 100644
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--- a/core/arch/arm/plat-n1sdp/main.c
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+++ b/core/arch/arm/plat-n1sdp/main.c
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@@ -31,6 +31,7 @@ static struct gic_data gic_data __nex_bss;
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static struct pl011_data console_data __nex_bss;
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register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
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+register_phys_mem_pgdir(MEM_AREA_EXT_DT, EXT_DT_BASE, EXT_DT_SIZE);
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register_ddr(DRAM0_BASE, DRAM0_SIZE);
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register_ddr(DRAM1_BASE, DRAM1_SIZE);
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diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h
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index bf0a3c834..8741a2503 100644
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--- a/core/arch/arm/plat-n1sdp/platform_config.h
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+++ b/core/arch/arm/plat-n1sdp/platform_config.h
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@@ -42,6 +42,9 @@
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#define GICC_BASE 0x2C000000
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#define GICR_BASE 0x300C0000
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+#define EXT_DT_BASE 0x04001600
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+#define EXT_DT_SIZE 0x200
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+
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#ifndef UART_BAUDRATE
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#define UART_BAUDRATE 115200
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#endif
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--
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2.17.1
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@@ -11,6 +11,7 @@ SRC_URI:append = " \
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file://0003-HACK-disable-instruction-cache-and-data-cache.patch \
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file://0004-Handle-logging-syscall.patch \
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file://0005-plat-n1sdp-register-DRAM1-to-optee-os.patch \
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file://0006-plat-n1sdp-add-external-device-tree-base-and-size.patch \
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"
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EXTRA_OEMAKE += " CFG_TEE_CORE_LOG_LEVEL=4"
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@@ -20,3 +21,9 @@ EXTRA_OEMAKE += " CFG_TEE_BENCHMARK=n"
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EXTRA_OEMAKE += " CFG_CORE_SEL1_SPMC=y CFG_CORE_FFA=y"
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EXTRA_OEMAKE += " CFG_WITH_SP=y"
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EXTRA_OEMAKE += " CFG_DT=y"
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EXTRA_OEMAKE += " CFG_SECURE_PARTITION=y"
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EXTRA_OEMAKE += " CFG_MAP_EXT_DT_SECURE=y"
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@@ -1,7 +1,7 @@
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From f189457b79989543f65b8a4e8729eff2cdf9a758 Mon Sep 17 00:00:00 2001
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From: Khem Raj <raj.khem@gmail.com>
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Date: Sat, 13 Aug 2022 19:24:55 -0700
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Subject: [PATCH] core: Define section attributes for clang
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From ff1b556ac2cd6bbb857a1ac03e0557eb490bc845 Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <emekcan.aras@arm.com>
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Date: Wed, 21 Dec 2022 10:55:58 +0000
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Subject: [PATCH] [PATCH] core: Define section attributes for clang
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Clang's attribute section is not same as gcc, here we need to add flags
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to sections so they can be eventually collected by linker into final
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@@ -32,14 +32,17 @@ Upstream-Status: Pending
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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core/arch/arm/kernel/thread.c | 19 +++++++++++++++--
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core/arch/arm/mm/core_mmu_lpae.c | 35 ++++++++++++++++++++++++++++----
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core/arch/arm/mm/core_mmu_lpae.c | 35 +++++++++++++++++++++++++++----
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core/arch/arm/mm/core_mmu_v7.c | 36 +++++++++++++++++++++++++++++---
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core/arch/arm/mm/pgt_cache.c | 12 ++++++++++-
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core/kernel/thread.c | 13 +++++++++++-
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4 files changed, 71 insertions(+), 8 deletions(-)
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5 files changed, 104 insertions(+), 11 deletions(-)
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diff --git a/core/arch/arm/kernel/thread.c b/core/arch/arm/kernel/thread.c
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index 05dbbe56..8e6ea034 100644
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--- a/core/arch/arm/kernel/thread.c
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+++ b/core/arch/arm/kernel/thread.c
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@@ -44,16 +44,31 @@ static size_t thread_user_kcode_size __n
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@@ -44,15 +44,30 @@ static size_t thread_user_kcode_size __nex_bss;
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#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) && \
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defined(CFG_CORE_WORKAROUND_SPECTRE_BP_SEC) && defined(ARM64)
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long thread_user_kdata_sp_offset __nex_bss;
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@@ -62,17 +65,18 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
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- __section(".nex_nozi.kdata_page");
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+ __section(".nex_nozi.kdata_page")
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#endif
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#endif
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+#endif
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+ ;
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+#endif
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+
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+/* reset BSS section to default ( .bss ) */
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+#ifdef __clang__
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+#pragma clang section bss=""
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+#endif
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#endif
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#ifdef ARM32
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uint32_t __nostackcheck thread_get_exceptions(void)
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diff --git a/core/arch/arm/mm/core_mmu_lpae.c b/core/arch/arm/mm/core_mmu_lpae.c
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index 3f08eec6..e6dc9261 100644
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--- a/core/arch/arm/mm/core_mmu_lpae.c
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+++ b/core/arch/arm/mm/core_mmu_lpae.c
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@@ -233,19 +233,46 @@ typedef uint16_t l1_idx_t;
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@@ -126,59 +130,11 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
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/*
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* TAs page table entry inside a level 1 page table.
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*
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--- a/core/arch/arm/mm/pgt_cache.c
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+++ b/core/arch/arm/mm/pgt_cache.c
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@@ -104,8 +104,18 @@ void pgt_init(void)
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* has a large alignment, while .bss has a small alignment. The current
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* link script is optimized for small alignment in .bss
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*/
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+#ifdef __clang__
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+#pragma clang section bss=".nozi.mmu.l2"
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+#endif
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static uint8_t pgt_tables[PGT_CACHE_SIZE][PGT_SIZE]
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- __aligned(PGT_SIZE) __section(".nozi.pgt_cache");
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+ __aligned(PGT_SIZE)
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+#ifndef __clang__
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+ __section(".nozi.pgt_cache")
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+#endif
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+ ;
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+#ifdef __clang__
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+#pragma clang section bss=""
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+#endif
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size_t n;
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for (n = 0; n < ARRAY_SIZE(pgt_tables); n++) {
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--- a/core/kernel/thread.c
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+++ b/core/kernel/thread.c
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@@ -37,13 +37,24 @@ struct thread_core_local thread_core_loc
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name[stack_num][sizeof(name[stack_num]) / sizeof(uint32_t) - 1]
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#endif
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+#define DO_PRAGMA(x) _Pragma (#x)
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+
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+#ifdef __clang__
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+#define DECLARE_STACK(name, num_stacks, stack_size, linkage) \
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+DO_PRAGMA (clang section bss=".nozi_stack." #name) \
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+linkage uint32_t name[num_stacks] \
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+ [ROUNDUP(stack_size + STACK_CANARY_SIZE + STACK_CHECK_EXTRA, \
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+ STACK_ALIGNMENT) / sizeof(uint32_t)] \
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+ __attribute__((aligned(STACK_ALIGNMENT))); \
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+DO_PRAGMA(clang section bss="")
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+#else
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#define DECLARE_STACK(name, num_stacks, stack_size, linkage) \
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linkage uint32_t name[num_stacks] \
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[ROUNDUP(stack_size + STACK_CANARY_SIZE + STACK_CHECK_EXTRA, \
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STACK_ALIGNMENT) / sizeof(uint32_t)] \
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__attribute__((section(".nozi_stack." # name), \
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aligned(STACK_ALIGNMENT)))
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-
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+#endif
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#define GET_STACK(stack) ((vaddr_t)(stack) + STACK_SIZE(stack))
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DECLARE_STACK(stack_tmp, CFG_TEE_CORE_NB_CORE,
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diff --git a/core/arch/arm/mm/core_mmu_v7.c b/core/arch/arm/mm/core_mmu_v7.c
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index cd85bd22..3e18f54f 100644
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--- a/core/arch/arm/mm/core_mmu_v7.c
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+++ b/core/arch/arm/mm/core_mmu_v7.c
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@@ -204,16 +204,46 @@ typedef uint32_t l1_xlat_tbl_t[NUM_L1_EN
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@@ -204,16 +204,46 @@ typedef uint32_t l1_xlat_tbl_t[NUM_L1_ENTRIES];
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typedef uint32_t l2_xlat_tbl_t[NUM_L2_ENTRIES];
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typedef uint32_t ul1_xlat_tbl_t[NUM_UL1_ENTRIES];
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@@ -228,3 +184,60 @@ Signed-off-by: Khem Raj <raj.khem@gmail.com>
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struct mmu_partition {
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l1_xlat_tbl_t *l1_table;
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diff --git a/core/arch/arm/mm/pgt_cache.c b/core/arch/arm/mm/pgt_cache.c
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index a7b1b10e..489859ce 100644
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--- a/core/arch/arm/mm/pgt_cache.c
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+++ b/core/arch/arm/mm/pgt_cache.c
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@@ -410,8 +410,18 @@ void pgt_init(void)
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* has a large alignment, while .bss has a small alignment. The current
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* link script is optimized for small alignment in .bss
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*/
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+#ifdef __clang__
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+#pragma clang section bss=".nozi.mmu.l2"
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+#endif
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static uint8_t pgt_tables[PGT_CACHE_SIZE][PGT_SIZE]
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- __aligned(PGT_SIZE) __section(".nozi.pgt_cache");
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+ __aligned(PGT_SIZE)
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+#ifndef __clang__
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+ __section(".nozi.pgt_cache")
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+#endif
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+ ;
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+#ifdef __clang__
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+#pragma clang section bss=""
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+#endif
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size_t n;
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for (n = 0; n < ARRAY_SIZE(pgt_tables); n++) {
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diff --git a/core/kernel/thread.c b/core/kernel/thread.c
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index d1f2f382..8de124ae 100644
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--- a/core/kernel/thread.c
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+++ b/core/kernel/thread.c
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@@ -38,13 +38,24 @@ struct thread_core_local thread_core_local[CFG_TEE_CORE_NB_CORE] __nex_bss;
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name[stack_num][sizeof(name[stack_num]) / sizeof(uint32_t) - 1]
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#endif
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+#define DO_PRAGMA(x) _Pragma (#x)
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+
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+#ifdef __clang__
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+#define DECLARE_STACK(name, num_stacks, stack_size, linkage) \
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+DO_PRAGMA (clang section bss=".nozi_stack." #name) \
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+linkage uint32_t name[num_stacks] \
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+ [ROUNDUP(stack_size + STACK_CANARY_SIZE + STACK_CHECK_EXTRA, \
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+ STACK_ALIGNMENT) / sizeof(uint32_t)] \
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+ __attribute__((aligned(STACK_ALIGNMENT))); \
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+DO_PRAGMA(clang section bss="")
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+#else
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#define DECLARE_STACK(name, num_stacks, stack_size, linkage) \
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linkage uint32_t name[num_stacks] \
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[ROUNDUP(stack_size + STACK_CANARY_SIZE + STACK_CHECK_EXTRA, \
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STACK_ALIGNMENT) / sizeof(uint32_t)] \
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__attribute__((section(".nozi_stack." # name), \
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aligned(STACK_ALIGNMENT)))
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-
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+#endif
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#define GET_STACK(stack) ((vaddr_t)(stack) + STACK_SIZE(stack))
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DECLARE_STACK(stack_tmp, CFG_TEE_CORE_NB_CORE, STACK_TMP_SIZE,
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--
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2.17.1
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@@ -3,3 +3,7 @@ require optee-os-3_19.inc
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DEPENDS += "dtc-native"
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SRCREV = "afacf356f9593a7f83cae9f96026824ec242ff52"
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SRC_URI:append = " \
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file://0001-core-Define-section-attributes-for-clang.patch \
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"
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