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mirror of https://git.yoctoproject.org/meta-arm synced 2026-06-05 14:30:10 +00:00

arm-bsp/n1sdp/scp-firmware: bump to latest master branch

SCP firmware recipes are updated to build latest SCP firmware,
the previous release version is 2.7.0.

New features required for N1SDP are integrated in SCP firmware repository, this mandates
us to migrate to latest master.

Change-Id: I1fb44ed790ca17f713333a0e371dce10c9399424
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Khasim Mohammed
2021-03-18 17:26:05 +05:30
committed by Jon Mason
parent 4f1f77d660
commit 61291f6d80
2 changed files with 4 additions and 82 deletions
@@ -1,78 +0,0 @@
Upstream-Status: Backport
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
From 3deb59c5f4c64aa092bb3a4ebc018acf3f746f47 Mon Sep 17 00:00:00 2001
From: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Date: Tue, 10 Nov 2020 12:31:04 +0530
Subject: [PATCH] product/n1sdp: set CCIX speed to GEN3 to work with interposer
C2C setup
Set CCIX speed to GEN3 to work with interposer C2C setup
In this use case set downstream/upstream port transmitter
preset value to 4.
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: I635566574babbb7591b5bba97105f76f1f8e550a
---
.../module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 30 ++++++++++++++-----
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
index 901e0464..ba02144f 100644
--- a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
+++ b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
@@ -206,7 +206,12 @@ static int n1sdp_pcie_phy_init(fwk_id_t id)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive())
+ gen_speed = PCIE_GEN_3;
+ else
+ gen_speed = PCIE_GEN_4;
+
lane_count = LAN_COUNT_IN_X_16;
FWK_LOG_INFO("[%s] Initializing PHY...", pcie_type[did]);
@@ -239,7 +244,12 @@ static int n1sdp_pcie_controller_init(fwk_id_t id, bool ep_mode)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive())
+ gen_speed = PCIE_GEN_3;
+ else
+ gen_speed = PCIE_GEN_4;
+
lane_count = LAN_COUNT_IN_X_16;
if (ep_mode) {
@@ -282,12 +292,18 @@ static int n1sdp_pcie_link_training(fwk_id_t id, bool ep_mode)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive()) {
+ gen_speed = PCIE_GEN_3;
+ down_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE;
+ up_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE;
+ } else {
+ gen_speed = PCIE_GEN_4;
+ down_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE;
+ up_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE;
+ }
+
lane_count = LAN_COUNT_IN_X_16;
- down_stream_tx_preset = dev_ctx->config->ccix_capable ?
- CCIX_RC_TX_PRESET_VALUE : PCIE_RC_TX_PRESET_VALUE;
- up_stream_tx_preset = dev_ctx->config->ccix_capable ?
- CCIX_RC_TX_PRESET_VALUE : PCIE_RC_TX_PRESET_VALUE;
if (gen_speed >= PCIE_GEN_3 && !ep_mode) {
FWK_LOG_INFO(
--
2.25.1
@@ -3,11 +3,11 @@
SCP_PLATFORM = "n1sdp"
SCP_LOG_LEVEL = "INFO"
FILESEXTRAPATHS_prepend := "${THISDIR}/files/:"
LIC_FILES_CHKSUM = "file://license.md;beginline=5;md5=9db9e3d2fb8d9300a6c3d15101b19731 \
file://contrib/cmsis/git/LICENSE.txt;md5=e3fc50a88d0a364313df4b21ef20c29e"
SRC_URI_append = " \
file://0001-product-n1sdp-set-CCIX-speed-to-GEN3-to-work-with-in.patch \
"
SRCREV = "6c15afb1b37d0728482c598b063cd69bfc733e93"
PV = "2.7+git${SRCPV}"
COMPATIBLE_MACHINE_n1sdp = "n1sdp"